E2G0019-17-41 ¡ Semiconductor MSM512800C ¡ Semiconductor This version: Jan. 1998 MSM512800C Previous version: May 1997 262,144-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM512800C is a 262,144-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM512800C achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM512800C is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP. FEATURES • 262,144-word ¥ 8-bit configuration • Single 5 V power supply, ±5% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 512 cycles/8 ms • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Package options: 26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM512800C-xxJS) 26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM512800C-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM512800C-40 40 ns 20 ns 10 ns 10 ns MSM512800C-45 45 ns 24 ns 14 ns 14 ns 90 ns 630 mW MSM512800C-50 50 ns 26 ns 14 ns 14 ns 100 ns 577.5 mW 80 ns 735 mW 5.25 mW 1/16 ¡ Semiconductor MSM512800C PIN CONFIGURATION (TOP VIEW) VSS 1 26 VSS VSS 1 26 VSS DQ1 2 25 DQ8 DQ1 2 25 DQ8 DQ2 3 24 DQ7 DQ2 3 24 DQ7 DQ3 4 23 DQ6 DQ3 4 23 DQ6 DQ4 5 22 DQ5 DQ4 5 22 DQ5 WE 6 21 CAS WE 6 21 CAS RAS 8 19 OE RAS 8 19 OE A0 9 18 A8 A0 9 18 A8 A1 10 17 A7 A1 10 17 A7 A2 11 16 A6 A2 11 16 A6 A3 12 15 A5 A3 12 15 A5 VCC 13 14 A4 VCC 13 14 A4 26/24-Pin Plastic SOJ Pin Name A0 - A8 Function Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ8 Note: 26/24-Pin Plastic TSOP (K Type) Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) The same GND voltage level must be provided to every VSS pin. 2/16 ¡ Semiconductor MSM512800C BLOCK DIAGRAM RAS Timing Generator Timing Generator CAS 9 Column Address Buffers 9 Write Clock Generator Column Decoders WE OE 8 Internal Address Counter A0 - A8 Refresh Control Clock Sense Amplifiers 8 I/O Selector Row Address Buffers 9 Row Decoders Word Drivers 8 8 8 8 9 Output Buffers Input Buffers DQ1 - DQ8 8 Memory Cells VCC On Chip VBB Generator VSS 3/16 ¡ Semiconductor MSM512800C ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VT –1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Voltage on Any Pin Relative to VSS *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.75 5.0 5.25 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance Parameter (VCC = 5 V ±5%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A8) CIN1 — 6 pF Input Capacitance (RAS, CAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ8) CI/O — 7 pF 4/16 ¡ Semiconductor MSM512800C DC Characteristics Parameter (VCC = 5 V ±5%, Ta = 0°C to 70°C) Symbol Condition MSM512800 MSM512800 MSM512800 C-45 C-40 C-50 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –5.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2 mA 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 130 — 120 — 110 mA 1, 2 — 2 — 2 — 2 — 1 — 1 — 1 — 130 — 120 — 110 — 5 — 5 — 5 — 130 — 120 — 110 mA 1, 2 — 110 — 100 — 90 mA 1, 3 0 V £ VI £ 6.5 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) Current (Standby) (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) tRC = Min. ≥ VCC –0.2 V mA 1 RAS cycling, ICC3 CAS = VIH, mA 1, 2 tRC = Min. RAS = VIH, ICC5 CAS = VIL, mA 1 DQ = enable Average Power Supply Current RAS, CAS cycling, RAS, CAS = VIH (RAS-only Refresh) Power Supply 0 V £ VO £ 5.25 V ICC2 RAS, CAS Average Power Supply Current DQ disable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/16 ¡ Semiconductor MSM512800C AC Characteristics (1/2) (VCC = 5 V ±5%, Ta = 0°C to 70°C, Input Pulse Levels 0 V to 3 V) Note 1, 2, 3 Parameter Random Read or Write Cycle Time MSM512800 MSM512800 MSM512800 C-40 C-50 C-45 Symbol Unit Note Min. Max. Min. Max. Min. Max. tRC 80 — 90 — 100 — ns tRWC 130 — — ns 30 — — 150 36 — tPC 140 34 — ns Fast Page Mode Read Modify Write Cycle Time Access Time from RAS tPRWC 70 — 75 — 77 — ns tRAC — 40 — 45 — 50 ns 4, 5, 6 Access Time from CAS Access Time from Column Address tCAC tAA — — 10 20 — — 14 24 — — 14 26 ns ns 4, 5 4, 6 Access Time from CAS Precharge tCPA — 25 — 28 — 30 ns 4 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 10 — — 0 14 — — 0 14 — ns ns 4 4 CAS to Data Output Buffer Turn-off Delay Time tOFF 0 10 0 7 0 3 — 10 50 8 0 3 — 0 3 — 10 13 50 8 ns tOEZ tT tREF 10 10 50 8 0 OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period ns ns ms 7 3 RAS Precharge Time tRP 30 — 35 — 40 — ns RAS Pulse Width tRAS 40 10,000 45 10,000 50 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 40 100,000 45 100,000 50 100,000 ns RAS Hold Time tRSH 10 — 14 — 14 — RAS Hold Time referenced to OE tROH 10 — 10 — 10 — ns ns CAS Precharge Time (Fast Page Mode) tCP 10 — 10 — 10 — ns CAS Pulse Width tCAS 10 10,000 14 10,000 14 10,000 ns CAS Hold Time tCSH 40 CAS to RAS Precharge Time tCRP 5 — — 45 5 — — 50 5 — — ns ns RAS Hold Time from CAS Precharge tRHCP RAS to CAS Delay Time tRCD RAS to Column Address Delay Time tRAD 25 15 10 — 30 20 28 17 12 — 31 21 30 18 13 — 36 24 ns ns ns Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 5 — 7 — 8 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Column Address Hold Time tCAH 10 — 12 — 13 — ns Column Address Hold Time from RAS Column Address to RAS Lead Time tAR 30 — 35 — 40 — ns tRAL 20 — 24 — 26 — ns Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 8 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 Read Modify Write Cycle Time Fast Page Mode Cycle Time 5 6 6/16 ¡ Semiconductor MSM512800C AC Characteristics (2/2) (VCC = 5 V ±5%, Ta = 0°C to 70°C, Input Pulse Levels 0 V to 3 V) Note 1, 2, 3 Parameter Symbol MSM512800 MSM512800 MSM512800 C-40 C-45 C-50 Unit Note Min. Max. Min. Max. Min. Max. Write Command Set-up Time tWCS 0 — 0 — 0 — ns Write Command Hold Time Write Command Hold Time from RAS tWCH tWCR 10 30 — — 12 35 — — 13 40 — — ns ns Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time tWP tOEH tRWL tCWL 10 10 — — 10 12 — — 10 13 — — ns ns 10 10 — — 14 14 — — 14 14 — — ns ns Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time tDS tDH tDHR tOED tCWD tAWD tRWD 0 10 — — 0 12 — — 0 13 — — ns ns 30 10 — — 35 12 — — 40 13 — — ns ns 30 40 60 — — — 36 48 70 — — — 38 52 75 — — — ns ns ns 9 9 9 CAS Precharge WE Delay Time 9 tCPWD 45 — 46 — 50 — ns CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) tRPC tCSR 0 10 — — 0 10 — — 0 10 — — ns ns RAS to CAS Hold Time (CAS before RAS) tCHR 20 — 25 — 25 — ns 9 10 10 7/16 ¡ Semiconductor Notes: MSM512800C 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 50 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 8/16 E2G0092-17-41E ¡ Semiconductor MSM512800C , ,, , ,,,, TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH – VIL – tAR tCSH tCRP tRCD VIH – CAS VIL – VIH – VIL – tRSH tCAS tRAD tASR Address tCRP tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tOEA VIH – VIL – tCAC tRAC DQ tRCH tRRH VOH – tOEZ Open VOL – tOFF Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tAR tCRP CAS VIH – VIL – WE VIH – VIL – tCSH tRCD tRSH tCAS tRAD tRAH tASR Address tCRP tASC Row tCAH Column tWCS tWCH VIH – tRWL VIH – VIL – tDS DQ tCWL tWP VIL – tWCR OE tRAL VIH – VIL – tDHR tDH Valid Data-in Open "H" or "L" 9/16 , ,, ¡ Semiconductor MSM512800C Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tRP tAR tCRP tCSH tCRP tRCD tRSH tCAS VIH – CAS VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tAWD tRCS tOEA tOED tCAC tRAC DQ VI/OH– VI/OL– tCWL tRWL tWP tCWD tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/16 ,,, , ,,, ¡ Semiconductor MSM512800C Fast Page Mode Read Cycle tRASP VIH – RAS V – IL VIH – CAS VIL – Address WE VIH – VIL – tRP tAR tCRP tRHCP tPC tRCD tCP tASR tCP tCAS tCAS tRAD tRAH tASC tCSH tCAH tASC Column Row VIH – VIL – tCAC VOH – DQ VOL – Column tRCS tRCH tRRH tCPA tOEA tOFF tOEZ tRCH tAA tAA tCAC tOEA tOFF tCAC tOEZ tCLZ Valid Data-out tCLZ tRCS tCPA tOEA tRAC tRAL tCAH tASC Column tAA VIH – OE VIL – tCAS tCAH tRCH tRCS tCRP tRSH tCLZ tOFF tOEZ Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tAR VIH – RAS V – IL tCRP VIH – CAS VIL – Address VIH – VIL – tRAH tASC Row tWCS tDS VIH – VIL – tCSH tCAH Column tCWL tWCH tWP tRAD tRHCP tRSH tRCD VIH – WE VIL – DQ tPC tCAS tASR tRP tWCR tDH Valid Data-in tDHR tCP tCRP tCP tCAS tASC tCAH tASC Column tCWL tWCS tWCH tWP tDS tDH Valid Data-in tCAS tCAH tRAL Column tRWL tCWL tWCS tWCH tWP tDS tDH Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/16 ¡ Semiconductor MSM512800C ,,, , ,, , Fast Page Mode Read Modify Write Cycle tRASP VIH – RAS VIL – tAR tRP tCSH tPRWC tRCD VIH – CAS VIL – tASC tCAH tRAH VIH – VIL – tCRP tCAS tASC tCAH tCAH Column Column tASC Column Row tRCS tCPWD tCWD tRWD tCWD tRCS V WE IH – VIL – tCWL tAWD tCWL tWP tDH VI/OH– VI/OL – Out tCLZ tOEA tOED tOEZ tCAC In tDH tDS tOEA tOEZ tCAC tWP tCPA tAA tOED VIH – OE V – IL tCWL tROH tWP tDH tDS tOEA tRWL tAWD tCPA tAA tAA tRAL tRCS tCPWD tCWD tAWD tDS tRAC DQ tCP tCAS tRAD tASR Address tCP tCAS tRSH Out tOED In tCLZ tOEZ tCAC Out In tCLZ "H" or "L" RAS-Only Refresh Cycle tRC RAS VIL – CAS Address VIH – VIL – VIH – VIL – tRP tRAS VIH – tCRP tASR tRPC tRAH Row tOFF DQ VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L" 12/16 ,, , ,, ¡ Semiconductor MSM512800C CAS before RAS Refresh Cycle tRC tRP RAS VIH – VIL – DQ tRP tRPC tRPC tCSR tCP CAS tRAS VIH – VIL – tCHR tOFF VOH – VOL – Open Note: WE, OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRAS RAS VIH – tRP tAR VIH – VIL – VIH – VIL – tRSH tRCD tRAD tASC tRAH tASR Address tRAS tRP VIL – tCRP CAS tRC Row tCHR tCAH Column tRCS tRAL VIH – WE V IL – tRRH tAA tROH tOEA VIH – OE V IL – tRAC DQ VOH – VOL – tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" 13/16 , ,, , ¡ Semiconductor MSM512800C Hidden Refresh Write Cycle tRC tRP tRAS RAS VIH – tRP tAR VIH – VIH – VIL – tRSH tRCD tRAD tASC tRAH VIL – tASR Address tRAS VIL – tCRP CAS tRC tCHR tCAH t RAL Column Row tWCS VIH – WE V IL – tWCH tWP tWCR VIH – OE V IL – tDS V – DQ IH VIL – tDH Valid Data-in tDHR "H" or "L" 14/16 ¡ Semiconductor MSM512800C PACKAGE DIMENSIONS (Unit : mm) SOJ26/24-P-300-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MSM512800C (Unit : mm) TSOPII26/24-P-300-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16