TI1 LP3944 Rgb/white/blue 8-led fun light driver Datasheet

LP3944
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SNVS264 – MAY 2004
LP3944 RGB/White/Blue 8-LED Fun Light Driver
Check for Samples: LP3944
FEATURES
DESCRIPTION
•
•
•
•
LP3944 is an integrated device capable of
independently driving 8 LEDs. This device also
contains an internal precision oscillator that provides
all the necessary timing required for driving each
LED. Two prescaler registers along with two PWM
registers provide a versatile duty cycle control. The
LP3944 contains the ability to dim LEDs in
SMBUS/I2C applications where it is required to cut
down on bus traffic.
1
2
Internal Power-on Reset
Active Low Reset
Internal Precision Oscillator
Variable Dim Rates (from 6.25 ms to 1.6s; 160
Hz–0.625 Hz)
APPLICATIONS
•
•
•
•
•
•
Customized Flashing LED Lights for Cellular
Phones
Portable Applications
Digital Cameras
Indicator Lamps
General Purpose I/O Expander
Toys
Traditionally, to dim LEDs using a serial shift register
such as 74LS594/5 would require a large amount of
traffic to be on the serial bus. LP3944 instead
requires only the setup of the frequency and duty
cycle for each output pin. From then on, only a single
command from the host is required to turn each
individual open drain output ON, OFF, or to cycle a
programmed frequency and duty cycle. Maximum
output sink current is 25 mA per pin and 200 mA per
package. Any ports not used for controlling the LEDs
can be used for general purpose input/output
expansion.
KEY SPECIFICATIONS
•
•
8 LED Driver (Multiple Programmable
States—On, Off, Input, and Dimming at a
Specified Rate)
8 Open Drain Outputs Capable of Driving up to
25 mA per LED
Typical Application Circuit
+5V
5V
R
SMBUS
G
B
2
+5V
/I C
Blue LEDs
VDD
LED7
SDA
SCL
PORTx.D
SDA
SCL
LED6
LED5
RESET
LED4
A2
Cell Phone Baseband
Controller/PController
A1
A0
LED3
LED2
LED1
LED0
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
LP3944
SNVS264 – MAY 2004
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LP3944 Pin Out
18
17
16
15
14
13
19
12
20
11
21
10
22
9
23
8
24
7
1
2
3
4
5
6
Figure 1. (Top View)
Package Number RTW0024A
LP3944 PIN DESCRIPTION
Pin #
Name
Description
1
LED0
Output of LED0 Driver
2
LED1
Output of LED1 Driver
3
LED2
Output of LED2 Driver
4
LED3
Output of LED3 Driver
5
LED4
Output of LED4 Driver
6
LED5
Output of LED5 Driver
7
LED6
Output of LED6 Driver
8
LED7
Output of LED7 Driver
9
GND
Ground
10
NC
No Connect
11
NC
No Connect
12
NC
No Connect
13
NC
No Connect
14
NC
No Connect
15
NC
No Connect
16
NC
No Connect
17
NC
No Connect
18
RST
Active Low Reset Input
19
SCL
Clock Line for I2C Interface
20
SDA
Serial Data Line for I2C Interface
21
VDD
Power Supply
22
A0
Address Input 0
23
A1
Address Input 1
24
A2
Address Input 2
2
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Architectural Block Diagram
A2 A1 A0
SCL
SDA
Input Register
2
2
I C Bus
Control
I C
Filters
Bit0 of Input Reg 1
LED Select Register
Bit1
0
Bit0
of
Select
Register
LS0
1
LED0
VDD
RST
Power-On Reset
Oscillator
Prescalar
0
Register
Prescalar
1
Register
PWM 0
Register
PWM 1
Register
COPIES
Bit 7 of Input Register1
Bit 6 of Select Register LS1
Bit 7 of Select Register LS1
0
1
LED7
PWM0 Register
Programming Example (See end of datasheet
for complete example)
PWM1 Register
Figure 2. For Explanation of LP3944 Operation,
Please Refer to Theory of Operation in Application Notes.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2) (3)
−0.5V to 6V
VDD
A0, A1, A2, SCL, SDA, RST
(Collectively called digital pins)
6V
VSS−0.5V to 6V
Voltage on LED pins
Junction Temperature
150°C
Storage Temperature
−65°C to 150°C
Power Dissipation (4)
1.76W
Human Body Model
ESD (5)
Machine Model
Charge Device Model
(1)
(2)
(3)
(4)
(5)
2 kV
150V
1 kV
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits
and associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
If Military/Aerospace specified devices are required, please contact Texas Instruments for availability and specifications.
The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formulaP =
(TJ—TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal
resistance. The 1.76W rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction
temperature, 150°C, for TJ, 85°C for TA, and 37°C/W for θJA. More power can be dissipated safely at ambient temperature below 85°C.
Less power can be dissipated safely at ambient temperatures above 85°C. The Absolute Maximum power dissipation can be increased
by 27 mW for each degree below 85°C, and it must be de-rated by 27 mW for each degree above 85°C. For Operating Ratings
maximum power dissipation, TJ = 125°C and TA = 85°C
The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is 0Ω in series with 220 pF.
Operating Ratings (1) (2)
VDD
2.3V to 5.5V
−40°C to +125°C
Junction Temperature
−40°C to +85°C
Operating Ambient Temperature
Thermal Resistance (θJA)
WQFN-24 (3)
Power Dissipation
(1)
(2)
(3)
4
37°C/W
1.08W
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits
and associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formulaP =
(TJ—TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal
resistance. The 1.76W rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction
temperature, 150°C, for TJ, 85°C for TA, and 37°C/W for θJA. More power can be dissipated safely at ambient temperature below 85°C.
Less power can be dissipated safely at ambient temperatures above 85°C. The Absolute Maximum power dissipation can be increased
by 27 mW for each degree below 85°C, and it must be de-rated by 27 mW for each degree above 85°C. For Operating Ratings
maximum power dissipation, TJ = 125°C and TA = 85°C
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Electrical Characteristics
Unless otherwise noted, VDD = 5.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, TJ = −40°C to +125°C. (1)
Symbol
Parameter
Conditions
Typical
Limit
Min
Units
Max
POWER SUPPLY
VDD
Supply Voltage
IQ
Supply Current
5
2.3
5.5
No Load
350
550
Standby
2.0
5
ΔIQ
Additional Standby Current
VPOR
Power-On Reset Voltage
1.8
tw
Reset Pulse Width
10
VDD = 5.5V, every LED pin at
4.3V
V
µA
2
mA
1.96
V
ns
LED
VIL
LOW Level Input Voltage
VIH
HIGH Level Input Voltage
IOL
Low Level Output Current (2)
ILEAK
Input Leakage Current
CI/O
Input/Output Capacitance
−0.5
0.8
V
2.0
5.5
V
VOL = 0.4V, VDD = 2.3V
9
VOL = 0.4V, VDD = 3.0V
12
VOL = 0.4V, VDD = 5.0V
15
VOL = 0.7V, VDD = 2.3V
15
VOL = 0.7V, VDD = 3.0V
20
VOL = 0.7V, VDD = 5.0V
25
−1
VDD = 3.6, VIN = 0V or VDD
See (3)
2.6
mA
1
µA
5
pF
V
ALL DIGITAL PINS (EXCEPT SCL AND SDA PINS)
VIL
LOW Level Input Voltage
−0.5
0.8
VIH
HIGH Level Input Voltage
2.0
5.5
V
ILEAK
Input Leakage Current
−1
1
µA
CIN
Input Capacitance
5
pF
VIN = 0V (3)
2.3
2
I C INTERFACE (SCL AND SDA PINS)
VIL
LOW Level Input Voltage
-0.5
0.3VDD
V
VIH
HIGH Level Input Voltage
0.7VDD
5.5
V
VOL
LOW Level Output Voltage
0
0.2VDD
IOL
LOW Level Output Current
VOL = 0.4V
FCLK
Clock Frequency
See (3)
tHOLD
Hold Time Repeated START
Condition
µs
1.3
µs
0.6
µs
See
See (3)
See
(3)
0.6
µs
See
(3)
300
ns
(3)
100
ns
0.6
µs
tDATA-SU
Data Set-Up Time
See
tSU
Set-Up Time for STOP Condition
See (3)
tTRANS
Maximum Pulse Width of Spikes
that Must Be Suppressed by the
Input Filter of Both DATA & CLK
Signals
See (3)
(1)
(2)
(3)
kHz
0.6
CLK High Period
Data Hold Time
400
(3)
CLK Low Period
tDATA-HOLD
mA
See
tCLK-HP
Set-Up Time Repeated START
Condition
V
3
(3)
tCLK-LP
tSU
6.5
50
ns
Limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Each LED pin should not exceed 25 mA and the package should not exceed a total of 200 mA.
Guaranteed by design.
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Typical Performance Characteristics
Frequency vs. Temp
(TA = −40°C to +85°C),
VDD = 2.3V to 3.0V
PERCENT VARIATION (%)
10
5
0
-5
-10
-40
-20
0
20
40
60
80
TEMPERATURE (°)
Figure 3.
6
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APPLICATION INFORMATION
Theory of Operation
The LP3944 takes incoming data and feed them into several registers that control the frequency and the duty
cycle of the LEDs. Two prescaler registers and two PWM registers provide two individual rates to dim or blink the
LEDs (for more information on these registers, refer to Table 1). The baseband controller/microprocessor can
program each LED to be in one of four states—on, off, DIM0 rate or DIM1 rate. One read-only registers provide
status on all 8 LEDs. The LP3944 can be used to drive RGB LEDs and/or single-color LEDs to create a colorful,
entertaining, and informative setting. This is particularly suitable for accessory functions in cellular phones and
toys. Any LED pins not used to drive LED can be used for General Purpose Parallel Input/Output (GPIO)
expansion.
The LP3944 is equipped with Power-On Reset that holds the chip in a reset state until VDD reaches VPOR during
power up. Once VPOR is achieved, the LP3944 comes out of reset and initializes itself to the default state.
To bring the LP3944 into reset, hold the RST pin LOW for a period of TW. This will put the chip to its default
state. The LP3944 can only be programmed after RST signal is HIGH again.
I2C Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
Figure 4. I2C Data Validity
I2C Start and Stop Conditions
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
Figure 5. I2C START and STOP Conditions
Transferring Data
Every byte put on the SDA line must be eight bits long with the most significant bit (MSB) being transferred first.
The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by
an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the
9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an
acknowledge after each byte has been received.
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After the START condition, a chip address is sent by the I2C master. This address is seven bits long followed by
an eighth bit which is a data direction bit (R/W). The LP3944 hardwires bits 7 to 4 and leaves bits 3 to 1
selectable, as shown in Figure 6. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The
LP3944 supports only a WRITE during chip addressing. The second byte selects the register to which the data
will be written. The third byte contains data to write to the selected register.
Figure 6. Chip Address Byte
ack from slave
msb Chip Address lsb w ack
start
ack from slave
msb Register Add lsb
ack from slave
msb
ack
DATA
lsb
ack
stop
SCL
SDA
start
id = h'xx
w ack
addr = h'02
address h'02
data
ack
ack stop
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
xx = 60 to 67
Figure 7. LP3944 Register Write
However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as
shown in Figure 8.
ack from slave
start
msb Chip Address lsb
w ack
ack from slave
msb Register Add lsb
repeated start
ack
rs
ac
k
r
s
ack from slave
msb Chip Address lsb
r
ack
r
ac
k
data from slave
msb
DATA
lsb
ack from master
ack stop
SC
L
SD
A
star
t
id = h'xx
w
ac
k
addr =
h'00
id = h'xx
address h'00
data
ac
k
sto
p
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
xx = 60 to 67
Figure 8. LP3944 Register Read
Auto Increment
Auto increment is a special feature supported by the LP3944 to eliminate repeated chip and register addressing
when data are to be written to or read from registers in sequential order. The auto increment bit is inside the
register address byte, as shown in Figure 9. Auto increment is enabled when this bit is programmed to “1” and
disabled when it is programmed to “0”.
8
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Figure 9. Register Address Byte
In the READ mode, when auto increment is enabled, I2C master could receive any number of bytes from LP3944
without selecting chip address and register address again. Every time the I2C master reads a register, the
LP3944 will increment the register address and the next data register will be read. When I2C master reaches the
last register (09H register), the register address will roll over to 00H.
In the WRITE mode, when auto increment is enabled, the LP3944 will increment the register address every time
I2C master writes to register. When the last register (09H register) is reached, the register address will roll over to
02H, because the first two registers in LP3944 are read-only registers. It is possible to write to these two
registers, and the LP3944 will acknowledge, but the data will be ignored.
In the LP3944, registers 0x01, 0x08 and 0x09 are not functional. However, it is still necessary to read from 0x01
and to write to 0x08 and 0x09 in Auto Increment mode. They cannot be skipped.
If auto increment is disabled, and the I2C master does not change register address, it will continue to write data
into the same register.
Figure 10. Programming with Auto Increment Disabled (in WRITE Mode)
Figure 11. Programming with Auto Increment Enabled (in WRITE Mode)
Table 1. LP3944 Register Table
Address (Hex)
Register Name
Read/Write
Register Function
0x00
Input 1
Read Only
LED0–7 Input Register
0x01
Register 1
Read Only
None
0x02
PSC0
R/W
Frequency Prescaler 0
0x03
PWM0
R/W
PWM Register 0
0x04
PSC1
R/W
Frequency Prescaler 1
0x05
PWM1
R/W
PWM Register 1
0x06
LS0
R/W
LED0–3 Selector
0x07
LS1
R/W
LED4–7 Selector
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Table 1. LP3944 Register Table (continued)
Address (Hex)
Register Name
Read/Write
Register Function
0x08
Register 8
R/W
None
0x09
Register 9
R/W
None
Binary Fomat for Input Registers (Read Only)—Address 0x00 and 0x01
Table 2. Address 0x00
Bit #
7
6
5
4
3
2
1
0
Default value
X
X
X
X
X
X
X
X
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
Binary Format for Frequency Prescaler and PWM Registers — Address 0x02 to 0x05
Table 3. Address 0x02 (PSC0)
Bit #
7
6
5
4
3
2
1
0
Default value
0
0
0
0
0
0
0
0
Table 4. Address 0x03 (PWM0)
Bit #
7
6
5
4
3
2
1
0
Default value
1
0
0
0
0
0
0
0
Table 5. Address 0x04 (PSC1)
Bit #
7
6
5
4
3
2
1
0
Default value
0
0
0
0
0
0
0
0
Table 6. Address 0x05 (PWM1)
Bit #
7
6
5
4
3
2
1
0
Default value
1
0
0
0
0
0
0
0
0
Binary Format for Selector Registers — Address 0x06 to 0x07
Table 7. Address 0x06 (LS0)
Bit #
7
6
5
4
3
2
1
Default value
0
0
0
0
0
0
0
0
B1
B0
B1
B0
B1
B0
B1
B0
LED3
LED2
LED1
LED0
Table 8. Address 0x07 (LS1)
Bit #
7
6
5
4
3
2
1
Default value
0
0
0
0
0
0
0
0
B1
B0
B1
B0
B1
B0
B1
B0
LED7
LED6
LED5
0
LED4
Table 9. LED States With Respect To Values in "B1" and "B0"
10
B1
B0
0
0
Output Hi-Z
(LED off)
0
1
Output LOW
(LED on)
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Table 9. LED States With Respect To Values in "B1" and "B0" (continued)
B1
B0
1
0
Output dims
(DIM0 rate)
Function
1
1
Output dims
(DIM1 rate)
Programming Example:
Dim LEDs 0 to 7 at 1 Hz at 25% duty cycle
1. Set PSC0 to achieve DIM0 of 1s
2. Set PWM0 duty cycle to 25%
3. Set PSC1 to achieve DIM1 of 0.2s
4. Set LEDs 0 to 7 to point to DIM0
Register Name
Set to (Hex)
1
Step
Set DIM0 = 1s
1 = (PSC0 + 1)/160
PSC0 = 159
Description
PSC0
0x09F
2
Set duty cycle to 25%
Duty Cycle = PWM0/256
PWM0 = 64
PWM0
0x40
3
Set DIM1 = 0.2s
0.2 = (PSC1 + 1)/160
PSC1 = 31
PSC1
0x1F
4
LEDs 0 to 7
Output = DIM0
LS0, LS1
LS0 = 0xAA
LS1 = 0xAA
Reducing IQ When LEDS are Off
In many applications, the LEDs and the LP3944 share the same VDD, as shown in Typical Application Circuit.
When the LEDs are off, the LED pins are at a lower potential than VDD, causing extra supply current (ΔIQ). To
minimize this current, consider keeping the LED pins at a voltage equal to or greater than VDD.
Figure 12. Methods to Reduce IQ When LEDs Are Off
VOUT
VDD
LED 7
2.2 PF
VIN
LM2750-5.0
2.7V to 5.5V
2.2 PF
CAP+
CFLY
1 PF
LP3944
CAPLED 0
Figure 13. Application Circuit
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PACKAGE OPTION ADDENDUM
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9-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LP3944ISQ
ACTIVE
WQFN
RTW
24
1000
TBD
Call TI
Call TI
-40 to 85
3944SQ
LP3944ISQ/NOPB
ACTIVE
WQFN
RTW
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
3944SQ
LP3944ISQX
ACTIVE
WQFN
RTW
24
4500
TBD
Call TI
Call TI
-40 to 85
3944SQ
LP3944ISQX/NOPB
ACTIVE
WQFN
RTW
24
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
3944SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP3944ISQ
WQFN
RTW
24
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP3944ISQ/NOPB
WQFN
RTW
24
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP3944ISQX
WQFN
RTW
24
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP3944ISQX/NOPB
WQFN
RTW
24
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3944ISQ
WQFN
RTW
24
1000
203.0
190.0
41.0
LP3944ISQ/NOPB
WQFN
RTW
24
1000
203.0
190.0
41.0
LP3944ISQX
WQFN
RTW
24
4500
358.0
343.0
63.0
LP3944ISQX/NOPB
WQFN
RTW
24
4500
358.0
343.0
63.0
Pack Materials-Page 2
MECHANICAL DATA
RTW0024A
SQA24A (Rev B)
www.ti.com
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