NXP MK12DX128VLH5 K12 sub-family Datasheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: K12P64M50SF4
Rev. 4, 08/2013
K12P64M50SF4
K12 Sub-Family
Supports the following:
MK12DX128VLH5, MK12DX256VLH5,
MK12DN512VLH5
Features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 50 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
• Memories and memory interfaces
– Up to 512 KB of program flash for devices without
FlexNVM.
– Up to 256 KB program flash for devices with
FlexNVM.
– 64 KB FlexNVM on FlexMemory devices
– 4 KB FlexRAM on FlexMemory devices
– Up to 64 KB RAM
– Serial programming interface (EzPort)
• Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– 16-channel DMA controller, supporting up to 63
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per chip
• Human-machine interface
– General-purpose input/output
• Analog modules
– 16-bit SAR ADC
– 12-bit DAC
– Two analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
• Timers
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel general purpose timers, one with
quadrature decoder functionality
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
• Communication interfaces
– USB Device Charger detect
– SPI module
– Two I2C modules
– Four UART modules
– I2S module
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012–2013 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................3
5.4 Thermal specifications.......................................................20
1.1 Determining valid orderable parts......................................3
5.4.1
Thermal operating requirements...........................21
2 Part identification......................................................................3
5.4.2
Thermal attributes.................................................21
2.1 Description.........................................................................3
6 Peripheral operating requirements and behaviors....................22
2.2 Format...............................................................................3
6.1 Core modules....................................................................22
2.3 Fields.................................................................................3
6.1.1
JTAG electricals....................................................22
2.4 Example............................................................................4
6.2 System modules................................................................25
2.5 Small package marking.....................................................4
6.3 Clock modules...................................................................25
3 Terminology and guidelines......................................................5
6.3.1
MCG specifications...............................................25
3.1 Definition: Operating requirement......................................5
6.3.2
Oscillator electrical specifications.........................27
3.2 Definition: Operating behavior...........................................5
6.3.3
32 kHz oscillator electrical characteristics.............29
3.3 Definition: Attribute............................................................6
6.4 Memories and memory interfaces.....................................30
3.4 Definition: Rating...............................................................6
6.4.1
Flash electrical specifications................................30
3.5 Result of exceeding a rating..............................................7
6.4.2
EzPort switching specifications.............................33
3.6 Relationship between ratings and operating
requirements......................................................................7
6.5 Security and integrity modules..........................................34
6.6 Analog...............................................................................34
3.7 Guidelines for ratings and operating requirements............8
6.6.1
ADC electrical specifications.................................34
3.8 Definition: Typical value.....................................................8
6.6.2
CMP and 6-bit DAC electrical specifications.........38
3.9 Typical value conditions....................................................9
6.6.3
12-bit DAC electrical characteristics.....................41
4 Ratings......................................................................................9
6.6.4
Voltage reference electrical specifications............44
4.1 Thermal handling ratings...................................................9
6.7 Timers................................................................................45
4.2 Moisture handling ratings..................................................10
6.8 Communication interfaces.................................................45
4.3 ESD handling ratings.........................................................10
6.8.1
4.4 Voltage and current operating ratings...............................10
DSPI switching specifications (limited voltage
range)....................................................................45
5 General.....................................................................................10
6.8.2
DSPI switching specifications (full voltage range).47
5.1 AC electrical characteristics..............................................11
6.8.3
I2C switching specifications..................................49
5.2 Nonswitching electrical specifications...............................11
6.8.4
UART switching specifications..............................49
6.8.5
Normal Run, Wait and Stop mode performance
5.2.1
Voltage and current operating requirements.........11
5.2.2
LVD and POR operating requirements.................12
5.2.3
Voltage and current operating behaviors..............13
5.2.4
Power mode transition operating behaviors..........13
over the full operating voltage range.....................51
5.2.5
Power consumption operating behaviors..............14
7 Dimensions...............................................................................53
5.2.6
EMC radiated emissions operating behaviors.......18
7.1 Obtaining package dimensions.........................................53
5.2.7
Designing with radiated emissions in mind...........19
8 Pinout........................................................................................53
5.2.8
Capacitance attributes..........................................19
8.1 K12 Signal Multiplexing and Pin Assignments..................53
5.3 Switching specifications.....................................................19
8.2 K12 Pinouts.......................................................................56
5.3.1
Device clock specifications...................................19
5.3.2
General switching specifications...........................20
over the full operating voltage range.....................49
6.8.6
VLPR, VLPW, and VLPS mode performance
9 Revision History........................................................................57
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
2
Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK12 and MK12 .
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K12
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
3
Part identification
Field
Description
Values
FFF
Program flash memory size
•
•
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
•
•
•
•
•
•
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK12DN512VLH5
2.5 Small package marking
In an effort to save space, small package devices use special marking on the chip. These
markings have the following format:
Q ## C F T PP
This table lists the possible values for each field in the part number for small packages
(not all combinations are valid):
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
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Freescale Semiconductor, Inc.
Terminology and guidelines
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
C
Speed
• G = 50 MHz
F
Flash memory configuration
• G = 128 KB + Flex
• H = 256 KB + Flex
• 9 = 512 KB
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
• MC = 121 MAPBGA
This tables lists some examples of small package marking along with the original part
numbers:
Original part number
Alternate part number
MK12DX256VLF5
M12GHVLF
MK12DN512VLH5
M12G9VLH
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
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Freescale Semiconductor, Inc.
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
Min.
1.0 V core supply
voltage
Max.
–0.3
Unit
1.2
V
3.5 Result of exceeding a rating
40
Failures in time (ppm)
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
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Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
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Expected permanent failure
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Handling (power off)
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K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
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Freescale Semiconductor, Inc.
Ratings
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
9
General
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
155
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
VAIO
Analog1, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Maximum current single pin limit (applies to all digital pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
ID
VDDA
VREGIN
VBAT
Analog supply voltage
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
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Freescale Semiconductor, Inc.
General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
VBAT
VIH
VIL
RTC battery supply voltage
Notes
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
1
mA
-3
—
—
+3
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
11
General
Table 1. Voltage and current operating requirements (continued)
Symbol
IICcont
Description
Min.
Max.
Unit
-25
—
mA
—
+25
1.2
—
V
VPOR_VBAT
—
V
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
VRAM
VRFVBAT
VDD voltage required to retain RAM
VBAT voltage required to retain the VBAT register file
Notes
1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
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Freescale Semiconductor, Inc.
General
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = - 9 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
VDD – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
0.5
V
—
100
mA
• @ full temperature range
—
1.0
μA
• @ 25 °C
—
0.1
μA
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
1
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
IOZ
Total Hi-Z (off-state) leakage current (all input pins)
—
4
μA
RPU
Internal pullup resistors
22
50
kΩ
2
RPD
Internal pulldown resistors
22
50
kΩ
3
1. Tested by ganged leakage method
2. Measured at Vinput = VSS
3. Measured at Vinput = VDD
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
13
General
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
CPU and system clocks = 50 MHz
Bus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
Max.
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• 1.71 V/(VDD slew rate) ≤ 300 μs
• 1.71 V/(VDD slew rate) > 300 μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
Unit
Notes
μs
1
—
300
—
1.7 V / (VDD
slew rate)
—
135
μs
—
135
μs
—
85
μs
—
85
μs
—
6
μs
—
5.2
μs
—
5.2
μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8 V
• @ 3.0 V
2
—
12.98
14
mA
—
12.93
13.8
mA
Table continues on the next page...
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Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8 V
Typ.
Max.
Unit
Notes
3, 4
—
17.04
19.3
mA
—
17.01
18.9
mA
—
19.8
21.3
mA
• @ 3.0 V
• @ 25°C
• @ 125°C
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
7.95
9.5
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
—
5.88
7.4
mA
5
IDD_STOP
Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
320
436
360
489
410
620
610
1100
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
754
—
μA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
1.1
—
mA
7
IDD_VLPW
Very-low-power wait mode current at 3.0 V
—
437
—
μA
8
IDD_VLPS
Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
7.33
24.2
14
32
28
48
110
280
3.14
4.8
6.48
28.3
13.85
44.6
55.53
71.3
2.19
3.4
4.35
4.35
8.92
24.6
35.33
45.3
1.77
3.1
2.81
13.8
5.20
22.3
19.88
34.2
IDD_LLS
IDD_VLLS3
Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
Very low-leakage stop mode 3 current at 3.0 V
•
•
•
•
IDD_VLLS2
—
—
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C
Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
μA
μA
μA
μA
μA
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
15
General
Table 6. Power consumption operating behaviors (continued)
Symbol
IDD_VLLS1
IDD_VLLS0
IDD_VLLS0
IDD_VBAT
Description
Min.
Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
Average current when CPU is not accessing RTC
registers at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
Typ.
Max.
1.03
1.8
1.92
7.5
4.03
15.9
17.43
28.7
0.543
1.1
1.36
7.58
3.39
14.3
16.52
24.1
0.359
0.95
1.03
6.8
2.87
15.4
15.20
25.3
0.91
1.1
1.1
1.35
1.5
1.85
4.3
5.7
Unit
Notes
μA
μA
μA
μA
9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
3. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, and peripherals are in active operation.
4. Max values are measured with CPU executing DSP instructions
5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz flash clock. MCG configured for FEI mode.
6. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash.
7. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled
but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
9. Includes 32 kHz oscillator current and RTC operation.
5.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
•
MCG in FBE mode
USB regulator disabled
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFL
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
16
Freescale Semiconductor, Inc.
General
Figure 2. Run mode supply current vs. core frequency
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
17
General
Figure 3. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors 1
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
19
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
21
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
19
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
11
dBμV
IEC level
0.15–1000
L
—
VRE_IEC
3, 4
1. This data was collected on a MK20DN128VLH5 64pin LQFP device.
2. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
18
Freescale Semiconductor, Inc.
General
3. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 48 MHz, fBUS = 48MHz
4. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
50
MHz
fBUS
Bus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
VLPR mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
LPTMR external reference clock
—
16
MHz
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
fLPTMR_pin
fLPTMR_ERCLK
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
19
General
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
Port rise and fall time (high drive strength)
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
13
ns
• 2.7 ≤ VDD ≤ 3.6V
—
7
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
Port rise and fall time (low drive strength)
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
20
Freescale Semiconductor, Inc.
General
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
5.4.2 Thermal attributes
Board type
Symbol
Description
Single-layer (1s)
RθJA
Four-layer (2s2p)
Unit
Notes
Thermal
65
resistance, junction
to ambient (natural
convection)
°C/W
1, 2
RθJA
Thermal
46
resistance, junction
to ambient (natural
convection)
°C/W
1, 3
Single-layer (1s)
RθJMA
Thermal
53
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,3
Four-layer (2s2p)
RθJMA
Thermal
40
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,3
—
RθJB
Thermal
28
resistance, junction
to board
°C/W
4
—
RθJC
Thermal
15
resistance, junction
to case
°C/W
5
—
ΨJT
Thermal
3
characterization
parameter, junction
to package top
outside center
(natural
convection)
°C/W
6
1.
2.
64 LQFP
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the
JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
3.
4.
5.
6.
Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 JTAG electricals
Table 12. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 4. Test clock input timing
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 5. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 6. Test Access Port timing
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 7. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 14. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
31.25
—
39.0625
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
Notes
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±2
%fdco
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
±1
%fdco
1, 2
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
48.0
—
100
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
8
8
9
• fvco = 48 MHz
—
120
—
ps
• fvco = 100 MHz
—
50
—
ps
PLL accumulated jitter over 1µs (RMS)
9
• fvco = 48 MHz
—
1350
—
ps
• fvco = 100 MHz
—
600
—
ps
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
tpll_lock
Description
Lock detector detection time
Min.
Typ.
Max.
Unit
Notes
—
—
150 × 10-6
+ 1075(1/
fpll_ref)
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
6.3.2.1
Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
IDDOSC
Supply current — high-gain mode (HGO=1)
Typ.
Max.
Unit
Notes
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Vpp5
1.
2.
3.
4.
5.
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.3.2.2
Symbol
Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that—it remains within the limits of
DCO input clock frequency when divided by FRDIV.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between oscillator being enabled and OSCINIT bit in the MCG_S register being
set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz oscillator electrical characteristics
6.3.3.1
32 kHz oscillator DC electrical specifications
Table 17. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Parasitical capacitance of EXTAL32 and XTAL32
—
5
7
pF
RF
Cpara
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
Table 17. 32kHz oscillator DC electrical specifications (continued)
Symbol
Vpp1
Description
Peak-to-peak amplitude of oscillation
Min.
Typ.
Max.
Unit
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2
Symbol
fosc_lo
tstart
32 kHz oscillator frequency specifications
Table 18. 32 kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
1
700
—
VBAT
mV
2, 3
vec_extal32 Externally provided input clock amplitude
Notes
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 19. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm4
thversscr
Longword Program high-voltage time
—
7.5
18
μs
Sector Erase high-voltage time
—
13
113
ms
1
—
104
904
ms
1
thversblk256k Erase Block high-voltage time for 256 KB
Notes
1. Maximum time based on expectations at cycling end-of-life.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.1.2
Symbol
Flash timing specifications — commands
Table 20. Flash command timing specifications
Description
Min.
Typ.
Max.
Unit
Notes
Read 1s Block execution time
trd1blk64k
• 64 KB data flash
—
—
0.9
ms
trd1blk256k
• 256 KB program flash
—
—
1.7
ms
trd1sec2k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
Erase Flash Block execution time
2
tersblk64k
• 64 KB data flash
—
58
580
ms
tersblk256k
• 256 KB program flash
—
122
985
ms
—
14
114
ms
tersscr
Erase Flash Sector execution time
2
Program Section execution time
tpgmsec512
• 512 bytes flash
—
2.4
—
ms
tpgmsec1k
• 1 KB flash
—
4.7
—
ms
tpgmsec2k
• 2 KB flash
—
9.3
—
ms
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
trdonce
Read Once execution time
—
—
25
μs
tpgmonce
1
Program Once execution time
—
65
—
μs
tersall
Erase All Blocks execution time
—
250
2000
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
Swap Control execution time
tswapx01
• control code 0x01
—
200
—
μs
tswapx02
• control code 0x02
—
70
150
μs
tswapx04
• control code 0x04
—
70
150
μs
tswapx08
• control code 0x08
—
—
30
μs
—
138
—
ms
• Control Code 0xFF
—
70
—
μs
tsetram32k
• 32 KB EEPROM backup
—
0.8
1.2
ms
tsetram64k
• 64 KB EEPROM backup
—
1.3
1.9
ms
260
μs
Program Partition for EEPROM execution time
tpgmpart64k
• 64 KB FlexNVM
Set FlexRAM Function execution time:
tsetramff
Byte-write to FlexRAM for EEPROM operation
teewr8bers
Byte-write to erased FlexRAM location execution
time
—
175
3
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 20. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
385
1800
μs
475
2000
μs
Notes
Byte-write to FlexRAM execution time:
teewr8b32k
• 32 KB EEPROM backup
teewr8b64k
• 64 KB EEPROM backup
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
260
μs
Word-write to FlexRAM execution time:
teewr16b32k
• 32 KB EEPROM backup
—
385
1800
μs
teewr16b64k
• 64 KB EEPROM backup
—
475
2000
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
540
μs
Longword-write to FlexRAM execution time:
teewr32b32k
• 32 KB EEPROM backup
—
630
2050
μs
teewr32b64k
• 64 KB EEPROM backup
—
810
2250
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3
Flash high voltage current behaviors
Table 21. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
6.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 22. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
50
—
years
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
5
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 22. NVM reliability specifications (continued)
Symbol
Description
tnvmretd1k
Data retention after up to 1 K cycles
nnvmcycd
Cycling endurance
Min.
Typ.1
Max.
Unit
20
100
—
years
10 K
50 K
—
cycles
Notes
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
tnvmretee10 Data retention up to 10% of write endurance
20
100
—
years
Write endurance
3
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
35 K
175 K
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
315 K
1.6 M
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
1.27 M
6.4 M
—
writes
nnvmwree4k
• EEPROM backup to FlexRAM ratio = 4096
10 M
50 M
—
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ °C.
3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ °C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
6.4.2 EzPort switching specifications
Table 23. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
ns
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 8. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 24 and Table 25 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1
16-bit ADC operating conditions
Table 24. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
Notes
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC operating conditions (continued)
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 *
VREFH
V
• All other modes
VREFL
—
• 16-bit mode
—
8
10
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
CADIN
RADIN
RAS
Input capacitance
Input resistance
Notes
VREFH
pF
kΩ
Analog source
resistance
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
18.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
3
5
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
5
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
ADC SAR
ENGINE
R ADIN
V ADIN
C AS
V AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 9. ADC input impedance equivalency diagram
6.6.1.2
16-bit ADC electrical characteristics
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
DNL
INL
EFS
Conditions1.
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
LSB4
VADIN =
VDDA
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12-bit modes
—
±0.7
-1.1 to +1.9
Integral nonlinearity
Full-scale error
-0.3 to 0.5
• <12-bit modes
—
±0.2
• 12-bit modes
—
±1.0
-2.7 to +1.9
-0.7 to +0.5
• <12-bit modes
—
±0.5
• 12-bit modes
—
-4
-5.4
• <12-bit modes
—
-1.4
-1.8
5
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
Description
EQ
Quantization
error
ENOB
Conditions1.
Min.
Typ.2
Max.
Unit
• 16-bit modes
—
-1 to 0
—
LSB4
• ≤13-bit modes
—
—
±0.5
Effective number 16-bit differential mode
of bits
• Avg = 32
• Avg = 4
Notes
6
12.8
14.5
—
bits
11.9
13.8
—
bits
12.2
13.9
—
bits
11.4
13.1
—
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
SINAD
THD
Signal-to-noise
plus distortion
See ENOB
Total harmonic
distortion
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
dB
7
—
–94
—
dB
—
-85
—
dB
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
EIL
6.02 × ENOB + 1.76
7
82
95
—
dB
78
90
—
dB
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
VTEMP25
Temp sensor
slope
Across the full temperature
range of the device
1.55
1.62
1.69
mV/°C
8
Temp sensor
voltage
25 °C
706
716
726
mV
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
8. ADC conversion clock < 3 MHz
Figure 10. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Figure 11. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.2 CMP and 6-bit DAC electrical specifications
Table 26. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
—
—
40
μs
6-bit DAC current adder (enabled)
—
7
—
μA
IDAC6b
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
0.08
0.07
0.06
HYSTCTR
Setting
CM P Hystereris (V)
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP
P Hystereris (V)
0.12
HYSTCTR
Setting
0.1
00
01
0
08
0.08
10
11
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
Vin level (V)
1.9
2.2
2.5
2.8
3.1
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1
Symbol
12-bit DAC operating requirements
Table 27. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
TA
Temperature
Operating temperature
range of the device
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1
°C
2
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
6.6.3.2
Symbol
12-bit DAC operating behaviors
Table 28. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
330
μA
—
—
1200
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
—
0.7
1
μs
1
—
—
100
mV
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance (load = 3 kΩ)
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
VOFFSET Offset error
EG
PSRR
1.
2.
3.
4.
5.
6.
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
CT
Channel to channel cross talk
BW
3dB bandwidth
6
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 14. Typical INL error vs. digital code
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Figure 15. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 29. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
TA
Temperature
CL
Output load capacitance
Operating temperature
range of the device
°C
100
nF
Notes
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
44
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 30. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915
1.195
1.1977
V
1
Vout
Voltage reference output — factory trim
1.1584
—
1.2376
V
1
Vout
Voltage reference output — user trim
1.193
—
1.197
V
1
Vstep
Voltage reference trim step
—
0.5
—
mV
1
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
80
mV
1
Bandgap only current
—
—
80
µA
1
µV
1, 2
Ibg
ΔVLOAD
Load regulation
• current = ± 1.0 mA
—
200
—
Tstup
Buffer startup time
—
—
100
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 31. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
50
°C
Notes
Table 32. VREF limited-range operating behaviors
Symbol
Vout
Description
Voltage reference output with factory trim
Min.
Max.
Unit
1.173
1.225
V
Notes
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
45
Peripheral operating requirements and behaviors
6.8.1 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 33. Master mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
2.7
3.6
V
Notes
—
25
MHz
2 x tBUS
—
ns
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
DS1
DSPI_SCK output cycle time
DS2
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS8
DS7
(CPOL=0)
DSPI_SIN
Data
First data
Last data
DS5
DSPI_SOUT
First data
DS6
Data
Last data
Figure 16. DSPI classic SPI timing — master mode
Table 34. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
12.5
MHz
—
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
4 x tBUS
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
46
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 34. Slave mode DSPI timing (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DS12
DSPI_SOUT
First data
DS13
DS16
DS11
Last data
Data
DS14
DSPI_SIN
First data
Data
Last data
Figure 17. DSPI classic SPI timing — slave mode
6.8.2 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 35. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
12.5
MHz
4 x tBUS
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
Table 35. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
Notes
(tBUS x 2) −
4
—
ns
3
—
10
ns
DS4
DSPI_SCK to DSPI_PCSn invalid delay
DS5
DSPI_SCK to DSPI_SOUT valid
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
20.5
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS8
DS7
(CPOL=0)
DSPI_SIN
Data
First data
Last data
DS5
DSPI_SOUT
First data
DS6
Data
Last data
Figure 18. DSPI classic SPI timing — master mode
Table 36. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
6.25
MHz
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
19
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
19
ns
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DS12
DSPI_SOUT
First data
DS13
DS16
DS11
Last data
Data
DS14
DSPI_SIN
First data
Data
Last data
Figure 19. DSPI classic SPI timing — slave mode
6.8.3 I2C switching specifications
See General switching specifications.
6.8.4 UART switching specifications
See General switching specifications.
6.8.5 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 37. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
49
Peripheral operating requirements and behaviors
Table 37. I2S/SAI master mode timing (continued)
Num.
Characteristic
Min.
Max.
Unit
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 20. I2S/SAI timing — master modes
Table 38. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
29
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
10
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1
—
21
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 21. I2S/SAI timing — slave modes
6.8.6 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 39. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
75
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
51
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 22. I2S/SAI timing — master modes
Table 40. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
87
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
52
Freescale Semiconductor, Inc.
Dimensions
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 23. I2S/SAI timing — slave modes
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
64-pin LQFP
Then use this document number
98ASS23234W
8 Pinout
8.1 K12 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
• The analog input signals ADC0_SE10, ADC0_SE11,
ADC0_DP1, and ADC0_DM1 are available only for K11,
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
53
Pinout
•
•
•
•
•
64
LQFP
K12, K21, and K22 devices and are not present on K10 and
K20 devices.
The TRACE signals on PTE0, PTE1, PTE2, PTE3, and
PTE4 are available only for K11, K12, K21, and K22
devices and are not present on K10 and K20 devices.
If the VBAT pin is not used, the VBAT pin should be left
floating. Do not connect VBAT pin to VSS.
The FTM_CLKIN signals on PTB16 and PTB17 are
available only for K11, K12, K21, and K22 devices and is
not present on K10 and K20 devices. For K22D devices
this signal is on ALT4, and for K22F devices, this signal is
on ALT7.
The FTM0_CH2 signal on PTC5/LLWU_P9 is available
only for K11, K12, K21, and K22 devices and is not
present on K10 and K20 devices.
The I2C0_SCL signal on PTD2/LLWU_P13 and
I2C0_SDA signal on PTD3 are available only for K11,
K12, K21, and K22 devices and are not present on K10 and
K20 devices.
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
1
ADC0_SE10
ADC0_SE10
PTE0
UART1_TX
TRACE_CLKOUT I2C1_SDA
2
ADC0_SE11
ADC0_SE11
PTE1/
LLWU_P0
UART1_RX
TRACE_D3
3
VDD
VDD
4
VSS
VSS
5
ADC0_SE4a
ADC0_SE4a
PTE16
SPI0_PCS0
UART2_TX
FTM_CLKIN0
FTM0_FLT3
6
ADC0_SE5a
ADC0_SE5a
PTE17
SPI0_SCK
UART2_RX
FTM_CLKIN1
LPTMR0_ALT3
7
ADC0_SE6a
ADC0_SE6a
PTE18
SPI0_SOUT
UART2_CTS_b
I2C0_SDA
8
ADC0_SE7a
ADC0_SE7a
PTE19
SPI0_SIN
UART2_RTS_b
I2C0_SCL
9
ADC0_DP0
ADC0_DP0
10
ADC0_DM0
ADC0_DM0
11
ADC0_DP3
ADC0_DP3
12
ADC0_DM3
ADC0_DM3
13
VDDA
VDDA
14
VREFH
VREFH
15
VREFL
VREFL
16
VSSA
VSSA
17
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
ALT7
EzPort
RTC_CLKOUT
I2C1_SCL
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
54
Freescale Semiconductor, Inc.
Pinout
64
LQFP
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
18
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
19
XTAL32
XTAL32
20
EXTAL32
EXTAL32
21
VBAT
VBAT
22
JTAG_TCLK/
SWD_CLK/
EZP_CLK
PTA0
UART0_CTS_b/
UART0_COL_b
FTM0_CH5
JTAG_TCLK/
SWD_CLK
EZP_CLK
23
JTAG_TDI/
EZP_DI
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
24
JTAG_TDO/
TRACE_SWO/
EZP_DO
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/
TRACE_SWO
EZP_DO
25
JTAG_TMS/
SWD_DIO
PTA3
UART0_RTS_b
FTM0_CH0
JTAG_TMS/
SWD_DIO
26
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1
NMI_b
27
DISABLED
PTA5
FTM0_CH2
I2S0_TX_BCLK
JTAG_TRST_b
28
DISABLED
PTA12
FTM1_CH0
I2S0_TXD0
FTM1_QD_PHA
29
DISABLED
PTA13/
LLWU_P4
FTM1_CH1
I2S0_TX_FS
FTM1_QD_PHB
30
VDD
VDD
31
VSS
VSS
32
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
33
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
34
RESET_b
RESET_b
35
ADC0_SE8
ADC0_SE8
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_PHA
36
ADC0_SE9
ADC0_SE9
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_PHB
37
ADC0_SE12
ADC0_SE12
PTB2
I2C0_SCL
UART0_RTS_b
FTM0_FLT3
38
ADC0_SE13
ADC0_SE13
PTB3
I2C0_SDA
UART0_CTS_b/
UART0_COL_b
FTM0_FLT0
39
DISABLED
PTB16
UART0_RX
EWM_IN
FTM_CLKIN0
40
DISABLED
PTB17
UART0_TX
EWM_OUT_b
FTM_CLKIN1
41
DISABLED
PTB18
FTM2_CH0
I2S0_TX_BCLK
42
DISABLED
PTB19
FTM2_CH1
I2S0_TX_FS
43
ADC0_SE14
ADC0_SE14
PTC0
SPI0_PCS4
PDB0_EXTRG
44
ADC0_SE15
ADC0_SE15
PTC1/
LLWU_P6
SPI0_PCS3
UART1_RTS_b
FTM0_CH0
I2S0_TXD0
45
ADC0_SE4b/
CMP1_IN0
ADC0_SE4b/
CMP1_IN0
PTC2
SPI0_PCS2
UART1_CTS_b
FTM0_CH1
I2S0_TX_FS
46
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
47
VSS
VSS
EZP_CS_b
LPTMR0_ALT1
I2S0_TXD1
CLKOUT
I2S0_TX_BCLK
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
55
Pinout
64
LQFP
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
48
VDD
49
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
CMP1_OUT
50
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_ALT2
I2S0_RXD0
CMP0_OUT
51
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_EXTRG
I2S0_RX_BCLK
I2S0_MCLK
52
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
53
CMP0_IN2
CMP0_IN2
PTC8
I2S0_MCLK
54
CMP0_IN3
CMP0_IN3
PTC9
I2S0_RX_BCLK
55
DISABLED
PTC10
I2C1_SCL
I2S0_RX_FS
56
DISABLED
PTC11/
LLWU_P11
I2C1_SDA
I2S0_RXD1
57
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0
UART2_RTS_b
58
ADC0_SE5b
PTD1
SPI0_SCK
UART2_CTS_b
59
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
I2C0_SCL
60
DISABLED
PTD3
SPI0_SIN
UART2_TX
I2C0_SDA
61
ADC0_SE21
ADC0_SE21
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_b
FTM0_CH4
EWM_IN
62
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_CTS_b/
UART0_COL_b
FTM0_CH5
EWM_OUT_b
63
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FTM0_FLT0
64
ADC0_SE22
ADC0_SE22
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
FTM0_FLT1
ALT7
EzPort
VDD
ADC0_SE5b
FTM0_CH2
I2S0_RX_FS
FTM2_FLT0
8.2 K12 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
56
Freescale Semiconductor, Inc.
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC11/LLWU_P11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Revision History
ADC0_DP0
9
40
PTB17
ADC0_DM0
10
39
PTB16
ADC0_DP3
11
38
PTB3
ADC0_DM3
12
37
PTB2
VDDA
13
36
PTB1
VREFH
14
35
PTB0/LLWU_P5
VREFL
15
34
RESET_b
VSSA
16
33
PTA19
32
PTB18
PTA18
41
31
8
VSS
PTE19
30
PTB19
VDD
42
29
7
PTA13/LLWU_P4
PTE18
28
PTC0
PTA12
43
27
6
PTA5
PTE17
26
PTC1/LLWU_P6
PTA4/LLWU_P3
44
25
5
PTA3
PTE16
24
PTC2
PTA2
45
23
4
PTA1
VSS
22
PTC3/LLWU_P7
PTA0
46
21
3
VBAT
VDD
20
VSS
EXTAL32
47
19
2
XTAL32
PTE1/LLWU_P0
18
VDD
DAC0_OUT/CMP1_IN3/ADC0_SE23
48
17
1
VREF_OUT/CMP1_IN5/CMP0_IN5
PTE0
Figure 24. K12 64 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
57
Revision History
Table 41. Revision History
Rev. No.
Date
Substantial Changes
1
6/2012
Alpha customer release.
1.1
6/2012
In Table 6, "Power consumption operating behaviors", changed the units of IDD_VLLS2,
IDD_VLLS1, IDD_VLLS0, and IDD_VBAT from nA to μA.
2
7/2012
•
•
•
•
•
•
Updated section "Power consumption operating behaviors".
Updated section "Flash timing specifications — program and erase".
Updated section "Flash timing specifications — commands".
Removed the 32K ratio from "Write endurance" in section "Reliability specifications".
Updated IDDstby maximum value in section "VREG electrical specifications".
Added the charts in section "Diagram: Typical IDD_RUN operating behavior".
3
8/2012
•
•
•
•
Updated section "Power consumption operating behaviors".
Updated section "EMC radiated emissions operating behaviors".
Updated section "MCG specifications".
Added applicable notes in section "Signal Multiplexing and Pin Assignments".
4
8/2013
•
•
•
•
Updated section "Power consumption operating behaviors"
Updated section "MCG specifications"
Updated section "16-bit ADC operating conditions"
Added section "Small package marking"
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
58
Freescale Semiconductor, Inc.
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© 2012-2013 Freescale Semiconductor, Inc.
Document Number: K12P64M50SF4
Rev. 4
08/2013