SCES607A − SEPTEMBER 2004 − REVISED APRIL 2008
D
D
D
D
D
D
D
D Latch-Up Performance Exceeds 100 mA
Qualified for Automotive Applications
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Per JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
Ioff Supports Partial-Power-Down Mode
Operation
DBV OR DCK PACKAGE
(TOP VIEW)
description/ordering information
CLK
GND
D
This single D-type flip-flop is designed for 1.65-V to
5.5-V VCC operation.
1
6
2
5
3
4
OE
VCC
Q
The SN74LVC1G374 features a 3-state output
designed specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer registers,
input/output (I/O) ports, bidirectional bus drivers, and
working registers.
On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D)
input.
A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION {
−40°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE}
TA
TOP-SIDE
MARKING§
SOT (SOT-23) − DBV
Reel of 3000
SN74LVC1G374QDBVRQ1
CA40
SOT (SC-70) − DCK
Reel of 3000
SN74LVC1G374QDCKRQ1
D40
† For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see
the TI web site at http://www.ti.com.
}Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§ DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2008, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0 !)) '!!&"&#+
POST OFFICE BOX 655303
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1
SCES607A − SEPTEMBER 2004 − REVISED APRIL 2008
FUNCTION TABLE
INPUTS
D
OUTPUT
Q
OE
CLK
L
↑
L
L
L
↑
H
H
L
H or L
X
Q
H
X
X
Z
logic diagram (positive logic)
OE
CLK
6
1
C1
D
3
D
4
Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES607A − SEPTEMBER 2004 − REVISED APRIL 2008
recommended operating conditions (see Note 4)
Operating
VCC
VIH
Supply voltage
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
1.65
5.5
0.65 × VCC
1.7
V
2
0.7 × VCC
0.35 × VCC
0.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V
VCC = 2.3 V
V
1.5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
Output voltage
UNIT
0.8
V
0.3 × VCC
0
5.5
V
0
VCC
−4
V
−8
−16
IOH
High-level output current
VCC = 3 V
VCC = 4.5 V
VCC = 5 V, TA = −40°C to 85°C
VCC = 1.65 V
VCC = 2.3 V
−24
mA
−32
−40
4
8
16
IOL
∆t/∆v
Low-level output current
Input transition rise or fall rate
VCC = 3 V
24
VCC = 4.5 V
VCC = 5 V, TA = −40°C to 85°C
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
20
VCC = 5 V ± 0.5 V
mA
40
10
ns/V
5
TA
Operating free-air temperature
−40
125
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCES607A − SEPTEMBER 2004 − REVISED APRIL 2008
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100 mA
IOH = −4 mA
VOH
1.65 V to 5.5 V
1.65 V
IOH = −8 mA
IOH = −16 mA
2.3 V
3V
IOH = −24 mA
1.9
2.4
2.4
2.3
2.3
3.8
3.8
IOH = −40 mA
5V
4.4
V
1.65 V to 5.5 V
0.1
0.1
1.65 V
0.45
0.45
2.3 V
0.3
0.3
0.4
0.5
0.55
0.65
0.65
3V
IOL = 24 mA
UNIT
VCC − 0.1
1.2
1.9
4.5 V
IOL = 8 mA
IOL = 16 mA
TA = −405C TO 1255C
MIN
MAX
TYP†
VCC − 0.1
1.2
IOH = −32 mA
IOL = 100 mA
IOL = 4 mA
VOL
TA = −405C TO 855C
MIN
MAX
TYP†
VCC
IOL = 32 mA
4.5 V
0.55
IOL = 40 mA
5V
0.513
V
II
IOZ
VI = 5.5 V or GND
VO = 0 to 5.5 V
0 to 5.5 V
±1
±2
mA
1.65 V to 5.5 V
±5
±12
mA
Ioff
ICC
VI or VO = 5.5 V
VI = 5.5 V or GND, IO = 0
±10
±25
mA
1.65 V to 5.5 V
10
10
mA
∆ICC
One input at VCC − 0.6 V,
Other inputs at VCC or GND
3 V to 5.5 V
500
500
mA
Ci
VI = VCC or GND
0
Co
VO = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
3.3 V
3
3
pF
3.3 V
6
6
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
MIN
4
MAX
VCC = 2.5 V
± 0.2 V
MIN
fclock
tw
Clock frequency
Pulse duration, CLK high or low
3.3
100
3
tsu
th
Setup time, data before CLK↑
3.5
Hold time, data after CLK↑
3.4
POST OFFICE BOX 655303
MAX
VCC = 3.3 V
± 0.3 V
MIN
125
MAX
VCC = 5 V
± 0.5 V
MIN
150
UNIT
MAX
175
MHz
2.8
2.5
ns
2.5
2
1.5
ns
1.6
1.5
1.5
ns
• DALLAS, TEXAS 75265
SCES607A − SEPTEMBER 2004 − REVISED APRIL 2008
switching characteristics over free-air temperature range of −405C to 855C, CL = 30 pF or 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
VCC = 1.8 V
± 0.15 V
MIN
VCC = 2.5 V
± 0.2 V
MAX
100
MIN
MAX
125
VCC = 3.3 V
± 0.3 V
MIN
MAX
150
VCC = 5 V
± 0.5 V
MIN
UNIT
MAX
175
MHz
tpd
CLK
Q
2.7
18.3
1.8
8.2
1.6
6
1
4
ns
ten
OE
Q
2
13
1.5
6.3
0.9
5
0.7
3.5
ns
tdis
OE
Q
2
14
1.1
5.3
1.4
4.5
0.8
3.1
ns
switching characteristics over free-air temperature range of −405C to 1255C, CL = 30 pF or 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
VCC = 1.8 V
± 0.15 V
MIN
VCC = 2.5 V
± 0.2 V
MAX
100
MIN
MAX
125
VCC = 3.3 V
± 0.3 V
MIN
MAX
150
VCC = 5 V
± 0.5 V
MIN
UNIT
MAX
175
MHz
tpd
CLK
Q
2.7
18.3
1.8
10.2
1.6
7
1
5
ns
ten
OE
Q
2
14
1.5
8.3
0.9
6.5
0.7
5.5
ns
tdis
OE
Q
2
16
1.1
7.3
1.4
6
0.8
5.1
ns
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation
capacitance
Outputs enabled
Outputs disabled
f = 10 MHz
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
VCC = 5 V
TYP
24
24
25
27
8
8
9
11
• DALLAS, TEXAS 75265
UNIT
pF
5
SCES607A − SEPTEMBER 2004 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CLVC1G374QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CLVC1G374QDCKRQ1
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G374-Q1 :
• Catalog: SN74LVC1G374
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
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