Low Noise, High Speed Amplifier for 16-Bit Systems AD8021 ADC preamps and drivers Instrumentation preamps Active filters Portable instrumentation Line receivers Precision instruments Ultrasound signal processing High gain circuits GENERAL DESCRIPTION The AD8021 is an exceptionally high performance, high speed voltage feedback amplifier that can be used in 16-bit resolution systems. It is designed to have both low voltage and low current noise (2.1 nV/√Hz typical and 2.1 pA/√Hz typical) while operating at the lowest quiescent supply current (7 mA @ ±5 V) among today’s high speed, low noise op amps. The AD8021 operates over a wide range of supply voltages from ±2.25 V to ±12 V, as well as from single 5 V supplies, making it ideal for high speed, low power instruments. An output disable pin allows further reduction of the quiescent supply current to 1.3 mA. LOGIC 1 REFERENCE AD8021 8 DISABLE –IN 2 7 +VS +IN 3 6 VOUT –VS 4 5 CCOMP Figure 1. SOIC-8 (R-8) and MSOP-8 (RM-8) The AD8021 allows the user to choose the gain bandwidth product that best suits the application. With a single capacitor, the user can compensate the AD8021 for the desired gain with little trade-off in bandwidth. The AD8021 is a well-behaved amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast overload recovery of 50 ns. The AD8021 is stable over temperature with low input offset voltage drift and input bias current drift, 0.5 μV/°C and 10 nA/°C, respectively. The AD8021 is also capable of driving a 75 Ω line with ±3 V video signals. The AD8021 is both technically superior and priced considerably less than comparable amps drawing much higher quiescent current. The AD8021 is a high speed, general-purpose amplifier, ideal for a wide variety of gain configurations and can be used throughout a signal processing chain and in control loops. The AD8021 is available in both standard 8-lead SOIC and MSOP packages in the industrial temperature range of −40°C to +85°C. 24 21 VOUT = 50mV p-p 18 G = –10, RF = 1kΩ, RG = 100Ω, RIN = 100Ω, CC = 0pF 15 12 G = –5, RF = 1kΩ, RG = 200Ω, RIN = 66.5Ω, CC = 1.5pF 9 6 3 0 –3 –6 0.1M G = –2, RF = 499Ω, RG = 249Ω, RIN = 63.4Ω, CC = 4pF G = –1, RF = 499Ω, RG = 499Ω, RIN = 56.2Ω, CC = 7pF 1M 10M FREQUENCY (Hz) 01888-002 APPLICATIONS CONNECTION DIAGRAM CLOSED-LOOP GAIN (dB) Low noise 2.1 nV/√Hz input voltage noise 2.1 pA/√Hz input current noise Custom compensation Constant bandwidth from G = −1 to G = −10 High speed 200 MHz (G = −1) 190 MHz (G = −10) Low power 34 mW or 6.7 mA typical for 5 V supply Output disable feature, 1.3 mA Low distortion −93 dBc second harmonic, fC = 1 MHz −108 dBc third harmonic, fC = 1 MHz DC precision 1 mV maximum input offset voltage 0.5 μV/°C input offset voltage drift Wide supply range, 5 V to 24 V Low price Small packaging Available in SOIC-8 and MSOP-8 01888-001 FEATURES 100M 1G Figure 2. Small Signal Frequency Response Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD8021 TABLE OF CONTENTS Features .............................................................................................. 1 Applications..................................................................................... 19 Applications....................................................................................... 1 Using the Disable Feature.......................................................... 20 General Description ......................................................................... 1 Theory of Operation ...................................................................... 21 Connection Diagram ....................................................................... 1 PCB Layout Considerations...................................................... 21 Revision History ............................................................................... 2 Driving 16-Bit ADCs ................................................................. 22 Specifications..................................................................................... 3 Differential Driver...................................................................... 22 Absolute Maximum Ratings............................................................ 7 Using the AD8021 in Active Filters ......................................... 23 Maximum Power Dissipation ..................................................... 7 Driving Capacitive Loads.......................................................... 23 ESD Caution.................................................................................. 7 Outline Dimensions ....................................................................... 25 Pin Configuration and Function Descriptions............................. 8 Ordering Guide .......................................................................... 25 Typical Performance Characteristics ............................................. 9 Test Circuits................................................................................. 17 REVISION HISTORY 5/06—Rev. E to Rev. F Updated Format..................................................................Universal Changes to General Description .................................................... 1 Changes to Figure 3.......................................................................... 7 Changes to Figure 60...................................................................... 19 Changes to Table 9.......................................................................... 23 3/05—Rev. D to Rev. E Updated Format..................................................................Universal Change to Figure 19 ....................................................................... 11 Change to Figure 25 ....................................................................... 12 Change to Table 7 and Table 8 ...................................................... 22 Change to Driving 16-Bit ADCs Section .................................... 22 7/03—Rev. B to Rev. C Deleted All References to Evaluation Board...................Universal Replaced Figure 2 ..............................................................................5 Updated Outline Dimensions....................................................... 20 2/03—Rev. A to Rev. B Edits to Evaluation Board Applications....................................... 20 Edits to Figure 17 ........................................................................... 20 6/02—Rev. 0 to Rev. A Edits to Specifications .......................................................................2 10/03—Rev. C to Rev. D Updated Format..................................................................Universal Rev. F | Page 2 of 28 AD8021 SPECIFICATIONS VS = ±5 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth Slew Rate, 1 V Step Settling Time to 0.01% Overload Recovery (50%) DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 HD3 f = 5 MHz HD2 HD3 Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive for 30% Overshoot DISABLE CHARACTERISTICS Off Isolation Turn-On Time Turn-Off Time DISABLE Voltage—Off/On Enabled Leakage Current Conditions Min G = +1, CC = 10 pF, VO = 0.05 V p-p G = +2, CC = 7 pF, VO = 0.05 V p-p G = +5, CC = 2 pF, VO = 0.05 V p-p G = +10, CC = 0 pF, VO = 0.05 V p-p G = +1, CC = 10 pF G = +2, CC = 7 pF G = +5, CC = 2 pF G = +10, CC = 0 pF VO = 1 V step, RL = 500 Ω ±2.5 V input step, G = +2 355 160 150 110 95 120 250 380 AD8021AR/AD8021ARM Typ Max Unit 490 205 185 150 120 150 300 420 23 50 MHz MHz MHz MHz V/μs V/μs V/μs V/μs ns ns VO = 2 V p-p VO = 2 V p-p −93 −108 dBc dBc VO = 2 V p-p VO = 2 V p-p f = 50 kHz f = 50 kHz NTSC, RL = 150 Ω NTSC, RL = 150 Ω −70 −80 2.1 2.1 0.03 0.04 dBc dBc nV/√Hz pA/√Hz % Degrees 2.6 82 0.4 0.5 7.5 10 0.1 86 −86 10 1 −4.1 to +4.6 −98 MΩ pF V dB VO = 50 mV p-p/1 V p-p −3.8 to +3.4 60 75 15/120 V mA mA pF f = 10 MHz VO = 0 V to 2 V, 50% logic to 50% output VO = 0 V to 2 V, 50% logic to 50% output VDISABLE − VLOGIC REFERENCE LOGIC REFERENCE = 0.4 V DISABLE = 4.0 V −40 45 50 1.75/1.90 70 2 dB ns ns V μA μA TMIN to TMAX +Input or −input VCM = ±4 V −3.5 to +3.2 Rev. F | Page 3 of 28 1.0 10.5 0.5 mV μV/°C μA nA/°C ±μA dB AD8021 Parameter Disabled Leakage Current POWER SUPPLY Operating Range Quiescent Current +Power Supply Rejection Ratio −Power Supply Rejection Ratio Conditions Min LOGIC REFERENCE = 0.4 V DISABLE = 0.4 V AD8021AR/AD8021ARM Typ Max 30 33 ±2.25 Output enabled Output disabled VCC = 4 V to 6 V, VEE = −5 V VCC = 5 V, VEE = −6 V to −4 V −86 −86 ±5 7.0 1.3 −95 −95 ±12.0 7.7 1.6 Unit μA μA V mA mA dB dB VS = ±12 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth Slew Rate, 1 V Step Settling Time to 0.01% Overload Recovery (50%) DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 HD3 f = 5 MHz HD2 HD3 Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Conditions Min G = +1, CC = 10 pF, VO = 0.05 V p-p G = +2, CC = 7 pF, VO = 0.05 V p-p G = +5, CC = 2 pF, VO = 0.05 V p-p G = +10, CC = 0 pF, VO = 0.05 V p-p G = +1, CC = 10 pF G = +2, CC = 7 pF G = +5, CC = 2 pF G = +10, CC = 0 pF VO = 1 V step, RL = 500 Ω ±6 V input step, G = +2 520 175 170 125 105 140 265 400 AD8021AR/AD8021ARM Typ Max Unit 560 220 200 165 130 170 340 460 21 90 MHz MHz MHz MHz V/μs V/μs V/μs V/μs ns ns VO = 2 V p-p VO = 2 V p-p −95 −116 dBc dBc VO = 2 V p-p VO = 2 V p-p f = 50 kHz f = 50 kHz NTSC, RL = 150 Ω NTSC, RL = 150 Ω −71 −83 2.1 2.1 0.03 0.04 dBc dBc nV/√Hz pA/√Hz % Degrees 84 0.4 0.2 8 10 0.1 88 −86 10 1 −11.1 to +11.6 −96 TMIN to TMAX +Input or −input VCM = ±10 V Rev. F | Page 4 of 28 2.6 1.0 11.3 0.5 mV μV/°C μA nA/°C ±μA dB MΩ pF V dB AD8021 Parameter OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive for 30% Overshoot DISABLE CHARACTERISTICS Off Isolation Turn-On Time Turn-Off Time DISABLE Voltage—Off/On Enabled Leakage Current Disabled Leakage Current POWER SUPPLY Operating Range Quiescent Current +Power Supply Rejection Ratio −Power Supply Rejection Ratio Conditions Min AD8021AR/AD8021ARM Typ Max −10.2 to +9.8 Unit VO = 50 mV p-p/1 V p-p −10.6 to +10.2 70 115 15/120 V mA mA pF f = 10 MHz VO = 0 V to 2 V, 50% logic to 50% output VO = 0 V to 2 V, 50% logic to 50% output VDISABLE − VLOGIC REFERENCE LOGIC REFERENCE = 0.4 V DISABLE = 4.0 V LOGIC REFERENCE = 0.4 V DISABLE = 0.4 V −40 45 50 1.80/1.95 70 2 30 33 dB ns ns V μA μA μA μA ±2.25 Output enabled Output disabled VCC = 11 V to 13 V, VEE = −12 V VCC = 12 V, VEE = −13 V to −11 V ±5 7.8 1.7 −96 −100 −86 −86 ±12.0 8.6 2.0 V mA mA dB dB VS = 5 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth Slew Rate, 1 V Step Settling Time to 0.01% Overload Recovery (50%) DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 HD3 f = 5 MHz HD2 HD3 Input Voltage Noise Input Current Noise Conditions G = +1, CC = 10 pF, VO = 0.05 V p-p G = +2, CC = 7 pF, VO = 0.05 V p-p G = +5, CC = 2 pF, VO = 0.05 V p-p G = +10, CC = 0 pF, VO = 0.05 V p-p G = +1, CC = 10 pF G = +2, CC = 7 pF G = +5, CC = 2 pF G = +10, CC = 0 pF VO = 1 V step, RL = 500 Ω 0 V to 2.5 V input step, G = +2 AD8021AR/AD8021ARM Min Typ Max 305 190 165 130 110 140 280 390 28 40 MHz MHz MHz MHz V/μs V/μs V/μs V/μs ns ns VO = 2 V p-p VO = 2 V p-p −84 −91 dBc dBc VO = 2 V p-p VO = 2 V p-p f = 50 kHz f = 50 kHz −68 −81 2.1 2.1 dBc dBc nV/√Hz pA/√Hz Rev. F | Page 5 of 28 270 155 135 95 80 110 210 290 Unit 2.6 AD8021 Parameter DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive for 30% Overshoot DISABLE CHARACTERISTICS Off Isolation Turn-On Time Turn-Off Time DISABLE Voltage—Off/On Enabled Leakage Current Disabled Leakage Current POWER SUPPLY Operating Range Quiescent Current +Power Supply Rejection Ratio −Power Supply Rejection Ratio Conditions AD8021AR/AD8021ARM Min Typ Max 72 0.4 0.8 7.5 10 0.1 76 −84 10 1 0.9 to 4.6 −98 MΩ pF V dB VO = 50 mV p-p/1 V p-p 1.10 to 3.60 30 50 10/120 V mA mA pF f = 10 MHz VO = 0 V to 1 V, 50% logic to 50% output VO = 0 V to 1 V, 50% logic to 50% output VDISABLE − VLOGIC REFERENCE LOGIC REFERENCE = 0.4 V DISABLE = 4.0 V LOGIC REFERENCE = 0.4 V DISABLE = 0.4 V −40 45 50 1.55/1.70 70 2 30 33 dB ns ns V μA μA μA μA TMIN to TMAX +Input or −input 1.5 V to 3.5 V 1.25 to 3.38 ±2.25 Output enabled Output disabled VCC = 4.5 V to 5.5 V, VEE = 0 V VCC = 5 V, VEE = −0.5 V to +0.5 V Rev. F | Page 6 of 28 −74 −76 ±5 6.7 1.2 −82 −84 1.0 Unit 10.3 0.5 ±12.0 7.5 1.5 mV μV/°C μA nA/°C ±μA dB V mA mA dB dB AD8021 ABSOLUTE MAXIMUM RATINGS Table 4. Input Voltage (Common Mode) Differential Input Voltage1 Differential Input Current Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) 1 MAXIMUM POWER DISSIPATION Rating 26.4 V Observed power derating curves ±VS ± 1 V ±0.8 V ±10 mA Observed power derating curves −65°C to +125°C −40°C to +85°C 300°C The AD8021 inputs are protected by diodes. Current-limiting resistors are not used to preserve the low noise. If a differential input exceeds ±0.8 V, the input current should be limited to ±10 mA. The maximum power that can be safely dissipated by the AD8021 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit can cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8021 is internally short-circuit protected, this can not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION (W) 2.0 1.5 8-LEAD SOIC 1.0 8-LEAD MSOP 0.5 01888-004 Parameter Supply Voltage Power Dissipation 0.01 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 AMBIENT TEMPERATURE (°C) Figure 3. Maximum Power Dissipation vs. Temperature 1 1 Specification is for device in free air: 8-lead SOIC: θJA = 125°C/W; 8-lead MSOP: θJA = 145°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F | Page 7 of 28 AD8021 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8021 8 DISABLE –IN 2 7 +VS +IN 3 6 VOUT –VS 4 5 CCOMP 01888-003 LOGIC 1 REFERENCE Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 1 Mnemonic LOGIC REFERENCE −IN +IN −VS CCOMP VOUT +VS DISABLE Description Reference for Pin 8 1 Voltage Level. Connect to logic low supply. Inverting Input. Noninverting Input. Negative Supply Voltage. Compensation Capacitor. Tie to −VS. (See the Applications section for value.) Output. Positive Supply Voltage. Disable, Active Low. When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC REFERENCE) by approximately 2 V or more, the part is enabled. When Pin 8 is brought down to within about 1.5 V of Pin 1, the part is disabled. (See the Specifications tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied to +VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state. Rev. F | Page 8 of 28 AD8021 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±5 V, RL = 1 kΩ, G = +2, RF = RG = 499 Ω, RS = 49.9 Ω, RO = 976 Ω, RD = 53.6 Ω, CC = 7 pF, CL = 0, CF = 0, VOUT = 2 V p-p, frequency = 1 MHz, unless otherwise noted. 24 G = +2 G = +10, RF = 1kΩ, RG = 110Ω, CC = 0pF G = +5, RF = 1kΩ, RG = 249Ω, CC = 2pF 6 5 GAIN (dB) 12 9 G = +2, RF = RG = 499Ω, CC = 7pF 4 3 2 G = +1, RF = 75Ω, CC = 10pF –3 –6 0.1M 1M 10M FREQUENCY (Hz) 100M 0 –1 1G Figure 5. Small Signal Frequency Response vs. Frequency and Gain, VOUT = 50 mV p-p, Noninverting (See Figure 48) 3 21 2 G = –1 1G G = –10, RF = 1kΩ, RG = 100Ω, RIN = 100Ω, CC = 0pF 1 G = –5, RF = 1kΩ, RG = 200Ω, RIN = 66.5Ω, CC = 1.5pF –1 VS = ±2.5V VS = ±5V 0 GAIN (dB) 12 9 6 VS = ±12V –2 –3 G = –2, RF = 499Ω, RG = 249Ω, RIN = 63.4Ω, CC = 4pF 3 –4 –5 0 –6 0.1M 1M 01888-006 G = –1, RF = 499Ω, RG = 499Ω, RIN = 56.2Ω, CC = 7pF –3 10M FREQUENCY (Hz) 100M VS = ±2.5V –6 –7 1M 1G Figure 6. Small Signal Frequency Response vs. Frequency and Gain, VOUT = 50 mV p-p Inverting (See Figure 48) 9 10M 100M FREQUENCY (Hz) Figure 8. Small Signal Frequency Response vs. Frequency and Supply, VOUT = 50 mV p-p, Noninverting (See Figure 48) 15 GAIN (dB) 1M 24 18 10M 100M FREQUENCY (Hz) 1G Figure 9. Small Signal Frequency Response vs. Frequency and Supply, VOUT = 50 mV p-p, Inverting (See Figure 50) 9 G = +2 G = +2 CC = 5pF 8 7 8 7 CC = 7pF GAIN (dB) 5 CC = 9pF 4 5 4 3 3 2 2 1 01888-007 CC = 9pF 1M 10M FREQUENCY (Hz) 100M VOUT = 4V p-p VOUT = 1V p-p 1 CC = 7pF 0 –1 0.1M VOUT = 0.1V AND 50mV p-p 6 6 GAIN (dB) VS = ±2.5V 1 01888-008 0 VS = ±12V 3 01888-009 6 VS = ±5V 7 01888-005 CLOSED-LOOP GAIN (dB) 18 15 VS = ±2.5V 8 1G Figure 7. Small Signal Frequency Response vs. Frequency and Compensation Capacitor, VOUT = 50 mV p-p (See Figure 48) 01888-010 21 9 0 –1 1M 10M 100M FREQUENCY (Hz) 1G Figure 10. Frequency Response vs. Frequency and VOUT, Noninverting (See Figure 48) Rev. F | Page 9 of 28 AD8021 10 10 9 8 8 7 7 GAIN (dB) 6 5 4 RF = 150Ω 5 0 0.1M 1M 10M FREQUENCY (Hz) 1 8 12 +25°C 7 10M FREQUENCY (Hz) 100M 1G 15 +85°C G = +2 1M Figure 14. Small Signal Frequency Response vs. Frequency and RF, Noninverting, VOUT = 50 mV p-p (See Figure 48) Figure 11. Large Signal Frequency Response vs. Frequency and Load, Noninverting (See Figure 49) 9 RF = 1kΩ AND CF = 2.2pF 0 0.1M 1G 100M RF = 75Ω 01888-014 01888-011 2 1 G = +2 9 6 6 –40°C +85°C VOUT = 2V p-p 3 2 3 RS = 49.9Ω 0 –3 RS = 100Ω –6 +25°C 0 –9 01888-012 1 –40°C –1 1M –15 0.1M 1G 10M 100M FREQUENCY (Hz) Figure 12. Frequency Response vs. Frequency, Temperature, and VOUT, Noninverting (See Figure 48) 18 G = +2 1G 80 20pF OPEN-LOOP GAIN (dB) 9 10pF 3 0pF –3 01888-013 –6 –9 100M 10M FREQUENCY (Hz) 100M 90 30pF 0 10M FREQUENCY (Hz) 100 12 6 1M Figure 15. Small Signal Frequency Response vs. Frequency and RS, Noninverting, VOUT = 50 mV p-p (See Figure 48) 50pF 15 RS = 249Ω –12 01888-015 4 VOUT = 50mV p-p 1G Figure 13. Small Signal Frequency Response vs. Frequency and Capacitive Load, Noninverting, VOUT = 50 mV p-p (See Figure 49 and Figure 71) Rev. F | Page 10 of 28 70 180 60 135 50 90 40 45 30 0 20 –45 10 –90 0 10k 100k 1M 10M FREQUENCY (Hz) 100M PHASE (Degrees) 5 GAIN (dB) GAIN (dB) RF = 250Ω 6 3 RL = 100Ω 2 GAIN (dB) RF = 1kΩ RF = 499Ω 4 RL = 1kΩ 3 –12 1M G = +2 RF = RG –135 1G Figure 16. Open-Loop Gain and Phase vs. Frequency, RG = 100 Ω, RF = 1 kΩ, RO = 976 Ω, RD = 53.6 Ω, CC = 0 pF (See Figure 50) 01888-016 GAIN (dB) 9 G = +2 AD8021 6.4 –20 G = +2 –30 VS = ±2.5V 6.2 –40 f1 6.0 VS = ±5V 5.8 VS = ±12V f2 Δf = 0.2MHz –60 POUT (dBm) GAIN (dB) –50 POUT 976Ω –70 53.6Ω 50Ω –80 –90 5.6 5.4 1M 10M FREQUENCY (Hz) 01888-020 01888-017 –100 –110 –120 9.5 100M Figure 17. 0.1 dB Flatness vs. Frequency and Supply, VOUT = 1 V p-p, RL = 150 Ω, Noninverting (See Figure 49) 9.7 10.3 10.0 FREQUENCY (MHz) 10.5 Figure 20. Intermodulation Distortion vs. Frequency 50 –20 –30 SECOND –60 –70 –80 RL = 100Ω RL = 1kΩ –90 –100 –120 01888-018 –110 THIRD –130 0.1M 1M FREQUENCY (Hz) 10M 45 40 VS = ±5V 35 25 20 20M VS = ±2.5V 30 01888-021 DISTORTION (dBc) –50 THIRD-ORDER INTERCEPT (dBm) –40 0 5 10 15 20 FREQUENCY (MHz) Figure 18. Second and Third Harmonic Distortion vs. Frequency and RL Figure 21. Third-Order Intercept vs. Frequency and Supply Voltage –30 –50 –40 –60 THIRD SECOND VS = ±2.5V –80 –90 SECOND –100 –120 THIRD –130 100k SECOND –80 RL = 100Ω THIRD –90 SECOND –100 VS = ±5V –110 –70 SECOND 1M FREQUENCY (Hz) VS = ±12V 10M 20M Figure 19. Second and Third Harmonic Distortion vs. Frequency and VS Rev. F | Page 11 of 28 RL = 1kΩ –110 01888-022 –70 DISTORTION (dBc) –60 01888-019 DISTORTION (dBc) –50 THIRD –120 1 2 3 4 VOUT (V p-p) 5 6 Figure 22. Second and Third Harmonic Distortion vs. VOUT and RL AD8021 fC = 5MHz –80 THIRD SECOND –90 –110 01888-023 fC = 1MHz –100 THIRD 1 2 3 4 VOUT (V p-p) 5 6 3.3 –3.3 3.2 –3.4 3.1 –3.5 3.0 –3.6 2.9 2.8 NEGATIVE OUTPUT 0 400 Figure 23. Second and Third Harmonic Distortion vs. VOUT and Fundamental Frequency (fC), G = +2 120 –60 SECOND –70 THIRD –80 SECOND fC = 1MHz –90 THIRD 01888-024 –100 1 2 3 4 VOUT (V p-p) 5 100 VS = ±12V 80 VS = ±5.0V 60 VS = ±2.5V 40 20 0 –50 6 01888-027 fC = 5MHz SHORT-CIRCUIT CURRENT (mA) –30 –10 10 30 50 70 90 110 TEMPERATURE (°C) Figure 24. Second and Third Harmonic Distortion vs. VOUT and Fundamental Frequency (fC), G = +10 Figure 27. Short-Circuit Current to Ground vs. Temperature –70 50 G=2 fC = 1MHz 40 RL = 1kΩ RF = RG G = +2 –80 RL = 1kΩ, 150Ω 30 –90 VOUT (mV) 20 SECOND –100 –10 –20 THIRD –110 –30 01888-025 –120 10 0 200 400 600 800 1000 FEEDBACK RESISTANCE (Ω) Figure 25. Second and Third Harmonic Distortion vs. Feedback Resistor (RF) Rev. F | Page 12 of 28 01888-028 DISTORTION (dBc) –50 DISTORTION (dBc) –3.8 2000 1600 Figure 26. DC Output Voltages vs. Load (See Figure 48) –40 –110 800 1200 LOAD (Ω) –3.7 NEGATIVE OUTPUT VOLTAGE (V) –70 POSITIVE OUTPUT –40 –50 0 40 80 120 TIME (ns) 160 Figure 28. Small Signal Transient Response vs. RL, VO = 50 mV p-p, Noninverting (See Figure 49) 200 01888-026 POSITIVE OUTPUT VOLTAGE (V) SECOND DISTORTION (dBc) –3.2 3.4 –60 –120 –3.1 3.5 –50 AD8021 VO = 4V p-p G=2 2.0 VO = 2V p-p G=2 2.0 RL = 1kΩ 1.0 VOUT (V) VOUT (V) 1.0 RL = 150Ω –1.0 VS = ±2.5V –1.0 –2.0 0 40 80 120 160 01888-032 01888-029 VS = ±5V –2.0 0 200 40 80 TIME (ns) VIN = ±3V G = +2 VIN = 1V/DIV VOUT = 2V/DIV VO = 4V p-p G = –1 4 3 200 VOUT, RL = 1kΩ VIN 2 1 VOLTS 160 Figure 32. Large Signal Transient Response vs. VS (See Figure 48) Figure 29. Large Signal Transient Response vs. RL, Noninverting (See Figure 49) 5 120 TIME (ns) RL = 150Ω –1 VOUT –2 –5 0 50 100 150 TIME (ns) 200 VIN 0 250 CL = 50pF G=2 VO = 4V p-p OUTPUT SETTLING VOUT (V) 01888-031 –1.0 –2.0 0 40 80 120 160 400 500 G=2 CL = 10pF, 0pF 1.0 200 300 TIME (ns) Figure 33. Overdrive Recovery vs. RL (See Figure 49) Figure 30. Large Signal Transient Response, Inverting (See Figure 50) 2.0 100 +0.01% –0.01% 25ns VERT = 0.2mV/DIV HOR = 5ns/DIV 200 TIME (ns) Figure 31. Large Signal Transient Response vs. CL (See Figure 48) Rev. F | Page 13 of 28 Figure 34. 0.01% Settling Time, 2 V Step 01888-034 –4 01888-033 01888-030 –3 AD8021 100 100 60 SETTLING (µV) 40 PULSE WIDTH = 120ns 20 0 –20 PULSE WIDTH = 300µs –60 5V –80 0V –100 01888-035 –40 t1 0 4 8 12 16 20 24 28 10 1 10 32 01888-038 INPUT CURRENT NOISE (pA/√Hz) 80 100 1k TIME (µs) Figure 35. Long-Term Settling, 0 V to 5 V, VS = ±12 V, G = +13 10M 0.48 G = +1 40 0.44 VOLTAGE OFFSET (mV) 30 20 10 –10 –20 –30 0.40 0.36 0.32 01888-036 0.28 –40 0 40 80 120 TIME (ns) 160 0.24 –50 200 01888-039 VOUT (mV) 1M Figure 38. Input Current Noise vs. Frequency 50 –50 10k 100k FREQUENCY (Hz) –25 0 25 50 75 100 75 100 TEMPERATURE (°C) Figure 36. Small Signal Transient Response, VO = 50 mV p-p, G = +1 (See Figure 48) Figure 39. VOS vs. Temperature 100 8.4 INPUT BIAS CURRENT (μA) 10 2.1nV/ √Hz 7.6 7.2 6.8 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 6.0 –50 01888-040 6.4 01888-037 VOLTAGE NOISE (nV/ √ Hz) 8.0 –25 0 25 50 TEMPERATURE (°C) Figure 37. Input Voltage Noise vs. Frequency Figure 40. Input Bias Current vs. Temperature Rev. F | Page 14 of 28 AD8021 0 –30 –10 –40 –20 DISABLED ISOLATION (dB) –20 –60 –70 –80 –90 –30 –40 –50 –60 –70 01888-041 –110 –120 10k 100k 1M FREQUENCY (Hz) 10M 100M –90 –100 0.1M 1M 10M FREQUENCY (Hz) 100M 1G Figure 44. Input-to-Output Isolation, Chip Disabled (See Figure 54) 300 300k 100 100k 30 30k OUTPUT IMPEDANCE (Ω) OUTPUT IMPEDANCE (Ω) Figure 41. CMRR vs. Frequency (See Figure 51) 01888-044 –80 –100 10 3 1 0.3 0.1 10k 3k 1k 300 100 0.03 01888-042 30 0.01 0.003 10k 100k 10M 1M FREQUENCY (Hz) 100M 10 3 10k 1G Figure 42. Output Impedance vs. Frequency, Chip Enabled (See Figure 52) 100k 1M 10M FREQUENCY (Hz) 100M 1G Figure 45. Output Impedance vs. Frequency, Chip Disabled (See Figure 55) 0 DISABLE 4V 01888-045 CMRR (dB) –50 –10 2V –PSRR –20 PSRR (dB) –30 VOUTPUT 2V tEN = 45ns 1V –40 –50 VS = ±2.5V VS = ±12V –60 –70 tDIS = 50ns VS = ±5V 100 200 300 TIME (ns) 400 500 Figure 43. Enable (tEN)/Disable (tDIS) Time vs. VOUT (See Figure 53) Rev. F | Page 15 of 28 –90 –100 10k 01888-046 01888-043 –80 0 +PSRR 100k 1M 10M FREQUENCY (Hz) 100M Figure 46. PSRR vs. Frequency and Supply Voltage (See Figure 56 and Figure 57) 500M AD8021 8.5 7.5 7.0 6.5 6.0 5.5 –50 01888-047 SUPPLY CURRENT (mA) 8.0 –25 0 25 50 75 100 TEMPERATURE (°C) Figure 47. Quiescent Supply Current vs. Temperature Rev. F | Page 16 of 28 AD8021 TEST CIRCUITS +VS RS AD8021 50Ω HP8753D +VS 50Ω CABLE RO NETWORK ANALYZER 5 100Ω RD 01888-048 CF RG 499Ω Figure 48. Noninverting Gain +VS RF 499Ω Figure 52. Output Impedance, Chip Enabled FET PROBE AD8021 +VS 49.9Ω RS 50Ω RIN 49.9Ω 1 49.9Ω 1.0V 5 LOGIC REF 8 DISABLE 5 CC CL RL CC –VS 49.9Ω 4V –VS 01888-049 RF RG CF 49.9Ω NETWORK ANALYZER 5 RD 50Ω CC 50Ω CABLE RF 49.9Ω Figure 50. Inverting Gain 8 NETWORK ANALYZER 499Ω AD8021 +VS 49.9Ω 5 CC 55.6Ω 499Ω CC 7pF 499Ω HP8753D 8 +VS 100Ω 5 NETWORK ANALYZER 50Ω 7pF 499Ω 01888-051 –VS 1kΩ 5 AD8021 1 499Ω FET PROBE Figure 54. Input-to-Output Isolation, Chip Disabled 50Ω 499Ω LOGIC REF DISABLE –VS HP8753D 50Ω AD8021 1 49.9Ω 01888-054 RG 50Ω +VS 01888-050 RIN 49.9Ω 7pF HP8753D 50Ω CABLE RO –VS 53.6Ω Figure 53. Enable/Disable +VS 50Ω CABLE 976Ω 499Ω 499Ω Figure 49. Noninverting Gain and FET Probe 50Ω 50Ω 7pF –VS RF RG 50Ω CABLE 5 CC 01888-052 –VS 01888-053 CC RIN 49.9Ω –VS CC 7pF Figure 55. Output Impedance, Chip Disabled Figure 51. CMRR Rev. F | Page 17 of 28 01888-055 50Ω CABLE AD8021 BIAS BNC HP8753D NETWORK ANALYZER 50Ω +VS HP8753D NETWORK ANALYZER 50Ω 50Ω –VS 50Ω 50Ω CABLE 50Ω CABLE +VS 49.9Ω, 5W +VS 976Ω 249Ω 5 976Ω 249Ω 5 499Ω –VS CC 7pF 499Ω 53.6Ω CC 7pF 49.9Ω 5W 01888-056 –VS 53.6Ω 499Ω Figure 56. Positive PSRR 499Ω Figure 57. Negative PSRR Rev. F | Page 18 of 28 01888-057 BIAS BNC AD8021 APPLICATIONS degraded to about 20 MHz and the phase margin increases to 90° (Arrow B). However, by reducing CC to 0 pF, the bandwidth and phase margin return to about 200 MHz and 60° (Arrow C), respectively. In addition, the slew rate is dramatically increased, as it roughly varies with the inverse of CC. 10 Unlike the typical op amp with fixed compensation, the AD8021 allows the user to: Maximize the amplifier bandwidth for closed-loop gains between 1 and 10, avoiding the usual loss of bandwidth and slew rate. Optimize the trade-off between bandwidth and phase margin for a particular application. • Match bandwidth in gain blocks with different noise gains, such as when designing differential amplifiers (as shown in Figure 65). 180 100 135 (B) CC = 10pF (A) (C) 45 0 60 50 40 (C) 30 PHASE (Degrees) 70 90 CC = 0pF 5 4 3 2 0 110 90 86 80 7 6 1 1 2 3 4 5 6 7 NOISE GAIN (V/V) (B) 0 –10 1k (A) 10k 100k 10M 100M 1M FREQUENCY (Hz) 1G 9 10 11 Table 6 and Figure 59 provide recommended values of compensation capacitance at various gains and the corresponding slew rate, bandwidth, and noise. Note that the value of the compensation capacitor depends on the circuit noise gain, not the voltage gain. As shown in Figure 60, the noise gain, GN, of an op amp gain block is equal to its noninverting voltage gain, regardless of whether it is actually used for inverting or noninverting gain. Thus, Noninverting GN = RF/RG + 1 Inverting GN = RF/RG + 1 20 10 8 Figure 59. Suggested Compensation Capacitance vs. Gain for Maintaining 1 dB Peaking 01888-058 OPEN-LOOP GAIN (dB) • 8 1 RS 3 + Figure 58. Simplified Diagram of Open-Loop Gain and Phase Response Figure 58 is the AD8021 gain and phase plot that has been simplified for instructional purposes. Arrow A in Figure 58 shows a bandwidth of about 200 MHz and a phase margin at about 60° when the desired closed-loop gain is G = +1 and the value chosen for the external compensation capacitor is CC = 10 pF. If the gain is changed to G = +10 and CC is fixed at 10 pF, then (as expected for a typical op amp) the bandwidth is Rev. F | Page 19 of 28 2 6 AD8021 10G 2 RF 1kΩ RG 249Ω – –VS RF 1kΩ NONINVERTING 3 5 + –VS CCOMP G = GN = +5 6 AD8021 5 – RG 249Ω G = –4 GN = +5 CCOMP INVERTING Figure 60. The Noise Gain of Both is 5 01888-060 • 9 01888-059 COMPENSATION CAPACITANCE (pF) The typical voltage feedback op amp is frequency stabilized with a fixed internal capacitor, CINTERNAL, using dominant pole compensation. To a first-order approximation, voltage feedback op amps have a fixed gain bandwidth product. For example, if its −3 dB bandwidth is 200 MHz for a gain of G = +1; at a gain of G = +10, its bandwidth is only about 20 MHz. The AD8021 is a voltage feedback op amp with a minimal CINTERNAL of about 1.5 pF. By adding an external compensation capacitor, CC, the user can circumvent the fixed gain bandwidth limitation of other voltage feedback op amps. AD8021 CF = CL = 0, RL = 1 kΩ, RIN = 49.9 Ω (see Figure 49). Table 6. Recommended Component Values Noise Gain (Noninverting Gain) 1 2 5 10 20 100 RS (Ω) 75 49.9 49.9 49.9 49.9 49.9 RF (Ω) 75 499 1k 1k 1k 1k RG (Ω) NA 499 249 110 52.3 10 CCOMP (pF) 10 7 2 0 0 0 Slew Rate (V/μs) 120 150 300 420 200 34 With the AD8021, a variety of trade-offs can be made to finetune its dynamic performance. Sometimes more bandwidth or slew rate is needed at a particular gain. Reducing the compensation capacitance, as illustrated in Figure 7, increases the bandwidth and peaking due to a decrease in phase margin. On the other hand, if more stability is needed, increasing the compensation capacitor decreases the bandwidth while increasing the phase margin. As with all high speed amplifiers, parasitic capacitance and inductance around the amplifier can affect its dynamic response. Often, the input capacitance (due to the op amp itself, as well as the PC board) has a significant effect. The feedback resistance, together with the input capacitance, can contribute to a loss of phase margin, thereby affecting the high frequency response, as shown in Figure 14. A capacitor (CF) in parallel with the feedback resistor can compensate for this phase loss. −3 dB SS BW (MHz) 490 205 185 150 42 6 Output Noise (AD8021 Only) (nV/√Hz) 2.1 4.3 10.7 21.2 42.2 211.1 Output Noise (AD8021 with Resistors) (nV/√Hz) 2.8 8.2 15.5 27.9 52.7 264.1 Additionally, any resistance in series with the source creates a pole with the input capacitance (as well as dampen high frequency resonance due to package and board inductance and capacitance), the effect of which is shown in Figure 15. It must also be noted that increasing resistor values increases the overall noise of the amplifier and that reducing the feedback resistor value increases the load on the output stage, thus increasing distortion (see Figure 22). USING THE DISABLE FEATURE When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC REFERENCE) by approximately 2 V or more, the part is enabled. When Pin 8 is brought down to within about 1.5 V of Pin 1, the part is disabled. See Table 1 for exact disable and enable voltage levels. If the disable feature is not used, Pin 8 can be tied to VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state. Rev. F | Page 20 of 28 AD8021 THEORY OF OPERATION The AD8021 is fabricated on the second generation of Analog Devices proprietary High Voltage eXtra-Fast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fTs in the 3 GHz region. The transistors are dielectrically isolated from the substrate (and each other), eliminating the parasitic and latch-up problems caused by junction isolation. It also reduces nonlinear capacitance (a source of distortion) and allows a higher transistor, fT, for a given quiescent current. The supply current is trimmed, which results in less part-to-part variation of bandwidth, slew rate, distortion, and settling time. As shown in Figure 61, the AD8021 input stage consists of an NPN differential pair in which each transistor operates at a 0.8 mA collector current. This allows the input devices a high transconductance; thus, the AD8021 has a low input noise of 2.1 nV/√Hz @ 50 kHz. The input stage drives a folded cascode that consists of a pair of PNP transistors. The folded cascode and current mirror provide a differential-to-single-ended conversion of signal current. This current then drives the high impedance node (Pin 5), where the CC external capacitor is connected. The output stage preserves this high impedance with a current gain of 5000, so that the AD8021 can maintain a high open-loop gain even when driving heavy loads. Two internal diode clamps across the inputs (Pin 2 and Pin 3) protect the input transistors from large voltages that could otherwise cause emitter-base breakdown, which would result in degradation of offset voltage and input bias current. PCB LAYOUT CONSIDERATIONS As with all high speed op amps, achieving optimum performance from the AD8021 requires careful attention to PC board layout. Particular care must be exercised to minimize lead lengths between the ground leads of the bypass capacitors and between the compensation capacitor and the negative supply. Otherwise, lead inductance can influence the frequency response and even cause high frequency oscillations. Use of a multilayer printed circuit board, with an internal ground plane, reduces ground noise and enables a compact component arrangement. Due to the relatively high impedance of Pin 5 and low values of the compensation capacitor, a guard ring is recommended. The guard ring is simply a PC trace that encircles Pin 5 and is connected to the output, Pin 6, which is at the same potential as Pin 5. This serves two functions. It shields Pin 5 from any local circuit noise generated by surrounding circuitry. It also minimizes stray capacitance, which would tend to otherwise reduce the bandwidth. An example of a guard ring layout is shown in Figure 62. Also shown in Figure 62, the compensation capacitor is located immediately adjacent to the edge of the AD8021 package, spanning Pin 4 and Pin 5. This capacitor must be a high quality surfacemount COG or NPO ceramic. The use of leaded capacitors is not recommended. The high frequency bypass capacitor(s) should be located immediately adjacent to the supplies, Pin 4 and Pin 7. To achieve the shortest possible lead length at the inverting input, the feedback resistor RF is located beneath the board and spans the distance from the output, Pin 6, to inverting input Pin 2. The return node of Resistor RG should be situated as close as possible to the return node of the negative supply bypass capacitor connected to Pin 4. +VS OUTPUT +IN (TOP VIEW) CINTERNAL 1.5pF LOGIC REFERENCE 1 8 –IN 2 +VS 7 +IN 3 6 –VS 4 5 –IN CC Figure 61. Simplified Schematic VOUT GROUND PLANE CCOMP METAL BYPASS CAPACITOR COMPENSATION CAPACITOR GROUND PLANE Figure 62. Recommended Location of Critical Components and Guard Ring Rev. F | Page 21 of 28 01888-062 CCOMP 01888-061 –VS BYPASS CAPACITOR DISABLE AD8021 DRIVING 16-BIT ADCs Low noise and adjustable compensation make the AD8021 especially suitable as a buffer/driver for high resolution ADCs. As seen in Figure 19, the harmonic distortion is better than 90 dBc at frequencies between 100 kHz and 1 MHz. This is an advantage for complex waveforms that contain high frequency information, because the phase and gain integrity of the sampled waveform can be preserved throughout the conversion process. The increase in loop gain results in improved output regulation and lower noise when the converter input changes state during a sample. This advantage is particularly apparent when using 16-bit high resolution ADCs with high sampling rates. Figure 63 shows a typical ADC driver configuration. The AD8021 is in an inverting gain of −7.5, fC is 65 kHz, and its output voltage is 10 V p-p. The results are listed in Table 7. 590Ω 2 RG 200Ω +5V + AD8021 – 6 IN HI 5 CC 10pF AD7665 570kSPS RF 1.5kΩ –12V 50Ω 01888-063 IN HI 56pF Figure 63. Inverting ADC Driver, Gain = −7.5, fC = 65 kHz Table 7. Summary of ADC Driver Performance (fC = 65 kHz, VOUT = 10 V p-p) Parameter Second Harmonic Distortion Third Harmonic Distortion THD SFDR Measurement −101.3 −109.5 −100.0 +100.3 Measurement −92.6 −86.4 −84.4 +5.4 DIFFERENTIAL DRIVER The AD8021 is uniquely suited as a low noise differential driver for many ADCs, balanced lines, and other applications requiring differential drive. If pairs of internally compensated op amps are configured as inverter and follower, the noise gain of the inverter is higher than that of the follower section, resulting in an imbalance in the frequency response (see Figure 66). Figure 65 illustrates an inverter-follower driver circuit operating at a gain of 2, using individually compensated AD8021s. The values of feedback and load resistors were selected to provide a total load of less than 1 kΩ, and the equivalent resistances seen at each op amp’s inputs were matched to minimize offset voltage and drift. Figure 67 is a plot of the resulting ac responses of driver halves. Unit dBc dBc dBc dBc VIN 249Ω 3 + G = +2 AD8021 49.9Ω 2 – –VS 6 5 7pF 499Ω 499Ω Figure 64 shows another ADC driver connection. The circuit was tested with a noninverting gain of 10.1 and an output voltage of approximately 20 V p-p for optimum resolution and noise performance. No filtering was used. An FFT was performed using Analog Devices evaluation software for the AD7665 16-bit converter. The results are listed in Table 8. VOUT1 1kΩ 232Ω 3 + G = –2 AD8021 2 – –VS 332Ω 6 5 VOUT2 1kΩ 5pF 664Ω +12V 5 – IN HI CC –12V RG 82.5Ω 6 AD8021 2 AD7665 RF 750Ω 570kSPS 16 BITS 50Ω Figure 65. Differential Amplifier +5V ADC OPTIONAL CF IN LO 01888-064 50Ω 50Ω 3 + Unit dBc dBc dBc dBc A better solution takes advantage of the external compensation feature of the AD8021. By reducing the CCOMP value of the inverter, its bandwidth can be increased to match that of the follower, avoiding compromises in gain bandwidth and phase delay. The inverting and noninverting bandwidths can be closely matched using the compensation feature, thus minimizing distortion. 16 BITS 3 Parameter Second Harmonic Distortion Third Harmonic Distortion THD SFDR Figure 64. Noninverting ADC Driver, Gain = 10, fC = 100 kHz Rev. F | Page 22 of 28 01888-065 +12V Table 8. Summary of ADC Driver Performance (fC = 100 kHz, VOUT = 20 V p-p) AD8021 12 C1 +VS 9 VIN 6 R1 CC –VS RF RG –6 –9 Figure 68. Schematic of a Second-Order, Low-Pass Active Filter –12 Table 9. Typical Component Values for Second-Order, LowPass Active Filter of Figure 68 01888-066 –15 1M 10M 100M Gain 1G FREQUENCY (Hz) Figure 66. AC Response of Two Identically Compensated High Speed Op Amps Configured for a Gain of +2 and a Gain of −2 2 5 12 R1 (Ω) 71.5 44.2 R2 (Ω) 215 365 RF (Ω) 499 365 RG (Ω) 499 90.9 C1 (nF) 10 10 C2 (nF) 10 10 CC (pF) 7 2 50 9 40 6 30 3 G = ±2 20 GAIN (dB) 0 –3 –6 –9 G=5 10 0 –10 G=2 –20 –12 1M 10M FREQUENCY (Hz) 100M 01888-069 01888-067 –30 –15 –18 100k VOUT 5 01888-068 GAIN (dB) G = –2 G = +2 –3 AD8021 2 C2 0 –18 100k 3 6 3 GAIN (dB) R2 –40 –50 1k 1G Figure 67. AC Response of Two Dissimilarly Compensated AD8021 Op Amps (Figure 66) Configured for a Gain of +2 and a Gain of −2, (Note the Close Gain Match) 10k 100k FREQUENCY (Hz) 1M 10M Figure 69. Frequency Response of the Filter Circuit of Figure 68 for Two Different Gains USING THE AD8021 IN ACTIVE FILTERS DRIVING CAPACITIVE LOADS The low noise and high gain bandwidth of the AD8021 make it an excellent choice in active filter circuits. Most active filter literature provides resistor and capacitor values for various filters but neglects the effect of the op amp’s finite bandwidth on filter performance; ideal filter response with infinite loop gain is implied. Unfortunately, real filters do not behave in this manner. Instead, they exhibit finite limits of attenuation, depending on the gain bandwidth of the active device. Good low-pass filter performance requires an op amp with high gain bandwidth for attenuation at high frequencies, and low noise and high dc gain for low frequency, pass-band performance. When the AD8021 drives a capacitive load, the high frequency response can show excessive peaking before it rolls off. Two techniques can be used to improve stability at high frequency and reduce peaking. The first technique is to increase the compensation capacitor, CC, which reduces the peaking while maintaining gain flatness at low frequencies. The second technique is to add a resistor, RSNUB, in series between the output pin of the AD8021 and the capacitive load, CL. Figure 70 shows the response of the AD8021 when both CC and RSNUB are used to reduce peaking. For a given CL, Figure 71 can be used to determine the value of RSNUB that maintains 2 dB of peaking in the frequency response. Note, however, that using RSNUB attenuates the low frequency output by a factor of RLOAD/(RSNUB + RLOAD). Figure 68 shows the schematic of a 2-pole, low-pass active filter and lists typical component values for filters having a Besseltype response with a gain of 2 and a gain of 5. Figure 69 is a network analyzer plot of this filter’s performance. Rev. F | Page 23 of 28 B B B B AD8021 49.9Ω 49.9Ω –VS 10 8 499Ω 33pF RL 1kΩ 16 CC = 8pF; RSNUB = 0Ω CC 14 499Ω 6 4 2 10 8 4 CC = 8pF; RSNUB = 17.4Ω 0 0.1 12 6 1.0 10 FREQUENCY (MHz) 100 Figure 70. Peaking vs. RSNUB and CC for CL = 33 pF 01888-070 GAIN (dB) 12 6 18 CC = 7pF; RSNUB = 0Ω 01888-071 14 20 FET PROBE 5 RSNUB +VS 16 R SNUB (Ω) 18 2 0 1000 0 5 10 15 20 25 30 35 CAPACITIVE LOAD (pF) 40 45 50 Figure 71. Relationship of RSNUB vs. CL for 2 dB Peaking at a Gain of +2 B Rev. F | Page 24 of 28 AD8021 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.50 (0.0196) × 45° 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 72. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8° 0° 0.80 0.60 0.40 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 73. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model AD8021AR AD8021AR-REEL AD8021AR-REEL7 AD8021ARZ 1 AD8021ARZ-REEL1 AD8021ARZ-REEL71 AD8021ARM AD8021ARM-REEL AD8021ARM-REEL7 AD8021ARMZ1 AD8021ARMZ-REEL1 AD8021ARMZ-REEL71 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 1 Z = Pb-free part, # denotes lead-free product may be top or bottom marked. Rev. F | Page 25 of 28 Package Option R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding HNA HNA HNA HNA# HNA# HNA# AD8021 NOTES Rev. F | Page 26 of 28 AD8021 NOTES Rev. F | Page 27 of 28 AD8021 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01888-0-5/06(F) Rev. F | Page 28 of 28