IC62VV5128L IC62VV5128LL Document Title 512K x 8 bit 1.8V and Ultra Low Power CMOS Static RAM Revision History Revision No History Draft Date Remark 0A Initial Draft November 26,2001 Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 1 IC62VV5128L IC62VV5128LL 512K x 8 1.8V and LOW VCC CMOS STATIC RAM DESCRIPTION The ICSI IC62VV5128L and IC62VV5128LL is a low voltage, FEATURES • Access times of 55, 70, 100 ns • CMOS Low power operation: ICC1=10mA (typical)* operation ISB2=1µA (typical)* standby * Typical values are measured at VCC=1. 8V, TA=25°C • Low data retention voltage: 1.0V (min.) • Output Enable (OE) and Chip Enable (CE) inputs for ease in applications • TTL compatible inputs and outputs • Fully static operation: — No clock or refresh reguired • Single 1.65V-2.2V power supply • Available in the 32-pin 8*20mm TSOP1, 32-pin 8*13.4mm TSOP-1 and 48pin 6*8mm TF-BGA 524,288 words by 8 bits, CMOS SRAM. It is fabricated using ICSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable ( WE) controls both writing and reading of the memory. The IC62VV5128L and IC62VV5128LL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TFBGA. FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 IC62VV5128L IC62VV5128LL PIN CONFIGURATIONS 32-Pin 8*20mm TSOP-1, 8*13.4mm STSOP-1 A11 A9 A8 A13 WE A17 A15 Vcc A18 A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48-Pin 6*8mm TF-BGA (TOP-View) OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 1 2 3 4 5 6 A A0 A1 NC A3 A6 A8 B I/O4 A2 WE A4 A7 I/O0 C I/O5 NC A5 D GND Vcc E Vcc GND F I/O6 G I/O7 H A9 I/O1 A18 A17 OE CE A16 A15 I/O3 A10 A11 A12 A13 A14 I/O2 PIN DESCRIPTIONS A0-A18 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Data Input/Output NC No Connection Vcc Power GND Ground TRUTH TABLE WE CE OE I/O Operation Vcc Current Not Selected X H X High-Z ISB1, ISB2 Output Disabled Read Write H H L L L L H L X High-Z DOUT DIN ICC ICC ICC Mode OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C VCC 1.65V - 2.2V –40°C to +85°C 1.65V - 2.2V Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 3 IC62VV5128L IC62VV5128LL ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.4 –0.3 to +4.0 –40 to +85 –65 to +150 1 Unit V V °C °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1)(2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25oC, f = 1 MHz, VCC = 1.8 V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage(1) Input LOW Voltage(2) Input Leakage Output Leakage VCC = Min., IOH = -0.1 mA VCC = Min., IOL = 0.1 mA 1.4 — 1.4 –0.2 –1 –1 — 0.2 VCC + 0.3 0.4 1 1 V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC Notes: 1. VIH(max) =VCC +2.0V for pulse width less than 10ns. 2. VIL(min) = –2.0V for pulse width less than 10 ns. 4 Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 IC62VV5128L IC62VV5128LL IC62VV5128L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -55 Min. Max. -70 Min. Max. -100 Min. Max. Symbol Parameter Test Conditions Unit ICC Vcc Dynamic Operating Supply Current VCC = 1.8V, CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. — — 20 20 — — 15 15 — — 10 10 mA ICC2 Vcc Dynamic Operating Supply Current VCC = 1.8V, IOUT = 0 mA CE ≤ VIL ,f = 1MHZ Com. Ind. — — 2 2 — — 2 2 — — 2 2 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., f = 0 Com. 1) CE ≥ VCC – 0.2V, (CE Control) Ind. 2) UB, LB ≥ VCC – 0.2V, (UB, LB Control) VIN ≥ VCC – 0.2V or VIN ≤ 0.2V — — 35 50 — — 35 50 — — 35 50 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. IC62VV5128LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -55 Min. Max. -70 Min. Max. -100 Min. Max. Symbol Parameter Test Conditions Unit ICC Vcc Dynamic Operating Supply Current VCC = 3V, CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. — — 20 20 — — 15 15 — — 10 10 mA ICC2 Vcc Dynamic Operating Supply Current VCC = 1.8V, IOUT = 0 mA, CE ≤ VIL ,f = 1MHZ Com. Ind. — — 2 2 — — 2 2 — — 2 2 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., f = 0 Com. 1) CE ≥ VCC – 0.2V, (CE Control) Ind. 2) UB, LB ≥ VCC – 0.2V, (UB, LB Control) VIN ≥ VCC – 0.2V or VIN ≤ 0.2V — — 15 20 — — 15 20 — — 15 20 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 5 IC62VV5128L IC62VV5128LL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -55 Symbol Parameter Min. Max. -70 Min. Max. -100 Min. Max. Unit tRC Read Cycle Time 55 — 70 — 100 — ns tAA Address Access Time — 55 — 70 — 100 ns tOHA Output Hold Time 10 — 10 — 15 — ns tACE CE Access Time — 55 — 70 — 100 ns OE Access Time — 30 — 35 — 50 ns (2) tHZOE OE to High-Z Output — 20 0 25 0 30 ns tLZOE(2) OE to Low-Z Output 5 — 5 — 5 — ns tLZCE(2) CE to Low-Z Output 10 — 10 — 10 — ns tHZCE CE to High-Z Output 0 20 0 25 0 30 ns tDOE (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input Reference Level Output Reference Level Output Load Unit 0.4V to 1.4V 5 ns 0.9V 0.9V See Figures 1 and 2 AC TEST LOADS 1 TTL OUTPUT OUTPUT 100 pF Including jig and scope Figure 1 6 1 TTL 5 pF Including jig and scope Figure 2 Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 IC62VV5128L IC62VV5128LL AC TEST LOADS READ CYCLE NO.1(1,2) (Address Controlled, CE = OE = UB = LB = VIL) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (CE CE , OE , and Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t ACE t HZCE t LZCE DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 7 IC62VV5128L IC62VV5128LL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power) Symbol Parameter Min. -55 Max. -70 Min. Max. -100 Min. Max Unit tWC Write Cycle Time 55 — 70 — 100 — ns tSCE CE to Write End 50 — 65 — 80 — ns tAW Address Setup Time to Write End 50 — 65 — 80 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — ns tPWE WE Pulse Width 45 — 55 — 80 — ns tSD Data Setup to Write End 25 — 30 — 40 — ns tHD Data Hold from Write End 0 — 0 — 0 — ns tHZWE(3) WE LOW to High-Z Output — 30 — 30 — 40 ns tLZWE WE HIGH to Low-Z Output 5 — 5 — 5 — ns (3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled) tWC ADDRESS tHA tSCE CE tAW tPWE WE tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN 8 tHD DATA-IN VALID Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 IC62VV5128L IC62VV5128LL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)) tWC ADDRESS OE tHA tSCE CE tAW tPWE WE tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)) tWC ADDRESS OE tHA tSCE CE tAW tPWE WE tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 tHD DATA-IN VALID 9 IC62VV5128L IC62VV5128LL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 1.0 2.2 V IDR Data Retention Current Vcc = 1.0V, CE ≥ Vcc – 0.2V — — — — 15 5 20 9 µA µA µA µA tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns tRDR Recovery Time See Data Retention Waveform 5 — ns DATA RETENTION WAVEFORM tSDR Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) (CE Controlled) Data Retention Mode tRDR VCC 1.65V 1.4V VDR CE GND 10 CE ≥ VCC - 0.2V Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 IC62VV5128L IC62VV5128LL ORDERING INFORMATION Commercial Range: 0°C to +70°C Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 55 IC62VV5128L-55T IC62VV5128L-55H IC62VV5128L-55B 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 55 IC62VV5128L-55TI IC62VV5128L-55HI IC62VV5128L-55BI 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 70 IC62VV5128L-70T IC62VV5128L-70H IC62VV5128L-70B 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 70 IC62VV5128L-70TI IC62VV5128L-70HI IC62VV5128L-70BI 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 100 IC62VV5128L-100T IC62VV5128L-100H IC62VV5128L-100B 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 100 IC62VV5128L-100TI IC62VV5128L-100HI IC62VV5128L-100BI 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA ORDERING INFORMATION Commercial Range: 0°C to +70°C Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 55 IC62VV5128LL-55T IC62VV5128LL-55H IC62VV5128LL-55B 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 55 IC62VV5128LL-55TI IC62VV5128LL-55HI IC62VV5128LL-55BI 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 70 IC62VV5128LL-70T IC62VV5128LL-70H IC62VV5128LL-70B 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 70 IC62VV5128LL-70TI IC62VV5128LL-70HI IC62VV5128LL-70BI 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 100 IC62VV5128LL-100T IC62VV5128LL-100H IC62VV5128LL-100B 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA 100 IC62VV5128LL-100TI IC62VV5128LL-100HI IC62VV5128LL-100BI 8*20mmTSOP-1 8*13.4mmTSOP-1 6*8mmTF-BGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 11