SN54/74LS669 SYNCHRONOUS 4-BIT UP/DOWN COUNTER The SN54 / 74LS669 is a synchronous 4-bit up/down counter. The LS669 is a 4-bit binary counter. For high speed counting applications, this presettable counter features an internal carry lookahead for cascading purposes. By clocking all flip-flops simultaneously so the outputs change coincident with each other (when instructed to do so by the count enable inputs and internal gating) synchronous operation is provided. This helps to eliminate output counting spikes, normally associated with asynchronous (ripple-clock) counters. The four master-slave flip-flops are triggered on the rising (positive-going) edge of the clock waveform by a buffered clock input. Circuitry of the load inputs allows loading with the carry-enable output of the cascaded counters. Because loading is synchronous, disabling of the counter by setting up a low level on the load input will cause the outputs to agree with the data inputs after the next clock pulse. Cascading counters for N-bit synchronous applications are provided by the carry look-ahead circuitry, without additional gating. Two count-enable inputs and a carry output help accomplish this function. Count-enable inputs (P and T) must both be low to count. The level of the up-down input determines the direction of the count. When the input level is low, the counter counts down, and when the input is high, the count is up. Input T is fed forward to enable the carry output. The carry output will now produce a low level output pulse with a duration ≈ equal to the high portion of the QA output when counting up and when counting down ≈ equal to the low portion of the QA output. This low level carry pulse may be utilized to enable successive cascaded stages. Regardless of the level of the clock input, transitions at the P or T inputs are allowed. By diode-clamping all inputs, transmission line effects are minimized which allows simplification of system design. Any changes at control inputs (ENABLE P, ENABLE T, LOAD, UP/ DOWN) will have no effect on the operating mode until clocking occurs because of the fully independant clock circuits. Whether enabled, disabled, loading or counting, the function of the counter is dictated entirely by the conditions meeting the stable setup and hold times. • • • • • • SYNCHRONOUS 4-BIT UP/DOWN COUNTER LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 16 1 16 1 SN54LSXXXJ SN74LSXXXN SN74LSXXXD CONNECTION DIAGRAM (TOP VIEW) RIPPLE QA CARRY OUTPUT UP/DOWN 1 U/D OUTPUTS ENABLE T LOAD QB QC QD 13 12 11 QB QC QD ENABLE T LOAD ENABLE D P CK A B C 2 CK 3 A 4 B 5 C 10 9 8 6 7 D ENABLE GND P DATA INPUTS FAST AND LS TTL DATA 5-1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION Programmable Look-Ahead Up/ Down Binary/ Decade Counters Fully Synchronous Operation for Counting and Programming Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Fully Independent Clock Circuit Buffered Outputs RIPPLE CARRY VCC OUTPUT QA 16 15 14 N SUFFIX PLASTIC CASE 648-08 Ceramic Plastic SOIC SN54/74LS669 LOGIC DIAGRAM (3) DATA (4) DATA (5) DATA (6) DATA P0 P1 P2 P3 (9) LOAD (7) ENP (10) ENT (1) U/D RCO (15) (RIPPLE CARRY OUTPUT) (2) CP CP D CP D QA (14) QB (13) CP D CP QC (12) D QD (11) GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/74LS669 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol Min P Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage Typ Max 2.0 Output HIGH Voltage VOL Output LOW Voltage IIH Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current V Guaranteed Input p LOW Voltage g for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 – 0.65 3.5 – 1.5 V 74 2.7 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH or VIL per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA Others 20 µA Enable T 40 µA Others 0.1 mA Enable T 0.2 mA Others –0.4 mA Enable T –0.8 mA – 100 mA VCC = MAX 34 mA VCC = MAX Max U i Unit I Input HIGH C Current IIL Guaranteed Input HIGH Voltage for All Inputs 0.8 74 T Test C Conditions di i V 0.7 54 VOH U i Unit – 20 VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX MAX, VIN = 2 2.7 7V VCC = MAX MAX, VIN = 7 7.0 0V VCC = MAX MAX, VIN = 0 0.4 4V Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits S b l Symbol P Parameter Min Typ 25 32 fMAX Maximum Clock Frequency tPLH tPHL Propagation Delay, Clock to RCO 26 40 40 60 ns tPLH tPHL Propagation Delay, Clock to Any Q 18 18 27 27 ns tPLH tPHL Enable to RCO 11 29 17 45 ns tPLH tPHL U/D to RCO 22 26 35 40 ns Max U i Unit T Test C Conditions di i MHz CL = 15 pF F AC SETUP REQUIREMENTS (TA = 25°C) Limits S b l Symbol P Parameter Min Typ tW Clock Pulse Width 20 ns ts Data Setup Time 20 ns ts Enable Setup Time 35 ns ts Load Setup Time 25 ns ts U/D Setup Time 30 ns th Hold Time, Any Input 0 ns FAST AND LS TTL DATA 5-3 T Test C Conditions di i VCC = 5 5.0 0V SN54/74LS669 PARAMETER MEASUREMENT INFORMATION tw(clock) CLOCK INPUT tw(clock) 3V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 0V ts ts LOAD INPUT th 1.3 V 3V 1.3 V 0V ts th 3V DATA INPUTS A,B,C, and D 1.3 V 1.3 V 0V th ts 1.3 V ENABLE P or ENABLE T 0V 1.3 V 3V ts 1.3 V UP/DOWN INPUT ts th 1.3 V th 1.3 V 3V 1.3 V 0V VOLTAGE WAVEFORMS 3V ENABLE T INPUT 1.3 V 1.3 V 0V tPHL tPLH VOL RIPPLE CARRY OUTPUT 1.3 V 1.3 V VOH FAST AND LS TTL DATA 5-4