NM93CS06L/CS46L/CS56L/CS66L 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) and Data Protect (MICROWIRE TM Bus Interface) General Description The NM93CS06L/CS46L/CS56L/CS66L devices are 256/1024/2048/4096 bits, respectively, of non-volatile electrically erasable memory divided into 16/64/128/256 x 16-bit registers (addresses). The NM93CSxxL Family functions in an extended voltage operating range, and is fabricated using National Semiconductor’s floating gate CMOS technology for high reliability, high endurance and low power consumption. N registers (N s 16, N s 64, N s 128, N s 256) can be protected against data modification by programming the Protect Register with the address of the first register to be protected against data modification. (All registers greater than, or equal to, the selected address are then protected from further change.) Additionally, this address can be ‘‘locked’’ into the device, making all future attempts to change data impossible. These devices are available in both SO and TSSOP packages for small space considerations. The serial interface that controls these EEPROMs is MICROWIRE compatible, providing simple interfacing to standard microcontrollers and microprocessors. There are a total of 10 instructions, 5 which operate on the EEPROM memory and 5 which operate on the Protect Register. The memory instructions are READ, WRITE, WRITE ALL, WRITE ENABLE, and WRITE DISABLE. The Protect register instructions are PRREAD, PRWRITE, PRCLEAR, PRDISABLE and PRENABLE. Features Y Y Y Y Y Y Y Y Y Y Y Y Sequential register read Write protection in a user defined section of memory 2.7V to 5.5V operating range in all modes Typical active current of 200 mA; typical standby current of 1 mA No erase required before write Reliable CMOS floating gate technology MICROWIRE compatible serial I/O Self timed write cycle Device status during programming mode 40 year data retention Endurance: 106 data changes Packages Available: 8-pin SO, 8-pin DIP, and 8-pin TSSOP Block Diagram TL/D/10044 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. MICROWIRETM is a trademark of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/D/10044 RRD-B30M126/Printed in U. S. A. http://www.national.com NM93CS06L/CS46L/CS56L/CS66L 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) and Data Protect (MICROWIRE Bus Interface) August 1996 Connection Diagrams Pin Names Dual-In-Line Package (N) 8-Pin SO Package (M8) and 8-Pin TSSOP Package (MT8) CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND TL/D/10044–2 PE Top View See NS Package Number N08E (N) See NS Package Number M08A (M8) See NS Package Number MTC08 (MT8) Ground Program Enable PRE Protect Register Enable VCC Power Supply Ordering Information Commercial Temp. Range (0§ C to a 70§ C) Order Number NM93CS06LN/NM93CS46LN/NM93CS56LN/NM93CS66LN NM93CS06LM8/NM93CS46LM8/NM93CS56LM8/NM93CS66LM8 NM93CS46LMT8/NM93CS56LMT8/NM93CS66LMT8 Extended Temp. Range (b40§ C to a 85§ C) Order Number NM93CS06LEN/NM93CS46LEN/NM93CS56LEN/NM93CS66LEN NM93CS06LEM8/NM93CS46LEM8/NM93CS56LEM8/NM93CS66LEM8 NM93CS46LEMT8/NM93CS56LEMT8/NM93CS66LEMT8 Automotive Temp. Range (b40§ C to a 125§ C) Order Number NM93CS06LVN/NM93CS46LVN/NM93CS56LVN/NM93CS66LVN NM93CS06LVM8/NM93CS46LVM8/NM93CS56LVM8/NM93CS66LVM8 NM93CS46LVMT8/NM93CS56LVMT8/NM93CS66LVMT8 http://www.national.com 2 Absolute Maximum Ratings Operating Conditions (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Ambient Operating Temperature NM93CSxxL NM93CSxxLE Ambient Storage Temperature Power Supply (VCC) Range Read Mode WRALL Bulk Programming All Other Modes All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 sec.) ESD rating b 65§ C to a 150§ C a 6.5V to b 0.3V a 300§ C 0§ C to a 70§ C b 40§ C to a 85§ C 2.0V to 5.5V 3.0V to 5.5V 2.5V to 5.5V 2000V DC and AC Electrical Characteristics: 2V k VCC k 4.5V Max Units ICCA Symbol Operating Current Parameter CS e VIH, SK e 250 kHz Conditions Min 1 mA ICCS Standby Current CS e VIL 50 mA IIL IOL Input Leakage Output Leakage VIN e 0V to VCC (Note 4) g1 mA VIL VIH Input Low Voltage Input High Voltage 0.15 VCC VCC a 1 V VOL VOH Output Low Voltage Output High Voltage IOL e 10 mA IOH e b10 mA fSK SK Clock Frequency (Note 5) tSKH SK High Time tSKL SK Low Time tSKS SK Setup Time SK must be at VIL for tSKS before CS goes high tCS Minimum CS Low Time (Note 2) tCSS b 0.1 0.8 VCC 0.1 VCC V 250 kHz 0.9 VCC 0 1 ms 1 ms 0.2 ms 1 ms CS Setup Time 0.2 ms tPRES PRE Setup Time 0.2 ms tPES PE Setup Time 0.2 ms tDIS DI Setup Time 0.4 ms tDH DO Hold Time 70 ns tCSH CS Hold Time 0 ms tPEH PE Hold Time 0.4 ms tPREH PRE Hold Time 0.4 ms tDIH DI Hold Time 0.4 tPD1 Output Delay to ‘‘1’’ tPD0 tSV tDF CS to DO in TRI-STATEÉ tWP Write Cycle Time ms 2 ms Output Delay to ‘‘0’’ 2 ms CS to Status Valid 1 ms 0.4 ms 15 ms CS e VIL 3 http://www.national.com DC and AC Electrical Characteristics: 4.5V k VCC k 5.5V Max Units ICCA Symbol Operating Current CMOS Input Levels Parameter CS e VIH, SK e 1.0 MHz 1 mA ICCS Standby Current CS e VIL 50 mA IIL IOL Input Leakage Output Leakage VIN e 0V to VCC g1 mA VIL VIH Input Low Voltage Input High Voltage 0.8 VCC a 1 V VOL1 VOH1 Output Low Voltage Output High Voltage IOL e 2.1 mA IOL e 400 mA 2.4V VOL2 VOH2 Output Low Voltage Output High Voltage IOL e 10 mA IOL e b10 mA VCCb0.2 fSK SK Clock Frequency tSKH SK High Time tSKL SK Low Time tSKS SK Setup Time SK must be at VIL for tSKS before CS goes High tCS Minimum CS Low Time (Note 2) 250 tCSS CS Setup Time 50 ns tPRES PRE Setup Time 50 ns tDH DO Hold Time 70 ns tPES PE Setup Time 50 ns tDIS DI Setup Time 100 ns tCSH CS Hold Time 0 ns tPEH PE Hold Time 250 ns tPREH PRE Hold Time 50 ns tDIH DI Hold Time 20 tPD1 Output Delay to ‘‘1’’ 500 ns tPD0 Output Delay to ‘‘0’’ 500 ns tSV CS to Status Valid 500 ns tDF CS to DO in TRI-STATE 100 ns tWP Write Cycle Time 10 ms http://www.national.com Part Number Conditions Min (Note 4) b 0.1 2 (Note 5) NM93CS06L-NM93CS66L NM93CS06LE-NM93CS66LE CS e VIL 4 0.4 0.2 0 1 V V MHz 250 300 ns 250 ns 50 ns ns ns Capacitance (Note 3) TA e 25§ C f e 1 MHz Test Max Units COUT Symbol Output Capacitance 5 pF CIN Input Capacitance 5 pF Note 1: Stress ratings above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle (This is shown in the opcode diagrams in the following pages). Note 3: This parameter is periodically sampled and not 100% tested. Note 4: Typical leakage values are in the 20 nA range. Note 5: The shortest allowable SK clock period e 1/fSK (as shown under the fSK parameter). Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not allowable to set 1/fSK e tSKH (minimum) a tSKL (minimum) for shorter SK cycle time operation, AC Test Conditions VIL/VIH Input Levels VIL/VIH Timing Level VOL/VOH Timing Level IOL/IOH 2.0V s VCC k 4.5V (Extended Voltage Levels) 0.3V/1.8V 1.0V 0.8V/1.5V g 10 mA 4.5V s VCC s 5.5V (TTL Levels) 0.4V/2.4V 1.0V/2.0V 0.4V/2.4V b 2.1 mA/0.4 mA VCC Range Output Load: 1 TTL Gate (CL e 100 pF) 5 http://www.national.com Functional Description The extended voltage EEPROMs of the NM93CSxxL Family have 10 instructions as described below. Note that MSB of any instruction is a ‘‘1’’ and is viewed as a start bit in the interface sequence. For the CS06 and CS46 the next 8 bits carry the opcode and the 6-bit address for register selection. For the CS56 and CS66, the next 10 bits carry the opcode and the 8-bit address for register selection. All Data In signals are clocked into the device on the low-to-high SK transition. Protect Register Read (PRREAD): The PRREAD instruction outputs the address stored in the Protect Register on the DO pin. The PRE pin MUST be held high while loading the instruction sequence. Following the PRREAD instruction the 6- or 8-bit address stored in the memory protect register is transferred to the serial out shift register. As in the READ mode, a dummy bit (logical 0) precedes the 6- or 8-bit address string. Protect Register Enable (PREN): The PREN instruction is used to enable the PRCLEAR, PRWRITE, and PRDS modes. Before the PREN mode can be entered, the part must be in the Write Enable (WEN) mode. Both the PRE and PE pins MUST be held high while loading the instruction sequence. Note that a PREN instruction must immediately precede a PRCLEAR, PRWRITE, or PRDS instruction. Read and Sequential Register Read (READ): The READ instruction outputs serial data on the D0 pin. After a READ instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output string. Output data changes are initiated by a low to high transition of the SK clock. In the Sequential Read mode of operation, the memory automatically cycles to the next register after each 16 data bits are clocked out. The dummy-bit is suppressed in this mode and a continuous string of data is obtained. Protect Register Clear (PRCLEAR): The PRCLEAR instruction clears the address stored in the Protect Register and therefore enables all registers for the WRITE and WRALL instruction. The PRE and PE pins must be held high while loading the instruction sequence; however, after loading the PRCLEAR instruction, the PRE and PE pins become ‘‘don’t care’’. Note that a PREN instruction must immediately precede a PRCLEAR instruction. Please note that the PRCLEAR instruction and the PRWRITE instruction will both program the Protect Register with all 1s. However, the PRCLEAR instruction will allow the LAST register to be programmed, whereas the PRWRITE instruction e all 1s will PREVENT the last register from being programmed. In addition, the PRCLEAR instruction will allow the use of the WRALL command, where the PRWRITE e all 1s will lock out the Bulk programming opcode. Write Enable (WEN): When VCC is applied to the part, it ‘‘powers up’’ in the Write Disable (WDS) state. Therefore, all programming modes must be preceded by a Write Enable (WEN) instruction. Once a Write Enable instruction is executed, programming remains enabled until a Write Disable (WDS) instruction is executed or VCC is removed from the part. Write (WRITE): The WRITE instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data is allocated to the data-in (DI) pin, CS must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The PE pin MUST be held high while loading the WRITE instruction; however, after loading the WRITE instruction, the PE pin becomes a ‘‘don’t care’’. The D0 pin indicates the READY/ BUSY status of the chip if CS is brought high after the tCS internal. D0 e logical 0 indicates that programming is still in progress. D0 e logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and that the part is ready for another instruction. Protect Register Write (PRWRITE): The PRWRITE instruction is used to write into the Protect Register the address of the first register to be protected. After the PRWRITE instruction is executed, all memory registers whose addresses are greater than or equal to the address specified in the Protect Register are protected from the WRITE operation. Note that before executing a PRWRITE instruction, the Protect Register must first be cleared by executing a PRCLEAR operation and the PRE and PE pins must be held high while loading the instruction; however, after loading the PRWRITE instruction, the PRE and PE pins become ‘‘don’t care’’. Note that a PREN instruction must immediately precede a PRWRITE instruction. Write All (WRALL): The WRALL instruction is valid only when the Protect Register has been cleared by executing a PRCLEAR instruction. The WRALL instruction will simultaneously program all registers with the data pattern specified in the instruction. Like the WRITE instruction, the PE pin MUST be held high while loading the WRALL instruction; however, after loading the WRITE instruction, the PE pin becomes a ‘‘don’t care’’. As in the WRITE mode, the DO pin indicates the READY/ BUSY status of the chip if CS is brought high after the tCS interval. This function is DISABLED if the protect register is in use to lock out a section memory. Protect Register Disable (PRDS): The PRDS instruction is a ONE TIME ONLY instruction which renders the Protect Register unalterable in the future. Therefore, the specified registers become PERMANENTLY protected against data changes. As in the PRWRITE instruction the PRE and PE pins must be held high while loading the instruction, and after loading the PRDS instruction the PRE and PE pins become ‘‘don’t care’’. Note that a PREN instruction must immediately precede a PRDS instruction. Write Disable (WDS): To protect against accidental data disturb, the WDS instruction disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent of both the WEN and WDS instructions. Note: For all protect register operations: If the PRE pin is not held at VIH, all instructions will be applied to the EEPROM array, rather than the Protect Register. http://www.national.com 6 Instruction Set for the NM93CS06L and NM93CS46L SB Op Code Address READ Instruction 1 10 A5–A0 Data PRE PE Comments 0 X Reads data stored in memory, starting at specified address. WEN 1 00 11XXXX WRITE 1 01 A5–A0 D15–D0 0 1 Enable all programming modes. 0 1 WRALL 1 00 01XXXX D15–D0 Writes address if unprotected. 0 1 Writes all registers. Valid only when Protect Register is cleared. WDS 1 00 PRREAD 1 10 00XXXX 0 X Disables all programming modes. XXXXXX 1 X PREN 1 00 Reads address stored in Protect Register. 11XXXX 1 1 Must immediately precede PRCLEAR, PRWRITE, and PRDS instructions. PRCLEAR 1 11 111111 1 1 Clears the Protect Register so that no registers are protected from WRITE. PRWRITE 1 01 A5–A0 1 1 Programs address into Protect Register. Thereafter, memory addresses t the address in Protect Register are protected from WRITE. PRDS 1 00 000000 1 1 ONE TIME ONLY instruction after which the address in the Protect Register cannot be altered. Note: Address bits A5 and A4 become ‘‘Don’t Care’’ for the NM93CS06L. Instruction Set for the NM93CS56L and NM93CS66L SB Op Code Address PRE PE Comments READ Instruction 1 10 A7–A0 Data 0 X Reads data stored in memory, starting at specified address. WEN 1 00 11XXXXXX 0 1 Enable all programming modes. WRITE 1 01 A7–A0 D15– D0 0 1 Writes address if unprotected. WRALL 1 00 01XXXXXX D15– D0 0 1 Writes all registers. Valid only when Protect Register is cleared. WDS 1 00 00XXXXXX 0 X Disables all programming modes. PRREAD 1 10 XXXXXXXX 1 X Reads address stored in Protect Register. PREN 1 00 11XXXXXX 1 1 Must immediately precede PRCLEAR, PRWRITE, and PRDS instructions. PRCLEAR 1 11 11111111 1 1 Clears the ‘‘protect register’’ so that no registers are protected from WRITE. PRWRITE 1 01 A7–A0 1 1 Programs address into Protect Register. Thereafter, memory addresses t the address in Protect Register are protected from WRITE. PRDS 1 00 00000000 1 1 ONE TIME ONLY instruction after which the address in the Protect Register cannot be altered. Note: Address bit A7 becomes ‘‘Don’t Care’’ for the NM93CS56L. 7 http://www.national.com Timing Diagrams Synchronous Data Timing TL/D/10044 – 15 READ: PRE e 0, PE e X TL/D/10044 – 5 ² The memory automatically cycles to the next register. http://www.national.com 8 Timing Diagrams (Continued) WEN: PRE e 0, D0 e TRI-STATE TL/D/10044 – 6 WDS: PRE e 0, PE e X, DO e TRI-STATE TL/D/10044 – 7 WRITE: PRE e 0 TL/D/10044 – 8 9 http://www.national.com Timing Diagrams (Continued) WRALL: PRE e 0 (PROTECT REGISTER MUST BE CLEARED) TL/D/10044 – 9 PRREAD: PE e X TL/D/10044 – 10 http://www.national.com 10 Timing Diagrams (Continued) PREN: D0 e TRI-STATE (A WEN CYCLE MUST PRECEDE A PREN CYCLE) TL/D/10044 – 11 PRCLEAR: (A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRCLEAR CYCLE) TL/D/10044 – 12 11 http://www.national.com Timing Diagrams (Continued) PRWRITE: (A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRWRITE CYCLE. TL/D/10044 – 13 PRDS: (ONE TIME ONLY INSTRUCTION. A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRDS CYCLE.) TL/D/10044 – 14 http://www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted Molded Small Out-Line Package (M8) NS Package Number M08A Notes: Unless otherwise specified. 1. Reference JEDEC Registration M0-153, Variation AA. Dated 7/93. 8-Pin Molded TSSOP, JEDEC (MT8) NS Package Number MTC08 13 http://www.national.com NM93CS06L/CS46L/CS56L/CS66L 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) and Data Protect (MICROWIRE Bus Interface) Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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