Catalyst CAT24C03WI-T 2-kb i2c cmos serial eeprom with partial array write protection Datasheet

CAT24C03
2-Kb I2C CMOS Serial EEPROM with Partial Array Write Protection
FEATURES
DEVICE DESCRIPTION
■ Supports Standard and Fast I2C Protocol
The CAT24C03 is a 2-Kb Serial CMOS EEPROM,
internally organized as 16 pages of 16 bytes each, for
a total of 256 bytes of 8 bits each.
■ 1.8 V to 5.5 V Supply Voltage Range
■ 16-Byte Page Write Buffer
It features a 16-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
■ Hardware Write Protection for upper half of
memory
■ Schmitt Triggers and Noise Suppression Filters
Write operations can be inhibited by taking the WP pin
High (this protects the upper half of the memory).
on I2C Bus Inputs (SCL and SDA).
■ Low power CMOS technology
The CAT24C03 is available in RoHS compliant “Green”
and “Gold” 8-lead PDIP, SOIC, TSSOP and TDFN
packages.
■ 1,000,000 program/erase cycles
■ 100 year data retention
“
”&“
”
8-pin PDIP, SOIC, TSSOP and TDFN packages
■ RoHS compliant
■ Industrial temperature range
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (W)
TSSOP (Y)
TDFN (VP2)
VCC
A0
1
8
VCC
A1
A2
2
7
WP
3
6
SCL
VSS
4
5
SDA
SCL
A2, A1, A0
For the location of Pin 1, please consult the
corresponding package drawing.
Device Address
SDA
Serial Data
SCL
Serial Clock
WP
Write Protect
VCC
Power Supply
VSS
Ground
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
SDA
WP
VSS
PIN FUNCTIONS
A0, A1, A2
CAT24C03
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
1
Doc. No. 1113, Rev. A
CAT24C03
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
-65°C to +150°C
Voltage on Any Pin with Respect to Ground(1)
-0.5 V to +6.5 V
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS(2)
Symbol
Parameter
Min
Units
NEND(*)
Endurance
1,000,000
Program/ Erase Cycles
100
Years
TDR
Data Retention
(*) Page Mode, VCC = 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC
Supply Current
ISB
Min
Max
Units
Read or Write at 400 kHz
1
mA
Standby Current
All I/O Pins at GND or VCC
2
μA
IL
I/O Pin Leakage
Pin at GND or VCC
2
μA
VIL
Input Low Voltage
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7 VCC + 0.5
V
VOL1
Output Low Voltage
VCC > 2.5 V, IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
VCC > 1.8 V, IOL = 1.0 mA
0.2
V
Max
Units
-0.5
PIN IMPEDANCE CHARACTERISTICS
TA = 25°C, f = 400 kHz, VCC = 5 V
Symbol
Parameter
Conditions
Min
CIN(2)
SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN(2)
Input Capacitance (other pins)
VIN = 0 V
6
pF
ZWPL
WP Input Low Impedance
VIN < 0.5 V
70
kΩ
ILWPH
WP Input High Leakage
VIN > VCC x 0.7
2
μA
5
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
Doc. No. 1113, Rev. A
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03
A.C. CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
1.8 V - 5.5 V
Symbol
Parameter
Min
Max
2.5 V - 5.5 V
Min
Max
Units
FSCL
Clock Frequency
100
400
kHz
TI(1)
Noise Suppression Time Constant at
SCL, SDA Inputs
0.1
0.1
μs
tAA(2)
SCL Low to SDA Data Out
3.5
0.9
μs
tBUF(1)
Time the Bus Must be Free Before a
New Transmission Can Start
tHD:STA
Start Condition Hold Time
4.7
1.3
μs
4
0.6
μs
tLOW
Clock Low Period
4.7
1.3
μs
tHIGH
Clock High Period
4
0.6
μs
4.7
0.6
μs
tSU:STA
Start Condition Setup Time
tHD:DAT
Data In Hold Time
0
0
μs
tSU:DAT
Data In Setup Time
0.25
0.1
μs
tR(1)
SDA and SCL Rise Time
1
0.3
μs
tF(1)
SDA and SCL Fall Time
0.3
0.3
μs
tSU:STO
Stop Condition Setup Time
4
0.6
μs
0.1
0.1
μs
tDH
Data Out Hold Time
tWR
Write Cycle Time
5
5
ms
Power-up to Ready Mode
1
1
ms
tPU(1), (3)
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) For timing measurements the SDA line capacitance is ~ 100 pF; the SCL input is driven with rise and fall times of < 50 ns; the SDA I/O
is pulled-up by a 3 mA current source; input driving signals swing from 20% to 80% of VCC. Output level reference levels are 30% and
respectively 70% of VCC.
(3) tPU is the delay required from the time VCC is stable until the device is ready to accept commands.
Power-On Reset (POR)
The CAT24C03 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
The CAT24C03 will power up into Standby mode after
VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
The POR circuitry triggers at the minimum VCC level
required for proper initialization of the internal state
machines. The POR trigger level automatically tracks the
internal CMOS device thresholds, and is naturally well
below the minimum recommended VCC supply voltage.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1113, Rev. A
CAT24C03
PIN DESCRIPTION
START
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake-up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby
mode (when following a Read command).
A0, A1 and A2: The Address pins accept the device address. These pins have on-chip pull-down resistors.
WP: The Write Protect input pin inhibits all write operations to the upper half of the memory array, when pulled
HIGH. (locations 80H to FFH)This pin has an on-chip
pull-down resistor.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address are set to 1010, for normal Read/Write operations (Figure 2). The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices. The last bit, R/W,
specifies whether a Read (1) or Write (0) operation is
to be performed.
FUNCTIONAL DESCRIPTION
The CAT24C03 supports the Inter-Integrated Circuit (I2C)
Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by
a Master device, which generates the serial clock and
all START and STOP conditions. The CAT24C03 acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected
to the bus as determined by the device address inputs
A0, A1, and A2.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge the byte address and every data
byte presented in Write mode. In Read mode the Slave
shifts out a data byte, and then releases the SDA line
during the 9th clock cycle. If the Master acknowledges
the data, then the Slave continues transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by sending a STOP to
the Slave. Bus timing is illustrated in Figure 4.
I2C BUS PROTOCOL
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1).
Doc. No. 1113, Rev. A
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03
Figure 1. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 2. Slave Address Bits
1
0
1
A2
0
A1
A0
R/W
DEVICE ADDRESS
Figure 3. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 4. Bus Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1113, Rev. A
CAT24C03
WRITE OPERATIONS
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, byte address and data to be written
(Figure 5). The Slave acknowledges all 3 bytes, and the
Master then follows up with a STOP, which in turn starts
the internal Write operation (Figure 6). During internal
Write, the Slave will not acknowledge any Read or Write
request from the Master.
Page Write
The CAT24C03 contains 256 bytes of data, arranged
in 16 pages of 16 bytes each. A page is selected by the
4 most significant bits of the address byte following the
Slave address, while the 4 least significant bits point to
the byte within the page. Up to 16 bytes can be written
in one Write cycle (Figure 7).
The internal byte address counter is automatically incremented after each data byte is loaded. If the Master
transmits more than 16 data bytes, then earlier bytes will
be overwritten by later bytes in a ‘wrap-around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT24C03 is busy writing or is ready to accept commands. Polling is implemented by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS).
The CAT24C03 will not acknowledge the Slave address,
as long as internal Write is in progress.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation
of the CAT24C03.
Doc. No. 1113, Rev. A
6
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03
Figure 5. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS
SLAVE
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
A
C
K
A
C
K
Figure 6. Write Cycle Timing
SCL
8th Bit
Byte n
SDA
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n+1
DATA n
S
T
O
P
DATA n+P
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc No. 1113, Rev. A
CAT24C03
READ OPERATIONS
Immediate Address Read
In standby mode, the CAT24C03 internal address counter
points to the data byte immediately following the last byte
accessed by a previous operation. If that ‘previous’ byte
was the last byte in memory, then the address counter
will point to the 1st memory byte, etc.
When, following a START, the CAT24C03 is presented
with a Slave address containing a ‘1’ in the R/W bit
position (Figure 8), it will acknowledge (ACK) in the 9th
clock cycle, and will then transmit data being pointed
at by the internal address counter. The Master can stop
further transmission by issuing a NoACK, followed by a
STOP condition.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address counter. The address counter can be initialized by performing
a ‘dummy’ Write operation (Figure 9). Here the START
is followed by the Slave address (with the R/W bit set
to ‘0’) and the desired byte address. Instead of following up with data, the Master then issues a 2nd START,
followed by the ‘Immediate Address Read’ sequence,
as described earlier.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAT24C03, then the device will continue transmitting as long as each data byte is acknowledged by
the Master (Figure 10). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap-around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting
byte address.
Doc. No. 1113, Rev. A
8
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03
Figure 8. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
N
O
A
C
K
8
SCL
9
8th Bit
SDA
DATA OUT
NO ACK
STOP
Figure 9. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
A
R
T
BYTE
ADDRESS (n)
SLAVE
ADDRESS
S
T
O
P
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
DATA n
N
O
A
C
K
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
S
T
O
P
DATA n+x
DATA n+2
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc No. 1113, Rev. A
CAT24C03
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
A1
L
e
eB
b2
b
SYMBOL
MIN
A
A1
A2
b
b2
D
D2
E
E1
e
eB
L
0.120
0.015
0.115
0.014
0.045
0.355
0.300
0.300
0.240
0.115
NOM
MAX
0.210
0.130
0.018
0.060
0.365
0.310
0.250
0.100 BSC
0.130
0.195
0.022
0.070
0.400
0.325
0.325
0.280
0.430
0.150
Notes:
1. Complies with JEDEC Standard MS001.
2. All dimensions are in inches.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
Doc. No. 1113, Rev. A
10
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03
8-LEAD 150 MIL WIDE SOIC (W)
E1
E
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
A1
A2
b
C
D
E
E1
e
f
θ1
0.0040
0.0532
0.013
0.0075
0.1890
02284
0.149
NOM
MAX
0.0098
0.0688
0.020
0.0098
0.1968
0.2440
0.1574
0.050 BSC
0.0099
0°
0.0196
8°
Notes:
1. Complies with JEDEC specification MS-012 dimensions.
2. All linear dimensions in millimeters.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc No. 1113, Rev. A
CAT24C03
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
4
1
PIN #1 IDENT.
0.25
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
θ1
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.50
0.00
NOM
0.90
3.00
6.4
4.40
0.65 BSC
0.60
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.75
8.00
Notes:
1.
All dimensions in millimeters.
Doc. No. 1113, Rev. A
12
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03
8-PAD TDFN 2X3 PACKAGE (VP2)
A
E
PIN 1 INDEX AREA
A1
D
D2
A2
A3
SYMBOL
MIN
NOM
MAX
A
A1
A2
A3
b
D
D2
E
E2
e
L
0.70
0.00
0.45
0.75
0.02
0.55
0.20 REF
0.25
2.00
1.40
3.00
1.30
0.50 TYP
0.30
0.80
0.05
0.65
0.20
1.90
1.30
2.90
1.20
0.20
E2
0.30
2.10
1.50
3.10
1.40
PIN 1 ID
L
0.40
b
e
3xe
NOTE:
1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMNALS. COPLANARITY SHALL NOT EXCEED 0.08 mm.
3. WARPAGE SHALL NOT EXCEED 0.10 mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC.
5. REFER JEDEC MO-229.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc No. 1113, Rev. A
CAT24C03
ORDERING INFORMATION
Prefix
CAT
Company ID
Device #
24C03
Product
Number
Suffix
Y
I
–
GT3
Temperature Range
I = Industrial (-40°C to +85°C)
Package
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
VP2: TDFN (Lead-free, Halogen-free)
Lead Finish/Tape & Reel
G: NiPdAu Lead Plating
T: Tape & Reel
3: 3000/Reel
Notes:
(1) The device used in the above example is a CAT24C03YI-GT3 (TSSOP, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
(2) For additional package and temperature options, please contact your nearest Catalyst Semiconductor sales office.
Doc. No. 1113, Rev. A
14
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03
PACKAGE MARKING
8-Lead PDIP
8-Lead SOIC
24C03LI
YYWWG
CSI
24C03L
I
YY
WW
G
24C03WI
YYWWG
= Catalyst Semiconductor, Inc.
= Device Code
= Temperature Range
= Production Year
= Production Week
= Product Revision
CSI
24C03W
I
YY
WW
G
8-Lead TSSOP
= Catalyst Semiconductor, Inc.
= Device Code
= Temperature Range
= Production Year
= Production Week
= Product Revision
8-Lead TDFN
YMG
EMN
24C03I
NNN
YM
Y
M
G
24C03
I
= Production Year
= Production Month
= Die Revision
= Device Code
= Industrial Temperature Range
E M = Device Code
N = Traceability Code
Y = Production Year
M = Production Month
Notes:
(1) The circle on the package marking indicates the location of Pin 1.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc No. 1113, Rev. A
CAT24C03
TAPE AND REEL
Direction of Feed
Device Orientation
SPROKET HOLE
TOP COVER
TAPE THICKNESS (t1)
0.10mm (0.004) MAX THICK
DEVICE ORIENTATION
EMBOSSED
CARRIER
PIN 1
EMBOSSMENT
PIN 1
TDFN
Reel Dimensions(1)
40mm (1.575) MIN.
ACCESS HOLE
AT SLOT LOCATION
PIN 1
SOIC
TSSOP
T
B*
A
D*
C
FULL RADIUS*
N
TAPE SLOT IN CORE
FOR TAPE START.
2.5mm (0.098) MIN WIDTH
10mm (0.394) MIN DEPTH
* DRIVE SPOKES OPTIONAL, IF USED
ASTERISKED DIMENSIONS APPLY.
G (MEASURED AT HUB)
Embossed Carrier Dimensions
A
Tape
Size
Max
8MM
12MM
Qty/Reel
330
(13.00)
3000
B Min
1.5
(0.059)
C
D* Min
12.80 (0.504)
13.20 (0.5200)
20.2
(0.795)
N Min
50
(1.969)
G
T Max
8.4 (0.328)
9.9 (1.389)
14.4
(0.566)
12.4 (0.488)
14.4 (0.558)
18.4
(0.724)
Embossed Carrier Dimensions
Component
Package Type
Tape Size (W)
Part Pitch (P)
8L SOIC
W, Y
12mm
8mm
8L TDFN 2x3mm
VP2
8mm
4mm
Note:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
Doc. No. 1113, Rev. A
16
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03
Embossed Carrier Dimensions (12 Tape Only)
K
D
T
10 PITCHES
CUMULATIVE TOLERANCE
ON TAPE 0.2mm( 0.008)
P0
P2
TOP
COVER
TAPE
E
(2)
A0
(2)
K0
B1
F
W
B0
P
CENTER LINES
OF CAVITY
EMBOSSMENT
FOR MACHINE REFERENCE ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC ABOUT B0
D1
FOR COMPONENTS
2.0mm X 1.2mm
AND LARGER
USER DIRECTION OF FEED
Embossed Tape—Constant Dimensions (1)
Tape Sizes
D
E
P0
T Max.
D1 Min.
12mm
1.5 (0.059)
1.6 (0.063)
1.65 (0.065)
1.85 (0.073)
3.9 (0.153)
4.1 (0.161)
400
(0.016)
1.5
(0.059)
A0 B0 K0(2)
Embossed Carrier Dimensions (12 Tape Only)
Tape Sizes
B1 Max.
F
K Max.
P2
R Min.
W
P
12mm
8.2
(0.0323)
5.45 (0.0215)
5.55 (0.219)
4.5
(0.177)
1.95 (0.077)
2.05 (0.081)
30
(1.181)
11.7 (0.460)
12.3 (0.484)
7.9 (0.275)
8.1 (0.355)
Note:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
(2) A0 B0 K0 are determined by component size. The clearance between the component and the cavity must be within 0.05 (0.002) min. to
0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035) max. for 16mm tape, and 0.05 (0.002) min. to 1.00 (0.039) max. for
24mm tape and larger. The component cannot rotate more than 20° within the determined cavity, see Component Rotation.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
17
Doc No. 1113, Rev. A
CAT24C03
REVISION HISTORY
Date
03/08/06
Doc. No. 1113, Rev. A
Revision Comments
A
Initial Issue
18
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03
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© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
19
Doc No. 1113, Rev. A
Catalyst Semiconductor, Inc.
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