LINER LT6660 Easy-to-use, ultra-tiny, differential, 16-bit adc with i2c interface Datasheet

LTC2453
Easy-to-Use, Ultra-Tiny,
Differential, 16-Bit ΔΣ ADC
With I2C Interface
DESCRIPTION
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
±VCC Differential Input Range
16-Bit Resolution (Including Sign), No Missing
Codes
2LSB Offset Error
4LSB Full-Scale Error
60 Conversions Per Second
Single Conversion Settling Time for Multiplexed
Applications
Single-Cycle Operation with Auto Shutdown
800μA Supply Current
0.2μA Sleep Current
Internal Oscillator—No External Components
Required
2-Wire I2C Interface
Ultra-Tiny 3mm × 2mm DFN Package
APPLICATIONS
■
■
■
■
■
■
■
System Monitoring
Environmental Monitoring
Direct Temperature Measurements
Instrumentation
Industrial Process Control
Data Acquisition
Embedded ADC Upgrades
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
The LTC®2453 is an ultra-tiny, fully differential, 16-bit,
analog-to-digital converter. The LTC2453 uses a single
2.7V to 5.5V supply and communicates through an I2C
interface. The ADC is available in an 8-pin, 3mm × 2mm
DFN package. It includes an integrated oscillator that does
not require any external components. It uses a delta-sigma
modulator as a converter core and has no latency for
multiplexed applications. The LTC2453 includes a proprietary input sampling scheme that reduces the average
input sampling current several orders of magnitude lower
than conventional delta-sigma converters. Additionally,
due to its architecture, there is negligible current leakage
between the input pins.
The LTC2453 can sample at 60 conversions per second,
and due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. The LTC2453
includes continuous internal offset and full-scale calibration
algorithms which are transparent to the user, ensuring
accuracy over time and over the operating temperature
range. The converter has external REF+ and REF– pins
and the differential input voltage range can extend up to
±(VREF+ – VREF–).
Following a single conversion, the LTC2453 can automatically enter a sleep mode and reduce its power to less
than 0.2μA. If the user reads the ADC once a second, the
LTC2453 consumes an average of less than 50μW from
a 2.7V supply.
Integral Nonlinearity, VCC = 3V
TYPICAL APPLICATION
2.0
1.5
2.7V TO 5.5V
REF+
0.1μF
IN+
10k
VCC
SCL
10k
LTC2453
IN–
SDA
1.0
10μF
2-WIRE I2C
INTERFACE
INL (LSB)
0.1μF
VCC = 3V
VREF+ = 3V
VREF– = 0V
0.5
TA = –45°C, 25°C, 90°C
0
–0.5
–1.0
10k
R
0.1μF
REF–
GND
–1.5
–2.0
2453 TA01
–3
–2
–1
1
2
0
DIFFERENTIAL INPUT VOLTAGE (V)
3
2453 G02
2453f
1
LTC2453
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VCC) ................................... –0.3V to 6V
Analog Input Voltage (VIN+, VIN–) .. –0.3V to (VCC + 0.3V)
Reference Voltage (VREF+, VREF–) .. –0.3V to (VCC + 0.3V)
Digital Voltage (SDA, SCL) ............ –0.3V to (VCC + 0.3V)
Storage Temperature Range................... –65°C to 150°C
Operating Temperature Range
LTC2453C ................................................ 0°C to 70°C
LTC2453I ............................................. –40°C to 85°C
TOP VIEW
GND 1
8
SDA
REF– 2
7
SCL
6
IN+
5
IN–
9
REF+ 3
VCC 4
DD8 PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
C/I GRADE TJMAX = 125°C, θJA = 76°C/W (NOTE 4)
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2453CDDB#TRMPBF
LTC2453CDDB#TRPBF
LDBQ
8-Lead Plastic (3mm × 2mm) DFN
LTC2453IDDB#TRMPBF
LTC2453IDDB#TRPBF
LDBQ
8-Lead Plastic (3mm × 2mm) DFN
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
0°C to 70°C
–40°C to 85°C
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
(Note 3)
●
Integral Nonlinearity
(Note 4)
●
Offset Error
MIN
●
Offset Error Drift
Gain Error
TYP
MAX
16
Bits
2
10
2
10
0.02
●
UNITS
0.01
LSB
LSB
LSB/°C
0.02
% of FS
Gain Error Drift
0.02
LSB/°C
Transition Noise
1.4
μVRMS
Power Supply Rejection DC
80
dB
2453f
2
LTC2453
ANALOG INPUTS AND REFERENCES
The ● denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
+
Positive Input Voltage Range
–
Negative Input Voltage Range
VIN
CONDITIONS
MIN
TYP
MAX
UNITS
●
0
VCC
V
VCC
V
●
0
VREF+ – VREF– ≥ 2.5V
VREF+ – VREF– ≥ 2.5V
VREF = 5V, VIN– = 2.5V (See Figure 2)
VREF = 5V, VIN+ = 2.5V (See Figure 2)
●
VCC – 2.5
VCC
V
●
0
VCC – 2.5
V
IDC_LEAK(IN+)
IN+ DC Leakage Current
VIN = GND (Note 8)
VIN = VCC (Note 8)
●
●
–10
–10
1
1
10
10
nA
nA
IDC_LEAK(IN–)
IN– DC Leakage Current
VIN = GND (Note 8)
VIN = VCC (Note 8)
●
●
–10
–10
1
1
10
10
nA
nA
VREF = 3V (Note 8)
●
–10
1
10
nA
VIN
VREF+
VREF–
VOR+, VUR+
VOR–, VUR–
Positive Reference Voltage Range
CIN
IN+, IN– Sampling Capacitance
Negative Reference Voltage Range
Overrange/Underrange Voltage, IN+
Overrange/Underrange Voltage, IN–
IDC_LEAK(REF+, REF–) REF+, REF– DC Leakage Current
ICONV
8
LSB
8
LSB
0.35
Input Sampling Current (Note 5)
pF
50
nA
POWER REQUIREMENTS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
VCC
Supply Voltage
●
ICC
Supply Current
Conversion
Sleep
●
●
TYP
2.7
800
0.2
MAX
UNITS
5.5
V
1200
0.6
μA
μA
I2C INPUTS AND OUTPUTS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 2, 7)
SYMBOL
PARAMETER
VIH
High Level Input Voltage
CONDITIONS
●
MIN
TYP
MAX
VIL
Low Level Input Voltage
●
II
Digital Input Current
●
–10
VHYS
Hysteresis of Schmidt Trigger Inputs
(Note 3)
●
0.05VCC
VOL
Low Level Output Voltage (SDA)
I = 3mA
●
0.4
V
IIN
Input Leakage
0.1VCC ≤ VIN ≤ VCC
●
1
μA
CI
Capacitance for Each I/O Pin
●
CB
Capacitance Load for Each Bus Line
●
0.7VCC
UNITS
V
0.3VCC
V
10
μA
V
10
pF
400
pF
2453f
3
LTC2453
I2C TIMING CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
16.6
MAX
UNITS
tCONV
Conversion Time
●
13
fSCL
SCL Clock Frequency
●
0
tHD(SDA)
Hold Time (Repeated) START Condition
●
0.6
μs
tLOW
LOW Period of the SCL Pin
●
1.3
μs
tHIGH
HIGH Period of the SCL Pin
●
0.6
μs
tSU(STA)
Set-Up Time for a Repeated START Condition
●
0.6
μs
tHD(DAT)
Data Hold Time
●
0
tSU(DAT)
Data Set-Up Time
●
100
tr
Rise Time for SDA/SCL Signals
(Note 6)
●
20 + 0.1CB
300
ns
tf
Fall Time for SDA/SCL Signals
(Note 6)
●
20 + 0.1CB
300
ns
23
ms
400
kHz
μs
0.9
ns
tSU(STO)
Set-Up Time for STOP Condition
●
0.6
μs
tBUF
Bus Free Time Between a Stop and Start Condition
●
1.3
μs
tOF
Output Fall Time VIHMIN to VILMAX
●
20 + 0.1CB
tSP
Input Spike Suppression
Bus Load CB 10pF to
400pF (Note 6)
●
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 5V
VREF+ = 5V
VREF– = 0V
1.5
0.5
VCC = 3V
VREF+ = 3V
VREF– = 0V
TA = –45°C, 25°C, 90°C
0
–0.5
0.5
0.5
–1.5
–1.5
5
2453 G01
1.0
–0.5
–1.0
–5 –4 –3 –2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
TA = –45°C, 25°C, 90°C
0
–1.0
–2.0
VCC = VREF+ = 5V, 4.1V, 3V
1.5
1.0
INL (LSB)
INL (LSB)
1.0
ns
Maximum INL vs Temperature
2.0
INL (LSB)
1.5
2.0
50
(TA = 25°C, unless otherwise noted)
Integral Nonlinearity, VCC = 3V
Integral Nonlinearity, VCC = 5V
ns
Note 4. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
Guaranteed by design and test correlation.
Note 5. Input sampling current is the average input current drawn from
the input sampling network while the LTC2453 is converting.
Note 6. CB = capacitance of one bus line in pF.
Note 7. All values refer to VIH(MIN) and VIL(MAX) levels.
Note 8. A positive current is flowing into the DUT pin.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V
unless otherwise specified.
VREF = VREF+ – VREF–, VREFCM = (VREF+ + VREF–)/2, FS = VREF+ – VREF–;
VIN = VIN+ – VIN–, –VREF ≤ VIN ≤ VREF; VINCM = (VIN+ + VIN–)/2.
Note 3. Guaranteed by design, not subject to test.
2.0
250
–2.0
–3
–2
–1
1
2
0
DIFFERENTIAL INPUT VOLTAGE (V)
3
2453 G02
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
2453 G03
2453f
4
LTC2453
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs Temperature
Gain Error vs Temperature
5
Transition Noise vs Temperature
3.0
TRANSITION NOISE RMS (μV)
5
4
4
3
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
(TA = 25°C, unless otherwise noted)
VCC = VREF+ = 3V
VCC = VREF+ = 4.1V
2
1
VCC = VREF+ = 5V
VCC = VREF+ = 3V
3
VCC = VREF+ = 4.1V
2
1
0
VCC = VREF+ = 5V
–1
–50
–25
0
25
50
TEMPERATURE (°C)
75
0
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
2453 G04
VCC = 4.1V
1.5
1.0
VCC = 5V
0
–50
100
VCC = 3V
0.5
–25
0
25
50
TEMPERATURE (°C)
75
3.0
1200
2.5
1000
100
2453 G06
Conversion Mode Power Supply
Current vs Temperature
Sleep Mode Power Supply
Current vs Temperature
250
60Hz OUTPUT SAMPLE RATE
CONVERSION CURRENT (μA)
2.0
1.5
VCC = VREF+ = 5V
1.0
800
–16384
0
16384
OUTPUT CODE
VCC = 3V
600
VCC = 4.1V
400
200
0.5
0
–32768
200
VCC = 5V
0
–50
32768
–25
0
25
50
TEMPERATURE (°C)
75
VCC = 5V
150
100
VCC = 4.1V
50
VCC = 3V
0
–50
100
25Hz OUTPUT SAMPLE RATE
REJECTIOIN (dB)
100
Conversion Time vs Temperature
VCC = 4.1V
VREF+ = 2.7V
VREF– = 0V
VIN+ = 1V
VIN– = 2V
–20
1Hz OUTPUT SAMPLE RATE
75
21
0
10000
100
0
25
50
TEMPERATURE (°C)
2453 G09
Power Supply Rejection vs
Frequency at VCC
Average Power Dissipation vs
Temperature, VCC = 3V
10Hz OUTPUT SAMPLE RATE
–25
2453 G08
2453 G07
1000
SLEEP CURRENT (nA)
VCC = VREF+ = 3V
20
CONVERSION TIME (ms)
TRANSITION NOISE RMS (μV)
2.0
2453 G05
Transition Noise vs Output Code
AVERAGE POWER DISSIPATION (μW)
2.5
–40
–60
10
VCC = 3V
19
VCC = 4.1V
18
VCC = 5V
17
16
–80
15
1
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
2453 G10
–100
1
10
100 1k 10k 100k
FREQUENCY AT VCC (Hz)
1M
10M
2453 G11
14
–50
–25
50
25
0
TEMPERATURE (°C)
75
100
2453 G12
2453f
5
LTC2453
PIN FUNCTIONS
GND (Pin 1): Ground. Connect to a ground plane through
a low impedance connection.
REF– (Pin 2), REF+ (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 2.5V. The differential reference voltage
(VREF = REF+ to REF–) sets the full-scale range.
VCC (Pin 4): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10μF capacitor in parallel with a low-series-inductance 0.1μF capacitor located as close to the
part as possible.
IN– (Pin 5), IN+ (Pin 6): Differential Analog Input.
SCL (Pin 7): Serial Clock Input of the I2C Interface. The
LTC2453 can only act as a slave and the SCL pin only
accepts external serial clock. Data is shifted into the SDA
pin on the rising edges of SCL and output through the
SDA pin on the falling edges of SCL.
SDA (Pin 8): Bidirectional Serial Data Line of the I2C
Interface. The conversion result is output through the
SDA pin. The pin is high impedance unless the LTC2453
is in the data output mode. While the LTC2453 is in the
data output mode, SDA is an open drain pull down (which
requires an external 1.7k pull-up resistor to VCC).
Exposed Pad (Pin 9): Ground. Must be soldered to PCB
ground.
BLOCK DIAGRAM
3
6
IN+
4
REF+
16-BIT ΔΣ
A/D CONVERTER
I2C
INTERFACE
–
5
IN–
VCC
REF–
SDA
7
8
DECIMATING
SINC FILTER
16-BIT ΔΣ
A/D CONVERTER
2
SCL
INTERNAL
OSCILLATOR
1
GND
2453 BD
2453f
6
LTC2453
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2453 is a low-power, fully differential, delta-sigma
analog-to-digital converter with an I2C interface. Its operation, as shown in Figure 1, is composed of three successive
states: CONVERSION, SLEEP and DATA OUTPUT.
Initially, at power up, the LTC2453 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, power consumption is
reduced by several orders of magnitude. The part remains
in the sleep state as long it is not addressed for a read
operation. The conversion result is held indefinitely in a
static shift register while the part is in the sleep state.
POWER-ON RESET
CONVERSION
SLEEP
NO
READ
ACKNOWLEDGE
YES
DATA OUTPUT
NO
STOP
OR READ
16-BITS
YES
2453 F01
Figure 1. LTC2453 State Diagram
The device will not acknowledge an external request during
the conversion state. After a conversion is finished, the
device is ready to accept a read request. The LTC2453’s
address is hard-wired at 0010100. Once the LTC2453 is
addressed for a read operation, the device begins outputting the conversion result under the control of the serial
clock (SCL). There is no latency in the conversion result.
The data output is 16 bits long and contains a 15-bit plus
sign conversion result. Data is updated on the falling
edges of SCL, allowing the user to reliably latch data on
the rising edge of SCL. A new conversion is initiated by
a stop condition following a valid read operation, or by
the conclusion of a complete read cycle (all 16 bits read
out of the device).
Power-Up Sequence
When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When VCC rises above this threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2453 starts
a conversion cycle and follows the succession of states
described in Figure 1. The first conversion result following POR is accurate within the specifications of the
device if the power supply voltage VCC is restored within
the operating range (2.7V to 5.5V) before the end of the
POR time interval.
Ease of Use
The LTC2453 data output has no latency, filter settling delay
or redundant results associated with the conversion cycle.
There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple
analog input voltages requires no special actions.
The LTC2453 performs offset calibrations every conversion. This calibration is transparent to the user and has
no effect upon the cyclic operation described previously. The advantage of continuous calibration is extreme
stability of the ADC performance with respect to time and
temperature.
The LTC2453 includes a proprietary input sampling scheme
that reduces the average input current by several orders
of magnitude when compared to traditional delta-sigma
architectures. This allows external filter networks to interface directly to the LTC2453. Since the average input
sampling current is 50nA, an external RC lowpass filter
using a 1kΩ and 0.1μF results in <1LSB additional error.
Additionally, there is negligible leakage current between
IN+ and IN–.
2453f
7
LTC2453
APPLICATIONS INFORMATION
Reference Voltage Range
I2C INTERFACE
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for
REF+ and REF– pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
VREF+ must be >(2.5V + VREF–).
The LTC2453 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting
multiple devices and masters on a single bus. The connected devices can only pull the data line (SDA) LOW and
never drive it HIGH. SDA must be externally connected to
the supply through a pull-up resistor. When the data line
is free, it is HIGH. Data on the I2C bus can be transferred
at rates up to 100kbits/s in the Standard-Mode and up to
400kbits/s in the Fast-Mode.
The LTC2453 differential reference input range is 2.5V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF– can be shorted to GND.
Input Voltage Range
For most applications, VREF– ≤ (VIN+, VIN–) ≤ VREF+. Under
these conditions the output code is given (see Data Format
section) as 32768 • (VIN+ – VIN–)/(VREF+ – VREF–). The
output of the LTC2453 is clamped at a maximum value of
32767 and clamped at a minimum value of –32768.
The LTC2453 includes a proprietary system that can,
typically, correctly digitize each input 8LSB above VREF+
and below VREF–, if the LTC2453’s output is not clamped.
As an example (Figure 2), if the user desires to measure
a signal slightly below ground, the user could set VIN– =
VREF– = GND, and VREF+ = 5V. If VIN+ = GND, the output
code would be approximately 0. If VIN+ = GND – 8LSB =
–1.22 mV, the output code would be approximately –8.
16
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
12
8
OUTPUT CODE
The LTC2453 can only be addressed as a slave. It can only
transmit the last conversion result. The serial clock line,
SCL, is always an input to the LTC2453 and the serial data
line SDA is bidirectional. Figure 3 shows the definition of
the I2C timing.
The START and STOP Conditions
20
4
0
–4
SIGNALS
BELOW
GND
–8
–12
–16
–20
–0.001
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Devices addressed
by the master are considered a slave. The address of the
LTC2453 is 0010100.
–0.005
0.005
0
VIN+/VREF+
0.001
0.0015
2453 F02
Figure 2. Output Code vs VIN+ with VIN– = 0 and VREF– = 0
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and
is used for reading from the device before the initiation
of a new conversion.
2453f
8
LTC2453
APPLICATIONS INFORMATION
SDA
tf
tSU(DAT)
tr
tLOW
tf
tHD(SDA)
tr
tSP
tBUF
SCL
tHD(STA)
tHD(DAT)
S
tSU(STA)
tHIGH
tSU(STO)
Sr
P
S
2453 F03
Figure 3. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
1
7
8
9
1
2
3
8
D15
D14
D13
D8
SGN
MSB
9
1
2
D7
D6
3
8
9
SCL
SDA
7-BIT
ADDRESS
START BY
MASTER
R
ACK BY
LTC2453
SLEEP
D5
D0
LSB
ACK BY
MASTER
DATA OUTPUT
NACK BY
MASTER
CONVERSION
2453 F04
Figure 4. Read Sequence Timing Diagram
Data Transferring
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NAK) by leaving the
SDA line HIGH impedance (the external pull-up resistor
will hold the line HIGH). Change of data only occurs while
the clock line (SCL) is LOW.
Following the ACK, the LTC2453 can output data. The data
output stream is 16 bits long and is shifted out on the
falling edges of SCL (see Figure 4). The first bit output by
the LTC2453 is the sign, which is 1 for VIN+ ≥ VIN– and 0
for VIN+ < VIN–. The next bit is the MSB (D14) and is followed by successively less significant bits (D13, D12…)
until the LSB is output by the LTC2453. This sequence is
shown in Figure 5.
OPERATION SEQUENCE
Continuous Read
Data Format
After a START condition, the master sends a 7-bit address
followed by a read request (R) bit. The bit R is 1 for a Read
Request. If the 7-bit address matches the LTC2453’s address (hard-wired at 0010100) the ADC is selected. When
the device is addressed during the conversion state, it does
not accept the request and issues a NAK by leaving the
SDA line HIGH. If the conversion is complete, the LTC2453
issues an ACK by pulling the SDA line LOW.
Conversions from the LTC2453 can be continuously
read, see Figure 6. At the end of a read operation, a new
conversion automatically begins. At the conclusion of
the conversion cycle, the next result may be read using
the method described above. If the conversion cycle is
not complete and a valid address selects the device, the
LTC2453 generates a NAK signal indicating the conversion
cycle is in progress.
2453f
9
LTC2453
APPLICATIONS INFORMATION
S
7-BIT ADDRESS
(0010100)
CONVERSION
R
ACK
READ
P
DATA OUTPUT
SLEEP
CONVERSION
2453 F05
Figure 5. The LTC2453 Coversion Sequence
S
CONVERSION
7-BIT ADDRESS
(0010100)
R
ACK
READ
P
DATA OUTPUT
SLEEP
S
7-BIT ADDRESS
(0010100)
CONVERSION
R ACK
READ
DATA OUTPUT
SLEEP
P
CONVERSION
2453 F06
Figure 6. Consecutive Reading at the Same Configuration
S
CONVERSION
7-BIT ADDRESS
(0010100)
SLEEP
R
ACK READ (OPTIONAL)
DATA OUTPUT
P
CONVERSION
2453 F07
Figure 7. Start a New Conversion without Reading Old Conversion Result
Discarding a Conversion Result and Initiating a New
Conversion
It is possible to start a new conversion without reading
the old result, as shown in Figure 7. Following a valid 7-bit
address, a read request (R) bit, and a valid ACK, a STOP
command will start a new conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2453 is designed to dramatically reduce the conversion result’s sensitivity to device decoupling, PCB layout,
antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability
of this part, some simple precautions are desirable.
Digital Signal Levels
Due to the nature of CMOS logic, it is advisable to keep
input digital signals near GND or VCC. Voltages in the
range of 0.5V to VCC – 0.5V may result in additional current leakage from the part.
Driving VCC and GND
In relation to the VCC and GND pins, the LTC2453 combines
internal high frequency decoupling with damping elements,
which reduce the ADC performance sensitivity to PCB
layout and external components. Nevertheless, the very
high accuracy of this converter is best preserved by careful
low and high frequency power supply decoupling.
A 0.1μF, high quality, ceramic capacitor in parallel with a
10μF ceramic capacitor should be connected between the
VCC and GND pins, as close as possible to the package.
The 0.1μF capacitor should be placed closest to the ADC
package. It is also desirable to avoid any via in the circuit
path, starting from the converter VCC pin, passing through
these two decoupling capacitors, and returning to the
converter GND pin. The area encompassed by this circuit
path, as well as the path length, should be minimized.
Very low impedance ground and power planes, and star
connections at both VCC and GND pins, are preferable.
The VCC pin should have three distinct connections: the
2453f
10
LTC2453
APPLICATIONS INFORMATION
VCC
ILEAK
VCC
RSW
15k
(TYP)
RS
REF+
ILEAK
SIG+
VCC
ILEAK
ILEAK
+
–
IN+
ILEAK
CIN
VCC
IN+
ILEAK
RS
IN–
ILEAK
SIG–
VCC
ILEAK
CEQ
0.35pF
(TYP)
CPAR
RSW
15k
(TYP)
CEQ
0.35pF
(TYP)
RSW
15k
(TYP)
IN–
+
–
ILEAK
CIN
CPAR
RSW
15k
(TYP)
ICONV
RSW
15k
(TYP)
CEQ
0.35pF
(TYP)
ICONV
2453 F09
Figure 9. LTC2453 Input Drive Equivalent Circuit
ILEAK
VCC
ILEAK
REF–
package. The 0.1μF capacitor should be placed closest
to the ADC.
RSW
15k
(TYP)
2453 F08
ILEAK
Figure 8. LTC2453 Analog Input/Reference Equivalent Circuit
first to the decoupling capacitors described above, the
second to the ground return for the input signal source,
and the third to the ground return for the power supply
voltage source.
Driving REF+ and REF–
A simplified equivalent circuit for REF+ and REF– is shown
in Figure 8. Like all other A/D converters, the LTC2453 is
only as accurate as the reference it is using. Therefore, it
is important to keep the reference line quiet by careful low
and high frequency power supply decoupling.
The LT6660 reference is an ideal match for driving the
LTC2453’s REF+ pin. The LTC6660 is available in a 2mm ×
2mm DFN package with 2.5V, 3V, 3.3V and 5V options.
A 0.1μF, high quality, ceramic capacitor in parallel with
a 10μF ceramic capacitor should be connected between
the REF+/REF– and GND pins, as close as possible to the
Driving VIN+ and VIN–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 9. The input signal VSIG is
connected to the ADC input pins (IN+ and IN–) through an
equivalent source resistance RS. This resistor includes both
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors CIN are also connected to the ADC input
pins. This capacitor is placed in parallel with the ADC
input parasitic capacitance CPAR. Depending on the PCB
layout, CPAR has typical values between 2pF and 15pF. In
addition, the equivalent circuit of Figure 9 includes the
converter equivalent internal resistor RSW and sampling
capacitor CEQ.
There are some immediate trade-offs in RS and CIN without
needing a full circuit analysis. Increasing RS and CIN can
give the following benefits:
1) Due to the LTC2453’s input sampling algorithm, the
input current drawn by either VIN+ or VIN– over a conversion cycle is 50nA. A high RS • CIN attenuates the
high frequency components of the input current, and
RS values up to 1k result in <1LSB error.
2453f
11
LTC2453
APPLICATIONS INFORMATION
2) The bandwidth from VSIG is reduced at the input pins
(IN+, IN–). This bandwidth reduction isolates the ADC
from high frequency signals, and as such provides
simple antialiasing and input noise reduction.
3) Switching transients generated by the ADC are attenuated before they go back to the signal source.
4) A large CIN gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing RS protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large RS • CIN should be for a given
application. Increasing RS beyond a given point increases
the voltage drop across RS due to the input current,
to the point that significant measurement errors exist.
Additionally, for some applications, increasing the RS • CIN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For most applications, it is desirable to implement CIN as
a high-quality 0.1μF ceramic capacitor and RS ≤ 1k. This
capacitor should be located as close as possible to the
actual VIN package pin. Furthermore, the area encompassed
by this circuit path, as well as the path length, should be
minimized.
In the case of a 2-wire sensor that is not remotely
grounded, it is desirable to split RS and place series
resistors in the ADC input line as well as in the sensor
ground return line, which should be tied to the ADC GND
pin using a star connection topology.
Figure 10 shows the measured LTC2453 INL vs Input
Voltage as a function of RS value with an input capacitor
CIN = 0.1μF.
In some cases, RS can be increased above these guidelines.
The input current is zero when the ADC is either in sleep
or I/O modes. Thus, if the time constant of the input RC
circuit τ = RS • CIN, is of the same order of magnitude or
longer than the time periods between actual conversions,
then one can consider the input current to be reduced
correspondingly.
These considerations need to be balanced out by the input
signal bandwidth. The 3dB bandwidth ≈ 1/(2πRSCIN).
Finally, if the recommended choice for CIN is unacceptable
for the user’s specific application, an alternate strategy is to
eliminate CIN and minimize CPAR and RS. In practical terms,
this configuration corresponds to a low impedance sensor
directly connected to the ADC through minimum length
traces. Actual applications include current measurements
through low value sense resistors, temperature measurements, low impedance voltage source monitoring, and so
on. The resultant INL vs VIN is shown in Figure 11. The
measurements of Figure 11 include a capacitor CPAR corresponding to a minimum sized layout pad and a minimum
width input trace of about 1 inch length.
10
10
6
CIN = 0
8 V = 5V
CC
6 TA = 25°C
RS = 10k
INL (LSB)
4
2
0
–2
4
RS = 2k
RS = 1k
INL (LSB)
8
CIN = 0.1μF
VCC = 5V
TA = 25°C
RS = 0
2
0
–2
–4
–4
–6
–6
–8
–8
–10
–10
–5 –4 –3 –2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
5
2453 F10
Figure 10. Measured INL vs Input Voltage,
CIN = 0.1μF, VCC = 5V, TA = 25°C
RS = 10k
RS = 0
RS = 1k, 2k
–5 –4 –3 –2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
5
2453 F11
Figure 11. Measured INL vs Input Voltage,
CIN = 0, VCC = 5V, TA = 25°C
2453f
12
LTC2453
APPLICATIONS INFORMATION
0
INPUT SIGNAL ATTENUATIOIN (dB)
INPUT SIGNAL ATTENUATION (dB)
0
–20
–40
–60
–80
–5
–10
–15
–20
–25
–30
–35
–40
–45
–100
0
2.5
5.0
7.5
1.00
1.25
1.50
INPUT SIGNAL FREQUENCY (MHz)
–50
0
60 120 180 240 300 360 420 480 540 600
INPUT SIGNAL FREQUENCY (Hz)
2453 F12
Figure 12. LTC2453 Input Signal Attentuation vs Frequency
Signal Bandwidth, Transition Noise and Noise
Equivalent Input Bandwidth
The LTC2453 includes a sinc1 type digital filter with the first
notch located at f0 = 60Hz. As such, the 3dB input signal
bandwidth is 26.54Hz. The calculated LTC2453 input signal
attenuation vs frequency over a wide frequency range is
shown in Figure 12. The calculated LTC2453 input signal
attenuation vs frequency at low frequencies is shown in
Figure 13. The converter noise level is about 1.4μVRMS
and can be modeled by a white noise source connected
at the input of a noise-free converter.
On a related note, the LTC2453 uses two separate A/D
converters to digitize the positive and negative inputs.
Each of these A/D converters has 1.4μVRMS transition
noise. If one of the input voltages is within this small
transition noise band, then the output will fluctuate one
2453 F13
Figure 13. LTC2453 Input Signal Attenuation
vs Frequency (Low Frequencies)
bit, regardless of the value of the other input voltage. If
both of the input voltages are within their transition noise
bands, the output can fluctuate 2 bits.
For a simple system noise analysis, the VIN drive circuit can
be modeled as a single-pole equivalent circuit characterized by a pole location fi and a noise spectral density ni.
If the converter has an unlimited bandwidth, or at least a
bandwidth substantially larger than fi, then the total noise
contribution of the external drive circuit would be:
Vn = ni π / 2 • fi
Then, the total system noise level can be estimated as
the square root of the sum of (Vn2) and the square of the
LTC2453 noise floor (~1.4μV2).
2453f
13
LTC2453
TYPICAL APPLICATION
DC1266A Demo Board Schematic
V+
LT6660
3
IN
OUT
1
5V
C4
1μF GND GND
2
4
JP1
VCC
EXT
C9
1μF
C3
1μF
R4
1.0Ω
E5
REF+
V+
1
2
C1
0.1μF
6
SCL SDA
VCC
4
C10
0.1μF
7
5
E1
IN+
E2
IN–
E3
VCC
3
R1
1k
R9
1k
C6
0.1μF
VCC
6
+
IN+
REF
4
VCC
SCL
C2
0.1μF
IN–
–
REF
C8
0.1μF
2
SDA
GND GND
1
9
10
8
R6
4.99k
1%
R7
4.99k
1%
8
6
7
SCL
R8
4.99k
1%
VCC
3
2
EXT
1
9
12
14
WP
C5
0.1μF
24LC025-I/ST
E4
GND
E6
REF–
7
LTC2453
5
C7
0.1μF
11
SDA
A2
A1
5
VUNREG
5V
CS
SCK/SCL
MOSI/SDA
MISO
TO
CONTROLLER
J1
EESCL
EEVCC
EESDA
EEGND
NC
GND GND GND
3
8
13
2453 TA02
A0
GND
JP2
GND
4
2453f
14
LTC2453
PACKAGE DESCRIPTION
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
0.61 ±0.05
(2 SIDES)
0.70 ±0.05
2.55 ±0.05
1.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
2.20 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(2 SIDES)
R = 0.115
TYP
5
R = 0.05
TYP
0.40 ± 0.10
8
2.00 ±0.10
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.56 ± 0.05
(2 SIDES)
0.200 REF
0.75 ±0.05
0 – 0.05
4
0.25 ± 0.05
1
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
(DDB8) DFN 0905 REV B
0.50 BSC
2.15 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
2453f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC2453
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/°C Drift
LT1461
Micropower Series Reference, 2.5V
0.04% Max, 3ppm/°C Drift
LT1790
Micropower Precision Reference in TSOT-23-6 Package
60μA Max Supply Current, 10ppm/°C Max Drift, 1.25V, 2.048V,
2.5V, 3V, 3.3V, 4.096V and 5V Options
LTC1860/LTC1861
12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L
12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
LTC1864/LTC1865
16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
LTC1864L/LTC1865L
16-bit, 3V, 1-/2-Channel 150ksps SAR ADC
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
LTC2440
24-Bit No Latency ΔΣTMADC
200nVRMS Noise, 8kHz Output Rate, 15ppm INL
LTC2480
16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,
Temp. Sensor, SPI
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2481
16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,
Temp. Sensor, I2C
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2482
16-Bit, Differential Input, No Latency ΔΣ ADC, SPI
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2483
16-Bit, Differential Input, No Latency ΔΣ ADC, I2C
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2484
24-Bit, Differential Input, No Latency ΔΣ ADC, SPI
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2485
24-Bit, Differential Input, No Latency ΔΣ ADC, I2C
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC6241
Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp
550nVP-P Noise, 125μV Offset Max
LT6660
Micropower References in 2mm × 2mm DFN Package,
2.5V, 3V, 3.3V, 5V
20ppm/°C max drift, 0.2% Max
LTC2450
Easy-to-Use, Ultra-Tiny 16-Bit ADC
2 LSB INL, 50nA Sleep current, Tiny 2mm × 2mm DFN-6 Package,
30Hz Output Rate
LTC2450-1
Easy-to-Use, Ultra-Tiny 16-Bit ADC
2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,
60Hz Output Rate
No Latency ΔΣ is a trademark of Linear Technology Corporation.
2453f
16 Linear Technology Corporation
LT 1007 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
Similar pages