H CAT5409 EE GEN FR ALO Quad Digitally Programmable Potentiometers (DPP™) with 64 Taps and 2-wire Interface LE FEATURES A D F R E ETM ■ Four linear-taper digital potentiometers ■ Recall of saved wiper settings at power-up ■ 64 resistor taps per potentiometer ■ 2.5 to 6.0 volt operation ■ End-to-end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ ■ Standby current less than 1µA ■ 2-wire interface (I C like) ■ 1,000,000 nonvolatile WRITE cycles Ω ■ Low wiper resistance, typically 80Ω ■ 100 year nonvolatile memory data retention ■ Four non-volatile wiper settings for each ■ 24-lead SOIC, 24-lead TSSOP and BGA 2 potentiometer ■ Write protection for data register DESCRIPTION The CAT5409 is four Digitally Programmable Potentiometers (DPP™) integrated with control logic and 16 bytes of NVRAM memory. contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control register (WCR). A separate 6-bit control register (WCR) independently controls the wiper tap position for each DPP. Associated with each wiper control register are four 6bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a 2-wire serial bus (I2C-like). On power-up, the The Write Protection (WP) pin protects against inadvertent programming of the data register. PIN CONFIGURATION FUNCTIONAL DIAGRAM SOIC Package (J, W) TSSOP Package (U, Y) NC SDA 1 24 WP VCC 1 24 RL0 RH0 2 23 RL3 23 A2 22 RH3 A1 RL1 2 3 3 22 RW0 RW0 4 21 RW3 RH1 4 21 RH0 A2 WP 5 20 5 20 RL0 GND 6 7 NC 7 A1 8 17 A3 SCL CAT 19 5409 18 VCC SDA CAT 19 5409 18 A0 NC RW1 6 RW2 8 17 RL3 RL1 RH1 RW1 9 16 RL2 RH2 9 16 RH3 10 15 RH2 RL2 10 15 RW3 11 14 RW2 SCL 11 14 A0 GND 12 13 NC A3 12 13 NC A B BGA C D E F The CAT5409 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. 1 2 3 4 RW0 A2 A1 RL1 RL0 WP SDA RW1 VCC RH0 RH1 VSS NC RH3 RH2 NC RL3 NC A3 RW2 RW3 A0 SCL © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice RH0 RH1 SCL SDA 2-WIRE BUS INTERFACE RH2 R H3 R W0 WIPER CONTROL REGISTERS R W1 WP NC R W2 A0 A1 A2 A3 CONTROL LOGIC NONVOLATILE DATA REGISTERS R W3 RL0 RL1 RL2 R L3 RL2 Top View - Bump Side Down 1 Document No. 2010, Rev. I CAT5409 PIN DESCRIPTION PIN DESCRIPTIONS Pin (TSSOP) Pin (SOIC) Pin (BGA) Name 19 1 C1 VCC Supply Voltage 20 2 B1 RL0 Low Reference Terminal for Potentiometer 0 21 3 C2 RH0 High Reference Terminal for Potentiometer 0 SCL: Serial Clock The CAT5409 serial clock input pin is used to clock all data transfers into or out of the device. Function 22 4 A1 RW0 23 5 A2 A2 Device Address Wiper Terminal for Potentiometer 0 24 6 B2 WP Write Protection 1 7 B3 SDA 2 8 A3 A1 Device Address 3 9 A4 RL1 Low Reference Terminal for Potentiometer 1 4 10 C3 RH1 High Reference Terminal for Potentiometer 1 5 11 B4 RW1 Wiper Terminal for Potentiometer 1 6 12 C4 GND Ground 7 13 D4 NC No Connect 8 14 E4 RW2 Wiper Terminal for Potentiometer 2 9 15 D3 RH2 High Reference Terminal for Potentiometer 2 10 16 F4 RL2 Low Reference Terminal for Potentiometer 2 11 17 F3 SCL Bus Serial Clock 12 18 E3 A3 Device Address 13 19 D1 NC No Connect 14 20 F2 A0 Device Address, LSB 15 21 F1 RW3 Wiper Terminal for Potentiometer 3 16 22 D2 RH3 High Reference Terminal for Potentiometer 3 17 23 E1 RL3 Low Reference Terminal for Potentiometer 3 18 24 E2 NC No Connect SDA: Serial Data The CAT5409 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wireOred with the other open drain or open collector outputs. A0, A1, A2, A3: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of sixteen devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5409. Serial Data Input/Output RH, RL: Resistor End Points The four sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The four RW pins are equivalent to the wiper terminal of a mechanical potentiometer. WP: Write Protect Input The WP pin when tied low prevents non-volatile writes to the data registers (change of wiper control register is allowed) and when tied high or left floating normal read/write operations are allowed. See Write Protection on page 7 for more details. DEVICE OPERATION The CAT5409 is four resistor arrays integrated with 2wire serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a Document No. 2010, Rev. I CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allows data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode. 2 CAT5409 ABSOLUTE MAXIMUM RATINGS* *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Temperature Under Bias .................. -55°C to +125°C Storage Temperature ........................ -65°C to +150°C Voltage on any Pin with Respect to VSS(1)(2) ................ -2.0V to +VCC +2.0V Recommended Operating Conditions: VCC with Respect to Ground ................ -2.0V to +7.0V VCC = +2.5V to +6.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Temperature Industrial Lead Soldering Temperature (10 secs) ............ 300°C Min -40°C Max 85°C Wiper Current .................................................. +12mA Notes: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. POTENTIOMETER CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Test Conditions Min Typ Max Units RPOT Potentiometer Resistance (-00) 100 kΩ RPOT Potentiometer Resistance (-50) 50 kΩ RPOT Potentiometer Resistance (-10) 10 kΩ RPOT Potentiometer Resistance (-2.5) 2.5 kΩ Potentiometer Resistance Tolerance +20 % RPOT Matching 1 % 50 mW +6 mA 300 Ω 150 Ω VCC V Power Rating 25°C, each pot IW Wiper Current RW Wiper Resistance IW = +3mA @ VCC =3V RW Wiper Resistance IW = +3mA @ VCC = 5V VTERM Voltage on any RH or RL Pin VSS = 0V VN Noise (1) Resolution 80 GND TBD nV/ Hz 1.6 % Absolute Linearity (2) Rw(n)(actual)-R(n)(expected)(5) +1 LSB (4) Relative Linearity (3) Rw(n+1)-[Rw(n)+LSB](5) +0.2 LSB (4) TCRPOT Temperature Coefficient of RPOT (1) TCRATIO Ratiometric Temp. Coefficient (1) CH/CL/CW Potentiometer Capacitances (1) 10/10/25 pF fc Frequency Response RPOT = 50kΩ(1) 0.4 MHz +300 ppm/°C 20 ppm/°C Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (4) LSB = RTOT / 63 or (RH - RL) / 63, single pot (5) n = 0, 1, 2, ..., 63 3 Document No. 2010, Rev. I CAT5409 D.C. OPERATING CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Test Conditions Min Typ Max Units fSCL = 400kHz 1 mA VIN = GND or VCC; SDA Open 1 µA VIN = GND to VCC 10 µA VOUT = GND to VCC 10 µA ICC Power Supply Current ISB Standby Current (VCC = 5.0V) ILI Input Leakage Current ILO Output Leakage Current VIL Input Low Voltage -1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 1.0 V 0.4 V Max Units VOL1 Output Low Voltage (VCC = 3.0V) IOL = 3 mA CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Conditions Min Typ Input/Output Capacitance (SDA) VI/O = 0V 8 pF (1) Input Capacitance (A0, A1, A2, A3, SCL, WP) VIN = 0V 6 pF Max Units CI/O CIN Test (1) A.C. CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Min Typ fSCL Clock Frequency 400 kHz TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 50 ns tAA SLC Low to SDA Data Out and ACK Out 0.9 µs tBUF(1) Time the bus must be free before a new transmission can start 1.2 µs tHD:STA Start Condition Hold Time 0.6 µs tLOW Clock Low Period 1.2 µs tHIGH Clock High Period 0.6 µs tSU:STA Start Condition SetupTime (for a Repeated Start Condition) 0.6 µs tHD:DAT Data in Hold Time 0 ns tSU:DAT Data in Setup Time 100 ns SDA and SCL Rise Time 0.3 µs tF(1) SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Out Hold Time 50 ns tR (1) POWER UP TIMING (1) Over recommended operating conditions unless otherwise stated. Symbol Parameter Min Typ Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Document No. 2010, Rev. I 4 CAT5409 WRITE CYCLE LIMITS Over recommended operating conditions unless otherwise stated. Symbol tWR Parameter Min Typ Write Cycle Time Max Units 5 ms The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. RELIABILITY CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Reference Test Method Min (1) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR(1) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA NEND Typ Max Units Figure 1. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 2. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 3. Start/Stop Timing SDA SCL START BIT STOP BIT Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 5 Document No. 2010, Rev. I CAT5409 SERIAL BUS PROTOCOL the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 0101 for the CAT5409 (see Figure 5). The next four significant bits (A3, A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to sixteen devices may be individually addressed by the system. Typically, +5V and ground are hard-wired to these pins to establish the device's address. The following defines the features of the 2-wire bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. After the Master sends a START condition and the slave address byte, the CAT5409 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5409 will be considered a slave device in all applications. Acknowledge START Condition After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5409 monitors the SDA and SCL lines and will not respond until this condition is met. The CAT5409 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. STOP Condition When the CAT5409 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5409 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master then sends the address of Figure 4. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START 5020 FHD F06 Document No. 2010, Rev. I 6 CAT5409 the CAT5409 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5409 is still busy with the write operation, no ACK will be returned. If the CAT5409 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation. WRITE OPERATIONS In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of CAT5409. The instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the selected register. The CAT5409 acknowledges once more and the Master generates the STOP condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent programming of the non-volatile data registers. If the WP pin is tied to LOW, the data registers are protected and become read only. Similarly, the WP pin going low after start but after start will interrupt non-volatile write to data registers, while the WP pin going low after internal write cycle has started, will have no effect on any write operation. The CAT5409 will accept both slave addresses and instructions, but the data registers are protected from programming by the device’s failure to send an acknowledge after data is received. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, Figure 5. Slave Address Bits CAT5409 * ** 0 1 0 1 A3 A2 A1 A0 A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device. A0, A1, A2 and A3 must compare to its corresponding hard wired input pins. Figure 6. Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T INSTRUCTION BYTE SLAVE/DPP ADDRESS Fixed Variable op code Data Register Pot/WCR Address Address S T O P DR1 WCR DATA S P A C K A C K 7 A C K Document No. 2010, Rev. I CAT5409 INSTRUCTION AND REGISTER DESCRIPTION INSTRUCTION BYTE The next byte sent to the CAT5409 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I [3:0]. The R1 and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of four Wiper Control Registers. The format is shown in Table 2. SLAVE ADDRESS BYTE The first byte sent to the CAT5409 from the master/ processor is called the Slave/DPP Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5409 are fixed at 0101[B] (refer to Table 1). Data Register Selection The next four bits, A3 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 - A0 input pins for the CAT5409 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Data Register Selected R1 R0 DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 Table 1. Identification Byte Format Device Type Identifier Slave Address ID3 ID2 ID1 ID0 0 1 0 1 A3 A2 A1 (MSB) A0 (LSB) Table 2. Instruction Byte Format Instruction Opcode I3 I2 Data Register Selection I1 I0 R1 (MSB) Document No. 2010, Rev. I R0 WCR/Pot Selection P1 P0 (LSB) 8 CAT5409 four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 5ms. WIPER CONTROL AND DATA REGISTERS Wiper Control Register (WCR) The CAT5409 contains four 6-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 64 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data. INSTRUCTIONS Four of the nine instructions are three bytes in length. These instructions are: — Read Wiper Control Register - read the current wiper position of the selected potentiometer in the WCR — Write Wiper Control Register - change current wiper position in the WCR of the selected potentiometer The Wiper Control Register is a volatile register that loses its contents when the CAT5409 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. — Read Data Register - read the contents of the selected Data Register Data Registers (DR) — Write Data Register - write a new value to the selected Data Register Each potentiometer has four 6-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions Table 3. Instruction Set Instruction Set Instruction I3 I2 I1 I0 R1 R0 WCR1/ P1 WCR0/ P0 Read Wiper Control Register Write Wiper Control Register 1 0 0 1 0 0 1/0 1/0 1 0 1 0 0 0 1/0 1/0 Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 XFR Data Register to Wiper Control Register 1 1 0 1 1/0 1/0 1/0 1/0 XFR Wiper Control Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Global XFR Data Registers to Wiper Control Registers 0 0 0 1 1/0 1/0 0 0 Global XFR Wiper Control Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Increment/Decrement Wiper Control Register 0 0 1 0 1/0 1/0 0 0 Operation Read the contents of the Wiper Control Register pointed to by P1-P0 Write new value to the Wiper Control Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and R1-R0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Data Register pointed to by P1-P0 and R1-R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P1-P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Control Register s Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of all four pots Enable Increment/decrement of the Control Latch pointed to by P1-P0 Note: 1/0 = data is one or zero 9 Document No. 2010, Rev. I CAT5409 exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. — Global XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. — Global XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5409; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 5 and 9). The Increment/Decrement command is different from the other commands. Once the command is issued and the CAT5409 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. — XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. — XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. See Instructions format for more detail. Figure 7. Two-Byte Instruction Sequence SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 A2 A1 A0 T A Internal R Device ID Address T A I3 C K I2 I1 I0 Instruction Opcode R1 R0 P1 P0 A C K Pot/WCR Address Register Address S T O P Figure 8. Three-Byte Instruction Sequence SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 T A Device ID R T A2 A0 A I3 C K Internal Address I2 A1 I1 I0 R1 R0 P1 P0 A C K Data Pot/WCR Register Address Address Instruction Opcode D7 D6 D5 D4 D3 D2 D1 D0 A C K WCR[7:0] or Data Register D[7:0] S T O P Figure 9. Increment/Decrement Instruction Sequence 0 SDA S T A R T 1 0 1 ID3 ID2 ID1 ID0 Device ID Document No. 2010, Rev. I A3 A2 A1 A0 Internal Address A C K I3 I2 I1 I0 Instruction Opcode 10 R1 R0 P1 P0 A C Pot/WCR K Data Address Register Address I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P CAT5409 Figure 10. Increment/Decrement Timing Limits INC/DEC Command Issued tWRID SCL SDA Voltage Out RW INSTRUCTION FORMAT Read Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K A C 1 0 0 1 0 0 P1 P0 K A C K S T O P A C K S T O P A A DATA C C 1 0 1 1 R1 R0 P1 P0 7 6 5 4 3 2 1 0 K K 0 0 S T O P A A DATA C C 1 1 0 0 R1 R0 P1 P0 7 6 5 4 3 2 1 0 K K 0 0 S T O P INSTRUCTION DATA 7 6 5 4 3 2 1 0 0 0 Write Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K A C 1 0 1 0 0 0 P1 P0 K INSTRUCTION DATA 7 6 5 4 3 2 1 0 0 0 Read Data Register (DR) S T A R T A C 0 1 0 1 A3 A2A1 A0 K DEVICE ADDRESS INSTRUCTION Write Data Register (DR) S T A R T A C 0 1 0 1 A3 A2A1 A0 K DEVICE ADDRESS INSTRUCTION 11 Document No. 2010, Rev. I CAT5409 INSTRUCTION FORMAT (continued) Global Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS INSTRUCTION 0 0 0 1 R1 R0 0 0 A C K S T O P Global Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS INSTRUCTION 1 0 0 0 R1 R0 0 0 A C K S T O P Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS A C 1 1 1 0 R1 R0 P1 P0 K INSTRUCTION S T O P Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS A C 1 1 0 1 R1 R0 P1 P0 K INSTRUCTION S T O P Increment (I)/Decrement (D) Wiper Control Register (WCR) S T A R T A A INSTRUCTION C C 0 1 0 1 A3 A2 A1 A0 0 0 1 0 0 0 P1 P0 K K DEVICE ADDRESS DATA I/D I/D • • • A C I/D I/D K Notes: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued. Document No. 2010, Rev. I 12 S T O P CAT5409 ORDERING INFORMATION Prefix Device # Suffix CAT 5409 J Optional Company ID Product Number I Package J: SOIC B: BGA U: TSSOP W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) -TE13 -00 Tape & Reel TE13: 2000/Reel Resistance -25: 2.5kohm -10: 10kohm -50: 50kohm -00: 100kohm Temperature Range I = Industrial (-40 C to 85 C) Notes: (1) The device used in the above example is a CAT5409JI-00-TE13 (SOIC, Industrial Temperature, 10kohm, Tape & Reel) 13 Document No. 2010, Rev. I CAT5409 PACKAGING INFORMATION 24-LEAD 300 MIL WIDE SOIC (J, W) 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.5985 (15.20) 0.6141 (15.60) 0.0926 (2.35) 0.1043 (2.65) 0.050 (1.27) BSC 0.0040 (0.10) 0.0118 (0.30) 0.013 (0.33) 0.020 (0.51) 0.010 (0.25) X 45 0.029 (0.75) 0.0091 (0.23) 0.0125 (0.32) 0 —8 0.016 (0.40) 0.050 (1.27) Document No. 2010, Rev. I 14 CAT5409 PACKAGING INFORMATION CON'T 24 Lead TSSOP (U, Y) 7.8 + 0.1 -A- 7.72 TYP 6.4 4.16 TYP 4.4 + 0.1 -B(1.78 TYP) 3.2 0.42 TYP 0.65 TYP 0.2 C B A ALL LEAD TIPS PIN #1 INDENT. 1.1 MAX TYP LAND PATTERN RECOMMENDATION 0.1 C ALL LEAD TIPS (0.9) -C0.10 + 0.05 TYP 0.65 TYP 0.19 - 0.30 TYP 0.3 M A B S C S SEE DETAIL A GAGE PLANE 0.25 0.09 - 0.20 TYP o o 0-8 0.6+0.1 SEATING PLANE DETAIL A 15 Document No. 2010, Rev. I CAT5409 PACKAGING INFORMATION CON'T 24 Ball BGA a a 1 2 j 3 m 4 4 3 2 A A B B k C b 1 C D D E E F F f Top View (Bump Side Down) b Bottom View (Bump Side Up) Note: Drawing not to scale = Die orientation mark d c e Side View (Bump Side Down) Millimeters Inches Symbol Min Nom Max Nom Min Max Package Body Dimension X a TBD TBD TBD TBD TBD TBD Package Body Dimension Y b TBD TBD TBD TBD TBD TBD Package Height c 0.635 0.505 0.765 0.02500 0.01988 0.03012 Package Body Thickness d 0.433 0.395 0.471 0.01705 0.01555 0.01854 Ball Height e 0.202 0.110 0.294 0.00795 0.00433 0.01157 Ball Diameter f 0.284 0.180 0.388 0.01118 0.00709 0.01528 Total Ball Count g 24 Ball Count X Axis h 4 Ball Count Y Axis i 6 Pins Pitch X Axis j 0.5 Pins Pitch Y Axis k 0.5 Edge to Ball Center (Corner) Distance Along X l TBD TBD TBD TBD TBD TBD Edge to Ball Center (Corner) Distance Along Y m TBD TBD TBD TBD TBD TBD Document No. 2010, Rev. I 16 REVISION HISTORY Date Rev. Reason 10/8/2003 H 3/30/2004 I Updated Features Updated Description Changed Preliminary designation to Final Eliminated Commercial temp range in all areas Updated WP Pin Description Updaed notes in Absolute Max Ratings and Potentiometer Characteristics Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: Type: 2010 I 3/30/04 Final