ON MC14060BF 14-bit binary counter and oscillator Datasheet

MC14060B
14-Bit Binary Counter and
Oscillator
The MC14060B is a 14–stage binary ripple counter with an on–chip
oscillator buffer. The oscillator configuration allows design of either
RC or crystal oscillator circuits. Also included on the chip is a reset
function which places all outputs into the zero state and disables the
oscillator. A negative transition on Clock will advance the counter to
the next state. Schmitt trigger action on the input line permits very
slow input rise and fall times. Applications include time delay circuits,
counter controls, and frequency dividing circuits.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
Fully static operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 V to 18 V
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Buffered Outputs Available from Stages 4 Through 10 and
12 Through 14
Common Reset Line
Pin–for–Pin Replacement for CD4060B
MC14060BCP
AWLYYWW
1
16
SOIC–16
D SUFFIX
CASE 751B
14060B
AWLYWW
1
16
TSSOP–16
DT SUFFIX
CASE 948F
14
060B
ALYW
1
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Parameter
Symbol
VDD
V
– 0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
Iin, Iout
Input or Output Voltage Range
(DC or Transient)
SOEIAJ–16
F SUFFIX
CASE 966
MC14060B
AWLYWW
1
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
v
16
Unit
– 0.5 to +18.0
Vin, Vout
DC Supply Voltage Range
Value
v
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14060BCP
PDIP–16
2000/Box
MC14060BD
SOIC–16
2400/Box
MC14060BDR2
SOIC–16
2500/Tape & Reel
MC14060BDT
TSSOP–16
96/Rail
MC14060BDTR2
TSSOP–16 2500/Tape & Reel
MC14060BF
SOEIAJ–16
See Note 1.
MC14060BFEL
SOEIAJ–16
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14060B/D
MC14060B
PIN ASSIGNMENT
Q12
1
16
VDD
Q13
2
15
Q10
Q14
3
14
Q8
Q6
4
13
Q9
Q5
5
12
RESET
Q7
6
11
CLOCK
Q4
7
10
OUT 1
VSS
8
9
OUT 2
TRUTH TABLE
Clock
Reset
Output State
X
L
L
H
No Change
Advance to next state
All Outputs are low
X = Don’t Care
LOGIC DIAGRAM
OUT 2
9
Q4
OUT 1
Q5
7
10
Q12
1
5
Q13
2
Q14
3
CLOCK
11
C
C
R
Q
C
Q
C
R
Q
C
Q
C
R
Q
C
Q
C
R
Q
C
Q
C
R
Q
C
Q
C
Q
R
Q
RESET
12
Q6 = PIN 4
Q7 = PIN 6
http://onsemi.com
2
Q8 = PIN 14
Q9 = PIN 13
Q10 = PIN 15
VDD = PIN 16
VSS = PIN 8
MC14060B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
– 55_C
Min
Max
Min
25_C
Typ (4.)
Max
125_C
Min
Max
Unit
Output Voltage
Vin = VDD or 0
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
V
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
V
Input Voltage
(VO = 4.5 or 0.5 V)
(VO = 9.0 or 1.0 V)
(VO = 13.5 or 1.5 V)
“0” Level
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
(VO = 0.5 or 4.5 V)
(VO = 1.0 or 9.0 V)
(VO = 1.5 or 13.5 V)
“1” Level
VIH
5.0
10
15
3.5
7.0
11.0
—
—
—
3.5
7.0
11.0
2.75
5.50
8.25
—
—
—
3.5
7.0
11.0
—
—
—
“0” Level
(For Input 11
and Output 10)
VIL
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
2.25
4.50
6.75
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
“1” Level
VIH
5.0
10
15
4.0
8.0
12.5
—
—
—
4.0
8.0
12.5
2.75
5.50
8.25
—
—
—
4.0
8.0
12.5
—
—
—
Output Drive Current
(VOH = 2.5 V)
(Except Source
(VOH = 4.6 V)
Pins 9 and 10)
(VOH = 9.5 V)
(VOH = 13.5 V)
IOH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mA
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µA
Input Capacitance (Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µA
IT
5.0
10
15
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Total Supply Current (5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs,
all buffers switching)
Sink
V
V
Vdc
Vdc
mA
IT = (0.25 µA/kHz) f + IDD
IT = (0.54 µA/kHz) f + IDD
IT = (0.85 µA/kHz) f + IDD
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
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3
µA
MC14060B
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SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Vdc
Min
Typ (7.)
Max
Unit
Output Rise Time (Counter Outputs)
tTLH
5.0
10
15
—
—
—
40
25
20
200
100
80
ns
Output Fall Time (Counter Outputs)
tTHL
5.0
10
15
—
—
—
50
30
20
200
100
80
ns
Propagation Delay Time
Clock to Q4
tPLH
tPHL
5.0
10
15
—
—
—
415
175
125
740
300
200
ns
5.0
10
15
—
—
—
1.5
0.7
0.4
2.7
1.3
1.0
µs
twH
5.0
10
15
100
40
30
65
30
20
—
—
—
ns
fφ
5.0
10
15
—
—
—
5
14
17
3.5
8
12
MHz
tTLH
tTHL
5.0
10
15
tw
5.0
10
15
120
60
40
40
15
10
—
—
5.0
10
15
—
—
—
170
80
60
350
160
100
Clock to Q14
Clock Pulse Width
Clock Pulse Frequency
Clock Rise and Fall Time
Reset Pulse Width
Propagation Delay Time
Reset to On
tPHL
ns
No Limit
ns
—
ns
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
VDD
500 µF
PULSE
GENERATOR
CLOCK
NC
NC
CLOCK
NC
NC
Q4
OUT1 Q5
OUT2 Qn
R
VSS
20 ns
CLOCK
PULSE
GENERATOR
0.01 µF
ID
90%
50%
10%
Q4
OUT1 Q5
OUT2
Qn
R
CL
VSS
CL
CL
20 ns
CL
CL
20 ns
90%
50%
10%
CLOCK
20 ns
tPLH
VDD
Q
VSS
tTLH
50% DUTY CYCLE
Figure 1. Power Dissipation Test Circuit
and Waveform
tWH
tPHL
90%
50%
10%
tTHL
Figure 2. Switching Time Test Circuit
and Waveforms
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4
CL
MC14060B
CLOCK 11
f
10 OUT 1
RESET
if 1 kHz ≤ f ≤ 100 kHz
and 2Rtc < RS < 10Rtc
(f in Hz, R in ohms, C in farads)
9 OUT 2
Rtc
The formula may vary for other frequencies. Recommended
maximum value for the resistors in 1 MΩ.
Ctc
RS
[ 2.3 R1tcCtc
Figure 3. Oscillator Circuit Using RC Configuration
TYPICAL RC OSCILLATOR CHARACTERISTICS
100
VDD = 15 V
4.0
f, OSCILLATOR FREQUENCY (kHz)
FREQUENCY DEVIATION (%)
8.0
0
1.0 V
– 4.0
– 8.0
5.0 V
– 12
RTC = 56 kΩ
C = 1000 pF
– 16
– 55
– 25
100
10
5
2
1
0.5
0.1
1.0 k
125
0.0001
Figure 4. RC Oscillator Stability
f AS A FUNCTION
OF C
(RTC = 56 kΩ)
(RS = 120 k)
10 k
100 k
RTC, RESISTANCE (OHMS)
0.001
0.01
C, CAPACITANCE (µF)
10 OUT 1
9 OUT 2
18M
RO
CT
Figure 6. Typical Crystal Oscillator Circuit
0.1
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ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic
RESET
1.0 M
Figure 5. RC Oscillator Frequency as a
Function of RTC and C
CLOCK
11
CS
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
20
0.2
RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25°C
RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
VDD = 10 V
50
500 kHz 32 kHz
Circuit Circuit Unit
Crystal Characteristics
Resonant Frequency
Equivalent Resistance, RS
500
1.0
32
6.2
kHz
kΩ
External Resistor/Capacitor Values
RO
CT
CS
47
82
20
750
82
20
kΩ
pF
pF
+ 6.0
+ 2.0
+ 2.0
+ 2.0
ppm
ppm
+ 100
+ 120
ppm
– 160
– 560
ppm
Frequency Stability
Frequency Changes as a
Function of VDD (TA = 25_C)
VDD Change from 5.0 V to 10 V
VDD Change from 10 V to 15 V
Frequency Change as a Function
of Temperature (VDD = 10 V)
TA Change from – 55_C to
+ 25_C Complete Oscillator (8.)
TA Change from + 25_C to
+ 125_C Complete Oscillator (8.)
8. Complete oscillator includes crystal, capacitors, and resistors.
Figure 7. Typical Data for Crystal Oscillator Circuit
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5
MC14060B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
–T–
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
M
T B
S
A
S
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6
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14060B
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
DETAIL E
H
D
G
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7
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC14060B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
16
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
0.78
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.031
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MC14060B/D
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