TI1 LM3S9U90 Stellaris lm3s9u90 microcontroller Datasheet

TE X AS I NS TRUM E NTS - P RO DUCTION D ATA
®
Stellaris LM3S9U90 Microcontroller
D ATA SHE E T
D S -LM3S 9U 90 - 1 5 8 5 2 . 2 7 4 3
S P M S 252C
C o p yri g h t © 2 0 07-2014
Te xa s In stru me n ts In co rporated
Copyright
Copyright © 2007-2014 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare® are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Table of Contents
Revision History ............................................................................................................................. 40
About This Document .................................................................................................................... 43
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
43
43
43
44
1
Architectural Overview .......................................................................................... 46
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.4
Overview ......................................................................................................................
Target Applications ........................................................................................................
Features .......................................................................................................................
ARM Cortex-M3 Processor Core ....................................................................................
On-Chip Memory ...........................................................................................................
External Peripheral Interface .........................................................................................
Serial Communications Peripherals ................................................................................
System Integration ........................................................................................................
Analog ..........................................................................................................................
JTAG and ARM Serial Wire Debug ................................................................................
Packaging and Temperature ..........................................................................................
Hardware Details ..........................................................................................................
46
48
48
48
50
51
53
59
64
66
67
67
2
The Cortex-M3 Processor ...................................................................................... 68
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.3
Block Diagram .............................................................................................................. 69
Overview ...................................................................................................................... 70
System-Level Interface .................................................................................................. 70
Integrated Configurable Debug ...................................................................................... 70
Trace Port Interface Unit (TPIU) ..................................................................................... 71
Cortex-M3 System Component Details ........................................................................... 71
Programming Model ...................................................................................................... 72
Processor Mode and Privilege Levels for Software Execution ........................................... 72
Stacks .......................................................................................................................... 72
Register Map ................................................................................................................ 73
Register Descriptions .................................................................................................... 74
Exceptions and Interrupts .............................................................................................. 87
Data Types ................................................................................................................... 87
Memory Model .............................................................................................................. 87
Memory Regions, Types and Attributes ........................................................................... 89
Memory System Ordering of Memory Accesses .............................................................. 90
Behavior of Memory Accesses ....................................................................................... 90
Software Ordering of Memory Accesses ......................................................................... 91
Bit-Banding ................................................................................................................... 92
Data Storage ................................................................................................................ 94
Synchronization Primitives ............................................................................................. 95
Exception Model ........................................................................................................... 96
Exception States ........................................................................................................... 97
Exception Types ............................................................................................................ 97
Exception Handlers ..................................................................................................... 100
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2.5.4
2.5.5
2.5.6
2.5.7
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.7
2.7.1
2.7.2
2.8
Vector Table ................................................................................................................
Exception Priorities ......................................................................................................
Interrupt Priority Grouping ............................................................................................
Exception Entry and Return .........................................................................................
Fault Handling .............................................................................................................
Fault Types .................................................................................................................
Fault Escalation and Hard Faults ..................................................................................
Fault Status Registers and Fault Address Registers ......................................................
Lockup .......................................................................................................................
Power Management ....................................................................................................
Entering Sleep Modes .................................................................................................
Wake Up from Sleep Mode ..........................................................................................
Instruction Set Summary ..............................................................................................
100
101
102
102
104
104
105
106
106
106
106
107
108
3
Cortex-M3 Peripherals ......................................................................................... 111
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.3
3.4
3.5
3.6
Functional Description ................................................................................................. 111
System Timer (SysTick) ............................................................................................... 111
Nested Vectored Interrupt Controller (NVIC) .................................................................. 112
System Control Block (SCB) ........................................................................................ 114
Memory Protection Unit (MPU) ..................................................................................... 114
Register Map .............................................................................................................. 119
System Timer (SysTick) Register Descriptions .............................................................. 121
NVIC Register Descriptions .......................................................................................... 125
System Control Block (SCB) Register Descriptions ........................................................ 138
Memory Protection Unit (MPU) Register Descriptions .................................................... 167
4
JTAG Interface ...................................................................................................... 177
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.5.1
4.5.2
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
JTAG Interface Pins .....................................................................................................
JTAG TAP Controller ...................................................................................................
Shift Registers ............................................................................................................
Operational Considerations ..........................................................................................
Initialization and Configuration .....................................................................................
Register Descriptions ..................................................................................................
Instruction Register (IR) ...............................................................................................
Data Registers ............................................................................................................
178
178
179
179
181
181
182
184
185
185
187
5
System Control ..................................................................................................... 189
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
5.4
5.5
Signal Description .......................................................................................................
Functional Description .................................................................................................
Device Identification ....................................................................................................
Reset Control ..............................................................................................................
Non-Maskable Interrupt ...............................................................................................
Power Control .............................................................................................................
Clock Control ..............................................................................................................
System Control ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
4
189
189
190
190
195
195
196
203
205
205
207
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Hibernation Module .............................................................................................. 293
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Register Access Timing ...............................................................................................
Hibernation Clock Source ............................................................................................
System Implementation ...............................................................................................
Battery Management ...................................................................................................
Real-Time Clock ..........................................................................................................
Battery-Backed Memory ..............................................................................................
Power Control Using HIB .............................................................................................
Power Control Using VDD3ON Mode ...........................................................................
Initiating Hibernate ......................................................................................................
Waking from Hibernate ................................................................................................
Interrupts and Status ...................................................................................................
Initialization and Configuration .....................................................................................
Initialization .................................................................................................................
RTC Match Functionality (No Hibernation) ....................................................................
RTC Match/Wake-Up from Hibernation .........................................................................
External Wake-Up from Hibernation ..............................................................................
RTC or External Wake-Up from Hibernation ..................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
294
294
295
295
296
297
298
298
299
299
299
299
299
300
300
300
301
301
302
302
302
303
7
Internal Memory ................................................................................................... 320
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Block Diagram ............................................................................................................ 320
Functional Description ................................................................................................. 320
SRAM ........................................................................................................................ 321
ROM .......................................................................................................................... 321
Flash Memory ............................................................................................................. 323
Register Map .............................................................................................................. 328
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 330
Memory Register Descriptions (System Control Offset) .................................................. 342
8
Micro Direct Memory Access (μDMA) ................................................................ 366
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.3
8.3.1
8.3.2
Block Diagram ............................................................................................................ 367
Functional Description ................................................................................................. 367
Channel Assignments .................................................................................................. 368
Priority ........................................................................................................................ 369
Arbitration Size ............................................................................................................ 369
Request Types ............................................................................................................ 370
Channel Configuration ................................................................................................. 371
Transfer Modes ........................................................................................................... 372
Transfer Size and Increment ........................................................................................ 381
Peripheral Interface ..................................................................................................... 381
Software Request ........................................................................................................ 381
Interrupts and Errors .................................................................................................... 382
Initialization and Configuration ..................................................................................... 382
Module Initialization ..................................................................................................... 382
Configuring a Memory-to-Memory Transfer ................................................................... 383
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8.3.3
8.3.4
8.3.5
8.4
8.5
8.6
Configuring a Peripheral for Simple Transmit ................................................................
Configuring a Peripheral for Ping-Pong Receive ............................................................
Configuring Channel Assignments ................................................................................
Register Map ..............................................................................................................
μDMA Channel Control Structure .................................................................................
μDMA Register Descriptions ........................................................................................
384
386
388
388
390
397
9
General-Purpose Input/Outputs (GPIOs) ........................................................... 427
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.3
9.4
9.5
Signal Description ....................................................................................................... 427
Functional Description ................................................................................................. 431
Data Control ............................................................................................................... 433
Interrupt Control .......................................................................................................... 434
Mode Control .............................................................................................................. 435
Commit Control ........................................................................................................... 435
Pad Control ................................................................................................................. 436
Identification ............................................................................................................... 436
Initialization and Configuration ..................................................................................... 436
Register Map .............................................................................................................. 437
Register Descriptions .................................................................................................. 439
10
External Peripheral Interface (EPI) ..................................................................... 482
10.1
10.2
10.3
10.3.1
10.3.2
10.4
10.4.1
10.4.2
10.4.3
10.5
10.6
EPI Block Diagram ......................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Non-Blocking Reads ....................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
SDRAM Mode .............................................................................................................
Host Bus Mode ...........................................................................................................
General-Purpose Mode ...............................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
483
484
486
487
488
488
489
493
504
512
513
11
General-Purpose Timers ...................................................................................... 557
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.5
11.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
GPTM Reset Conditions ..............................................................................................
Timer Modes ...............................................................................................................
DMA Operation ...........................................................................................................
Accessing Concatenated Register Values .....................................................................
Initialization and Configuration .....................................................................................
One-Shot/Periodic Timer Mode ....................................................................................
Real-Time Clock (RTC) Mode ......................................................................................
Input Edge-Count Mode ...............................................................................................
Input Edge Timing Mode ..............................................................................................
PWM Mode .................................................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
6
557
558
561
561
561
568
568
569
569
570
570
571
571
572
573
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Watchdog Timers ................................................................................................. 604
12.1
12.2
12.2.1
12.3
12.4
12.5
Block Diagram ............................................................................................................
Functional Description .................................................................................................
Register Access Timing ...............................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
605
605
606
606
606
607
13
Analog-to-Digital Converter (ADC) ..................................................................... 629
13.1
13.2
13.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.4
13.4.1
13.4.2
13.5
13.6
Block Diagram ............................................................................................................ 630
Signal Description ....................................................................................................... 631
Functional Description ................................................................................................. 633
Sample Sequencers .................................................................................................... 633
Module Control ............................................................................................................ 634
Hardware Sample Averaging Circuit ............................................................................. 636
Analog-to-Digital Converter .......................................................................................... 637
Differential Sampling ................................................................................................... 641
Internal Temperature Sensor ........................................................................................ 643
Digital Comparator Unit ............................................................................................... 644
Initialization and Configuration ..................................................................................... 648
Module Initialization ..................................................................................................... 648
Sample Sequencer Configuration ................................................................................. 649
Register Map .............................................................................................................. 649
Register Descriptions .................................................................................................. 651
14
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 709
14.1
Block Diagram ............................................................................................................
14.2
Signal Description .......................................................................................................
14.3
Functional Description .................................................................................................
14.3.1 Transmit/Receive Logic ...............................................................................................
14.3.2 Baud-Rate Generation .................................................................................................
14.3.3 Data Transmission ......................................................................................................
14.3.4 Serial IR (SIR) .............................................................................................................
14.3.5 ISO 7816 Support .......................................................................................................
14.3.6 Modem Handshake Support .........................................................................................
14.3.7 LIN Support ................................................................................................................
14.3.8 FIFO Operation ...........................................................................................................
14.3.9 Interrupts ....................................................................................................................
14.3.10 Loopback Operation ....................................................................................................
14.3.11 DMA Operation ...........................................................................................................
14.4
Initialization and Configuration .....................................................................................
14.5
Register Map ..............................................................................................................
14.6
Register Descriptions ..................................................................................................
710
710
712
712
713
714
714
715
715
717
718
719
720
720
720
721
723
15
Synchronous Serial Interface (SSI) .................................................................... 773
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Bit Rate Generation .....................................................................................................
FIFO Operation ...........................................................................................................
Interrupts ....................................................................................................................
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774
775
776
776
776
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15.3.4
15.3.5
15.4
15.5
15.6
Frame Formats ...........................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
777
784
785
786
787
16
Inter-Integrated Circuit (I2C) Interface ................................................................ 815
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.4
16.5
16.6
16.7
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
I2C Bus Functional Overview ........................................................................................
Available Speed Modes ...............................................................................................
Interrupts ....................................................................................................................
Loopback Operation ....................................................................................................
Command Sequence Flow Charts ................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions (I2C Master) ...............................................................................
Register Descriptions (I2C Slave) .................................................................................
17
Inter-Integrated Circuit Sound (I2S) Interface .................................................... 853
17.1
17.2
17.3
17.3.1
17.3.2
17.4
17.5
17.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Transmit .....................................................................................................................
Receive ......................................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
18
Controller Area Network (CAN) Module ............................................................. 890
816
816
817
817
819
820
821
822
829
830
831
844
854
854
855
857
861
863
864
865
18.1
Block Diagram ............................................................................................................ 891
18.2
Signal Description ....................................................................................................... 891
18.3
Functional Description ................................................................................................. 892
18.3.1 Initialization ................................................................................................................. 893
18.3.2 Operation ................................................................................................................... 894
18.3.3 Transmitting Message Objects ..................................................................................... 895
18.3.4 Configuring a Transmit Message Object ........................................................................ 895
18.3.5 Updating a Transmit Message Object ........................................................................... 896
18.3.6 Accepting Received Message Objects .......................................................................... 897
18.3.7 Receiving a Data Frame .............................................................................................. 897
18.3.8 Receiving a Remote Frame .......................................................................................... 897
18.3.9 Receive/Transmit Priority ............................................................................................. 898
18.3.10 Configuring a Receive Message Object ........................................................................ 898
18.3.11 Handling of Received Message Objects ........................................................................ 899
18.3.12 Handling of Interrupts .................................................................................................. 901
18.3.13 Test Mode ................................................................................................................... 902
18.3.14 Bit Timing Configuration Error Considerations ............................................................... 904
18.3.15 Bit Time and Bit Rate ................................................................................................... 904
18.3.16 Calculating the Bit Timing Parameters .......................................................................... 906
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18.4
18.5
Register Map .............................................................................................................. 909
CAN Register Descriptions .......................................................................................... 910
19
Ethernet Controller .............................................................................................. 941
19.1
19.2
19.3
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.4
19.4.1
19.4.2
19.5
19.6
19.7
Block Diagram ............................................................................................................ 942
Signal Description ....................................................................................................... 943
Functional Description ................................................................................................. 944
MAC Operation ........................................................................................................... 944
Internal MII Operation .................................................................................................. 947
PHY Operation ............................................................................................................ 947
Interrupts .................................................................................................................... 950
DMA Operation ........................................................................................................... 950
Initialization and Configuration ..................................................................................... 951
Hardware Configuration ............................................................................................... 951
Software Configuration ................................................................................................ 952
Register Map .............................................................................................................. 952
Ethernet MAC Register Descriptions ............................................................................. 954
MII Management Register Descriptions ......................................................................... 979
20
Universal Serial Bus (USB) Controller ............................................................. 1000
20.1
20.2
20.3
20.3.1
20.3.2
20.3.3
20.3.4
20.4
20.4.1
20.4.2
20.5
20.6
Block Diagram ........................................................................................................... 1001
Signal Description ..................................................................................................... 1001
Functional Description ............................................................................................... 1003
Operation as a Device ............................................................................................... 1003
Operation as a Host ................................................................................................... 1008
OTG Mode ................................................................................................................ 1012
DMA Operation ......................................................................................................... 1014
Initialization and Configuration .................................................................................... 1015
Pin Configuration ....................................................................................................... 1015
Endpoint Configuration .............................................................................................. 1016
Register Map ............................................................................................................ 1016
Register Descriptions ................................................................................................. 1027
21
Analog Comparators .......................................................................................... 1139
21.1
21.2
21.3
21.3.1
21.4
21.5
21.6
Block Diagram ...........................................................................................................
Signal Description .....................................................................................................
Functional Description ...............................................................................................
Internal Reference Programming ................................................................................
Initialization and Configuration ....................................................................................
Register Map ............................................................................................................
Register Descriptions .................................................................................................
22
Pin Diagram ........................................................................................................ 1153
1140
1140
1141
1142
1143
1144
1145
23
Signal Tables ...................................................................................................... 1155
23.1
23.1.1
23.1.2
23.1.3
23.1.4
23.1.5
23.2
100-Pin LQFP Package Pin Tables .............................................................................
Signals by Pin Number ..............................................................................................
Signals by Signal Name .............................................................................................
Signals by Function, Except for GPIO .........................................................................
GPIO Pins and Alternate Functions ............................................................................
Possible Pin Assignments for Alternate Functions .......................................................
108-Ball BGA Package Pin Tables ..............................................................................
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1156
1165
1174
1181
1184
1187
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23.2.1
23.2.2
23.2.3
23.2.4
23.2.5
23.3
Signals by Pin Number ..............................................................................................
Signals by Signal Name .............................................................................................
Signals by Function, Except for GPIO .........................................................................
GPIO Pins and Alternate Functions ............................................................................
Possible Pin Assignments for Alternate Functions .......................................................
Connections for Unused Signals .................................................................................
1187
1197
1206
1213
1216
1218
24
Operating Characteristics ................................................................................. 1221
25
Electrical Characteristics .................................................................................. 1222
25.1
Maximum Ratings ...................................................................................................... 1222
25.2
Recommended Operating Conditions ......................................................................... 1222
25.3
Load Conditions ........................................................................................................ 1223
25.4
JTAG and Boundary Scan .......................................................................................... 1223
25.5
Power and Brown-Out ............................................................................................... 1225
25.6
Reset ........................................................................................................................ 1226
25.7
On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1227
25.8
Clocks ...................................................................................................................... 1227
25.8.1 PLL Specifications ..................................................................................................... 1227
25.8.2 PIOSC Specifications ................................................................................................ 1228
25.8.3 Internal 30-kHz Oscillator Specifications ..................................................................... 1228
25.8.4 Hibernation Clock Source Specifications ..................................................................... 1229
25.8.5 Main Oscillator Specifications ..................................................................................... 1229
25.8.6 System Clock Specification with ADC Operation .......................................................... 1230
25.8.7 System Clock Specification with USB Operation .......................................................... 1230
25.9
Sleep Modes ............................................................................................................. 1230
25.10 Hibernation Module ................................................................................................... 1231
25.11 Flash Memory ........................................................................................................... 1232
25.12 Input/Output Characteristics ....................................................................................... 1232
25.13 External Peripheral Interface (EPI) .............................................................................. 1233
25.14 Analog-to-Digital Converter (ADC) .............................................................................. 1239
25.15 Synchronous Serial Interface (SSI) ............................................................................. 1240
25.16 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1242
25.17 Inter-Integrated Circuit Sound (I2S) Interface ............................................................... 1243
25.18 Ethernet Controller .................................................................................................... 1244
25.19 Universal Serial Bus (USB) Controller ......................................................................... 1247
25.20 Analog Comparator ................................................................................................... 1247
25.21 Current Consumption ................................................................................................. 1248
25.21.1 Nominal Power Consumption ..................................................................................... 1248
25.21.2 Maximum Current Consumption ................................................................................. 1249
A
Register Quick Reference ................................................................................. 1251
B
Ordering and Contact Information ................................................................... 1302
B.1
B.2
B.3
B.4
Ordering Information ..................................................................................................
Part Markings ............................................................................................................
Kits ...........................................................................................................................
Support Information ...................................................................................................
1302
1302
1302
1303
C
Package Information .......................................................................................... 1304
C.1
C.1.1
100-Pin LQFP Package ............................................................................................. 1304
Package Dimensions ................................................................................................. 1304
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C.1.2
C.1.3
C.2
C.2.1
C.2.2
C.2.3
Tray Dimensions .......................................................................................................
Tape and Reel Dimensions ........................................................................................
108-Ball BGA Package ..............................................................................................
Package Dimensions .................................................................................................
Tray Dimensions .......................................................................................................
Tape and Reel Dimensions ........................................................................................
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1306
1306
1308
1308
1310
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Texas Instruments-Production Data
Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Stellaris LM3S9U90 Microcontroller High-Level Block Diagram ............................... 47
CPU Block Diagram ............................................................................................. 70
TPIU Block Diagram ............................................................................................ 71
Cortex-M3 Register Set ........................................................................................ 73
Bit-Band Mapping ................................................................................................ 94
Data Storage ....................................................................................................... 95
Vector Table ...................................................................................................... 101
Exception Stack Frame ...................................................................................... 103
SRD Use Example ............................................................................................. 117
JTAG Module Block Diagram .............................................................................. 178
Test Access Port State Machine ......................................................................... 181
IDCODE Register Format ................................................................................... 187
BYPASS Register Format ................................................................................... 188
Boundary Scan Register Format ......................................................................... 188
Basic RST Configuration .................................................................................... 192
External Circuitry to Extend Power-On Reset ....................................................... 192
Reset Circuit Controlled by Switch ...................................................................... 193
Power Architecture ............................................................................................ 196
Main Clock Tree ................................................................................................ 199
Hibernation Module Block Diagram ..................................................................... 294
Using a Crystal as the Hibernation Clock Source ................................................. 297
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 297
Figure 7-1.
Internal Memory Block Diagram .......................................................................... 320
Figure 8-1.
μDMA Block Diagram ......................................................................................... 367
Figure 8-2.
Example of Ping-Pong μDMA Transaction ........................................................... 374
Figure 8-3.
Memory Scatter-Gather, Setup and Configuration ................................................ 376
Figure 8-4.
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 377
Figure 8-5.
Peripheral Scatter-Gather, Setup and Configuration ............................................. 379
Figure 8-6.
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 380
Figure 9-1.
Digital I/O Pads ................................................................................................. 432
Figure 9-2.
Analog/Digital I/O Pads ...................................................................................... 433
Figure 9-3.
GPIODATA Write Example ................................................................................. 434
Figure 9-4.
GPIODATA Read Example ................................................................................. 434
Figure 10-1. EPI Block Diagram ............................................................................................. 484
Figure 10-2. SDRAM Non-Blocking Read Cycle ...................................................................... 492
Figure 10-3. SDRAM Normal Read Cycle ............................................................................... 492
Figure 10-4. SDRAM Write Cycle ........................................................................................... 493
Figure 10-5. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 499
Figure 10-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 501
Figure 10-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 502
Figure 10-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 502
Figure 10-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual
CSn .................................................................................................................. 503
Figure 10-10. Continuous Read Mode Accesses ...................................................................... 503
12
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Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Figure 10-11.
Figure 10-12.
Figure 10-13.
Figure 10-14.
Figure 10-15.
Figure 10-16.
Figure 10-17.
Figure 10-18.
Figure 10-19.
Figure 10-20.
Figure 10-21.
Figure 10-22.
Figure 10-23.
Figure 10-24.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 12-1.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10.
Figure 13-11.
Figure 13-12.
Figure 13-13.
Figure 13-14.
Figure 13-15.
Figure 13-16.
Figure 13-17.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Write Followed by Read to External FIFO ............................................................ 504
Two-Entry FIFO ................................................................................................. 504
Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 508
Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
WRCYC=1 ........................................................................................................ 508
Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 509
FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 509
FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 509
FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 510
FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 510
FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 510
FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 510
iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 511
EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 512
EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 512
GPTM Module Block Diagram ............................................................................ 558
Timer Daisy Chain ............................................................................................. 563
Input Edge-Count Mode Example ....................................................................... 565
16-Bit Input Edge-Time Mode Example ............................................................... 567
16-Bit PWM Mode Example ................................................................................ 568
WDT Module Block Diagram .............................................................................. 605
Implementation of Two ADC Blocks .................................................................... 630
ADC Module Block Diagram ............................................................................... 631
ADC Sample Phases ......................................................................................... 635
Doubling the ADC Sample Rate .......................................................................... 635
Skewed Sampling .............................................................................................. 636
Sample Averaging Example ............................................................................... 637
ADC Input Equivalency Diagram ......................................................................... 638
Internal Voltage Conversion Result ..................................................................... 639
External Voltage Conversion Result with 3.0-V Setting ......................................... 640
External Voltage Conversion Result with 1.0-V Setting ......................................... 640
Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 642
Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 642
Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 643
Internal Temperature Sensor Characteristic ......................................................... 644
Low-Band Operation (CIC=0x0) .......................................................................... 646
Mid-Band Operation (CIC=0x1) .......................................................................... 647
High-Band Operation (CIC=0x3) ......................................................................... 648
UART Module Block Diagram ............................................................................. 710
UART Character Frame ..................................................................................... 713
IrDA Data Modulation ......................................................................................... 715
LIN Message ..................................................................................................... 717
LIN Synchronization Field ................................................................................... 718
SSI Module Block Diagram ................................................................................. 774
TI Synchronous Serial Frame Format (Single Transfer) ........................................ 778
TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 778
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 779
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 779
July 03, 2014
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Texas Instruments-Production Data
Table of Contents
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10.
Figure 15-11.
Figure 15-12.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
Figure 16-10.
Figure 16-11.
Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 780
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 781
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 781
Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 782
MICROWIRE Frame Format (Single Frame) ........................................................ 783
MICROWIRE Frame Format (Continuous Transfer) ............................................. 784
MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 784
I2C Block Diagram ............................................................................................. 816
I2C Bus Configuration ........................................................................................ 817
START and STOP Conditions ............................................................................. 818
Complete Data Transfer with a 7-Bit Address ....................................................... 818
R/S Bit in First Byte ............................................................................................ 819
Data Validity During Bit Transfer on the I2C Bus ................................................... 819
Master Single TRANSMIT .................................................................................. 823
Master Single RECEIVE ..................................................................................... 824
Master TRANSMIT with Repeated START ........................................................... 825
Master RECEIVE with Repeated START ............................................................. 826
Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 827
Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 828
Figure 16-13. Slave Command Sequence ................................................................................ 829
Figure 17-1. I2S Block Diagram ............................................................................................. 854
Figure 17-2. I2S Data Transfer ............................................................................................... 857
Figure 17-3. Left-Justified Data Transfer ................................................................................ 857
Figure 17-4. Right-Justified Data Transfer .............................................................................. 857
Figure 18-1. CAN Controller Block Diagram ............................................................................ 891
Figure 18-2. CAN Data/Remote Frame .................................................................................. 893
Figure 18-3. Message Objects in a FIFO Buffer ...................................................................... 901
Figure 18-4. CAN Bit Time .................................................................................................... 905
Figure 19-1. Ethernet Controller ............................................................................................. 942
Figure 19-2. Ethernet Controller Block Diagram ...................................................................... 942
Figure 19-3. Ethernet Frame ................................................................................................. 944
Figure 19-4. Interface to an Ethernet Jack .............................................................................. 951
Figure 20-1. USB Module Block Diagram ............................................................................. 1001
Figure 21-1. Analog Comparator Module Block Diagram ....................................................... 1140
Figure 21-2. Structure of Comparator Unit ............................................................................ 1142
Figure 21-3. Comparator Internal Reference Structure .......................................................... 1142
Figure 22-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1153
Figure 22-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1154
Figure 25-1. Load Conditions ............................................................................................... 1223
Figure 25-2. JTAG Test Clock Input Timing ........................................................................... 1224
Figure 25-3. JTAG Test Access Port (TAP) Timing ................................................................ 1224
Figure 25-4. Power-On Reset Timing ................................................................................... 1225
Figure 25-5. Brown-Out Reset Timing .................................................................................. 1225
Figure 25-6. Power-On Reset and Voltage Parameters ......................................................... 1226
Figure 25-7. External Reset Timing (RST) ............................................................................ 1226
Figure 25-8. Software Reset Timing ..................................................................................... 1226
14
July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Figure 25-9.
Figure 25-10.
Figure 25-11.
Figure 25-12.
Figure 25-13.
Figure 25-14.
Figure 25-15.
Figure 25-16.
Figure 25-17.
Figure 25-18.
Figure 25-19.
Figure 25-20.
Figure 25-21.
Figure 25-22.
Figure 25-23.
Figure 25-24.
Figure 25-25.
Figure 25-26.
Figure 25-27.
Figure 25-28.
Figure 25-29.
Figure 25-30.
Figure 25-31.
Figure C-1.
Figure C-2.
Figure C-3.
Figure C-4.
Figure C-5.
Figure C-6.
Watchdog Reset Timing ................................................................................... 1227
MOSC Failure Reset Timing ............................................................................. 1227
Hibernation Module Timing with Internal Oscillator Running in Hibernation .......... 1232
Hibernation Module Timing with Internal Oscillator Stopped in Hibernation .......... 1232
SDRAM Initialization and Load Mode Register Timing ........................................ 1234
SDRAM Read Timing ....................................................................................... 1234
SDRAM Write Timing ....................................................................................... 1235
Host-Bus 8/16 Mode Read Timing ..................................................................... 1236
Host-Bus 8/16 Mode Write Timing ..................................................................... 1236
Host-Bus 8/16 Mode Muxed Read Timing .......................................................... 1237
Host-Bus 8/16 Mode Muxed Write Timing .......................................................... 1237
General-Purpose Mode Read and Write Timing ................................................. 1238
General-Purpose Mode iRDY Timing ................................................................. 1238
ADC Input Equivalency Diagram ....................................................................... 1240
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1241
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1241
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1242
I2C Timing ....................................................................................................... 1243
I2S Master Mode Transmit Timing ..................................................................... 1243
I2S Master Mode Receive Timing ...................................................................... 1244
I2S Slave Mode Transmit Timing ....................................................................... 1244
I2S Slave Mode Receive Timing ........................................................................ 1244
External XTLP Oscillator Characteristics ........................................................... 1247
Stellaris LM3S9U90 100-Pin LQFP Package Dimensions ................................... 1304
100-Pin LQFP Tray Dimensions ........................................................................ 1306
100-Pin LQFP Tape and Reel Dimensions ......................................................... 1307
Stellaris LM3S9U90 108-Ball BGA Package Dimensions .................................... 1308
108-Ball BGA Tray Dimensions ......................................................................... 1310
108-Ball BGA Tape and Reel Dimensions .......................................................... 1311
July 03, 2014
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Texas Instruments-Production Data
Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Revision History .................................................................................................. 40
Documentation Conventions ................................................................................ 44
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 73
Processor Register Map ....................................................................................... 74
PSR Register Combinations ................................................................................. 79
Memory Map ....................................................................................................... 87
Memory Access Behavior ..................................................................................... 90
SRAM Memory Bit-Banding Regions .................................................................... 92
Peripheral Memory Bit-Banding Regions ............................................................... 92
Exception Types .................................................................................................. 98
Interrupts ............................................................................................................ 99
Exception Return Behavior ................................................................................. 104
Faults ............................................................................................................... 104
Fault Status and Fault Address Registers ............................................................ 106
Cortex-M3 Instruction Summary ......................................................................... 108
Core Peripheral Register Regions ....................................................................... 111
Memory Attributes Summary .............................................................................. 114
TEX, S, C, and B Bit Field Encoding ................................................................... 117
Cache Policy for Memory Attribute Encoding ....................................................... 118
AP Bit Field Encoding ........................................................................................ 118
Memory Region Attributes for Stellaris Microcontrollers ........................................ 118
Peripherals Register Map ................................................................................... 119
Interrupt Priority Levels ...................................................................................... 146
Example SIZE Field Values ................................................................................ 174
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 178
JTAG_SWD_SWO Signals (108BGA) ................................................................. 179
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 180
JTAG Instruction Register Commands ................................................................. 185
System Control & Clocks Signals (100LQFP) ...................................................... 189
System Control & Clocks Signals (108BGA) ........................................................ 189
Reset Sources ................................................................................................... 190
Clock Source Options ........................................................................................ 197
Possible System Clock Frequencies Using the SYSDIV Field ............................... 200
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 200
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 201
System Control Register Map ............................................................................. 206
RCC2 Fields that Override RCC Fields ............................................................... 226
Hibernate Signals (100LQFP) ............................................................................. 294
Hibernate Signals (108BGA) .............................................................................. 295
Hibernation Module Clock Operation ................................................................... 301
Hibernation Module Register Map ....................................................................... 303
Flash Memory Protection Policy Combinations .................................................... 324
User-Programmable Flash Memory Resident Registers ....................................... 328
Flash Register Map ............................................................................................ 328
μDMA Channel Assignments .............................................................................. 368
Request Type Support ....................................................................................... 370
16
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Stellaris LM3S9U90 Microcontroller
Table 8-3.
Table 8-4.
Table 8-5.
Table 8-6.
Table 8-7.
Table 8-8.
Table 8-9.
Table 8-10.
Table 8-11.
Table 8-12.
Table 8-13.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Table 9-10.
Table 9-11.
Table 9-12.
Table 10-1.
Table 10-2.
Table 10-3.
Table 10-4.
Table 10-5.
Table 10-6.
Table 10-7.
Table 10-8.
Table 11-1.
Table 11-2.
Table 11-3.
Table 11-4.
Table 11-5.
Table 11-6.
Table 11-7.
Table 11-8.
Table 11-9.
Table 11-10.
Table 11-11.
Table 12-1.
Table 13-1.
Table 13-2.
Table 13-3.
Table 13-4.
Control Structure Memory Map ........................................................................... 371
Channel Control Structure .................................................................................. 371
μDMA Read Example: 8-Bit Peripheral ................................................................ 381
μDMA Interrupt Assignments .............................................................................. 382
Channel Control Structure Offsets for Channel 30 ................................................ 383
Channel Control Word Configuration for Memory Transfer Example ...................... 383
Channel Control Structure Offsets for Channel 7 .................................................. 384
Channel Control Word Configuration for Peripheral Transmit Example .................. 385
Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 386
Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 387
μDMA Register Map .......................................................................................... 389
GPIO Pins With Non-Zero Reset Values .............................................................. 428
GPIO Pins and Alternate Functions (100LQFP) ................................................... 428
GPIO Pins and Alternate Functions (108BGA) ..................................................... 430
GPIO Pad Configuration Examples ..................................................................... 436
GPIO Interrupt Configuration Example ................................................................ 437
GPIO Pins With Non-Zero Reset Values .............................................................. 438
GPIO Register Map ........................................................................................... 438
GPIO Pins With Non-Zero Reset Values .............................................................. 450
GPIO Pins With Non-Zero Reset Values .............................................................. 456
GPIO Pins With Non-Zero Reset Values .............................................................. 458
GPIO Pins With Non-Zero Reset Values .............................................................. 461
GPIO Pins With Non-Zero Reset Values .............................................................. 468
External Peripheral Interface Signals (100LQFP) ................................................. 484
External Peripheral Interface Signals (108BGA) ................................................... 485
EPI SDRAM Signal Connections ......................................................................... 490
Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 494
EPI Host-Bus 8 Signal Connections .................................................................... 495
EPI Host-Bus 16 Signal Connections .................................................................. 497
EPI General Purpose Signal Connections ........................................................... 506
External Peripheral Interface (EPI) Register Map ................................................. 512
Available CCP Pins ............................................................................................ 558
General-Purpose Timers Signals (100LQFP) ....................................................... 559
General-Purpose Timers Signals (108BGA) ......................................................... 560
General-Purpose Timer Capabilities .................................................................... 561
Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 562
16-Bit Timer With Prescaler Configurations ......................................................... 563
Counter Values When the Timer is Enabled in RTC Mode .................................... 564
Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 564
Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 566
Counter Values When the Timer is Enabled in PWM Mode ................................... 567
Timers Register Map .......................................................................................... 572
Watchdog Timers Register Map .......................................................................... 607
ADC Signals (100LQFP) .................................................................................... 631
ADC Signals (108BGA) ...................................................................................... 632
Samples and FIFO Depth of Sequencers ............................................................ 633
Differential Sampling Pairs ................................................................................. 641
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Texas Instruments-Production Data
Table of Contents
Table 13-5.
Table 14-1.
Table 14-2.
Table 14-3.
Table 14-4.
Table 15-1.
Table 15-2.
Table 15-3.
Table 16-1.
Table 16-2.
Table 16-3.
Table 16-4.
Table 16-5.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table 17-6.
Table 17-7.
Table 17-8.
Table 17-9.
Table 17-10.
Table 18-1.
Table 18-2.
Table 18-3.
Table 18-4.
Table 18-5.
Table 18-6.
Table 19-1.
Table 19-2.
Table 19-3.
Table 19-4.
Table 20-1.
Table 20-2.
Table 20-3.
Table 20-4.
Table 20-5.
Table 20-6.
Table 21-1.
Table 21-2.
Table 21-3.
Table 21-4.
Table 23-1.
Table 23-2.
Table 23-3.
Table 23-4.
Table 23-5.
ADC Register Map ............................................................................................. 649
UART Signals (100LQFP) .................................................................................. 711
UART Signals (108BGA) .................................................................................... 711
Flow Control Mode ............................................................................................. 716
UART Register Map ........................................................................................... 722
SSI Signals (100LQFP) ...................................................................................... 775
SSI Signals (108BGA) ........................................................................................ 775
SSI Register Map .............................................................................................. 786
I2C Signals (100LQFP) ...................................................................................... 816
I2C Signals (108BGA) ........................................................................................ 816
Examples of I2C Master Timer Period versus Speed Mode ................................... 820
Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 830
Write Field Decoding for I2CMCS[3:0] Field ......................................................... 836
I2S Signals (100LQFP) ...................................................................................... 855
I2S Signals (108BGA) ........................................................................................ 855
I2S Transmit FIFO Interface ................................................................................ 858
Crystal Frequency (Values from 3.5795 MHz to 5 MHz) ........................................ 859
Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) ..................................... 859
Crystal Frequency (Values from 10 MHz to 14.3181 MHz) .................................... 860
Crystal Frequency (Values from 16 MHz to 16.384 MHz) ...................................... 860
I2S Receive FIFO Interface ................................................................................. 862
Audio Formats Configuration .............................................................................. 864
Inter-Integrated Circuit Sound (I2S) Interface Register Map ................................... 865
Controller Area Network Signals (100LQFP) ........................................................ 892
Controller Area Network Signals (108BGA) ......................................................... 892
Message Object Configurations .......................................................................... 898
CAN Protocol Ranges ........................................................................................ 905
CANBIT Register Values .................................................................................... 905
CAN Register Map ............................................................................................. 909
Ethernet Signals (100LQFP) ............................................................................... 943
Ethernet Signals (108BGA) ................................................................................ 943
TX & RX FIFO Organization ............................................................................... 946
Ethernet Register Map ....................................................................................... 953
USB Signals (100LQFP) ................................................................................... 1002
USB Signals (108BGA) .................................................................................... 1002
Remainder (MAXLOAD/4) ................................................................................ 1014
Actual Bytes Read ........................................................................................... 1014
Packet Sizes That Clear RXRDY ...................................................................... 1015
Universal Serial Bus (USB) Controller Register Map ........................................... 1016
Analog Comparators Signals (100LQFP) ........................................................... 1140
Analog Comparators Signals (108BGA) ............................................................. 1141
Internal Reference Voltage and ACREFCTL Field Values ................................... 1143
Analog Comparators Register Map ................................................................... 1144
GPIO Pins With Default Alternate Functions ...................................................... 1155
Signals by Pin Number ..................................................................................... 1156
Signals by Signal Name ................................................................................... 1165
Signals by Function, Except for GPIO ............................................................... 1174
GPIO Pins and Alternate Functions ................................................................... 1181
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Stellaris LM3S9U90 Microcontroller
Table 23-6.
Table 23-7.
Table 23-8.
Table 23-9.
Table 23-10.
Table 23-11.
Table 23-12.
Table 23-13.
Table 24-1.
Table 24-2.
Table 24-3.
Table 25-1.
Table 25-2.
Table 25-3.
Table 25-4.
Table 25-5.
Table 25-6.
Table 25-7.
Table 25-8.
Table 25-9.
Table 25-10.
Table 25-11.
Table 25-12.
Table 25-13.
Table 25-14.
Table 25-15.
Table 25-16.
Table 25-17.
Table 25-18.
Table 25-19.
Table 25-20.
Table 25-21.
Table 25-22.
Table 25-23.
Table 25-24.
Table 25-25.
Table 25-26.
Table 25-27.
Table 25-28.
Table 25-29.
Table 25-30.
Table 25-31.
Table 25-32.
Table 25-33.
Table 25-34.
Table 25-35.
Table 25-36.
Table 25-37.
Possible Pin Assignments for Alternate Functions .............................................. 1184
Signals by Pin Number ..................................................................................... 1187
Signals by Signal Name ................................................................................... 1197
Signals by Function, Except for GPIO ............................................................... 1206
GPIO Pins and Alternate Functions ................................................................... 1213
Possible Pin Assignments for Alternate Functions .............................................. 1216
Connections for Unused Signals (100-Pin LQFP) ............................................... 1219
Connections for Unused Signals (108-Ball BGA) ................................................ 1220
Temperature Characteristics ............................................................................. 1221
Thermal Characteristics ................................................................................... 1221
ESD Absolute Maximum Ratings ...................................................................... 1221
Maximum Ratings ............................................................................................ 1222
Recommended DC Operating Conditions .......................................................... 1222
JTAG Characteristics ....................................................................................... 1223
Power Characteristics ...................................................................................... 1225
Reset Characteristics ....................................................................................... 1226
LDO Regulator Characteristics ......................................................................... 1227
Phase Locked Loop (PLL) Characteristics ......................................................... 1227
Actual PLL Frequency ...................................................................................... 1228
PIOSC Clock Characteristics ............................................................................ 1228
30-kHz Clock Characteristics ............................................................................ 1228
Hibernation Clock Characteristics ..................................................................... 1229
HIB Oscillator Input Characteristics ................................................................... 1229
Main Oscillator Clock Characteristics ................................................................ 1229
Supported MOSC Crystal Frequencies .............................................................. 1229
System Clock Characteristics with ADC Operation ............................................. 1230
System Clock Characteristics with USB Operation ............................................. 1230
Sleep Modes AC Characteristics ....................................................................... 1230
Hibernation Module Battery Characteristics ....................................................... 1231
Hibernation Module AC Characteristics ............................................................. 1231
Flash Memory Characteristics ........................................................................... 1232
GPIO Module Characteristics ............................................................................ 1232
EPI SDRAM Characteristics ............................................................................. 1233
EPI SDRAM Interface Characteristics ............................................................... 1233
EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics ................................. 1235
EPI General-Purpose Interface Characteristics .................................................. 1237
ADC Characteristics ......................................................................................... 1239
ADC Module External Reference Characteristics ............................................... 1240
ADC Module Internal Reference Characteristics ................................................ 1240
SSI Characteristics .......................................................................................... 1240
I2C Characteristics ........................................................................................... 1242
I2S Master Clock (Receive and Transmit) .......................................................... 1243
I2S Slave Clock (Receive and Transmit) ............................................................ 1243
I2S Master Mode .............................................................................................. 1243
I2S Slave Mode ................................................................................................ 1244
Ethernet Controller DC Characteristics .............................................................. 1244
100BASE-TX Transmitter Characteristics .......................................................... 1245
100BASE-TX Transmitter Characteristics (informative) ....................................... 1245
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Table 25-38.
Table 25-39.
Table 25-40.
Table 25-41.
Table 25-42.
Table 25-43.
Table 25-44.
Table 25-45.
Table 25-46.
Table 25-47.
Table 25-48.
Table 25-49.
Table 25-50.
100BASE-TX Receiver Characteristics ..............................................................
10BASE-T Transmitter Characteristics ..............................................................
10BASE-T Transmitter Characteristics (informative) ...........................................
10BASE-T Receiver Characteristics ..................................................................
Isolation Transformers ......................................................................................
Ethernet Reference Crystal ..............................................................................
External XTLP Oscillator Characteristics ...........................................................
USB Controller Characteristics .........................................................................
Analog Comparator Characteristics ...................................................................
Analog Comparator Voltage Reference Characteristics ......................................
Nominal Power Consumption ...........................................................................
Detailed Current Specifications .........................................................................
Hibernation Detailed Current Specifications .......................................................
20
1245
1245
1245
1246
1246
1246
1247
1247
1247
1248
1248
1249
1250
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List of Registers
The Cortex-M3 Processor ............................................................................................................. 68
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Cortex General-Purpose Register 0 (R0) ........................................................................... 75
Cortex General-Purpose Register 1 (R1) ........................................................................... 75
Cortex General-Purpose Register 2 (R2) ........................................................................... 75
Cortex General-Purpose Register 3 (R3) ........................................................................... 75
Cortex General-Purpose Register 4 (R4) ........................................................................... 75
Cortex General-Purpose Register 5 (R5) ........................................................................... 75
Cortex General-Purpose Register 6 (R6) ........................................................................... 75
Cortex General-Purpose Register 7 (R7) ........................................................................... 75
Cortex General-Purpose Register 8 (R8) ........................................................................... 75
Cortex General-Purpose Register 9 (R9) ........................................................................... 75
Cortex General-Purpose Register 10 (R10) ....................................................................... 75
Cortex General-Purpose Register 11 (R11) ........................................................................ 75
Cortex General-Purpose Register 12 (R12) ....................................................................... 75
Stack Pointer (SP) ........................................................................................................... 76
Link Register (LR) ............................................................................................................ 77
Program Counter (PC) ..................................................................................................... 78
Program Status Register (PSR) ........................................................................................ 79
Priority Mask Register (PRIMASK) .................................................................................... 83
Fault Mask Register (FAULTMASK) .................................................................................. 84
Base Priority Mask Register (BASEPRI) ............................................................................ 85
Control Register (CONTROL) ........................................................................................... 86
Cortex-M3 Peripherals ................................................................................................................. 111
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 122
SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 124
SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 125
Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 126
Interrupt 32-54 Set Enable (EN1), offset 0x104 ................................................................ 127
Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 128
Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ............................................................ 129
Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 130
Interrupt 32-54 Set Pending (PEND1), offset 0x204 ......................................................... 131
Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 132
Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 .................................................. 133
Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 134
Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ........................................................... 135
Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 136
Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 136
Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 136
Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 136
Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 136
Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 136
Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 136
Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 136
Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 136
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Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 136
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 136
Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 136
Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 136
Interrupt 52-54 Priority (PRI13), offset 0x434 ................................................................... 136
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 138
Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 139
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 141
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 142
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 145
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 146
System Control (SYSCTRL), offset 0xD10 ....................................................................... 148
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 150
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 152
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 153
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 154
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 155
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 159
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 165
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 166
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 167
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 168
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 169
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 171
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 172
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 172
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 172
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 172
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 174
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 174
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 174
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 174
System Control ............................................................................................................................ 189
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Device Identification 0 (DID0), offset 0x000 ..................................................................... 208
Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 210
Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 211
Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 213
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 215
Reset Cause (RESC), offset 0x05C ................................................................................ 217
Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 219
XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 223
GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 224
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 226
Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 229
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 230
Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 232
Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 234
I2S MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 235
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Stellaris LM3S9U90 Microcontroller
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Device Identification 1 (DID1), offset 0x004 ..................................................................... 237
Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 239
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 240
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 242
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 244
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 246
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 248
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 249
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 250
Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 254
Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 257
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 259
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 260
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 263
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 266
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 268
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 271
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 274
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 277
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 280
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 283
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 286
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 288
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 291
Hibernation Module ..................................................................................................................... 293
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Hibernation RTC Counter (HIBRTCC), offset 0x000 .........................................................
Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 .......................................................
Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 .......................................................
Hibernation RTC Load (HIBRTCLD), offset 0x00C ...........................................................
Hibernation Control (HIBCTL), offset 0x010 .....................................................................
Hibernation Interrupt Mask (HIBIM), offset 0x014 .............................................................
Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 ..................................................
Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................
Hibernation Interrupt Clear (HIBIC), offset 0x020 .............................................................
Hibernation RTC Trim (HIBRTCT), offset 0x024 ...............................................................
Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................
304
305
306
307
308
311
313
315
317
318
319
Internal Memory ........................................................................................................................... 320
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Flash Memory Address (FMA), offset 0x000 .................................................................... 331
Flash Memory Data (FMD), offset 0x004 ......................................................................... 332
Flash Memory Control (FMC), offset 0x008 ..................................................................... 333
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 336
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 337
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 338
Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 339
Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 340
Flash Control (FCTL), offset 0x0F8 ................................................................................. 341
Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 342
ROM Control (RMCTL), offset 0x0F0 .............................................................................. 343
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Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 344
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 345
Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 346
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 348
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 349
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 350
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 351
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 352
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 353
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 354
Flash Memory Protection Read Enable 4 (FMPRE4), offset 0x210 .................................... 355
Flash Memory Protection Read Enable 5 (FMPRE5), offset 0x214 .................................... 356
Flash Memory Protection Read Enable 6 (FMPRE6), offset 0x218 .................................... 357
Flash Memory Protection Read Enable 7 (FMPRE7), offset 0x21C ................................... 358
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 359
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 360
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 361
Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 ............................... 362
Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 ............................... 363
Flash Memory Protection Program Enable 6 (FMPPE6), offset 0x418 ............................... 364
Flash Memory Protection Program Enable 7 (FMPPE7), offset 0x41C ............................... 365
Micro Direct Memory Access (μDMA) ........................................................................................ 366
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 391
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 392
DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 393
DMA Status (DMASTAT), offset 0x000 ............................................................................ 398
DMA Configuration (DMACFG), offset 0x004 ................................................................... 400
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 401
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 402
DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 403
DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 404
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 405
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 406
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 407
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 408
DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 409
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 410
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 411
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 412
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 413
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 414
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 415
DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 416
DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 417
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 418
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 419
DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 420
DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 421
24
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Stellaris LM3S9U90 Microcontroller
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 .........................................
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ...........................................
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ...........................................
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ...........................................
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ...........................................
422
423
424
425
426
General-Purpose Input/Outputs (GPIOs) ................................................................................... 427
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 440
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 441
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 442
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 443
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 444
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 445
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 446
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 447
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 449
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 450
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 452
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 453
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 454
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 455
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 456
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 458
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 460
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 461
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 463
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 464
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 466
GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 468
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 470
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 471
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 472
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 473
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 474
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 475
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 476
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 477
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 478
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 479
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 480
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 481
External Peripheral Interface (EPI) ............................................................................................. 482
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
EPI Configuration (EPICFG), offset 0x000 .......................................................................
EPI Main Baud Rate (EPIBAUD), offset 0x004 .................................................................
EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 ..............................................
EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ...............................................
EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ...........................................
EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ........................................
EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 ..........................................
July 03, 2014
514
515
517
519
522
526
531
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Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 ....................................... 534
EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 ................................... 537
EPI Address Map (EPIADDRMAP), offset 0x01C ............................................................. 538
EPI Read Size 0 (EPIRSIZE0), offset 0x020 .................................................................... 540
EPI Read Size 1 (EPIRSIZE1), offset 0x030 .................................................................... 540
EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................ 541
EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................ 541
EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 ............................................. 542
EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 ............................................. 542
EPI Status (EPISTAT), offset 0x060 ................................................................................ 544
EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ...................................................... 546
EPI Read FIFO (EPIREADFIFO), offset 0x070 ................................................................ 547
EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 .................................................... 547
EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 .................................................... 547
EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ................................................... 547
EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 .................................................... 547
EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 .................................................... 547
EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 .................................................... 547
EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ................................................... 547
EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................ 548
EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ...................................................... 550
EPI Interrupt Mask (EPIIM), offset 0x210 ......................................................................... 551
EPI Raw Interrupt Status (EPIRIS), offset 0x214 .............................................................. 552
EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................ 554
EPI Error and Interrupt Status and Clear (EPIEISC), offset 0x21C .................................... 555
General-Purpose Timers ............................................................................................................. 557
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 574
GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 575
GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 577
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 579
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 582
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 584
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 587
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 590
GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 592
GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 593
GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 594
GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 595
GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 596
GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 597
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 598
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 599
GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 600
GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 601
GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 602
GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 603
Watchdog Timers ......................................................................................................................... 604
Register 1:
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 608
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Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 609
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 610
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 612
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 613
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 614
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 615
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 616
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 617
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 618
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 619
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 620
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 621
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 622
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 623
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 624
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 625
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 626
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 627
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 628
Analog-to-Digital Converter (ADC) ............................................................................................. 629
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 652
ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 653
ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 655
ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 657
ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 660
ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 662
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 667
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 668
ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 670
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 672
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 674
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 675
ADC Control (ADCCTL), offset 0x038 ............................................................................. 677
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 678
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 680
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 683
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 683
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 683
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 683
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 684
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 684
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 684
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 684
ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 686
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 688
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 690
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 690
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 691
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Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 691
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 693
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 693
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 694
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 694
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 696
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 697
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 698
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 699
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 700
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 705
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 705
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 705
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 705
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 705
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 705
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 705
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 705
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 707
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 707
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 707
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 707
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 707
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 707
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 707
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 707
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 709
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
UART Data (UARTDR), offset 0x000 ............................................................................... 724
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 726
UART Flag (UARTFR), offset 0x018 ................................................................................ 729
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 732
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 733
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 734
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 735
UART Control (UARTCTL), offset 0x030 ......................................................................... 737
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 741
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 743
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 747
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 751
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 755
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 757
UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 758
UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 759
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 760
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 761
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 762
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 763
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 764
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Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ......................................
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ......................................
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ......................................
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC .....................................
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................
765
766
767
768
769
770
771
772
Synchronous Serial Interface (SSI) ............................................................................................ 773
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 788
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 790
SSI Data (SSIDR), offset 0x008 ...................................................................................... 792
SSI Status (SSISR), offset 0x00C ................................................................................... 793
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 795
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 796
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 797
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 799
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 801
SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 802
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 803
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 804
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 805
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 806
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 807
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 808
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 809
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 810
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 811
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 812
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 813
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 814
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 815
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 832
I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 833
I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 838
I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 839
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 840
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 841
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 842
I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 843
I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 844
I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 845
I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 846
I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 848
I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 849
I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 850
I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 851
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Register 16:
I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 852
Inter-Integrated Circuit Sound (I2S) Interface ............................................................................ 853
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
I2S Transmit FIFO Data (I2STXFIFO), offset 0x000 .......................................................... 866
I2S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ...................................... 867
I2S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... 868
I2S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ 870
I2S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 871
I2S Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 872
I2S Receive FIFO Data (I2SRXFIFO), offset 0x800 .......................................................... 873
I2S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ...................................... 874
I2S Receive Module Configuration (I2SRXCFG), offset 0x808 ........................................... 875
I2S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ......................................................... 878
I2S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 ..................................... 879
I2S Receive FIFO Level (I2SRXLEV), offset 0x818 ........................................................... 880
I2S Module Configuration (I2SCFG), offset 0xC00 ............................................................ 881
I2S Interrupt Mask (I2SIM), offset 0xC10 ......................................................................... 883
I2S Raw Interrupt Status (I2SRIS), offset 0xC14 ............................................................... 885
I2S Masked Interrupt Status (I2SMIS), offset 0xC18 ......................................................... 887
I2S Interrupt Clear (I2SIC), offset 0xC1C ......................................................................... 889
Controller Area Network (CAN) Module ..................................................................................... 890
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
CAN Control (CANCTL), offset 0x000 ............................................................................. 912
CAN Status (CANSTS), offset 0x004 ............................................................................... 914
CAN Error Counter (CANERR), offset 0x008 ................................................................... 917
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 918
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 919
CAN Test (CANTST), offset 0x014 .................................................................................. 920
CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 922
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 923
CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 923
CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 924
CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 924
CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 927
CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 927
CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 928
CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 928
CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 930
CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 930
CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 931
CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 931
CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 933
CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 933
CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 936
CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 936
CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 936
CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 936
CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 936
CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 936
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Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 936
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 936
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 937
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 937
CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 938
CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 938
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 939
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 939
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 940
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 940
Ethernet Controller ...................................................................................................................... 941
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 955
Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 958
Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 960
Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 962
Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 964
Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 966
Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 967
Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 968
Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 970
Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 972
Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 973
Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 974
Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 975
Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 976
Ethernet MAC LED Encoding (MACLED), offset 0x040 .................................................... 977
Ethernet PHY MDIX (MDIX), offset 0x044 ....................................................................... 979
Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 980
Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 982
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 984
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 985
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 986
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 988
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 990
Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 991
Ethernet PHY Management Register 17 – Mode Control/Status (MR17), address 0x11 ...... 992
Ethernet PHY Management Register 27 – Special Control/Status (MR27), address
0x1B ............................................................................................................................. 994
Ethernet PHY Management Register 29 – Interrupt Status (MR29), address 0x1D ............. 995
Ethernet PHY Management Register 30 – Interrupt Mask (MR30), address 0x1E ............... 997
Ethernet PHY Management Register 31 – PHY Special Control/Status (MR31), address
0x1F ............................................................................................................................. 999
Universal Serial Bus (USB) Controller ..................................................................................... 1000
Register 1:
Register 2:
USB Device Functional Address (USBFADDR), offset 0x000 .......................................... 1028
USB Power (USBPOWER), offset 0x001 ....................................................................... 1029
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Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
USB Transmit Interrupt Status (USBTXIS), offset 0x002 ................................................. 1032
USB Receive Interrupt Status (USBRXIS), offset 0x004 ................................................. 1034
USB Transmit Interrupt Enable (USBTXIE), offset 0x006 ................................................ 1036
USB Receive Interrupt Enable (USBRXIE), offset 0x008 ................................................. 1038
USB General Interrupt Status (USBIS), offset 0x00A ...................................................... 1040
USB Interrupt Enable (USBIE), offset 0x00B .................................................................. 1043
USB Frame Value (USBFRAME), offset 0x00C .............................................................. 1046
USB Endpoint Index (USBEPIDX), offset 0x00E ............................................................ 1047
USB Test Mode (USBTEST), offset 0x00F ..................................................................... 1048
USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 ........................................................... 1050
USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 ........................................................... 1050
USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 ........................................................... 1050
USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C ........................................................... 1050
USB FIFO Endpoint 4 (USBFIFO4), offset 0x030 ........................................................... 1050
USB FIFO Endpoint 5 (USBFIFO5), offset 0x034 ........................................................... 1050
USB FIFO Endpoint 6 (USBFIFO6), offset 0x038 ........................................................... 1050
USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C ........................................................... 1050
USB FIFO Endpoint 8 (USBFIFO8), offset 0x040 ........................................................... 1050
USB FIFO Endpoint 9 (USBFIFO9), offset 0x044 ........................................................... 1050
USB FIFO Endpoint 10 (USBFIFO10), offset 0x048 ....................................................... 1050
USB FIFO Endpoint 11 (USBFIFO11), offset 0x04C ....................................................... 1050
USB FIFO Endpoint 12 (USBFIFO12), offset 0x050 ....................................................... 1050
USB FIFO Endpoint 13 (USBFIFO13), offset 0x054 ....................................................... 1050
USB FIFO Endpoint 14 (USBFIFO14), offset 0x058 ....................................................... 1050
USB FIFO Endpoint 15 (USBFIFO15), offset 0x05C ....................................................... 1050
USB Device Control (USBDEVCTL), offset 0x060 .......................................................... 1052
USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 ................................ 1054
USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 ................................ 1054
USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 ................................ 1055
USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 ................................ 1055
USB Connect Timing (USBCONTIM), offset 0x07A ........................................................ 1056
USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B ............................................ 1057
USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D .... 1058
USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E .... 1059
USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 ......... 1060
USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 ......... 1060
USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 ......... 1060
USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 ......... 1060
USB Transmit Functional Address Endpoint 4 (USBTXFUNCADDR4), offset 0x0A0 ......... 1060
USB Transmit Functional Address Endpoint 5 (USBTXFUNCADDR5), offset 0x0A8 ......... 1060
USB Transmit Functional Address Endpoint 6 (USBTXFUNCADDR6), offset 0x0B0 ......... 1060
USB Transmit Functional Address Endpoint 7 (USBTXFUNCADDR7), offset 0x0B8 ......... 1060
USB Transmit Functional Address Endpoint 8 (USBTXFUNCADDR8), offset 0x0C0 ........ 1060
USB Transmit Functional Address Endpoint 9 (USBTXFUNCADDR9), offset 0x0C8 ........ 1060
USB Transmit Functional Address Endpoint 10 (USBTXFUNCADDR10), offset 0x0D0 ..... 1060
USB Transmit Functional Address Endpoint 11 (USBTXFUNCADDR11), offset 0x0D8 ..... 1060
USB Transmit Functional Address Endpoint 12 (USBTXFUNCADDR12), offset 0x0E0 ..... 1060
USB Transmit Functional Address Endpoint 13 (USBTXFUNCADDR13), offset 0x0E8 ..... 1060
32
July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
Register 95:
Register 96:
Register 97:
Register 98:
USB Transmit Functional Address Endpoint 14 (USBTXFUNCADDR14), offset 0x0F0 ..... 1060
USB Transmit Functional Address Endpoint 15 (USBTXFUNCADDR15), offset 0x0F8 ..... 1060
USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 ..................... 1062
USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A .................... 1062
USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 ..................... 1062
USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A .................... 1062
USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4), offset 0x0A2 .................... 1062
USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5), offset 0x0AA .................... 1062
USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6), offset 0x0B2 .................... 1062
USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7), offset 0x0BA .................... 1062
USB Transmit Hub Address Endpoint 8 (USBTXHUBADDR8), offset 0x0C2 .................... 1062
USB Transmit Hub Address Endpoint 9 (USBTXHUBADDR9), offset 0x0CA .................... 1062
USB Transmit Hub Address Endpoint 10 (USBTXHUBADDR10), offset 0x0D2 ................ 1062
USB Transmit Hub Address Endpoint 11 (USBTXHUBADDR11), offset 0x0DA ................ 1062
USB Transmit Hub Address Endpoint 12 (USBTXHUBADDR12), offset 0x0E2 ................ 1062
USB Transmit Hub Address Endpoint 13 (USBTXHUBADDR13), offset 0x0EA ................ 1062
USB Transmit Hub Address Endpoint 14 (USBTXHUBADDR14), offset 0x0F2 ................. 1062
USB Transmit Hub Address Endpoint 15 (USBTXHUBADDR15), offset 0x0FA ................ 1062
USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 ........................... 1064
USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B ........................... 1064
USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 ........................... 1064
USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B ........................... 1064
USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset 0x0A3 ........................... 1064
USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset 0x0AB .......................... 1064
USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset 0x0B3 ........................... 1064
USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset 0x0BB .......................... 1064
USB Transmit Hub Port Endpoint 8 (USBTXHUBPORT8), offset 0x0C3 .......................... 1064
USB Transmit Hub Port Endpoint 9 (USBTXHUBPORT9), offset 0x0CB .......................... 1064
USB Transmit Hub Port Endpoint 10 (USBTXHUBPORT10), offset 0x0D3 ....................... 1064
USB Transmit Hub Port Endpoint 11 (USBTXHUBPORT11), offset 0x0DB ....................... 1064
USB Transmit Hub Port Endpoint 12 (USBTXHUBPORT12), offset 0x0E3 ....................... 1064
USB Transmit Hub Port Endpoint 13 (USBTXHUBPORT13), offset 0x0EB ...................... 1064
USB Transmit Hub Port Endpoint 14 (USBTXHUBPORT14), offset 0x0F3 ....................... 1064
USB Transmit Hub Port Endpoint 15 (USBTXHUBPORT15), offset 0x0FB ....................... 1064
USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C ......... 1066
USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 ......... 1066
USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C ......... 1066
USB Receive Functional Address Endpoint 4 (USBRXFUNCADDR4), offset 0x0A4 ......... 1066
USB Receive Functional Address Endpoint 5 (USBRXFUNCADDR5), offset 0x0AC ......... 1066
USB Receive Functional Address Endpoint 6 (USBRXFUNCADDR6), offset 0x0B4 ......... 1066
USB Receive Functional Address Endpoint 7 (USBRXFUNCADDR7), offset 0x0BC ......... 1066
USB Receive Functional Address Endpoint 8 (USBRXFUNCADDR8), offset 0x0C4 ......... 1066
USB Receive Functional Address Endpoint 9 (USBRXFUNCADDR9), offset 0x0CC ........ 1066
USB Receive Functional Address Endpoint 10 (USBRXFUNCADDR10), offset 0x0D4 ..... 1066
USB Receive Functional Address Endpoint 11 (USBRXFUNCADDR11), offset 0x0DC ..... 1066
USB Receive Functional Address Endpoint 12 (USBRXFUNCADDR12), offset 0x0E4 ..... 1066
USB Receive Functional Address Endpoint 13 (USBRXFUNCADDR13), offset 0x0EC ..... 1066
USB Receive Functional Address Endpoint 14 (USBRXFUNCADDR14), offset 0x0F4 ...... 1066
July 03, 2014
33
Texas Instruments-Production Data
Table of Contents
Register 99:
Register 100:
Register 101:
Register 102:
Register 103:
Register 104:
Register 105:
Register 106:
Register 107:
Register 108:
Register 109:
Register 110:
Register 111:
Register 112:
Register 113:
Register 114:
Register 115:
Register 116:
Register 117:
Register 118:
Register 119:
Register 120:
Register 121:
Register 122:
Register 123:
Register 124:
Register 125:
Register 126:
Register 127:
Register 128:
Register 129:
Register 130:
Register 131:
Register 132:
Register 133:
Register 134:
Register 135:
Register 136:
Register 137:
Register 138:
Register 139:
Register 140:
Register 141:
Register 142:
Register 143:
Register 144:
Register 145:
Register 146:
USB Receive Functional Address Endpoint 15 (USBRXFUNCADDR15), offset 0x0FC ..... 1066
USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E ..................... 1068
USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 ..................... 1068
USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E ..................... 1068
USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4), offset 0x0A6 ..................... 1068
USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5), offset 0x0AE .................... 1068
USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6), offset 0x0B6 ..................... 1068
USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7), offset 0x0BE .................... 1068
USB Receive Hub Address Endpoint 8 (USBRXHUBADDR8), offset 0x0C6 .................... 1068
USB Receive Hub Address Endpoint 9 (USBRXHUBADDR9), offset 0x0CE .................... 1068
USB Receive Hub Address Endpoint 10 (USBRXHUBADDR10), offset 0x0D6 ................. 1068
USB Receive Hub Address Endpoint 11 (USBRXHUBADDR11), offset 0x0DE ................. 1068
USB Receive Hub Address Endpoint 12 (USBRXHUBADDR12), offset 0x0E6 ................. 1068
USB Receive Hub Address Endpoint 13 (USBRXHUBADDR13), offset 0x0EE ................ 1068
USB Receive Hub Address Endpoint 14 (USBRXHUBADDR14), offset 0x0F6 ................. 1068
USB Receive Hub Address Endpoint 15 (USBRXHUBADDR15), offset 0x0FE ................. 1068
USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F ........................... 1070
USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 ........................... 1070
USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F ........................... 1070
USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset 0x0A7 ........................... 1070
USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset 0x0AF ........................... 1070
USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset 0x0B7 ........................... 1070
USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset 0x0BF ........................... 1070
USB Receive Hub Port Endpoint 8 (USBRXHUBPORT8), offset 0x0C7 ........................... 1070
USB Receive Hub Port Endpoint 9 (USBRXHUBPORT9), offset 0x0CF ........................... 1070
USB Receive Hub Port Endpoint 10 (USBRXHUBPORT10), offset 0x0D7 ....................... 1070
USB Receive Hub Port Endpoint 11 (USBRXHUBPORT11), offset 0x0DF ....................... 1070
USB Receive Hub Port Endpoint 12 (USBRXHUBPORT12), offset 0x0E7 ....................... 1070
USB Receive Hub Port Endpoint 13 (USBRXHUBPORT13), offset 0x0EF ....................... 1070
USB Receive Hub Port Endpoint 14 (USBRXHUBPORT14), offset 0x0F7 ....................... 1070
USB Receive Hub Port Endpoint 15 (USBRXHUBPORT15), offset 0x0FF ....................... 1070
USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 ......................... 1072
USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 ........................ 1072
USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 ........................ 1072
USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset 0x140 ........................ 1072
USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset 0x150 ........................ 1072
USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset 0x160 ........................ 1072
USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset 0x170 ........................ 1072
USB Maximum Transmit Data Endpoint 8 (USBTXMAXP8), offset 0x180 ........................ 1072
USB Maximum Transmit Data Endpoint 9 (USBTXMAXP9), offset 0x190 ........................ 1072
USB Maximum Transmit Data Endpoint 10 (USBTXMAXP10), offset 0x1A0 .................... 1072
USB Maximum Transmit Data Endpoint 11 (USBTXMAXP11), offset 0x1B0 ..................... 1072
USB Maximum Transmit Data Endpoint 12 (USBTXMAXP12), offset 0x1C0 .................... 1072
USB Maximum Transmit Data Endpoint 13 (USBTXMAXP13), offset 0x1D0 .................... 1072
USB Maximum Transmit Data Endpoint 14 (USBTXMAXP14), offset 0x1E0 .................... 1072
USB Maximum Transmit Data Endpoint 15 (USBTXMAXP15), offset 0x1F0 ..................... 1072
USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 ............................... 1074
USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 ............................. 1078
34
July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 147:
Register 148:
Register 149:
Register 150:
Register 151:
Register 152:
Register 153:
Register 154:
Register 155:
Register 156:
Register 157:
Register 158:
Register 159:
Register 160:
Register 161:
Register 162:
Register 163:
Register 164:
Register 165:
Register 166:
Register 167:
Register 168:
Register 169:
Register 170:
Register 171:
Register 172:
Register 173:
Register 174:
Register 175:
Register 176:
Register 177:
Register 178:
Register 179:
Register 180:
Register 181:
Register 182:
Register 183:
Register 184:
Register 185:
Register 186:
Register 187:
Register 188:
Register 189:
Register 190:
Register 191:
Register 192:
Register 193:
Register 194:
USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 ................................. 1080
USB Type Endpoint 0 (USBTYPE0), offset 0x10A .......................................................... 1081
USB NAK Limit (USBNAKLMT), offset 0x10B ................................................................ 1082
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 ............. 1083
USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 ............. 1083
USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 ............. 1083
USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142 ............. 1083
USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152 ............. 1083
USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162 ............. 1083
USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172 ............. 1083
USB Transmit Control and Status Endpoint 8 Low (USBTXCSRL8), offset 0x182 ............. 1083
USB Transmit Control and Status Endpoint 9 Low (USBTXCSRL9), offset 0x192 ............. 1083
USB Transmit Control and Status Endpoint 10 Low (USBTXCSRL10), offset 0x1A2 ......... 1083
USB Transmit Control and Status Endpoint 11 Low (USBTXCSRL11), offset 0x1B2 ......... 1083
USB Transmit Control and Status Endpoint 12 Low (USBTXCSRL12), offset 0x1C2 ........ 1083
USB Transmit Control and Status Endpoint 13 Low (USBTXCSRL13), offset 0x1D2 ........ 1083
USB Transmit Control and Status Endpoint 14 Low (USBTXCSRL14), offset 0x1E2 ......... 1083
USB Transmit Control and Status Endpoint 15 Low (USBTXCSRL15), offset 0x1F2 ......... 1083
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 ............ 1088
USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 ........... 1088
USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 ........... 1088
USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143 ........... 1088
USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153 ........... 1088
USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163 ........... 1088
USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173 ........... 1088
USB Transmit Control and Status Endpoint 8 High (USBTXCSRH8), offset 0x183 ........... 1088
USB Transmit Control and Status Endpoint 9 High (USBTXCSRH9), offset 0x193 ........... 1088
USB Transmit Control and Status Endpoint 10 High (USBTXCSRH10), offset 0x1A3 ....... 1088
USB Transmit Control and Status Endpoint 11 High (USBTXCSRH11), offset 0x1B3 ........ 1088
USB Transmit Control and Status Endpoint 12 High (USBTXCSRH12), offset 0x1C3 ....... 1088
USB Transmit Control and Status Endpoint 13 High (USBTXCSRH13), offset 0x1D3 ....... 1088
USB Transmit Control and Status Endpoint 14 High (USBTXCSRH14), offset 0x1E3 ....... 1088
USB Transmit Control and Status Endpoint 15 High (USBTXCSRH15), offset 0x1F3 ........ 1088
USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 ......................... 1092
USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 ......................... 1092
USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 ......................... 1092
USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144 ......................... 1092
USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154 ......................... 1092
USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164 ......................... 1092
USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174 ......................... 1092
USB Maximum Receive Data Endpoint 8 (USBRXMAXP8), offset 0x184 ......................... 1092
USB Maximum Receive Data Endpoint 9 (USBRXMAXP9), offset 0x194 ......................... 1092
USB Maximum Receive Data Endpoint 10 (USBRXMAXP10), offset 0x1A4 ..................... 1092
USB Maximum Receive Data Endpoint 11 (USBRXMAXP11), offset 0x1B4 ..................... 1092
USB Maximum Receive Data Endpoint 12 (USBRXMAXP12), offset 0x1C4 ..................... 1092
USB Maximum Receive Data Endpoint 13 (USBRXMAXP13), offset 0x1D4 ..................... 1092
USB Maximum Receive Data Endpoint 14 (USBRXMAXP14), offset 0x1E4 ..................... 1092
USB Maximum Receive Data Endpoint 15 (USBRXMAXP15), offset 0x1F4 ..................... 1092
July 03, 2014
35
Texas Instruments-Production Data
Table of Contents
Register 195:
Register 196:
Register 197:
Register 198:
Register 199:
Register 200:
Register 201:
Register 202:
Register 203:
Register 204:
Register 205:
Register 206:
Register 207:
Register 208:
Register 209:
Register 210:
Register 211:
Register 212:
Register 213:
Register 214:
Register 215:
Register 216:
Register 217:
Register 218:
Register 219:
Register 220:
Register 221:
Register 222:
Register 223:
Register 224:
Register 225:
Register 226:
Register 227:
Register 228:
Register 229:
Register 230:
Register 231:
Register 232:
Register 233:
Register 234:
Register 235:
Register 236:
Register 237:
Register 238:
Register 239:
Register 240:
Register 241:
Register 242:
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 ............. 1094
USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 ............. 1094
USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 ............. 1094
USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146 ............. 1094
USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156 ............. 1094
USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166 ............. 1094
USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 ............. 1094
USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8), offset 0x186 ............. 1094
USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9), offset 0x196 ............. 1094
USB Receive Control and Status Endpoint 10 Low (USBRXCSRL10), offset 0x1A6 ......... 1094
USB Receive Control and Status Endpoint 11 Low (USBRXCSRL11), offset 0x1B6 .......... 1094
USB Receive Control and Status Endpoint 12 Low (USBRXCSRL12), offset 0x1C6 ......... 1094
USB Receive Control and Status Endpoint 13 Low (USBRXCSRL13), offset 0x1D6 ......... 1094
USB Receive Control and Status Endpoint 14 Low (USBRXCSRL14), offset 0x1E6 ......... 1094
USB Receive Control and Status Endpoint 15 Low (USBRXCSRL15), offset 0x1F6 ......... 1094
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 ............ 1099
USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 ............ 1099
USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 ............ 1099
USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147 ............ 1099
USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157 ............ 1099
USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167 ............ 1099
USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177 ............ 1099
USB Receive Control and Status Endpoint 8 High (USBRXCSRH8), offset 0x187 ............ 1099
USB Receive Control and Status Endpoint 9 High (USBRXCSRH9), offset 0x197 ............ 1099
USB Receive Control and Status Endpoint 10 High (USBRXCSRH10), offset 0x1A7 ........ 1099
USB Receive Control and Status Endpoint 11 High (USBRXCSRH11), offset 0x1B7 ........ 1099
USB Receive Control and Status Endpoint 12 High (USBRXCSRH12), offset 0x1C7 ........ 1099
USB Receive Control and Status Endpoint 13 High (USBRXCSRH13), offset 0x1D7 ........ 1099
USB Receive Control and Status Endpoint 14 High (USBRXCSRH14), offset 0x1E7 ........ 1099
USB Receive Control and Status Endpoint 15 High (USBRXCSRH15), offset 0x1F7 ........ 1099
USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 ............................. 1104
USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 ............................ 1104
USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 ............................ 1104
USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148 ............................ 1104
USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158 ............................ 1104
USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168 ............................ 1104
USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178 ............................ 1104
USB Receive Byte Count Endpoint 8 (USBRXCOUNT8), offset 0x188 ............................ 1104
USB Receive Byte Count Endpoint 9 (USBRXCOUNT9), offset 0x198 ............................ 1104
USB Receive Byte Count Endpoint 10 (USBRXCOUNT10), offset 0x1A8 ........................ 1104
USB Receive Byte Count Endpoint 11 (USBRXCOUNT11), offset 0x1B8 ......................... 1104
USB Receive Byte Count Endpoint 12 (USBRXCOUNT12), offset 0x1C8 ........................ 1104
USB Receive Byte Count Endpoint 13 (USBRXCOUNT13), offset 0x1D8 ........................ 1104
USB Receive Byte Count Endpoint 14 (USBRXCOUNT14), offset 0x1E8 ........................ 1104
USB Receive Byte Count Endpoint 15 (USBRXCOUNT15), offset 0x1F8 ........................ 1104
USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ................. 1106
USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ................. 1106
USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ................. 1106
36
July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 243:
Register 244:
Register 245:
Register 246:
Register 247:
Register 248:
Register 249:
Register 250:
Register 251:
Register 252:
Register 253:
Register 254:
Register 255:
Register 256:
Register 257:
Register 258:
Register 259:
Register 260:
Register 261:
Register 262:
Register 263:
Register 264:
Register 265:
Register 266:
Register 267:
Register 268:
Register 269:
Register 270:
Register 271:
Register 272:
Register 273:
Register 274:
Register 275:
Register 276:
Register 277:
Register 278:
Register 279:
Register 280:
Register 281:
Register 282:
Register 283:
Register 284:
Register 285:
Register 286:
Register 287:
Register 288:
Register 289:
Register 290:
USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4), offset 0x14A ................. 1106
USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5), offset 0x15A ................. 1106
USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6), offset 0x16A ................. 1106
USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7), offset 0x17A ................. 1106
USB Host Transmit Configure Type Endpoint 8 (USBTXTYPE8), offset 0x18A ................. 1106
USB Host Transmit Configure Type Endpoint 9 (USBTXTYPE9), offset 0x19A ................. 1106
USB Host Transmit Configure Type Endpoint 10 (USBTXTYPE10), offset 0x1AA ............. 1106
USB Host Transmit Configure Type Endpoint 11 (USBTXTYPE11), offset 0x1BA ............. 1106
USB Host Transmit Configure Type Endpoint 12 (USBTXTYPE12), offset 0x1CA ............. 1106
USB Host Transmit Configure Type Endpoint 13 (USBTXTYPE13), offset 0x1DA ............. 1106
USB Host Transmit Configure Type Endpoint 14 (USBTXTYPE14), offset 0x1EA ............. 1106
USB Host Transmit Configure Type Endpoint 15 (USBTXTYPE15), offset 0x1FA ............. 1106
USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B ..................... 1108
USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B ..................... 1108
USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B ..................... 1108
USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4), offset 0x14B ..................... 1108
USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5), offset 0x15B ..................... 1108
USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6), offset 0x16B ..................... 1108
USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7), offset 0x17B ..................... 1108
USB Host Transmit Interval Endpoint 8 (USBTXINTERVAL8), offset 0x18B ..................... 1108
USB Host Transmit Interval Endpoint 9 (USBTXINTERVAL9), offset 0x19B ..................... 1108
USB Host Transmit Interval Endpoint 10 (USBTXINTERVAL10), offset 0x1AB ................. 1108
USB Host Transmit Interval Endpoint 11 (USBTXINTERVAL11), offset 0x1BB .................. 1108
USB Host Transmit Interval Endpoint 12 (USBTXINTERVAL12), offset 0x1CB ................. 1108
USB Host Transmit Interval Endpoint 13 (USBTXINTERVAL13), offset 0x1DB ................. 1108
USB Host Transmit Interval Endpoint 14 (USBTXINTERVAL14), offset 0x1EB ................. 1108
USB Host Transmit Interval Endpoint 15 (USBTXINTERVAL15), offset 0x1FB ................. 1108
USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................. 1110
USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................. 1110
USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ................. 1110
USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4), offset 0x14C ................. 1110
USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5), offset 0x15C ................. 1110
USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6), offset 0x16C ................. 1110
USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7), offset 0x17C ................. 1110
USB Host Configure Receive Type Endpoint 8 (USBRXTYPE8), offset 0x18C ................. 1110
USB Host Configure Receive Type Endpoint 9 (USBRXTYPE9), offset 0x19C ................. 1110
USB Host Configure Receive Type Endpoint 10 (USBRXTYPE10), offset 0x1AC ............. 1110
USB Host Configure Receive Type Endpoint 11 (USBRXTYPE11), offset 0x1BC ............. 1110
USB Host Configure Receive Type Endpoint 12 (USBRXTYPE12), offset 0x1CC ............. 1110
USB Host Configure Receive Type Endpoint 13 (USBRXTYPE13), offset 0x1DC ............. 1110
USB Host Configure Receive Type Endpoint 14 (USBRXTYPE14), offset 0x1EC ............. 1110
USB Host Configure Receive Type Endpoint 15 (USBRXTYPE15), offset 0x1FC ............. 1110
USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D ........... 1112
USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ........... 1112
USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ........... 1112
USB Host Receive Polling Interval Endpoint 4 (USBRXINTERVAL4), offset 0x14D ........... 1112
USB Host Receive Polling Interval Endpoint 5 (USBRXINTERVAL5), offset 0x15D ........... 1112
USB Host Receive Polling Interval Endpoint 6 (USBRXINTERVAL6), offset 0x16D ........... 1112
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Table of Contents
Register 291:
Register 292:
Register 293:
Register 294:
Register 295:
Register 296:
Register 297:
Register 298:
Register 299:
Register 300:
Register 301:
Register 302:
Register 303:
Register 304:
Register 305:
Register 306:
Register 307:
Register 308:
Register 309:
Register 310:
Register 311:
Register 312:
Register 313:
Register 314:
Register 315:
Register 316:
Register 317:
Register 318:
Register 319:
Register 320:
Register 321:
Register 322:
Register 323:
Register 324:
USB Host Receive Polling Interval Endpoint 7 (USBRXINTERVAL7), offset 0x17D ........... 1112
USB Host Receive Polling Interval Endpoint 8 (USBRXINTERVAL8), offset 0x18D ........... 1112
USB Host Receive Polling Interval Endpoint 9 (USBRXINTERVAL9), offset 0x19D ........... 1112
USB Host Receive Polling Interval Endpoint 10 (USBRXINTERVAL10), offset 0x1AD ...... 1112
USB Host Receive Polling Interval Endpoint 11 (USBRXINTERVAL11), offset 0x1BD ....... 1112
USB Host Receive Polling Interval Endpoint 12 (USBRXINTERVAL12), offset 0x1CD ...... 1112
USB Host Receive Polling Interval Endpoint 13 (USBRXINTERVAL13), offset 0x1DD ...... 1112
USB Host Receive Polling Interval Endpoint 14 (USBRXINTERVAL14), offset 0x1ED ...... 1112
USB Host Receive Polling Interval Endpoint 15 (USBRXINTERVAL15), offset 0x1FD ....... 1112
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset
0x304 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset
0x308 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset
0x30C ......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 4 (USBRQPKTCOUNT4), offset
0x310 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 5 (USBRQPKTCOUNT5), offset
0x314 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 6 (USBRQPKTCOUNT6), offset
0x318 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 7 (USBRQPKTCOUNT7), offset
0x31C ......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 8 (USBRQPKTCOUNT8), offset
0x320 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 9 (USBRQPKTCOUNT9), offset
0x324 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 10 (USBRQPKTCOUNT10), offset
0x328 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 11 (USBRQPKTCOUNT11), offset
0x32C ......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 12 (USBRQPKTCOUNT12), offset
0x330 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 13 (USBRQPKTCOUNT13), offset
0x334 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 14 (USBRQPKTCOUNT14), offset
0x338 .......................................................................................................................... 1114
USB Request Packet Count in Block Transfer Endpoint 15 (USBRQPKTCOUNT15), offset
0x33C ......................................................................................................................... 1114
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ........... 1116
USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 .......... 1118
USB External Power Control (USBEPC), offset 0x400 .................................................... 1120
USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ............... 1123
USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 .......................... 1124
USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ....... 1125
USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 .......................... 1126
USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ..................................... 1127
USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................. 1128
USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................. 1129
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Register 325:
Register 326:
Register 327:
Register 328:
Register 329:
Register 330:
Register 331:
Register 332:
USB VBUS Droop Control (USBVDC), offset 0x430 ....................................................... 1130
USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS), offset 0x434 .................. 1131
USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset 0x438 ............................. 1132
USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC), offset 0x43C .......... 1133
USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset 0x444 ............................. 1134
USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448 ........................................ 1135
USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C .................... 1136
USB DMA Select (USBDMASEL), offset 0x450 .............................................................. 1137
Analog Comparators ................................................................................................................. 1139
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1146
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1147
Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1148
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... 1149
Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... 1150
Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... 1150
Analog Comparator Status 2 (ACSTAT2), offset 0x060 ................................................... 1150
Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... 1151
Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1151
Analog Comparator Control 2 (ACCTL2), offset 0x064 ................................................... 1151
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Revision History
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S9U90
data sheet.
Table 1. Revision History
Date
July 2014
October 2012
January 2012
Revision
Description
15852.2743 ■
■
In System Control chapter, clarified behavior of Reset Cause (RESC) register external reset bit.
■
In Internal memory chapter, noted that the Boot Configuration (BOOTCFG) register requires a
POR before committed changes to the Flash-resident registers take effect.
■
In GPIO chapter, corrected values for GPIOPCTL in the table GPIO Pins With Non-Zero Reset
Values.
■
In UART chapter, clarified that the transmit interrupt is based on a transition through level.
■
In Ethernet chapter, corrected register type of Ethernet PHY Management Register 29 – Interrupt
Status (MR29) to RC.
■
In Ordering and Contact Information appendix, moved orderable part numbers table to addendum.
■
Additional minor data sheet clarifications and corrections.
13440.2549 ■
11425
In JTAG chapter, clarified JTAG-to-SWD Switching and SWD-to-JTAG Switching.
Marked LM3S9U90 device as not recommended for new designs (NRND). Device is in production
to support existing customers, but TI does not recommend using this part in a new design.
■
In the uDMA chapter, in the "μDMA Channel Assignments" and "Request Type Support" tables,
corrected to show uDMA support for burst requests from the general-purpose timer, not single
requests.
■
In the Watchdog Timers chapter, added information on servicing the watchdog timer to the
Initialization and Configuration section.
■
In the General-Purpose Timers chapter, added note to the GPTMTnV registers that in 16-bit mode,
only the lower 16-bits of the register can be written with a new value. Writes to the prescaler bits
have no effect.
■
Corrected reset for the UART Raw Interrupt Status (UARTRIS) register.
■
In the USB chapter, clarified that the USB PHY has internal termination resistors, and thus there is
no need for external resistors.
■
In the Electrical Characteristics chapter, added clarifying footnote to the GPIO Module Characteristics
table.
■
Additional minor data sheet clarifications and corrections.
■
In System Control chapter:
■
–
Clarified that an external LDO cannot be used.
–
Clarified system clock requirements when the ADC module is in operation.
–
Added important note to write the RCC register before the RCC2 register.
In Hibernation chapter:
–
Changed terminology from non-volatile memory to battery-backed memory.
–
Numerous clarifications, including adding a section "System Implementation".
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Table 1. Revision History (continued)
Date
Revision
Description
–
Clarified Hibernation module register reset conditions.
■
In Internal Memory chapter, clarified programming and use of the non-volatile registers.
■
In GPIO chapter, corrected "GPIO Pins With Non-Zero Reset Values" table and added note that if
the same signal is assigned to two different GPIO port pins, the signal is assigned to the port with
the lowest letter.
■
In EPI chapter:
–
Clarified table "Capabilities of Host Bus 8 and Host Bus 16 Modes".
–
Corrected bit and register resets for FREQ (Frequency Range) in EPI SDRAM Configuration
(EPISDRAMCFG) register.
–
Corrected bit and register resets for MAXWAIT (Maximum Wait) in EPI Host-Bus 8 Configuration
(EPIHB8CFG) and EPI Host-Bus 16 Configuration (EPIHB16CFG) registers. Also clarified
bit descriptions in these registers.
–
Corrected bit definitions for the EPSZ and ERSZ bits in the EPI Address Map (EPIADDRMAP)
register.
–
Corrected size of COUNT bit field in EPI Read FIFO Count (EPIRFIFOCNT) register.
■
In Timer chapter, clarified timer modes and interrupts.
■
In ADC chapter, added "ADC Input Equivalency Diagram".
■
In UART chapter, clarified interrupt behavior.
■
In SSI chapter, corrected SSIClk in the figure "Synchronous Serial Frame Format (Single Transfer)"
and clarified behavior of transmit bits in interrupt registers.
■
In I2C chapter, corrected bit and register reset values for IDLE bit in I2C Master Control/Status
(I2CMCS) register.
■
In USB chapter:
–
Clarified that when the USB module is in operation, MOSC must be provided with a clock source,
and the system clock must be at least 30 MHz.
–
Removed MULTTRAN bit from USB Transmit Hub Address Endpoint n (USBTXHUBADDRn)
and USB Receive Hub Address Endpoint n (USBRXHUBADDRn) registers.
–
Corrected description for the USB Device RESUME Interrupt Mask (USBDRIM) register.
■
In Analog Comparators chapter, clarified internal reference programming.
■
In Signal Tables chapter, clarified VDDC and LDO pin descriptions.
■
In Electrical Characteristics chapter:
–
In Maximum Ratings table, deleted parameter "Input voltage for a GPIO configured as an analog
input".
–
In Recommended DC Operating Conditions table, corrected values for IOH parameter.
–
In JTAG Characteristics, table, corrected values for parameters "TCK clock Low time" and "TCK
clock High time".
–
In LDO Regulator Characteristics table, added clarifying footnote to CLDO parameter.
–
In System Clock Characteristics with ADC Operation table, added clarifying footnote to Fsysadc
parameter.
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Revision History
Table 1. Revision History (continued)
Date
July 2011
March 2011
Revision
9970
9538
Description
–
Added "System Clock Characteristics with USB Operation" table.
–
In Sleep Modes AC Characteristics table, split parameter "Time to wake from interrupt" into
sleep mode and deep-sleep mode parameters.
–
In SSI Characteristics table, corrected value for parameter "SSIClk cycle time".
–
In Analog Comparator Characteristics table, added parameter "Input voltage range" and corrected
values for parameter "Input common mode voltage range".
–
In Analog Comparator Voltage Reference Characteristics table, corrected values for absolute
accuracy parameters.
–
Deleted table "USB Controller DC Characteristics".
–
In Nominal Power Consumption table, added parameter for sleep mode.
–
In Maximum Current Consumption section, changed reference value for MOSC and temperature
in tables that follow.
–
Deleted table "External VDDC Source Current Specifications".
■
Additional minor data sheet clarifications and corrections.
■
Corrected "Reset Sources" table.
■
Added Important Note that RCC register must be written before RCC2 register.
■
Added missing Start Calibration (CAL) bit to the Precision Internal Oscillator Calibration
(PIOSCCAL) register.
■
Added missing Precision Internal Oscillator Statistics (PIOSCSTAT) register.
■
In Hibernation Module chapter, deleted section "Special Considerations When Using a 4.194304-MHz
Crystal" as this content was added to the errata document.
■
Added a note that all GPIO signals are 5-V tolerant when configured as inputs except for PB0 and
PB1, which are limited to 3.6 V.
■
Corrected LIN Mode bit names in UART Interrupt Clear (UARTICR) register.
■
Corrected pin number for RST and added missing pin number for ERBIAS in table "Connections for
Unused Signals" (other pin tables were correct).
■
In the "Operating Characteristics" chapter:
–
In the "Thermal Characteristics" table, the Thermal resistance value was changed.
–
In the "ESD Absolute Maximum Ratings" table, the VESDCDM parameter was changed and the
VESDMM parameter was deleted.
■
The "Electrical Characteristics" chapter was reorganized by module. In addition, some of the
Recommended DC Operating Conditions, LDO Regulator, Clock, GPIO, EPI, Hibernation Module,
ADC, and SSI characteristics were finalized.
■
Additional minor data sheet clarifications and corrections.
Started tracking revision history.
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About This Document
This data sheet provides reference information for the LM3S9U90 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
®
The following related documents are available on the Stellaris web site at www.ti.com/stellaris:
■ Stellaris® Errata
■ ARM® Cortex™-M3 Errata
■ Cortex™-M3/M4 Instruction Set Technical User's Manual
■ Stellaris® Boot Loader User's Guide
■ Stellaris® Graphics Library User's Guide
■ Stellaris® Peripheral Driver Library User's Guide
■ Stellaris® ROM User’s Guide
■ Stellaris® USB Library User's Guide
The following related documents are also referenced:
■ ARM® Debug Interface V5 Architecture Specification
■ ARM® Embedded Trace Macrocell Architecture Specification
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
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About This Document
Documentation Conventions
This document uses the conventions shown in Table 2 on page 44.
Table 2. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
Two or more consecutive and related bits.
offset 0xnnn
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 87.
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field
Types
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
RC
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO
Software can read this field. Always write the chip reset value.
R/W
Software can read or write this field.
R/WC
Software can read or write this field. Writing to it with any value clears the register.
R/W1C
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1S
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO
Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field
Reset Value
This value in the register bit diagram shows the bit/field value after any reset, unless noted.
0
Bit cleared to 0 on chip reset.
1
Bit set to 1 on chip reset.
-
Nondeterministic.
Pin/Signal Notation
[]
Pin alternate function; a pin defaults to the signal without the brackets.
pin
Refers to the physical connection on the package.
signal
Refers to the electrical signal encoding of a pin.
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Table 2. Documentation Conventions (continued)
Notation
Meaning
assert a signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal
Change the value of the signal from the logically True state to the logically False state.
SIGNAL
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
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Architectural Overview
1
Architectural Overview
®
Texas Instruments is the industry leader in bringing 32-bit capabilities and the full benefits of ARM
Cortex™-M-based microcontrollers to the broadest reach of the microcontroller market. For current
®
users of 8- and 16-bit MCUs, Stellaris with Cortex-M offers a direct path to the strongest ecosystem
of development tools, software and knowledge in the industry. Designers who migrate to Stellaris
benefit from great tools, small code footprint and outstanding performance. Even more important,
designers can enter the ARM ecosystem with full confidence in a compatible roadmap from $1 to
1 GHz. For users of current 32-bit MCUs, the Stellaris family offers the industry’s first implementation
of Cortex-M3 and the Thumb-2 instruction set. With blazingly-fast responsiveness, Thumb-2
technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density
and performance. Thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system
cost while delivering 25 percent better performance. The Texas Instruments Stellaris family of
microcontrollers—the first ARM Cortex-M3 based controllers— brings high-performance 32-bit
computing to cost-sensitive embedded microcontroller applications.
1.1
Overview
The Stellaris LM3S9U90 microcontroller combines complex integration and high performance with
the following feature highlights:
■ ARM Cortex-M3 Processor Core
■ High Performance: 80-MHz operation; 100 DMIPS performance
■ 384 KB single-cycle Flash memory
■ 96 KB single-cycle SRAM
®
■ Internal ROM loaded with StellarisWare software
■ External Peripheral Interface (EPI)
■ Advanced Communication Interfaces: UART, SSI, I2C, I2S, CAN, Ethernet MAC and PHY, USB
■ System Integration: general-purpose timers, watchdog timers, DMA, general-purpose I/Os
■ Analog support: analog and digital comparators, Analog-to-Digital Converters (ADC), on-chip
voltage regulator
■ JTAG and ARM Serial Wire Debug (SWD)
■ 100-pin LQFP package
■ 108-ball BGA package
■ Industrial (-40°C to 85°C) temperature range
Figure 1-1 on page 47 depicts the features on the Stellaris LM3S9U90 microcontroller. Note that
there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus
(APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better
back-to-back access performance than the APB bus.
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Figure 1-1. Stellaris LM3S9U90 Microcontroller High-Level Block Diagram
JTAG/SWD
ARM®
Cortex™-M3
ROM
(80MHz)
System
Control and
Clocks
(w/ Precis. Osc.)
DCode bus
NVIC
Boot Loader
DriverLib
AES & CRC
Ethernet Boot Loader
Flash
(384KB)
MPU
ICode bus
System Bus
LM3S9U90
Bus Matrix
SRAM
(96KB)
SYSTEM PERIPHERALS
GeneralPurpose
Timer (4)
Hibernation
Module
External
Peripheral
Interface
GPIOs
(60)
USB OTG
(FS PHY)
SSI
(2)
CAN
Controller
(2)
Advanced Peripheral Bus (APB)
Watchdog
Timer
(2)
Advanced High-Performance Bus (AHB)
DMA
SERIAL PERIPHERALS
UART
(3)
I2C
(2)
Ethernet
MAC/PHY
I2S
ANALOG PERIPHERALS
Analog
Comparator
(3)
12- Bit ADC
Channels
(16)
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Architectural Overview
For applications requiring extreme conservation of power, the LM3S9U90 microcontroller features
a battery-backed Hibernation module to efficiently power down the LM3S9U90 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
battery-backed memory, the Hibernation module positions the LM3S9U90 microcontroller perfectly
for battery applications.
In addition, the LM3S9U90 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S9U90 microcontroller is code-compatible
to all members of the extensive Stellaris family; providing flexibility to fit precise needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network.
1.2
Target Applications
The Stellaris family is positioned for cost-conscious applications requiring significant control
processing and connectivity capabilities such as:
■
■
■
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1.3
Gaming equipment
Network appliances and switches
Home and commercial site monitoring and control
Electronic point-of-sale (POS) machines
Motion control
Medical instrumentation
Remote connectivity and monitoring
Test and measurement equipment
Factory automation
Fire and security
Lighting control
Transportation
Features
The LM3S9U90 microcontroller component features and general function are discussed in more
detail in the following section.
1.3.1
ARM Cortex-M3 Processor Core
All members of the Stellaris product family, including the LM3S9U90 microcontroller, are designed
around an ARM Cortex-M3 processor core. The ARM Cortex-M3 processor provides the core for a
high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
1.3.1.1
Processor Core (see page 68)
■ 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
■ 80-MHz operation; 100 DMIPS performance
■ Outstanding processing performance combined with fast interrupt handling
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■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast digital-signal-processing orientated multiply accumulate
■ Saturating arithmetic for signal processing
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7 processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage
■ Ultra-low power consumption with integrated sleep modes
1.3.1.2
System Timer (SysTick) (see page 111)
ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter
■ A simple counter used to measure time to completion and time used
■ An internal clock-source control based on missing/meeting durations.
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1.3.1.3
Nested Vectored Interrupt Controller (NVIC) (see page 112)
The LM3S9U90 controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC
and Cortex-M3 prioritize and handle all exceptions in Handler Mode. The processor state is
automatically stored to the stack on an exception and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state
saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 47 interrupts.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
1.3.1.4
System Control Block (SCB) (see page 114)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
1.3.1.5
Memory Protection Unit (MPU) (see page 114)
The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The
MPU provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
1.3.2
On-Chip Memory
The LM3S9U90 microcontroller is integrated with the following set of on-chip memory and features:
■ 96 KB single-cycle SRAM
■ 384 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance above
50 MHz
■ Internal ROM loaded with StellarisWare software:
– Stellaris Peripheral Driver Library
– Stellaris Boot Loader
– Advanced Encryption Standard (AES) cryptography tables
– Cyclic Redundancy Check (CRC) error detection functionality
1.3.2.1
SRAM (see page 321)
The LM3S9U90 microcontroller provides 96 KB of single-cycle on-chip SRAM. The internal SRAM
of the Stellaris devices is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller
(µDMA).
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1.3.2.2
Flash Memory (see page 323)
The LM3S9U90 microcontroller provides 384 KB of single-cycle on-chip Flash memory (above 50
MHz, the Flash memory can be accessed in a single cycle as long as the code is linear; branches
incur a one-cycle stall). The Flash memory is organized as a set of 1-KB blocks that can be
individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s.
These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can
be marked as read-only or execute-only, providing different levels of code protection. Read-only
blocks cannot be erased or programmed, protecting the contents of those blocks from being modified.
Execute-only blocks cannot be erased or programmed, and can only be read by the controller
instruction fetch mechanism, protecting the contents of those blocks from being read by either the
controller or by a debugger.
1.3.2.3
ROM (see page 321)
The LM3S9U90 ROM is preprogrammed with the following software and programs:
■ Stellaris Peripheral Driver Library
■ Stellaris Boot Loader
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error-detection functionality
The Stellaris Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M3 core.
No special pragmas or custom assembly code prologue/epilogue functions are required. For
applications that require in-field programmability, the royalty-free Stellaris Boot Loader can act as
an application loader and support in-field firmware updates.
The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government. AES is a strong encryption method with reasonable performance and size. In
addition, it is fast in both hardware and software, is fairly easy to implement, and requires little
memory. The Texas Instruments encryption package is available with full source code, and is based
on lesser general public license (LGPL) source. An LGPL means that the code can be used within
an application without any copyleft implications for the application (the code does not automatically
become open source). Modifications to the package source, however, must be open source.
CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents
as when previously checked. This technique can be used to validate correct receipt of messages
(nothing lost or modified in transit), to validate data after decompression, to validate that Flash
memory contents have not been changed, and for other cases where the data needs to be validated.
A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more
readily.
1.3.3
External Peripheral Interface (see page 482)
The External Peripheral Interface (EPI) provides access to external devices using a parallel path.
Unlike communications peripherals such as SSI, UART, and I2C, the EPI is designed to act like a
bus to external peripherals and memory.
The EPI has the following features:
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■ 8/16/32-bit dedicated parallel bus for external peripherals and memory
■ Memory interface supports contiguous memory access independent of data bus width, thus
enabling code execution directly from SDRAM, SRAM and Flash memory
■ Blocking and non-blocking reads
■ Separates processor from timing details through use of an internal write FIFO
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for read and write
– Read channel request asserted by programmable levels on the internal non-blocking read
FIFO (NBRFIFO)
– Write channel request asserted by empty on the internal write FIFO (WFIFO)
The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory
(SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also
provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same
way as a communication mechanism and is speed-controlled using clocking.
■ Synchronous Dynamic Random Access Memory (SDRAM) mode
– Supports x16 (single data rate) SDRAM at up to 50 MHz
– Supports low-cost SDRAMs up to 64 MB (512 megabits)
– Includes automatic refresh and access to all banks/rows
– Includes a Sleep/Standby mode to keep contents active with minimal power draw
– Multiplexed address/data interface for reduced pin count
■ Host-Bus mode
– Traditional x8 and x16 MCU bus interface capabilities
– Similar device compatibility options as PIC, ATmega, 8051, and others
– Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in
unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with
no byte selects)
– Support of both muxed and de-muxed address and data
– Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
with support for external FIFO (XFIFO) EMPTY and FULL signals
– Speed controlled, with read and write data wait-state counters
– Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn
– Manual chip-enable (or use extra address pins)
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■ General-Purpose mode
– Wide parallel interfaces for fast communications with CPLDs and FPGAs
– Data widths up to 32 bits
– Data rates up to 150 MB/second
– Optional "address" sizes from 4 bits to 20 bits
– Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable
input
■ General parallel GPIO
– 1 to 32 bits, FIFOed with speed control
– Useful for custom peripherals or for digital data acquisition and actuator controls
1.3.4
Serial Communications Peripherals
The LM3S9U90 controller supports both asynchronous and synchronous serial communications
with:
■ 10/100 Ethernet MAC and PHY
■ Two CAN 2.0 A/B controllers
■ USB 2.0 OTG/Host/Device
■ Three UARTs with IrDA and ISO 7816 support (one UART with modem flow control and status)
■ Two I2C modules
■ Two Synchronous Serial Interface modules (SSI)
■ Integrated Interchip Sound (I2S) module
The following sections provide more detail on each of these communications functions.
1.3.4.1
Ethernet Controller (see page 941)
Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet
has been standardized as IEEE 802.3. This specification defines a number of wiring and signaling
standards for the physical layer, two means of network access at the Media Access Control
(MAC)/Data Link Layer, and a common addressing format.
The Stellaris Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface and has the following features:
■ Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer
interface to the line
– 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
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– Full-featured auto-negotiation
■ Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
■ Highly configurable
– Programmable MAC address
– LED activity selection
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
■ Physical media manipulation
– MDI/MDI-X cross-over support through software assist
– Register-programmable transmit amplitude
– Automatic polarity correction and 10BASE-T signal reception
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive channel request asserted on packet receipt
– Transmit channel request asserted on empty transmit FIFO
1.3.4.2
Controller Area Network (see page 890)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally
created for automotive purposes, it is now used in many embedded control applications (for example,
industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters.
Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information.
The LM3S9U90 microcontroller includes two CAN units with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
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■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable Loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
1.3.4.3
USB (see page 1000)
Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected
and disconnected using a standardized interface without rebooting the system.
The LM3S9U90 microcontroller supports three configurations in USB 2.0 full and low speed: USB
Device, USB Host, and USB On-The-Go (negotiated on-the-go as host or device when connected
to other USB-enabled systems).
The USB module has the following features:
■ Complies with USB-IF certification standards
■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation with integrated PHY
■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous
■ 32 endpoints
– 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
■ VBUS droop and valid ID detection and interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive for up to three IN endpoints and three OUT
endpoints
– Channel requests asserted when FIFO contains required amount of data
1.3.4.4
UART (see page 709)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S9U90 microcontroller includes three fully programmable 16C550-type UARTs. Although
the functionality is similar to a 16C550 UART, this UART design is not register compatible. The
UART can generate individually masked interrupts from the Rx, Tx, modem flow control, modem
status, and error conditions. The module generates a single combined interrupt when any of the
interrupts are asserted and are unmasked.
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The three UARTs have the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Full modem handshake support (on UART1)
■ LIN protocol support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
1.3.4.5
I2C (see page 815)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices
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such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I2C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I2C bus can be designated as either a master or a slave. Each I2C module
supports both sending and receiving data as either a master or a slave and can operate
simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts.
The LM3S9U90 microcontroller includes two I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
1.3.4.6
SSI (see page 773)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts
data between parallel and serial. The SSI module performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The SSI module can be configured as either a master or slave device. As a slave device,
the SSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
The LM3S9U90 microcontroller includes two SSI modules with the following features:
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
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■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when FIFO contains 4 entries
1.3.4.7
Inter-Integrated Circuit Sound (I2S) Interface (see page 853)
The I2S interface is a configurable serial audio core that contains a transmit module and a receive
module. The module is configurable for the I2S as well as Left-Justified and Right-Justified serial
audio formats. Data can be in one of four modes: Stereo, Mono, Compact 16-bit Stereo and Compact
8-Bit Stereo.
The transmit and receive modules each have an 8-entry audio-sample FIFO. An audio sample can
consist of a Left and Right Stereo sample, a Mono sample, or a Left and Right Compact Stereo
sample. In Compact 16-Bit Stereo, each FIFO entry contains both the 16-bit left and 16-bit right
samples, allowing efficient data transfers and requiring less memory space. In Compact 8-bit Stereo,
each FIFO entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements
further.
Both the transmitter and receiver are capable of being a master or a slave.
The Stellaris I2S interface has the following features:
■ Configurable audio format supporting I2S, Left-justification, and Right-justification
■ Configurable sample size from 8 to 32 bits
■ Mono and Stereo support
■ 8-, 16-, and 32-bit FIFO interface for packing memory
■ Independent transmit and receive 8-entry FIFOs
■ Configurable FIFO-level interrupt and µDMA requests
■ Independent transmit and receive MCLK direction control
■ Transmit and receive internal MCLK sources
■ Independent transmit and receive control for serial clock and word select
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■ MCLK and SCLK can be independently set to master or slave
■ Configurable transmit zero or last sample when FIFO empty
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Burst requests
– Channel requests asserted when FIFO contains required amount of data
1.3.5
System Integration
The LM3S9U90 microcontroller provides a variety of standard system functions integrated into the
device, including:
■ Direct Memory Access Controller (DMA)
■ System control and clocks including on-chip precision 16-MHz oscillator
■ Four 32-bit timers (up to eight 16-bit)
■ Eight Capture Compare PWM (CCP) pins
■ Lower-power battery-backed Hibernation module
■ Real-Time Clock in Hibernation module
■ Two Watchdog Timers
– One timer runs off the main oscillator
– One timer runs off the precision internal oscillator
■ Up to 60 GPIOs, depending on configuration
– Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
– Independently configurable to 2, 4 or 8 mA drive capability
– Up to 4 GPIOs can have 18 mA drive capability
The following sections provide more detail on each of these functions.
1.3.5.1
Direct Memory Access (see page 366)
The LM3S9U90 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M3 processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
®
■ ARM PrimeCell 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
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– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single
request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– Primary and secondary channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable priority scheme
– Optional software-initiated requests for any channel
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Transfer size is programmable in binary steps from 1 to 1024
■ Source and destination address increment size of byte, half-word, word, or no increment
■ Maskable peripheral requests
■ Interrupt on transfer completion, with a separate interrupt per channel
1.3.5.2
System Control and Clocks (see page 189)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
■ Device identification information: version, part number, SRAM size, Flash memory size, and so
on
■ Power control
– On-chip fixed Low Drop-Out (LDO) voltage regulator
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
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– Low-power options for microcontroller: Sleep and Deep-sleep modes with clock gating
– Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Multiple clock sources for microcontroller system clock
– Precision Oscillator (PIOSC): On-chip resource providing a 16 MHz ±1% frequency at room
temperature
• 16 MHz ±3% across temperature
• Can be recalibrated with 7-bit trim resolution
• Software power down control for low power modes
– Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external
single-ended clock source is connected to the OSC0 input pin, or an external crystal is
connected across the OSC0 input and OSC1 output pins.
• External crystal used with or without on-chip PLL: select supported frequencies from 1
MHz to 16.384 MHz.
• External oscillator: from DC to maximum device speed
– Internal 30-kHz Oscillator: on chip resource providing a 30 kHz ± 50% frequency, used during
power-saving modes
– 32.768-kHz external oscillator for the Hibernation Module: eliminates need for additional
crystal for main clock source
■ Flexible reset sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out reset (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– MOSC failure
1.3.5.3
Programmable Timers (see page 557)
Programmable timers can be used to count or time external events that drive the Timer input pins.
Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently
as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time
Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions.
The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional
options:
■ Operating modes:
– 16- or 32-bit programmable one-shot timer
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– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
– 16-bit input-edge count- or time-capture modes
– 16-bit PWM mode with software-programmable output inversion of the PWM signal
■ Count up or down
■ Eight Capture Compare PWM pins (CCP)
■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
■ ADC event trigger
■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding
RTC mode)
■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine.
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each timer
– Burst request generated on timer interrupt
1.3.5.4
CCP Pins (see page 564)
Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM
output on the CCP pin.
The LM3S9U90 microcontroller includes eight Capture Compare PWM pins (CCP) that can be
programmed to operate in the following modes:
■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
1.3.5.5
Hibernation Module (see page 293)
The Hibernation module provides logic to switch power off to the main processor and peripherals
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic and has the following features:
■ 32-bit real-time counter (RTC)
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– Two 32-bit RTC match registers for timed wake-up and interrupt generation
– RTC predivider trim for making fine adjustments to the clock rate
■ Two mechanisms for power control
– System power control using discrete external regulator
– On-chip power control using internal switches under register control
■ Dedicated pin for waking using an external signal
■ RTC operational and hibernation memory valid as long as VBAT is valid
■ Low-battery detection, signaling, and interrupt generation
■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal; 32.768-kHz
external oscillator can be used for main controller clock
■ 64 32-bit words of battery-backed memory to save state during hibernation
■ Programmable interrupts for RTC match, external wake, and low battery events
1.3.5.6
Watchdog Timers (see page 604)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer can
generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog Timer
is ARM FiRM-compliant and can be configured to generate an interrupt to the microcontroller on its
first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has
been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
The LM3S9U90 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the
system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
1.3.5.7
Programmable GPIOs (see page 427)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris
GPIO module is comprised of nine physical GPIO blocks, each corresponding to an individual GPIO
port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time
Microcontrollers specification) and supports 0-60 programmable input/output pins. The number of
GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1155 for the
signals available to each GPIO pin).
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Architectural Overview
■ Up to 60 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant in input configuration
■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back
access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility
with existing code
■ Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for
ports on APB
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA
for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
1.3.6
Analog
The LM3S9U90 microcontroller provides analog functions integrated into the device, including:
■ Two 12-bit Analog-to-Digital Converters (ADC) with 16 analog input channels and a sample rate
of one million samples/second
■ Three analog comparators
■ 16 digital comparators
■ On-chip voltage regulator
The following provides more detail on these analog functions.
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1.3.6.1
ADC (see page 629)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number. The Stellaris ADC module features 12-bit conversion resolution and supports
16 input channels plus an internal temperature sensor. Four buffered sample sequencers allow
rapid sampling of up to 16 analog input sources without controller intervention. Each sample
sequencer provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequencer priority. Each ADC module has a digital comparator function that allows
the conversion value to be diverted to a comparison unit that provides eight digital comparators.
The LM3S9U90 microcontroller provides two ADC modules with the following features:
■ 16 shared analog input channels
■ 12-bit precision ADC with an accurate 10-bit data compatibility mode
■ Single-ended and differential-input configurations
■ On-chip internal temperature sensor
■ Maximum sample rate of one million samples/second
■ Optional phase shift in sample time programmable from 22.5º to 337.5º
■ Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– GPIO
■ Hardware averaging of up to 64 samples
■ Digital comparison unit providing eight digital comparators
■ Converter uses an internal 3-V reference or an external reference
■ Power and ground for the analog circuitry is separate from the digital power and ground
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each sample sequencer
– ADC module uses burst requests for DMA
1.3.6.2
Analog Comparators (see page 1139)
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result. The LM3S9U90 microcontroller provides three independent
integrated analog comparators that can be configured to drive an output or generate an interrupt or
ADC event.
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Architectural Overview
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The LM3S9U90 microcontroller provides three independent integrated analog comparators with the
following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
1.3.7
JTAG and ARM Serial Wire Debug (see page 177)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port
(SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one
module providing all the normal JTAG debug and test functionality plus real-time access to system
memory without halting the core or requiring any target resident code. The SWJ-DP interface has
the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
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1.3.8
Packaging and Temperature
■ Industrial-range (-40°C to 85°C) 100-pin RoHS-compliant LQFP package
■ Industrial-range (-40°C to 85°C) 108-ball RoHS-compliant BGA package
1.4
Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 1153
■ “Signal Tables” on page 1155
■ “Operating Characteristics” on page 1221
■ “Electrical Characteristics” on page 1222
■ “Package Information” on page 1304
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The Cortex-M3 Processor
2
The Cortex-M3 Processor
The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
®
■ 32-bit ARM Cortex™-M3 architecture optimized for small-footprint embedded applications
■ 80-MHz operation; 100 DMIPS performance
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast digital-signal-processing orientated multiply accumulate
■ Saturating arithmetic for signal processing
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7 processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage
■ Ultra-low power consumption with integrated sleep modes
®
The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motor control.
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This chapter provides information on the Stellaris implementation of the Cortex-M3 processor,
including the programming model, the memory model, the exception model, fault handling, and
power management.
For technical details on the instruction set, see the Cortex™-M3/M4 Instruction Set Technical User's
Manual.
2.1
Block Diagram
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including a range of single-cycle and SIMD multiplication
and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and
system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction
set based on Thumb-2 technology, ensuring high code density and reduced program memory
requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a
modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI)
and provides eight interrupt priority levels. The tight integration of the processor core and NVIC
provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency.
The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.
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Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
Interrupts
Sleep
ARM
Cortex-M3
CM3 Core
Debug
Instructions
Data
Trace
Port
Interface
Unit
Memory
Protection
Unit
Flash
Patch and
Breakpoint
Instrumentation
Data
Watchpoint Trace Macrocell
and Trace
ROM
Table
Private Peripheral
Bus
(internal)
Adv. Peripheral
Bus
Bus
Matrix
Serial Wire JTAG
Debug Port
Debug
Access Port
2.2
Overview
2.2.1
System-Level Interface
Serial
Wire
Output
Trace
Port
(SWO)
I-code bus
D-code bus
System bus
The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.
2.2.2
Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris
implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and
JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification
for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.
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The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions of up to eight
words in the program code in the CODE memory region. This enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5
Architecture Specification.
2.2.3
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 71.
Figure 2-2. TPIU Block Diagram
2.2.4
Debug
ATB
Slave
Port
ATB
Interface
APB
Slave
Port
APB
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
Cortex-M3 System Component Details
The Cortex-M3 includes the following system components:
■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 111).
■ Nested Vectored Interrupt Controller (NVIC)
An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 112).
■ System Control Block (SCB)
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The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions
(see “System Control Block (SCB)” on page 114).
■ Memory Protection Unit (MPU)
Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
“Memory Protection Unit (MPU)” on page 114).
2.3
Programming Model
This section describes the Cortex-M3 programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.
2.3.1
Processor Mode and Privilege Levels for Software Execution
The Cortex-M3 has two modes of operation:
■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.
In addition, the Cortex-M3 has two privilege levels:
■ Unprivileged
In this mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or system control block
– Possibly restricted access to memory or peripherals
■ Privileged
In this mode, software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register (see page 86) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.
2.3.2
Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the memory. When the processor pushes a new item onto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks:
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the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 76).
In Thread mode, the CONTROL register (see page 86) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 73.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode
Use
Privilege Level
Thread
Applications
Privileged or unprivileged
Stack Used
Handler
Exception handlers
Always privileged
a
Main stack or process stack
a
Main stack
a. See CONTROL (page 86).
2.3.3
Register Map
Figure 2-3 on page 73 shows the Cortex-M3 register set. Table 2-2 on page 74 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
Figure 2-3. Cortex-M3 Register Set
R0
R1
R2
Low registers
R3
R4
R5
R6
General-purpose registers
R7
R8
R9
High registers
R10
R11
R12
Stack Pointer
SP (R13)
Link Register
LR (R14)
Program Counter
PC (R15)
PSR
PSP‡
MSP‡
‡
Banked version of SP
Program status register
PRIMASK
FAULTMASK
Exception mask registers
Special registers
BASEPRI
CONTROL
CONTROL register
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Table 2-2. Processor Register Map
Offset
Type
Reset
-
R0
R/W
-
Cortex General-Purpose Register 0
75
-
R1
R/W
-
Cortex General-Purpose Register 1
75
-
R2
R/W
-
Cortex General-Purpose Register 2
75
-
R3
R/W
-
Cortex General-Purpose Register 3
75
-
R4
R/W
-
Cortex General-Purpose Register 4
75
-
R5
R/W
-
Cortex General-Purpose Register 5
75
-
R6
R/W
-
Cortex General-Purpose Register 6
75
-
R7
R/W
-
Cortex General-Purpose Register 7
75
-
R8
R/W
-
Cortex General-Purpose Register 8
75
-
R9
R/W
-
Cortex General-Purpose Register 9
75
-
R10
R/W
-
Cortex General-Purpose Register 10
75
-
R11
R/W
-
Cortex General-Purpose Register 11
75
-
R12
R/W
-
Cortex General-Purpose Register 12
75
-
SP
R/W
-
Stack Pointer
76
-
LR
R/W
0xFFFF.FFFF
Link Register
77
-
PC
R/W
-
Program Counter
78
-
PSR
R/W
0x0100.0000
Program Status Register
79
-
PRIMASK
R/W
0x0000.0000
Priority Mask Register
83
-
FAULTMASK
R/W
0x0000.0000
Fault Mask Register
84
-
BASEPRI
R/W
0x0000.0000
Base Priority Mask Register
85
-
CONTROL
R/W
0x0000.0000
Control Register
86
2.3.4
Description
See
page
Name
Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 73.
The core registers are not memory mapped and are accessed by register name rather than offset.
Note:
The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
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Register 1: Cortex General-Purpose Register 0 (R0)
Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
Cortex General-Purpose Register 0 (R0)
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
31:0
DATA
R/W
-
Description
Register data.
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Register 14: Stack Pointer (SP)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.
Stack Pointer (SP)
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
SP
Type
Reset
SP
Type
Reset
Bit/Field
Name
Type
Reset
31:0
SP
R/W
-
Description
This field is the address of the stack pointer.
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Register 15: Link Register (LR)
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. LR can be accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 104 for the values and
description.
Link Register (LR)
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
LINK
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
LINK
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
LINK
R/W
R/W
1
Reset
R/W
1
Description
0xFFFF.FFFF This field is the return address.
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Register 16: Program Counter (PC)
The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.
Program Counter (PC)
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
PC
Type
Reset
PC
Type
Reset
Bit/Field
Name
Type
Reset
31:0
PC
R/W
-
Description
This field is the current program address.
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Register 17: Program Status Register (PSR)
Note:
This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
■ Application Program Status Register (APSR), bits 31:27,
■ Execution Program Status Register (EPSR), bits 26:24, 15:10
■ Interrupt Program Status Register (IPSR), bits 6:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 102).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 79 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information about how to access the program status registers.
Table 2-3. PSR Register Combinations
Register
Type
PSR
R/W
Combination
APSR, EPSR, and IPSR
IEPSR
RO
EPSR and IPSR
a, b
a
APSR and IPSR
b
APSR and EPSR
IAPSR
R/W
EAPSR
R/W
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type R/W, reset 0x0100.0000
Type
Reset
31
30
29
28
27
N
Z
C
V
Q
26
25
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
15
14
13
12
11
10
9
ICI / IT
ICI / IT
Type
Reset
RO
0
RO
0
RO
0
24
23
22
21
20
THUMB
RO
1
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
reserved
ISRNUM
RO
0
RO
0
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0
RO
0
RO
0
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Bit/Field
Name
Type
Reset
31
N
R/W
0
Description
APSR Negative or Less Flag
Value Description
1
The previous operation result was negative or less than.
0
The previous operation result was positive, zero, greater than,
or equal.
The value of this bit is only meaningful when accessing PSR or APSR.
30
Z
R/W
0
APSR Zero Flag
Value Description
1
The previous operation result was zero.
0
The previous operation result was non-zero.
The value of this bit is only meaningful when accessing PSR or APSR.
29
C
R/W
0
APSR Carry or Borrow Flag
Value Description
1
The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
0
The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.
The value of this bit is only meaningful when accessing PSR or APSR.
28
V
R/W
0
APSR Overflow Flag
Value Description
1
The previous operation resulted in an overflow.
0
The previous operation did not result in an overflow.
The value of this bit is only meaningful when accessing PSR or APSR.
27
Q
R/W
0
APSR DSP Overflow and Saturation Flag
Value Description
1
DSP Overflow or saturation has occurred.
0
DSP overflow or saturation has not occurred since reset or since
the bit was last cleared.
The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.
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Bit/Field
Name
Type
Reset
26:25
ICI / IT
RO
0x0
Description
EPSR ICI / IT status
These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following an IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
24
THUMB
RO
1
EPSR Thumb State
This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:
■
The BLX, BX and POP{PC} instructions
■
Restoration from the stacked xPSR value on an exception return
■
Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a fault
or lockup. See “Lockup” on page 106 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
23:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:10
ICI / IT
RO
0x0
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
or POP instruction, the processor stops the load multiple or store multiple
instruction operation temporarily and stores the next register operand
in the multiple operation to bits 15:12. After servicing the interrupt, the
processor returns to the register pointed to by bits 15:12 and resumes
execution of the multiple load or store instruction. When EPSR holds
the ICI execution state, bits 11:10 are zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
9:7
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
Description
6:0
ISRNUM
RO
0x00
IPSR ISR Number
This field contains the exception type number of the current Interrupt
Service Routine (ISR).
Value
Description
0x00
Thread mode
0x01
Reserved
0x02
NMI
0x03
Hard fault
0x04
Memory management fault
0x05
Bus fault
0x06
Usage fault
0x07-0x0A Reserved
0x0B
SVCall
0x0C
Reserved for Debug
0x0D
Reserved
0x0E
PendSV
0x0F
SysTick
0x10
Interrupt Vector 0
0x11
Interrupt Vector 1
...
...
0x46
Interrupt Vector 54
0x47-0x7F Reserved
See “Exception Types” on page 97 for more information.
The value of this field is only meaningful when accessing PSR or IPSR.
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Register 18: Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the
Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on these instructions.
For more information on exception priority levels, see “Exception Types” on page 97.
Priority Mask Register (PRIMASK)
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PRIMASK
R/W
0
RO
0
PRIMASK
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Priority Mask
Value Description
1
Prevents the activation of all exceptions with configurable
priority.
0
No effect.
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Register 19: Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on
these instructions. For more information on exception priority levels, see “Exception
Types” on page 97.
Fault Mask Register (FAULTMASK)
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
FAULTMASK
R/W
0
RO
0
FAULTMASK
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Mask
Value Description
1
Prevents the activation of all exceptions except for NMI.
0
No effect.
The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.
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Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 97.
Base Priority Mask Register (BASEPRI)
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
BASEPRI
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:5
BASEPRI
R/W
0x0
R/W
0
reserved
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
Value Description
4:0
reserved
RO
0x0
0x0
All exceptions are unmasked.
0x1
All exceptions with priority level 1-7 are masked.
0x2
All exceptions with priority level 2-7 are masked.
0x3
All exceptions with priority level 3-7 are masked.
0x4
All exceptions with priority level 4-7 are masked.
0x5
All exceptions with priority level 5-7 are masked.
0x6
All exceptions with priority level 6-7 are masked.
0x7
All exceptions with priority level 7 are masked.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode. This register is only accessible in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 104).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch
the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as
detailed in the Cortex™-M3/M4 Instruction Set Technical User's Manual, or perform an exception
return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 104.
Note:
When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Control Register (CONTROL)
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
ASP
TMPL
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
ASP
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Active Stack Pointer
Value Description
1
PSP is the current stack pointer.
0
MSP is the current stack pointer
In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M3 updates this bit automatically on exception return.
0
TMPL
R/W
0
Thread Mode Privilege Level
Value Description
1
Unprivileged software can be executed in Thread mode.
0
Only privileged software can be executed in Thread mode.
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2.3.5
Exceptions and Interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses Handler mode to handle all exceptions except
for reset. See “Exception Entry and Return” on page 102 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 112 for more information.
2.3.6
Data Types
The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 89 for more information.
2.4
Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the LM3S9U90 controller is provided in Table 2-4 on page 87. In this manual,
register addresses are given as a hexadecimal increment, relative to the module’s base address
as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 92).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M3 Peripherals” on page 111).
Note:
Within the memory map, all reserved space returns a bus fault when read or written.
Table 2-4. Memory Map
Start
End
Description
For details,
see page ...
0x0000.0000
0x0005.FFFF
On-chip Flash
330
0x0006.0000
0x00FF.FFFF
Reserved
-
0x0100.0000
0x1FFF.FFFF
Reserved for ROM
321
0x2000.0000
0x2001.FFFF
Bit-banded on-chip SRAM
321
0x2002.0000
0x21FF.FFFF
Reserved
-
0x2200.0000
0x222F.FFFF
Bit-band alias of bit-banded on-chip SRAM starting at
0x2000.0000
321
0x2230.0000
0x3FFF.FFFF
Reserved
-
0x4000.0000
0x4000.0FFF
Watchdog timer 0
607
0x4000.1000
0x4000.1FFF
Watchdog timer 1
607
0x4000.2000
0x4000.3FFF
Reserved
-
0x4000.4000
0x4000.4FFF
GPIO Port A
439
0x4000.5000
0x4000.5FFF
GPIO Port B
439
0x4000.6000
0x4000.6FFF
GPIO Port C
439
Memory
FiRM Peripherals
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4000.7000
0x4000.7FFF
GPIO Port D
439
0x4000.8000
0x4000.8FFF
SSI0
787
0x4000.9000
0x4000.9FFF
SSI1
787
0x4000.A000
0x4000.BFFF
Reserved
-
0x4000.C000
0x4000.CFFF
UART0
723
0x4000.D000
0x4000.DFFF
UART1
723
0x4000.E000
0x4000.EFFF
UART2
723
0x4000.F000
0x4001.FFFF
Reserved
-
0x4002.0FFF
I2C 0
831
0x4002.1000
0x4002.1FFF
I2C
831
0x4002.2000
0x4002.3FFF
Reserved
-
0x4002.4000
0x4002.4FFF
GPIO Port E
439
0x4002.5000
0x4002.5FFF
GPIO Port F
439
0x4002.6000
0x4002.6FFF
GPIO Port G
439
0x4002.7000
0x4002.7FFF
GPIO Port H
439
0x4002.8000
0x4002.FFFF
Reserved
-
0x4003.0000
0x4003.0FFF
Timer 0
573
0x4003.1000
0x4003.1FFF
Timer 1
573
0x4003.2000
0x4003.2FFF
Timer 2
573
0x4003.3000
0x4003.3FFF
Timer 3
573
0x4003.4000
0x4003.7FFF
Reserved
-
0x4003.8000
0x4003.8FFF
ADC0
651
0x4003.9000
0x4003.9FFF
ADC1
651
0x4003.A000
0x4003.BFFF
Reserved
-
0x4003.C000
0x4003.CFFF
Analog Comparators
1139
0x4003.D000
0x4003.DFFF
GPIO Port J
439
0x4003.E000
0x4003.FFFF
Reserved
-
0x4004.0000
0x4004.0FFF
CAN0 Controller
910
0x4004.1000
0x4004.1FFF
CAN1 Controller
910
0x4004.2000
0x4004.7FFF
Reserved
-
0x4004.8000
0x4004.8FFF
Ethernet Controller
954
0x4004.9000
0x4004.FFFF
Reserved
-
0x4005.0000
0x4005.0FFF
USB
1027
0x4005.1000
0x4005.3FFF
Reserved
-
0x4005.4000
0x4005.4FFF
I2S0
865
0x4005.5000
0x4005.7FFF
Reserved
-
0x4005.8000
0x4005.8FFF
GPIO Port A (AHB aperture)
439
0x4005.9000
0x4005.9FFF
GPIO Port B (AHB aperture)
439
0x4005.A000
0x4005.AFFF
GPIO Port C (AHB aperture)
439
0x4005.B000
0x4005.BFFF
GPIO Port D (AHB aperture)
439
Peripherals
0x4002.0000
1
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4005.C000
0x4005.CFFF
GPIO Port E (AHB aperture)
439
0x4005.D000
0x4005.DFFF
GPIO Port F (AHB aperture)
439
0x4005.E000
0x4005.EFFF
GPIO Port G (AHB aperture)
439
0x4005.F000
0x4005.FFFF
GPIO Port H (AHB aperture)
439
0x4006.0000
0x4006.0FFF
GPIO Port J (AHB aperture)
439
0x4006.1000
0x400C.FFFF
Reserved
-
0x400D.0000
0x400D.0FFF
EPI 0
513
0x400D.1000
0x400F.BFFF
Reserved
-
0x400F.C000
0x400F.CFFF
Hibernation Module
303
0x400F.D000
0x400F.DFFF
Flash memory control
330
0x400F.E000
0x400F.EFFF
System control
207
0x400F.F000
0x400F.FFFF
µDMA
388
0x4010.0000
0x41FF.FFFF
Reserved
-
0x4200.0000
0x43FF.FFFF
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
-
0x4400.0000
0x5FFF.FFFF
Reserved
-
0x6000.0000
0xDFFF.FFFF
EPI0 mapped peripheral and RAM
-
0xE000.0000
0xE000.0FFF
Instrumentation Trace Macrocell (ITM)
70
0xE000.1000
0xE000.1FFF
Data Watchpoint and Trace (DWT)
70
0xE000.2000
0xE000.2FFF
Flash Patch and Breakpoint (FPB)
70
0xE000.3000
0xE000.DFFF
Reserved
-
0xE000.E000
0xE000.EFFF
Cortex-M3 Peripherals (SysTick, NVIC, MPU and SCB)
119
0xE000.F000
0xE003.FFFF
Reserved
-
0xE004.0000
0xE004.0FFF
Trace Port Interface Unit (TPIU)
71
0xE004.1000
0xFFFF.FFFF
Reserved
-
Private Peripheral Bus
2.4.1
Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
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An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 91).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3
Behavior of Memory Accesses
Table 2-5 on page 90 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 89 for more information on memory types and
the XN attribute. Stellaris devices may have reserved memory areas within the address ranges
shown below (refer to Table 2-4 on page 87 for more information).
Table 2-5. Memory Access Behavior
Address Range
Memory Region
Memory Type
Execute
Never
(XN)
Description
0x0000.0000 - 0x1FFF.FFFF Code
Normal
-
This executable region is for program code.
Data can also be stored here.
0x2000.0000 - 0x3FFF.FFFF SRAM
Normal
-
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 92).
0x4000.0000 - 0x5FFF.FFFF Peripheral
Device
XN
This region includes bit band and bit band
alias areas (see Table 2-7 on page 92).
0x6000.0000 - 0x9FFF.FFFF External RAM
Normal
-
This executable region is for data.
0xA000.0000 - 0xDFFF.FFFF External device
Device
XN
This region is for external device memory.
0xE000.0000- 0xE00F.FFFF Private peripheral
bus
Strongly
Ordered
XN
This region includes the NVIC, system
timer, and system control block.
0xE010.0000- 0xFFFF.FFFF Reserved
-
-
-
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 114.
The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch
target addresses.
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2.4.4
Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 90 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M3
has the following memory barrier instructions:
■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
■ MPU programming
– If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.
■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.
■ Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.
■ Memory map switching
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If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.
■ Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M3/M4 Instruction Set
Technical User's Manual.
2.4.5
Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 92. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 92. For the specific address range of the bit-band regions,
see Table 2-4 on page 87.
Note:
A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.
Table 2-6. SRAM Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
Start
End
0x2000.0000
0x2001.FFFF
SRAM bit-band region Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
0x2200.0000
0x222F.FFFF
SRAM bit-band alias
Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not remapped.
Table 2-7. Peripheral Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
0x400F.FFFF
Peripheral bit-band
region
Direct accesses to this memory range behave as
peripheral memory accesses, but this region is also bit
addressable through bit-band alias.
0x43FF.FFFF
Peripheral bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not permitted.
Start
End
0x4000.0000
0x4200.0000
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
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bit_word_addr = bit_band_base + bit_word_offset
where:
bit_word_offset
The position of the target bit in the bit-band memory region.
bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.
bit_band_base
The starting address of the alias region.
byte_offset
The number of the byte in the bit-band region that contains the targeted bit.
bit_number
The bit position, 0-7, of the targeted bit.
Figure 2-4 on page 94 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:
■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)
■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)
■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:
0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)
■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:
0x2200.001C = 0x2200.0000+ (0*32) + (7*4)
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Figure 2-4. Bit-Band Mapping
32-MB Alias Region
0x23FF.FFFC
0x23FF.FFF8
0x23FF.FFF4
0x23FF.FFF0
0x23FF.FFEC
0x23FF.FFE8
0x23FF.FFE4
0x23FF.FFE0
0x2200.001C
0x2200.0018
0x2200.0014
0x2200.0010
0x2200.000C
0x2200.0008
0x2200.0004
0x2200.0000
7
3
1-MB SRAM Bit-Band Region
7
6
5
4
3
2
1
0
7
6
0x200F.FFFF
7
6
5
4
3
2
0x2000.0003
2.4.5.1
5
4
3
2
1
0
7
6
0x200F.FFFE
1
0
7
6
5
4
3
2
5
4
3
2
1
0
6
0x200F.FFFD
1
0
0x2000.0002
7
6
5
4
3
2
0x2000.0001
5
4
2
1
0
1
0
0x200F.FFFC
1
0
7
6
5
4
3
2
0x2000.0000
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
2.4.5.2
Directly Accessing a Bit-Band Region
“Behavior of Memory Accesses” on page 90 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
2.4.6
Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 95 illustrates how data is stored.
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Figure 2-5. Data Storage
Memory
7
Register
0
31
2.4.7
Address A
B0
A+1
B1
A+2
B2
A+3
B3
lsbyte
24 23
B3
16 15
B2
8 7
B1
0
B0
msbyte
Synchronization Primitives
The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
■ The word instructions LDREX and STREX
■ The halfword instructions LDREXH and STREXH
■ The byte instructions LDREXB and STREXB
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Modify the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.
4. Test the returned status bit.
If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no
write was performed, which indicates that the value returned at step 1 might be out of date. The
software must retry the entire read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
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1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.
The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:
■ It executes a CLREX instruction.
■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.
For more information about the synchronization primitive instructions, see the Cortex™-M3/M4
Instruction Set Technical User's Manual.
2.5
Exception Model
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 98 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 47 interrupts (listed in Table 2-9 on page 99).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 112.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See “Nested Vectored Interrupt Controller (NVIC)” on page 112 for more information on exceptions
and interrupts.
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2.5.1
Exception States
Each exception is in one of the following states:
■ Inactive. The exception is not active and not pending.
■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
■ Active. An exception that is being serviced by the processor but has not completed.
Note:
An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2
Exception Types
The exception types are:
■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
■ Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.
■ Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.
■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.
■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
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– An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.
■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 99 lists the interrupts on the LM3S9U90 controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 98 shows as having
configurable priority (see the SYSHNDCTRL register on page 155 and the DIS0 register on page 128).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 104.
Table 2-8. Exception Types
Exception Type
a
Vector
Number
Priority
Vector Address or
b
Offset
-
0
-
0x0000.0000
Stack top is loaded from the first
entry of the vector table on reset.
Reset
1
-3 (highest)
0x0000.0004
Asynchronous
Non-Maskable Interrupt
(NMI)
2
-2
0x0000.0008
Asynchronous
Hard Fault
3
-1
0x0000.000C
-
c
0x0000.0010
Synchronous
c
0x0000.0014
Synchronous when precise and
asynchronous when imprecise
c
Synchronous
Memory Management
4
programmable
Bus Fault
5
programmable
Usage Fault
6
programmable
0x0000.0018
7-10
-
-
-
Activation
c
c
Reserved
SVCall
11
programmable
0x0000.002C
Synchronous
Debug Monitor
12
programmable
0x0000.0030
Synchronous
-
13
-
-
98
Reserved
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Table 2-8. Exception Types (continued)
Exception Type
PendSV
SysTick
a
Vector
Number
Priority
14
programmable
15
Interrupts
Vector Address or
b
Offset
c
0x0000.0038
Asynchronous
c
0x0000.003C
Asynchronous
programmable
16 and above
Activation
d
programmable
0x0000.0040 and above Asynchronous
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 100.
c. See SYSPRI1 on page 152.
d. See PRIn registers on page 136.
Table 2-9. Interrupts
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
0-15
-
0x0000.0000 0x0000.003C
16
0
0x0000.0040
GPIO Port A
17
1
0x0000.0044
GPIO Port B
18
2
0x0000.0048
GPIO Port C
19
3
0x0000.004C
GPIO Port D
20
4
0x0000.0050
GPIO Port E
21
5
0x0000.0054
UART0
22
6
0x0000.0058
UART1
23
7
0x0000.005C
SSI0
24
8
0x0000.0060
I2C0
25-29
9-13
-
30
14
0x0000.0078
ADC0 Sequence 0
31
15
0x0000.007C
ADC0 Sequence 1
32
16
0x0000.0080
ADC0 Sequence 2
33
17
0x0000.0084
ADC0 Sequence 3
34
18
0x0000.0088
Watchdog Timers 0 and 1
35
19
0x0000.008C
Timer 0A
36
20
0x0000.0090
Timer 0B
37
21
0x0000.0094
Timer 1A
38
22
0x0000.0098
Timer 1B
39
23
0x0000.009C
Timer 2A
40
24
0x0000.00A0
Timer 2B
41
25
0x0000.00A4
Analog Comparator 0
42
26
0x0000.00A8
Analog Comparator 1
43
27
0x0000.00AC
Analog Comparator 2
44
28
0x0000.00B0
System Control
45
29
0x0000.00B4
Flash Memory Control
46
30
0x0000.00B8
GPIO Port F
47
31
0x0000.00BC
GPIO Port G
48
32
0x0000.00C0
GPIO Port H
Processor exceptions
Reserved
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Table 2-9. Interrupts (continued)
2.5.3
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
49
33
0x0000.00C4
UART2
50
34
0x0000.00C8
SSI1
51
35
0x0000.00CC
Timer 3A
52
36
0x0000.00D0
Timer 3B
53
37
0x0000.00D4
I2C1
54
38
-
55
39
0x0000.00DC
CAN0
56
40
0x0000.00E0
CAN1
57
41
-
58
42
0x0000.00E8
Ethernet Controller
59
43
0x0000.00EC
Hibernation Module
60
44
0x0000.00F0
USB
61
45
-
Reserved
Reserved
Reserved
62
46
0x0000.00F8
µDMA Software
63
47
0x0000.00FC
µDMA Error
64
48
0x0000.0100
ADC1 Sequence 0
65
49
0x0000.0104
ADC1 Sequence 1
66
50
0x0000.0108
ADC1 Sequence 2
67
51
0x0000.010C
ADC1 Sequence 3
68
52
0x0000.0110
I2S0
69
53
0x0000.0114
EPI
70
54
0x0000.0118
GPIO Port J
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 98. Figure 2-6 on page 101 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
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Figure 2-6. Vector Table
Exception number IRQ number
70
54
.
.
.
18
2
17
1
16
0
15
-1
14
-2
13
Offset
0x0118
.
.
.
0x004C
0x0048
0x0044
0x0040
0x003C
0x0038
12
11
Vector
IRQ54
.
.
.
IRQ2
IRQ1
IRQ0
Systick
PendSV
Reserved
Reserved for Debug
-5
10
0x002C
9
SVCall
Reserved
8
7
6
-10
5
-11
4
-12
3
-13
2
-14
1
0x0018
0x0014
0x0010
0x000C
0x0008
0x0004
0x0000
Usage fault
Bus fault
Memory management fault
Hard fault
NMI
Reset
Initial SP value
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0200 to 0x3FFF.FE00 (see “Vector Table” on page 100). Note
that when configuring the VTABLE register, the offset must be aligned on a 512-byte boundary.
2.5.5
Exception Priorities
As Table 2-8 on page 98 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 152 and
page 136.
Note:
Configurable priority values for the Stellaris implementation are in the range 0-7. This means
that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always
have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
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If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.
2.5.6
Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:
■ An upper field that defines the group priority
■ A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 146.
2.5.7
Exception Entry and Return
Descriptions of exception handling use the following terms:
■ Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 102 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 103 more information.
■ Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 103 for
more information.
■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.
■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
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return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.
2.5.7.1
Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 83, FAULTMASK on page 84, and BASEPRI on page 85). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
Figure 2-7. Exception Stack Frame
...
{aligner}
xPSR
PC
LR
R12
R3
R2
R1
R0
Pre-IRQ top of stack
IRQ top of stack
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.
2.5.7.2
Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
■ An LDM or POP instruction that loads the PC
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■ A BX instruction using any register
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest four
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 104
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
EXC_RETURN[31:0]
Description
0xFFFF.FFF0
Reserved
0xFFFF.FFF1
Return to Handler mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFF2 - 0xFFFF.FFF8
Reserved
0xFFFF.FFF9
Return to Thread mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFFA - 0xFFFF.FFFC
Reserved
0xFFFF.FFFD
Return to Thread mode.
Exception return uses state from PSP.
Execution uses PSP after return.
0xFFFF.FFFE - 0xFFFF.FFFF
2.6
Reserved
Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 96). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.
■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.
2.6.1
Fault Types
Table 2-11 on page 104 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 159 for more
information about the fault status registers.
Table 2-11. Faults
Fault
Handler
Fault Status Register
Bit Name
Bus error on a vector read
Hard fault
Hard Fault Status (HFAULTSTAT)
VECT
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Table 2-11. Faults (continued)
Fault
Handler
Fault Status Register
Bit Name
Fault escalated to a hard fault
Hard fault
Hard Fault Status (HFAULTSTAT)
FORCED
MPU or default memory mismatch on Memory management
instruction access
fault
Memory Management Fault Status
(MFAULTSTAT)
IERR
MPU or default memory mismatch on Memory management
data access
fault
Memory Management Fault Status
(MFAULTSTAT)
DERR
MPU or default memory mismatch on Memory management
exception stacking
fault
Memory Management Fault Status
(MFAULTSTAT)
MSTKE
MPU or default memory mismatch on Memory management
exception unstacking
fault
Memory Management Fault Status
(MFAULTSTAT)
MUSTKE
Bus error during exception stacking
a
Bus fault
Bus Fault Status (BFAULTSTAT)
BSTKE
Bus error during exception unstacking Bus fault
Bus Fault Status (BFAULTSTAT)
BUSTKE
Bus error during instruction prefetch
Bus fault
Bus Fault Status (BFAULTSTAT)
IBUS
Precise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
PRECISE
Imprecise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
IMPRE
Attempt to access a coprocessor
Usage fault
Usage Fault Status (UFAULTSTAT)
NOCP
Undefined instruction
Usage fault
Usage Fault Status (UFAULTSTAT)
UNDEF
Attempt to enter an invalid instruction Usage fault
b
set state
Usage Fault Status (UFAULTSTAT)
INVSTAT
Invalid EXC_RETURN value
Usage fault
Usage Fault Status (UFAULTSTAT)
INVPC
Illegal unaligned load or store
Usage fault
Usage Fault Status (UFAULTSTAT)
UNALIGN
Divide by 0
Usage fault
Usage Fault Status (UFAULTSTAT)
DIV0
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction
with ICI continuation.
2.6.2
Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 152). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 155).
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 96.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
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■ A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note:
2.6.3
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 106.
Table 2-12. Fault Status and Fault Address Registers
2.6.4
Handler
Status Register Name
Address Register Name
Register Description
Hard fault
Hard Fault Status (HFAULTSTAT)
-
page 165
Memory management Memory Management Fault Status
fault
(MFAULTSTAT)
Memory Management Fault
Address (MMADDR)
page 159
Bus fault
Bus Fault Status (BFAULTSTAT)
Bus Fault Address
(FAULTADDR)
page 159
Usage fault
Usage Fault Status (UFAULTSTAT)
-
page 159
page 166
page 167
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note:
2.7
If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
Power Management
The Cortex-M3 processor sleep modes reduce power consumption:
■ Sleep mode stops the processor clock.
■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 148). For more information about the behavior of the sleep modes, see “System
Control” on page 203.
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.
2.7.1
Entering Sleep Modes
This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
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The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.
2.7.1.1
Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 107). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M3/M4 Instruction Set Technical User's Manual for more information.
2.7.1.2
Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information.
2.7.1.3
Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.
2.7.2
Wake Up from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep
mode.
2.7.2.1
Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 83 and page 84.
2.7.2.2
Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 148.
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2.8
Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 108 lists the
supported instructions.
Note:
In Table 2-13 on page 108:
■
■
■
■
■
Angle brackets, <>, enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Table 2-13. Cortex-M3 Instruction Summary
Mnemonic
Operands
Brief Description
Flags
ADC, ADCS
{Rd,} Rn, Op2
Add with carry
N,Z,C,V
ADD, ADDS
{Rd,} Rn, Op2
Add
N,Z,C,V
ADD, ADDW
{Rd,} Rn , #imm12
Add
N,Z,C,V
ADR
Rd, label
Load PC-relative address
-
AND, ANDS
{Rd,} Rn, Op2
Logical AND
N,Z,C
ASR, ASRS
Rd, Rm, <Rs|#n>
Arithmetic shift right
N,Z,C
B
label
Branch
-
BFC
Rd, #lsb, #width
Bit field clear
-
BFI
Rd, Rn, #lsb, #width
Bit field insert
-
BIC, BICS
{Rd,} Rn, Op2
Bit clear
N,Z,C
BKPT
#imm
Breakpoint
-
BL
label
Branch with link
-
BLX
Rm
Branch indirect with link
-
BX
Rm
Branch indirect
-
CBNZ
Rn, label
Compare and branch if non-zero
-
CBZ
Rn, label
Compare and branch if zero
-
CLREX
-
Clear exclusive
-
CLZ
Rd, Rm
Count leading zeros
-
CMN
Rn, Op2
Compare negative
N,Z,C,V
CMP
Rn, Op2
Compare
N,Z,C,V
CPSID
i
Change processor state, disable
interrupts
-
CPSIE
i
Change processor state, enable
interrupts
-
DMB
-
Data memory barrier
-
DSB
-
Data synchronization barrier
-
EOR, EORS
{Rd,} Rn, Op2
Exclusive OR
N,Z,C
ISB
-
Instruction synchronization barrier
-
IT
-
If-Then condition block
-
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Table 2-13. Cortex-M3 Instruction Summary (continued)
Mnemonic
Operands
Brief Description
LDM
Rn{!}, reglist
Load multiple registers, increment after -
LDMDB, LDMEA
Rn{!}, reglist
Load multiple registers, decrement
before
LDMFD, LDMIA
Rn{!}, reglist
Load multiple registers, increment after -
LDR
Rt, [Rn, #offset]
Load register with word
-
LDRB, LDRBT
Rt, [Rn, #offset]
Load register with byte
-
LDRD
Rt, Rt2, [Rn, #offset]
Load register with two bytes
-
LDREX
Rt, [Rn, #offset]
Load register exclusive
-
LDREXB
Rt, [Rn]
Load register exclusive with byte
-
LDREXH
Rt, [Rn]
Load register exclusive with halfword
-
LDRH, LDRHT
Rt, [Rn, #offset]
Load register with halfword
-
LDRSB, LDRSBT
Rt, [Rn, #offset]
Load register with signed byte
-
LDRSH, LDRSHT
Rt, [Rn, #offset]
Load register with signed halfword
-
LDRT
Rt, [Rn, #offset]
Load register with word
-
LSL, LSLS
Rd, Rm, <Rs|#n>
Logical shift left
N,Z,C
LSR, LSRS
Rd, Rm, <Rs|#n>
Logical shift right
N,Z,C
MLA
Rd, Rn, Rm, Ra
Multiply with accumulate, 32-bit result
-
MLS
Rd, Rn, Rm, Ra
Multiply and subtract, 32-bit result
-
MOV, MOVS
Rd, Op2
Move
N,Z,C
MOV, MOVW
Rd, #imm16
Move 16-bit constant
N,Z,C
MOVT
Rd, #imm16
Move top
-
MRS
Rd, spec_reg
Move from special register to general
register
-
MSR
spec_reg, Rm
Move from general register to special
register
N,Z,C,V
MUL, MULS
{Rd,} Rn, Rm
Multiply, 32-bit result
N,Z
MVN, MVNS
Rd, Op2
Move NOT
N,Z,C
NOP
-
No operation
-
ORN, ORNS
{Rd,} Rn, Op2
Logical OR NOT
N,Z,C
ORR, ORRS
{Rd,} Rn, Op2
Logical OR
N,Z,C
POP
reglist
Pop registers from stack
-
PUSH
reglist
Push registers onto stack
-
RBIT
Rd, Rn
Reverse bits
-
REV
Rd, Rn
Reverse byte order in a word
-
REV16
Rd, Rn
Reverse byte order in each halfword
-
REVSH
Rd, Rn
Reverse byte order in bottom halfword
and sign extend
-
ROR, RORS
Rd, Rm, <Rs|#n>
Rotate right
N,Z,C
RRX, RRXS
Rd, Rm
Rotate right with extend
N,Z,C
RSB, RSBS
{Rd,} Rn, Op2
Reverse subtract
N,Z,C,V
SBC, SBCS
{Rd,} Rn, Op2
Subtract with carry
N,Z,C,V
SBFX
Rd, Rn, #lsb, #width
Signed bit field extract
-
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Table 2-13. Cortex-M3 Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
SDIV
{Rd,} Rn, Rm
Signed divide
-
SEV
-
Send event
-
SMLAL
RdLo, RdHi, Rn, Rm
Signed multiply with accumulate
(32x32+64), 64-bit result
-
SMULL
RdLo, RdHi, Rn, Rm
Signed multiply (32x32), 64-bit result
-
SSAT
Rd, #n, Rm {,shift #s}
Signed saturate
Q
STM
Rn{!}, reglist
Store multiple registers, increment after -
STMDB, STMEA
Rn{!}, reglist
Store multiple registers, decrement
before
STMFD, STMIA
Rn{!}, reglist
Store multiple registers, increment after -
STR
Rt, [Rn {, #offset}]
Store register word
-
STRB, STRBT
Rt, [Rn {, #offset}]
Store register byte
-
STRD
Rt, Rt2, [Rn {, #offset}]
Store register two words
-
STREX
Rt, Rt, [Rn {, #offset}]
Store register exclusive
-
STREXB
Rd, Rt, [Rn]
Store register exclusive byte
-
STREXH
Rd, Rt, [Rn]
Store register exclusive halfword
-
STRH, STRHT
Rt, [Rn {, #offset}]
Store register halfword
-
STRSB, STRSBT
Rt, [Rn {, #offset}]
Store register signed byte
-
STRSH, STRSHT
Rt, [Rn {, #offset}]
Store register signed halfword
-
STRT
Rt, [Rn {, #offset}]
Store register word
-
SUB, SUBS
{Rd,} Rn, Op2
Subtract
N,Z,C,V
SUB, SUBW
{Rd,} Rn, #imm12
Subtract 12-bit constant
N,Z,C,V
SVC
#imm
Supervisor call
-
SXTB
{Rd,} Rm {,ROR #n}
Sign extend a byte
-
SXTH
{Rd,} Rm {,ROR #n}
Sign extend a halfword
-
TBB
[Rn, Rm]
Table branch byte
-
TBH
[Rn, Rm, LSL #1]
Table branch halfword
-
TEQ
Rn, Op2
Test equivalence
N,Z,C
TST
Rn, Op2
Test
N,Z,C
UBFX
Rd, Rn, #lsb, #width
Unsigned bit field extract
-
UDIV
{Rd,} Rn, Rm
Unsigned divide
-
UMLAL
RdLo, RdHi, Rn, Rm
Unsigned multiply with accumulate
(32x32+32+32), 64-bit result
-
UMULL
RdLo, RdHi, Rn, Rm
Unsigned multiply (32x 2), 64-bit result -
USAT
Rd, #n, Rm {,shift #s}
Unsigned Saturate
Q
UXTB
{Rd,} Rm, {,ROR #n}
Zero extend a Byte
-
UXTH
{Rd,} Rm, {,ROR #n}
Zero extend a Halfword
-
WFE
-
Wait for event
-
WFI
-
Wait for interrupt
-
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3
Cortex-M3 Peripherals
®
This chapter provides information on the Stellaris implementation of the Cortex-M3 processor
peripherals, including:
■ SysTick (see page 111)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC) (see page 112)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
■ System Control Block (SCB) (see page 114)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
■ Memory Protection Unit (MPU) (see page 114)
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
Table 3-1 on page 111 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Address
Core Peripheral
Description (see page ...)
0xE000.E010-0xE000.E01F
System Timer
111
0xE000.E100-0xE000.E4EF
Nested Vectored Interrupt Controller
112
System Control Block
114
Memory Protection Unit
114
0xE000.EF00-0xE000.EF03
0xE000.E008-0xE000.E00F
0xE000.ED00-0xE000.ED3F
0xE000.ED90-0xE000.EDB8
3.1
Functional Description
This chapter provides information on the Stellaris implementation of the Cortex-M3 processor
peripherals: SysTick, NVIC, SCB and MPU.
3.1.1
System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
■ A high-speed alarm timer using the system clock.
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■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.
■ SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode,
the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick
registers.
Note:
3.1.2
When the processor is halted for debugging, the counter does not decrement.
Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
■ 47 interrupts.
■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
■ Low-latency exception and interrupt handling.
■ Level and pulse detection of interrupt signals.
■ Dynamic reprioritization of interrupts.
■ Grouping of priority values into group priority and subpriority fields.
■ Interrupt tail-chaining.
■ An external Non-maskable interrupt (NMI).
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The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
3.1.2.1
Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 113 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.1.2.2
Hardware and Software Control of Interrupts
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
■ The NVIC detects that the interrupt signal is High and the interrupt is not active.
■ The NVIC detects a rising edge on the interrupt signal.
■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 130 or SWTRIG on page 138.
A pending interrupt remains pending until one of the following:
■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
■ Software writes to the corresponding interrupt clear-pending register bit
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
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– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
3.1.3
System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.1.4
Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 89 for more information).
Table 3-2 on page 114 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Stellaris Microcontroller” on page 118 for guidelines for programming a
microcontroller implementation.
Table 3-2. Memory Attributes Summary
Memory Type
Description
Strongly Ordered
All accesses to Strongly Ordered memory occur in program order.
Device
Memory-mapped peripherals
Normal
Normal memory
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.
■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
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The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.
3.1.4.1
Updating an MPU Region
To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.
Updating an MPU Region Using Separate Words
This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
STR R1, [R0, #0x0]
STR R4, [R0, #0x4]
STRH R2, [R0, #0x8]
STRH R3, [R0, #0xA]
;
;
;
;
;
0xE000ED98, MPU region number register
Region Number
Region Base Address
Region Size and Enable
Region Attribute
Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
STR R1, [R0, #0x0]
BIC R2, R2, #1
STRH R2, [R0, #0x8]
STR R4, [R0, #0x4]
STRH R3, [R0, #0xA]
ORR R2, #1
STRH R2, [R0, #0x8]
;
;
;
;
;
;
;
;
0xE000ED98, MPU region number register
Region Number
Disable
Region Size and Enable
Region Base Address
Region Attribute
Enable
Region Size and Enable
Software must use memory barrier instructions:
■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.
■ After MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
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For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.
Updating an MPU Region Using Multi-Word Writes
The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3}
; Region number, address, attribute, size and enable
This operation can be done in two words for pre-packed information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 172) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE
; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 174) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.
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Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 117 shows.
Figure 3-1. SRD Use Example
Region 2, with
subregions
Region 1
Base address of both regions
3.1.4.2
Offset from
base address
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Disabled subregion
64KB
Disabled subregion
0
MPU Access Permission Attributes
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 117 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M3 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Stellaris Microcontroller” on page 118 for information on programming the MPU for Stellaris
implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
TEX
S
000b
x
C
B
Memory Type
Shareability
Other Attributes
a
0
0
Strongly Ordered
Shareable
-
a
-
000
x
0
1
Device
Shareable
000
0
1
0
Normal
Not shareable
000
1
1
0
Normal
Shareable
000
0
1
1
Normal
Not shareable
000
1
1
1
Normal
Shareable
001
0
0
0
Normal
Not shareable
001
1
0
0
Normal
Shareable
Outer and inner
noncacheable.
001
x
a
0
1
Reserved encoding
-
-
a
Outer and inner
write-through. No write
allocate.
001
x
1
0
Reserved encoding
-
-
001
0
1
1
Normal
Not shareable
001
1
1
1
Normal
Shareable
Outer and inner
write-back. Write and
read allocate.
010
x
a
0
0
Device
Not shareable
Nonshared Device.
a
0
1
Reserved encoding
-
-
a
1
x
Reserved encoding
-
-
010
x
010
x
a
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Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)
TEX
S
C
B
Memory Type
Shareability
Other Attributes
1BB
0
A
A
Normal
Not shareable
1BB
1
A
A
Normal
Shareable
Cached memory (BB =
outer policy, AA = inner
policy).
See Table 3-4 for the
encoding of the AA and
BB bits.
a. The MPU ignores the value of this bit.
Table 3-4 on page 118 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.
Table 3-4. Cache Policy for Memory Attribute Encoding
Encoding, AA or BB
Corresponding Cache Policy
00
Non-cacheable
01
Write back, write and read allocate
10
Write through, no write allocate
11
Write back, no write allocate
Table 3-5 on page 118 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
AP Bit Field
Privileged
Permissions
Unprivileged
Permissions
Description
000
No access
No access
All accesses generate a permission fault.
001
R/W
No access
Access from privileged software only.
010
R/W
RO
Writes by unprivileged software generate a
permission fault.
011
R/W
R/W
Full access.
100
Unpredictable
Unpredictable
Reserved.
101
RO
No access
Reads by privileged software only.
110
RO
RO
Read-only, by privileged or unprivileged software.
111
RO
RO
Read-only, by privileged or unprivileged software.
MPU Configuration for a Stellaris Microcontroller
Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should
be programmed as shown in Table 3-6 on page 118.
Table 3-6. Memory Region Attributes for Stellaris Microcontrollers
Memory Region
TEX
S
C
B
Memory Type and Attributes
Flash memory
000b
0
1
0
Normal memory, non-shareable, write-through
Internal SRAM
000b
1
1
0
Normal memory, shareable, write-through
External SRAM
000b
1
1
1
Normal memory, shareable, write-back,
write-allocate
Peripherals
000b
1
0
1
Device memory, shareable
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In current Stellaris microcontroller implementations, the shareability and cache policy attributes do
not affect the system behavior. However, using these settings for the MPU regions can make the
application code more portable. The values given are for typical situations.
3.1.4.3
MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 87 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 159 for more information.
3.2
Register Map
Table 3-7 on page 119 lists the Cortex-M3 Peripheral SysTick, NVIC, MPU and SCB registers. The
offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Note:
Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-7. Peripherals Register Map
Offset
Name
Type
Reset
Description
See
page
System Timer (SysTick) Registers
0x010
STCTRL
R/W
0x0000.0004
SysTick Control and Status Register
122
0x014
STRELOAD
R/W
0x0000.0000
SysTick Reload Value Register
124
0x018
STCURRENT
R/WC
0x0000.0000
SysTick Current Value Register
125
Nested Vectored Interrupt Controller (NVIC) Registers
0x100
EN0
R/W
0x0000.0000
Interrupt 0-31 Set Enable
126
0x104
EN1
R/W
0x0000.0000
Interrupt 32-54 Set Enable
127
0x180
DIS0
R/W
0x0000.0000
Interrupt 0-31 Clear Enable
128
0x184
DIS1
R/W
0x0000.0000
Interrupt 32-54 Clear Enable
129
0x200
PEND0
R/W
0x0000.0000
Interrupt 0-31 Set Pending
130
0x204
PEND1
R/W
0x0000.0000
Interrupt 32-54 Set Pending
131
0x280
UNPEND0
R/W
0x0000.0000
Interrupt 0-31 Clear Pending
132
0x284
UNPEND1
R/W
0x0000.0000
Interrupt 32-54 Clear Pending
133
0x300
ACTIVE0
RO
0x0000.0000
Interrupt 0-31 Active Bit
134
0x304
ACTIVE1
RO
0x0000.0000
Interrupt 32-54 Active Bit
135
0x400
PRI0
R/W
0x0000.0000
Interrupt 0-3 Priority
136
0x404
PRI1
R/W
0x0000.0000
Interrupt 4-7 Priority
136
0x408
PRI2
R/W
0x0000.0000
Interrupt 8-11 Priority
136
0x40C
PRI3
R/W
0x0000.0000
Interrupt 12-15 Priority
136
0x410
PRI4
R/W
0x0000.0000
Interrupt 16-19 Priority
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Table 3-7. Peripherals Register Map (continued)
Description
See
page
Offset
Name
Type
Reset
0x414
PRI5
R/W
0x0000.0000
Interrupt 20-23 Priority
136
0x418
PRI6
R/W
0x0000.0000
Interrupt 24-27 Priority
136
0x41C
PRI7
R/W
0x0000.0000
Interrupt 28-31 Priority
136
0x420
PRI8
R/W
0x0000.0000
Interrupt 32-35 Priority
136
0x424
PRI9
R/W
0x0000.0000
Interrupt 36-39 Priority
136
0x428
PRI10
R/W
0x0000.0000
Interrupt 40-43 Priority
136
0x42C
PRI11
R/W
0x0000.0000
Interrupt 44-47 Priority
136
0x430
PRI12
R/W
0x0000.0000
Interrupt 48-51 Priority
136
0x434
PRI13
R/W
0x0000.0000
Interrupt 52-54 Priority
136
0xF00
SWTRIG
WO
0x0000.0000
Software Trigger Interrupt
138
System Control Block (SCB) Registers
0x008
ACTLR
R/W
0x0000.0000
Auxiliary Control
139
0xD00
CPUID
RO
0x412F.C230
CPU ID Base
141
0xD04
INTCTRL
R/W
0x0000.0000
Interrupt Control and State
142
0xD08
VTABLE
R/W
0x0000.0000
Vector Table Offset
145
0xD0C
APINT
R/W
0xFA05.0000
Application Interrupt and Reset Control
146
0xD10
SYSCTRL
R/W
0x0000.0000
System Control
148
0xD14
CFGCTRL
R/W
0x0000.0200
Configuration and Control
150
0xD18
SYSPRI1
R/W
0x0000.0000
System Handler Priority 1
152
0xD1C
SYSPRI2
R/W
0x0000.0000
System Handler Priority 2
153
0xD20
SYSPRI3
R/W
0x0000.0000
System Handler Priority 3
154
0xD24
SYSHNDCTRL
R/W
0x0000.0000
System Handler Control and State
155
0xD28
FAULTSTAT
R/W1C
0x0000.0000
Configurable Fault Status
159
0xD2C
HFAULTSTAT
R/W1C
0x0000.0000
Hard Fault Status
165
0xD34
MMADDR
R/W
-
Memory Management Fault Address
166
0xD38
FAULTADDR
R/W
-
Bus Fault Address
167
Memory Protection Unit (MPU) Registers
0xD90
MPUTYPE
RO
0x0000.0800
MPU Type
168
0xD94
MPUCTRL
R/W
0x0000.0000
MPU Control
169
0xD98
MPUNUMBER
R/W
0x0000.0000
MPU Region Number
171
0xD9C
MPUBASE
R/W
0x0000.0000
MPU Region Base Address
172
0xDA0
MPUATTR
R/W
0x0000.0000
MPU Region Attribute and Size
174
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Table 3-7. Peripherals Register Map (continued)
Name
Type
Reset
0xDA4
MPUBASE1
R/W
0x0000.0000
MPU Region Base Address Alias 1
172
0xDA8
MPUATTR1
R/W
0x0000.0000
MPU Region Attribute and Size Alias 1
174
0xDAC
MPUBASE2
R/W
0x0000.0000
MPU Region Base Address Alias 2
172
0xDB0
MPUATTR2
R/W
0x0000.0000
MPU Region Attribute and Size Alias 2
174
0xDB4
MPUBASE3
R/W
0x0000.0000
MPU Region Base Address Alias 3
172
0xDB8
MPUATTR3
R/W
0x0000.0000
MPU Region Attribute and Size Alias 3
174
3.3
Description
See
page
Offset
System Timer (SysTick) Register Descriptions
This section lists and describes the System Timer registers, in numerical order by address offset.
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Register 1: SysTick Control and Status Register (STCTRL), offset 0x010
Note:
This register can only be accessed from privileged mode.
The SysTick STCTRL register enables the SysTick features.
SysTick Control and Status Register (STCTRL)
Base 0xE000.E000
Offset 0x010
Type R/W, reset 0x0000.0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
16
COUNT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
0
CLK_SRC
INTEN
ENABLE
R/W
1
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
COUNT
RO
0
Count Flag
Value
Description
0
The SysTick timer has not counted to 0 since the last time
this bit was read.
1
The SysTick timer has counted to 0 since the last time
this bit was read.
This bit is cleared by a read of the register or if the STCURRENT register
is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise,
the COUNT bit is not changed by the debugger read. See the ARM®
Debug Interface V5 Architecture Specification for more information on
MasterType.
15:3
reserved
RO
0x000
2
CLK_SRC
R/W
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Source
Value Description
0
External reference clock. (Not implemented for most Stellaris
microcontrollers.)
1
System clock
Because an external reference clock is not implemented, this bit must
be set in order for SysTick to operate.
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Bit/Field
Name
Type
Reset
1
INTEN
R/W
0
0
ENABLE
R/W
0
Description
Interrupt Enable
Value
Description
0
Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached 0.
1
An interrupt is generated to the NVIC when SysTick counts
to 0.
Enable
Value
Description
0
The counter is disabled.
1
Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down.
On reaching 0, the COUNT bit is set and an interrupt is
generated if enabled by INTEN. The counter then loads the
RELOAD value again and begins counting.
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Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014
Note:
This register can only be accessed from privileged mode.
The STRELOAD register specifies the start value to load into the SysTick Current Value
(STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and
0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the
COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
SysTick Reload Value Register (STRELOAD)
Base 0xE000.E000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
R/W
0
R/W
0
R/W
0
27
26
25
24
23
22
21
20
18
17
16
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
19
RELOAD
RELOAD
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:0
RELOAD
R/W
0x00.0000
Reload Value
Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.
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Register 3: SysTick Current Value Register (STCURRENT), offset 0x018
Note:
This register can only be accessed from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.
SysTick Current Value Register (STCURRENT)
Base 0xE000.E000
Offset 0x018
Type R/WC, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
reserved
Type
Reset
20
19
18
17
16
CURRENT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
CURRENT
Type
Reset
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:0
CURRENT
R/WC
0x00.0000
Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.
3.4
NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 145.
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Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100
Note:
This register can only be accessed from privileged mode.
See Table 2-9 on page 99 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 0-31 Set Enable (EN0)
Base 0xE000.E000
Offset 0x100
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
INT
Type
Reset
INT
Type
Reset
Bit/Field
Name
Type
31:0
INT
R/W
Reset
Description
0x0000.0000 Interrupt Enable
Value
Description
0
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in
the DISn register.
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Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104
Note:
This register can only be accessed from privileged mode.
The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 99 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 32-54 Set Enable (EN1)
Base 0xE000.E000
Offset 0x104
Type R/W, reset 0x0000.0000
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
R/W
0
R/W
0
R/W
0
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
INT
INT
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:23
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:0
INT
R/W
0x00.0000
Interrupt Enable
Value
Description
0
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in
the DIS1 register.
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Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
Note:
This register can only be accessed from privileged mode.
See Table 2-9 on page 99 for interrupt assignments.
Interrupt 0-31 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
INT
R/W
R/W
0
Reset
R/W
0
Description
0x0000.0000 Interrupt Disable
Value Description
0
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
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Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184
Note:
This register can only be accessed from privileged mode.
The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt
54. See Table 2-9 on page 99 for interrupt assignments.
Interrupt 32-54 Clear Enable (DIS1)
Base 0xE000.E000
Offset 0x184
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
19
18
17
16
INT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:23
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:0
INT
R/W
0x00.0000
Interrupt Disable
Value Description
0
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN1
register, disabling interrupt [n].
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Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200
Note:
This register can only be accessed from privileged mode.
See Table 2-9 on page 99 for interrupt assignments.
Interrupt 0-31 Set Pending (PEND0)
Base 0xE000.E000
Offset 0x200
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
INT
R/W
R/W
0
Reset
R/W
0
Description
0x0000.0000 Interrupt Set Pending
Value
Description
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.
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Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204
Note:
This register can only be accessed from privileged mode.
The PEND1 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 99 for
interrupt assignments.
Interrupt 32-54 Set Pending (PEND1)
Base 0xE000.E000
Offset 0x204
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
19
18
17
16
INT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:23
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:0
INT
R/W
0x00.0000
Interrupt Set Pending
Value
Description
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND1 register.
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Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
Note:
This register can only be accessed from privileged mode.
See Table 2-9 on page 99 for interrupt assignments.
Interrupt 0-31 Clear Pending (UNPEND0)
Base 0xE000.E000
Offset 0x280
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
INT
R/W
R/W
0
Reset
R/W
0
Description
0x0000.0000 Interrupt Clear Pending
Value Description
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
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Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284
Note:
This register can only be accessed from privileged mode.
The UNPEND1 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table
2-9 on page 99 for interrupt assignments.
Interrupt 32-54 Clear Pending (UNPEND1)
Base 0xE000.E000
Offset 0x284
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
19
18
17
16
INT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:23
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:0
INT
R/W
0x00.0000
Interrupt Clear Pending
Value Description
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND1
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
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Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300
Note:
This register can only be accessed from privileged mode.
See Table 2-9 on page 99 for interrupt assignments.
Caution – Do not manually set or clear the bits in this register.
Interrupt 0-31 Active Bit (ACTIVE0)
Base 0xE000.E000
Offset 0x300
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
INT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
INT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
31:0
INT
RO
RO
0
Reset
RO
0
Description
0x0000.0000 Interrupt Active
Value Description
0
The corresponding interrupt is not active.
1
The corresponding interrupt is active, or active and pending.
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Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304
Note:
This register can only be accessed from privileged mode.
The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit
22 corresponds to Interrupt 54. See Table 2-9 on page 99 for interrupt assignments.
Caution – Do not manually set or clear the bits in this register.
Interrupt 32-54 Active Bit (ACTIVE1)
Base 0xE000.E000
Offset 0x304
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
19
18
17
16
INT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
INT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:23
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:0
INT
RO
0x00.0000
Interrupt Active
Value Description
0
The corresponding interrupt is not active.
1
The corresponding interrupt is active, or active and pending.
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Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420
Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428
Register 25: Interrupt 44-47 Priority (PRI11), offset 0x42C
Register 26: Interrupt 48-51 Priority (PRI12), offset 0x430
Register 27: Interrupt 52-54 Priority (PRI13), offset 0x434
Note:
This register can only be accessed from privileged mode.
The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible.
Each register holds four priority fields that are assigned to interrupts as follows:
PRIn Register Bit Field
Interrupt
Bits 31:29
Interrupt [4n+3]
Bits 23:21
Interrupt [4n+2]
Bits 15:13
Interrupt [4n+1]
Bits 7:5
Interrupt [4n]
See Table 2-9 on page 99 for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 146) indicates the
position of the binary point that splits the priority and subpriority fields.
These registers can only be accessed from privileged mode.
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Interrupt 0-3 Priority (PRI0)
Base 0xE000.E000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
INTD
Type
Reset
25
24
23
reserved
22
21
20
19
INTC
18
17
16
reserved
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
INTB
Type
Reset
26
R/W
0
R/W
0
reserved
RO
0
INTA
Bit/Field
Name
Type
Reset
31:29
INTD
R/W
0x0
R/W
0
reserved
RO
0
Description
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
28:24
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21
INTC
R/W
0x0
Interrupt Priority for Interrupt [4n+2]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
20:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13
INTB
R/W
0x0
Interrupt Priority for Interrupt [4n+1]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
12:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
INTA
R/W
0x0
Interrupt Priority for Interrupt [4n]
This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
4:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 28: Software Trigger Interrupt (SWTRIG), offset 0xF00
Note:
Only privileged software can enable unprivileged access to the SWTRIG register.
Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI).
See Table 2-9 on page 99 for interrupt assignments.
When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 150) is
set, unprivileged software can access the SWTRIG register.
Software Trigger Interrupt (SWTRIG)
Base 0xE000.E000
Offset 0xF00
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
INTID
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5:0
INTID
WO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt ID
This field holds the interrupt ID of the required SGI. For example, a value
of 0x3 generates an interrupt on IRQ3.
3.5
System Control Block (SCB) Register Descriptions
This section lists and describes the System Control Block (SCB) registers, in numerical order by
address offset. The SCB registers can only be accessed from privileged mode.
All registers must be accessed with aligned word accesses except for the FAULTSTAT and
SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to system control block registers.
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Register 29: Auxiliary Control (ACTLR), offset 0x008
Note:
This register can only be accessed from privileged mode.
The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default
memory map, and interruption of multi-cycle instructions. By default, this register is set to provide
optimum performance from the Cortex-M3 processor and does not normally require modification.
Auxiliary Control (ACTLR)
Base 0xE000.E000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
DISFOLD DISWBUF DISMCYC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
DISFOLD
R/W
0
Disable IT Folding
Value Description
0
No effect.
1
Disables IT folding.
In some situations, the processor can start executing the first instruction
in an IT block while it is still executing the IT instruction. This behavior
is called IT folding, and improves performance, However, IT folding can
cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit
before executing the task, to disable IT folding.
1
DISWBUF
R/W
0
Disable Write Buffer
Value Description
0
No effect.
1
Disables write buffer use during default memory map accesses.
In this situation, all bus faults are precise bus faults but
performance is decreased because any store to memory must
complete before the processor can execute the next instruction.
Note:
This bit only affects write buffers implemented in the
Cortex-M3 processor.
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Bit/Field
Name
Type
Reset
0
DISMCYC
R/W
0
Description
Disable Interrupts of Multiple Cycle Instructions
Value Description
0
No effect.
1
Disables interruption of load multiple and store multiple
instructions. In this situation, the interrupt latency of the
processor is increased because any LDM or STM must complete
before the processor can stack the current state and enter the
interrupt handler.
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Register 30: CPU ID Base (CPUID), offset 0xD00
Note:
This register can only be accessed from privileged mode.
The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and
implementation information.
CPU ID Base (CPUID)
Base 0xE000.E000
Offset 0xD00
Type RO, reset 0x412F.C230
31
30
29
28
27
26
25
24
23
22
IMP
Type
Reset
21
20
19
18
VAR
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
PARTNO
Type
Reset
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
1
17
16
RO
1
RO
1
1
0
RO
0
RO
0
CON
REV
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:24
IMP
RO
0x41
Implementer Code
RO
1
RO
1
RO
0
RO
0
Value Description
0x41 ARM
23:20
VAR
RO
0x2
Variant Number
Value Description
0x2
19:16
CON
RO
0xF
The rn value in the rnpn product revision identifier, for example,
the 2 in r2p0.
Constant
Value Description
0xF
15:4
PARTNO
RO
0xC23
Always reads as 0xF.
Part Number
Value Description
0xC23 Cortex-M3 processor.
3:0
REV
RO
0x0
Revision Number
Value Description
0x0
The pn value in the rnpn product revision identifier, for example,
the 0 in r2p0.
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Register 31: Interrupt Control and State (INTCTRL), offset 0xD04
Note:
This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.
Interrupt Control and State (INTCTRL)
Base 0xE000.E000
Offset 0xD04
Type R/W, reset 0x0000.0000
31
NMISET
Type
Reset
30
29
reserved
28
26
PENDSV UNPENDSV
25
PENDSTSET PENDSTCLR
24
reserved
23
22
21
ISRPRE ISRPEND
20
19
18
reserved
17
16
VECPEND
R/W
0
RO
0
RO
0
R/W
0
WO
0
R/W
0
WO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
VECPEND
Type
Reset
27
RO
0
RETBASE
RO
0
reserved
RO
0
Bit/Field
Name
Type
Reset
31
NMISET
R/W
0
VECACT
RO
0
Description
NMI Set Pending
Value Description
0
On a read, indicates an NMI exception is not pending.
On a write, no effect.
1
On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.
Because NMI is the highest-priority exception, normally the processor
enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
30:29
reserved
RO
0x0
28
PENDSV
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PendSV Set Pending
Value Description
0
On a read, indicates a PendSV exception is not pending.
On a write, no effect.
1
On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.
Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.
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Bit/Field
Name
Type
Reset
27
UNPENDSV
WO
0
Description
PendSV Clear Pending
Value Description
0
On a write, no effect.
1
On a write, removes the pending state from the PendSV
exception.
This bit is write only; on a register read, its value is unknown.
26
PENDSTSET
R/W
0
SysTick Set Pending
Value Description
0
On a read, indicates a SysTick exception is not pending.
On a write, no effect.
1
On a read, indicates a SysTick exception is pending.
On a write, changes the SysTick exception state to pending.
This bit is cleared by writing a 1 to the PENDSTCLR bit.
25
PENDSTCLR
WO
0
SysTick Clear Pending
Value Description
0
On a write, no effect.
1
On a write, removes the pending state from the SysTick
exception.
This bit is write only; on a register read, its value is unknown.
24
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23
ISRPRE
RO
0
Debug Interrupt Handling
Value Description
0
The release from halt does not take an interrupt.
1
The release from halt takes an interrupt.
This bit is only meaningful in Debug mode and reads as zero when the
processor is not in Debug mode.
22
ISRPEND
RO
0
Interrupt Pending
Value Description
0
No interrupt is pending.
1
An interrupt is pending.
This bit provides status for all interrupts excluding NMI and Faults.
21:19
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
Description
18:12
VECPEND
RO
0x00
Interrupt Pending Vector Number
This field contains the exception number of the highest priority pending
enabled exception. The value indicated by this field includes the effect
of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
Value
Description
0x00
No exceptions are pending
0x01
Reserved
0x02
NMI
0x03
Hard fault
0x04
Memory management fault
0x05
Bus fault
0x06
Usage fault
0x07-0x0A Reserved
0x0B
SVCall
0x0C
Reserved for Debug
0x0D
Reserved
0x0E
PendSV
0x0F
SysTick
0x10
Interrupt Vector 0
0x11
Interrupt Vector 1
...
...
0x46
Interrupt Vector 54
0x47-0x7F Reserved
11
RETBASE
RO
0
Return to Base
Value Description
0
There are preempted active exceptions to execute.
1
There are no active exceptions, or the currently executing
exception is the only active exception.
This bit provides status for all interrupts excluding NMI and Faults. This
bit only has meaning if the processor is currently executing an ISR (the
Interrupt Program Status (IPSR) register is non-zero).
10:7
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:0
VECACT
RO
0x00
Interrupt Pending Vector Number
This field contains the active exception number. The exception numbers
can be found in the description for the VECPEND field. If this field is clear,
the processor is in Thread mode. This field contains the same value as
the ISRNUM field in the IPSR register.
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn),
Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn),
and Interrupt Priority (PRIn) registers (see page 79).
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Register 32: Vector Table Offset (VTABLE), offset 0xD08
Note:
This register can only be accessed from privileged mode.
The VTABLE register indicates the offset of the vector table base address from memory address
0x0000.0000.
Vector Table Offset (VTABLE)
Base 0xE000.E000
Offset 0xD08
Type R/W, reset 0x0000.0000
31
30
reserved
Type
Reset
29
28
27
26
25
24
23
BASE
RO
0
RO
0
R/W
0
15
14
13
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
OFFSET
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12
11
10
9
8
7
6
5
OFFSET
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
reserved
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:30
reserved
RO
0x0
29
BASE
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Vector Table Base
Value Description
28:9
OFFSET
R/W
0x000.00
0
The vector table is in the code memory region.
1
The vector table is in the SRAM memory region.
Vector Table Offset
When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 54
interrupts, the offset must be aligned on a 512-byte boundary.
8:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 33: Application Interrupt and Reset Control (APINT), offset 0xD0C
Note:
This register can only be accessed from privileged mode.
The APINT register provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. To write to this register, 0x05FA must be written to
the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the
Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table
3-8 on page 146 shows how the PRIGROUP value controls this split. The bit numbers in the Group
Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the
INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note:
Determining preemption of an exception uses only the group priority field.
Table 3-8. Interrupt Priority Levels
a
PRIGROUP Bit Field
Binary Point
Group Priority Field Subpriority Field
Group
Priorities
Subpriorities
0x0 - 0x4
bxxx.
[7:5]
None
8
1
0x5
bxx.y
[7:6]
[5]
4
2
0x6
bx.yy
[7]
[6:5]
2
4
0x7
b.yyy
None
[7:5]
1
8
a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.
Application Interrupt and Reset Control (APINT)
Base 0xE000.E000
Offset 0xD0C
Type R/W, reset 0xFA05.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
5
4
3
2
1
0
VECTKEY
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
15
14
13
12
11
10
reserved
ENDIANESS
Type
Reset
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
0
R/W
0
R/W
0
9
8
7
6
PRIGROUP
RO
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:16
VECTKEY
R/W
0xFA05
reserved
R/W
0
RO
0
RO
0
RO
0
SYSRESREQ VECTCLRACT VECTRESET
RO
0
RO
0
WO
0
WO
0
WO
0
Description
Register Key
This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this
register. On a read, 0xFA05 is returned.
15
ENDIANESS
RO
0
Data Endianess
The Stellaris implementation uses only little-endian mode so this is
cleared to 0.
14:11
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
10:8
PRIGROUP
R/W
0x0
Description
Interrupt Priority Grouping
This field determines the split of group priority from subpriority (see
Table 3-8 on page 146 for more information).
7:3
reserved
RO
0x0
2
SYSRESREQ
WO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Reset Request
Value Description
0
No effect.
1
Resets the core and all on-chip peripherals except the Debug
interface.
This bit is automatically cleared during the reset of the core and reads
as 0.
1
VECTCLRACT
WO
0
Clear Active NMI / Fault
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
0
VECTRESET
WO
0
System Reset
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
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Register 34: System Control (SYSCTRL), offset 0xD10
Note:
This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.
System Control (SYSCTRL)
Base 0xE000.E000
Offset 0xD10
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.00
4
SEVONPEND
R/W
0
RO
0
RO
0
RO
0
RO
0
4
3
SEVONPEND
reserved
R/W
0
RO
0
SLEEPDEEP SLEEPEXIT
R/W
0
R/W
0
0
reserved
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Wake Up on Pending
Value Description
0
Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
1
Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
SLEEPDEEP
R/W
0
Deep Sleep Enable
Value Description
0
Use Sleep mode as the low power mode.
1
Use Deep-sleep mode as the low power mode.
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Bit/Field
Name
Type
Reset
1
SLEEPEXIT
R/W
0
Description
Sleep on ISR Exit
Value Description
0
When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode.
1
When returning from Handler mode to Thread mode, enter sleep
or deep sleep on return from an ISR.
Setting this bit enables an interrupt-driven application to avoid returning
to an empty main application.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 35: Configuration and Control (CFGCTRL), offset 0xD14
Note:
This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 138).
Configuration and Control (CFGCTRL)
Base 0xE000.E000
Offset 0xD14
Type R/W, reset 0x0000.0200
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
reserved
STKALIGN BFHFNMIGN
RO
0
RO
0
R/W
1
Bit/Field
Name
Type
Reset
31:10
reserved
RO
0x0000.00
9
STKALIGN
R/W
1
R/W
0
RO
0
RO
0
RO
0
4
3
DIV0
UNALIGNED
R/W
0
R/W
0
reserved MAINPEND BASETHR
RO
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stack Alignment on Exception Entry
Value Description
0
The stack is 4-byte aligned.
1
The stack is 8-byte aligned.
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
8
BFHFNMIGN
R/W
0
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
Value Description
0
Data bus faults caused by load and store instructions cause a
lock-up.
1
Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
4
DIV0
R/W
0
Description
Trap on Divide by 0
This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.
Value Description
3
UNALIGNED
R/W
0
0
Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
1
Trap on divide by 0.
Trap on Unaligned Access
Value Description
0
Do not trap on unaligned halfword and word accesses.
1
Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
MAINPEND
R/W
0
Allow Main Interrupt Trigger
Value Description
0
BASETHR
R/W
0
0
Disables unprivileged software access to the SWTRIG register.
1
Enables unprivileged software access to the SWTRIG register
(see page 138).
Thread State Control
Value Description
0
The processor can enter Thread mode only when no exception
is active.
1
The processor can enter Thread mode from any level under the
control of an EXC_RETURN value (see “Exception
Return” on page 103 for more information).
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Register 36: System Handler Priority 1 (SYSPRI1), offset 0xD18
Note:
This register can only be accessed from privileged mode.
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory
management fault exception handlers. This register is byte-accessible.
System Handler Priority 1 (SYSPRI1)
Base 0xE000.E000
Offset 0xD18
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
reserved
Type
Reset
RO
0
15
RO
0
RO
0
RO
0
RO
0
14
13
12
11
BUS
Type
Reset
R/W
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
10
9
8
7
reserved
R/W
0
RO
0
22
21
20
19
USAGE
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
6
5
4
3
MEM
RO
0
RO
0
R/W
0
R/W
0
18
17
16
RO
0
RO
0
RO
0
2
1
0
RO
0
RO
0
reserved
reserved
R/W
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21
USAGE
R/W
0x0
Usage Fault Priority
This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
20:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13
BUS
R/W
0x0
Bus Fault Priority
This field configures the priority level of the bus fault. Configurable priority
values are in the range 0-7, with lower values having higher priority.
12:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
MEM
R/W
0x0
Memory Management Fault Priority
This field configures the priority level of the memory management fault.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
4:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 37: System Handler Priority 2 (SYSPRI2), offset 0xD1C
Note:
This register can only be accessed from privileged mode.
The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is
byte-accessible.
System Handler Priority 2 (SYSPRI2)
Base 0xE000.E000
Offset 0xD1C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
SVC
Type
Reset
22
21
20
19
18
17
16
reserved
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:29
SVC
R/W
0x0
RO
0
Description
SVCall Priority
This field configures the priority level of SVCall. Configurable priority
values are in the range 0-7, with lower values having higher priority.
28:0
reserved
RO
0x000.0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 38: System Handler Priority 3 (SYSPRI3), offset 0xD20
Note:
This register can only be accessed from privileged mode.
The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV
handlers. This register is byte-accessible.
System Handler Priority 3 (SYSPRI3)
Base 0xE000.E000
Offset 0xD20
Type R/W, reset 0x0000.0000
31
30
29
28
27
TICK
Type
Reset
26
25
24
23
reserved
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
15
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
22
21
20
19
PENDSV
R/W
0
R/W
0
RO
0
RO
0
6
5
4
3
DEBUG
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:29
TICK
R/W
0x0
RO
0
R/W
0
R/W
0
18
17
16
RO
0
RO
0
RO
0
2
1
0
RO
0
RO
0
reserved
reserved
R/W
0
RO
0
RO
0
RO
0
Description
SysTick Exception Priority
This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
28:24
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21
PENDSV
R/W
0x0
PendSV Priority
This field configures the priority level of PendSV. Configurable priority
values are in the range 0-7, with lower values having higher priority.
20:8
reserved
RO
0x000
7:5
DEBUG
R/W
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Debug Priority
This field configures the priority level of Debug. Configurable priority
values are in the range 0-7, with lower values having higher priority.
4:0
reserved
RO
0x0.0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 39: System Handler Control and State (SYSHNDCTRL), offset 0xD24
Note:
This register can only be accessed from privileged mode.
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the
usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status
of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as
a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS
kernel can write to the active bits to perform a context switch that changes the current exception
type.
Caution – Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure software that writes
to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modified after enabling the system handlers, a
read-modify-write procedure must be used to ensure that only the required bit is modified.
System Handler Control and State (SYSHNDCTRL)
Base 0xE000.E000
Offset 0xD24
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
SVC
BUSP
MEMP
USAGEP
R/W
0
R/W
0
R/W
0
R/W
0
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
USAGE
BUS
MEM
R/W
0
R/W
0
R/W
0
10
9
8
7
6
5
4
3
2
1
0
TICK
PNDSV
reserved
MON
SVCA
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
USGA
reserved
BUSA
MEMA
R/W
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
Type
Reset
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:19
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
18
USAGE
R/W
0
Usage Fault Enable
Value Description
17
BUS
R/W
0
0
Disables the usage fault exception.
1
Enables the usage fault exception.
Bus Fault Enable
Value Description
0
Disables the bus fault exception.
1
Enables the bus fault exception.
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Bit/Field
Name
Type
Reset
16
MEM
R/W
0
Description
Memory Management Fault Enable
Value Description
15
SVC
R/W
0
0
Disables the memory management fault exception.
1
Enables the memory management fault exception.
SVC Call Pending
Value Description
0
An SVC call exception is not pending.
1
An SVC call exception is pending.
This bit can be modified to change the pending status of the SVC call
exception.
14
BUSP
R/W
0
Bus Fault Pending
Value Description
0
A bus fault exception is not pending.
1
A bus fault exception is pending.
This bit can be modified to change the pending status of the bus fault
exception.
13
MEMP
R/W
0
Memory Management Fault Pending
Value Description
0
A memory management fault exception is not pending.
1
A memory management fault exception is pending.
This bit can be modified to change the pending status of the memory
management fault exception.
12
USAGEP
R/W
0
Usage Fault Pending
Value Description
0
A usage fault exception is not pending.
1
A usage fault exception is pending.
This bit can be modified to change the pending status of the usage fault
exception.
11
TICK
R/W
0
SysTick Exception Active
Value Description
0
A SysTick exception is not active.
1
A SysTick exception is active.
This bit can be modified to change the active status of the SysTick
exception, however, see the Caution above before setting this bit.
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Bit/Field
Name
Type
Reset
10
PNDSV
R/W
0
Description
PendSV Exception Active
Value Description
0
A PendSV exception is not active.
1
A PendSV exception is active.
This bit can be modified to change the active status of the PendSV
exception, however, see the Caution above before setting this bit.
9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
MON
R/W
0
Debug Monitor Active
Value Description
7
SVCA
R/W
0
0
The Debug monitor is not active.
1
The Debug monitor is active.
SVC Call Active
Value Description
0
SVC call is not active.
1
SVC call is active.
This bit can be modified to change the active status of the SVC call
exception, however, see the Caution above before setting this bit.
6:4
reserved
RO
0x0
3
USGA
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Usage Fault Active
Value Description
0
Usage fault is not active.
1
Usage fault is active.
This bit can be modified to change the active status of the usage fault
exception, however, see the Caution above before setting this bit.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BUSA
R/W
0
Bus Fault Active
Value Description
0
Bus fault is not active.
1
Bus fault is active.
This bit can be modified to change the active status of the bus fault
exception, however, see the Caution above before setting this bit.
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Bit/Field
Name
Type
Reset
0
MEMA
R/W
0
Description
Memory Management Fault Active
Value Description
0
Memory management fault is not active.
1
Memory management fault is active.
This bit can be modified to change the active status of the memory
management fault exception, however, see the Caution above before
setting this bit.
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Register 40: Configurable Fault Status (FAULTSTAT), offset 0xD28
Note:
This register can only be accessed from privileged mode.
The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage
fault. Each of these functions is assigned to a subregister as follows:
■ Usage Fault Status (UFAULTSTAT), bits 31:16
■ Bus Fault Status (BFAULTSTAT), bits 15:8
■ Memory Management Fault Status (MFAULTSTAT), bits 7:0
FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:
■
■
■
■
■
The complete FAULTSTAT register, with a word access to offset 0xD28
The MFAULTSTAT, with a byte access to offset 0xD28
The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
The BFAULTSTAT, with a byte access to offset 0xD29
The UFAULTSTAT, with a halfword access to offset 0xD2A
Bits are cleared by writing a 1 to them.
In a fault handler, the true faulting address can be determined by:
1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.
2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.
Software must follow this sequence because another higher priority exception might change the
MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMADDR or FAULTADDR value.
Configurable Fault Status (FAULTSTAT)
Base 0xE000.E000
Offset 0xD28
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
reserved
Type
Reset
RO
0
RO
0
RO
0
15
14
13
BFARV
Type
Reset
R/W1C
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
DIV0
UNALIGN
R/W1C
0
R/W1C
0
23
22
21
20
reserved
RO
0
RO
0
RO
0
6
5
12
11
10
9
8
7
BSTKE
BUSTKE
IMPRE
PRECISE
IBUS
MMARV
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
RO
0
RO
0
RO
0
4
MSTKE
R/W1C
0
19
18
17
16
NOCP
INVPC
INVSTAT
UNDEF
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
3
2
MUSTKE reserved
R/W1C
0
RO
0
1
0
DERR
IERR
R/W1C
0
R/W1C
0
Bit/Field
Name
Type
Reset
Description
31:26
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
25
DIV0
R/W1C
0
Description
Divide-by-Zero Usage Fault
Value Description
0
No divide-by-zero fault has occurred, or divide-by-zero trapping
is not enabled.
1
The processor has executed an SDIV or UDIV instruction with
a divisor of 0.
When this bit is set, the PC value stacked for the exception return points
to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register (see page 150).
This bit is cleared by writing a 1 to it.
24
UNALIGN
R/W1C
0
Unaligned Access Usage Fault
Value Description
0
No unaligned access fault has occurred, or unaligned access
trapping is not enabled.
1
The processor has made an unaligned memory access.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting the UNALIGNED bit
in the CFGCTRL register (see page 150).
This bit is cleared by writing a 1 to it.
23:20
reserved
RO
0x00
19
NOCP
R/W1C
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
No Coprocessor Usage Fault
Value Description
0
A usage fault has not been caused by attempting to access a
coprocessor.
1
The processor has attempted to access a coprocessor.
This bit is cleared by writing a 1 to it.
18
INVPC
R/W1C
0
Invalid PC Load Usage Fault
Value Description
0
A usage fault has not been caused by attempting to load an
invalid PC value.
1
The processor has attempted an illegal load of EXC_RETURN
to the PC as a result of an invalid context or an invalid
EXC_RETURN value.
When this bit is set, the PC value stacked for the exception return points
to the instruction that tried to perform the illegal load of the PC.
This bit is cleared by writing a 1 to it.
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Bit/Field
Name
Type
Reset
17
INVSTAT
R/W1C
0
Description
Invalid State Usage Fault
Value Description
0
A usage fault has not been caused by an invalid state.
1
The processor has attempted to execute an instruction that
makes illegal use of the EPSR register.
When this bit is set, the PC value stacked for the exception return points
to the instruction that attempted the illegal use of the Execution
Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
This bit is cleared by writing a 1 to it.
16
UNDEF
R/W1C
0
Undefined Instruction Usage Fault
Value Description
0
A usage fault has not been caused by an undefined instruction.
1
The processor has attempted to execute an undefined
instruction.
When this bit is set, the PC value stacked for the exception return points
to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
This bit is cleared by writing a 1 to it.
15
BFARV
R/W1C
0
Bus Fault Address Register Valid
Value Description
0
The value in the Bus Fault Address (FAULTADDR) register
is not a valid fault address.
1
The FAULTADDR register is holding a valid fault address.
This bit is set after a bus fault, where the address is known. Other faults
can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority,
the hard fault handler must clear this bit. This action prevents problems
if returning to a stacked active bus fault handler whose FAULTADDR
register value has been overwritten.
This bit is cleared by writing a 1 to it.
14:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
12
BSTKE
R/W1C
0
Description
Stack Bus Fault
Value Description
0
No bus fault has occurred on stacking for exception entry.
1
Stacking for an exception entry has caused one or more bus
faults.
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the FAULTADDR register.
This bit is cleared by writing a 1 to it.
11
BUSTKE
R/W1C
0
Unstack Bus Fault
Value Description
0
No bus fault has occurred on unstacking for a return from
exception.
1
Unstacking for a return from exception has caused one or more
bus faults.
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
FAULTADDR register.
This bit is cleared by writing a 1 to it.
10
IMPRE
R/W1C
0
Imprecise Data Bus Error
Value Description
0
An imprecise data bus error has not occurred.
1
A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This fault is asynchronous. Therefore, if the fault is detected when the
priority of the current process is higher than the bus fault priority, the
bus fault becomes pending and becomes active only when the processor
returns from all higher-priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects that both the IMPRE bit is set and one of the precise fault status
bits is set.
This bit is cleared by writing a 1 to it.
9
PRECISE
R/W1C
0
Precise Data Bus Error
Value Description
0
A precise data bus error has not occurred.
1
A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the
fault.
When this bit is set, the fault address is written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
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Bit/Field
Name
Type
Reset
8
IBUS
R/W1C
0
Description
Instruction Bus Error
Value Description
0
An instruction bus error has not occurred.
1
An instruction bus error has occurred.
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
7
MMARV
R/W1C
0
Memory Management Fault Address Register Valid
Value Description
0
The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
1
The MMADDR register is holding a valid fault address.
If a memory management fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
6:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
MSTKE
R/W1C
0
Stack Access Violation
Value Description
0
No memory management fault has occurred on stacking for
exception entry.
1
Stacking for an exception entry has caused one or more access
violations.
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
This bit is cleared by writing a 1 to it.
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Bit/Field
Name
Type
Reset
3
MUSTKE
R/W1C
0
Description
Unstack Access Violation
Value Description
0
No memory management fault has occurred on unstacking for
a return from exception.
1
Unstacking for a return from exception has caused one or more
access violations.
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
MMADDR register.
This bit is cleared by writing a 1 to it.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
DERR
R/W1C
0
Data Access Violation
Value Description
0
A data access violation has not occurred.
1
The processor attempted a load or store at a location that does
not permit the operation.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
written to the MMADDR register.
This bit is cleared by writing a 1 to it.
0
IERR
R/W1C
0
Instruction Access Violation
Value Description
0
An instruction access violation has not occurred.
1
The processor attempted an instruction fetch from a location
that does not permit execution.
This fault occurs on any access to an XN region, even when the MPU
is disabled or not present.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
not written to the MMADDR register.
This bit is cleared by writing a 1 to it.
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Register 41: Hard Fault Status (HFAULTSTAT), offset 0xD2C
Note:
This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.
Hard Fault Status (HFAULTSTAT)
Base 0xE000.E000
Offset 0xD2C
Type R/W1C, reset 0x0000.0000
Type
Reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DBG
FORCED
R/W1C
0
R/W1C
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VECT
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
RO
0
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31
DBG
R/W1C
0
Description
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.
30
FORCED
R/W1C
0
Forced Hard Fault
Value Description
0
No forced hard fault has occurred.
1
A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
This bit is cleared by writing a 1 to it.
29:2
reserved
RO
0x00
1
VECT
R/W1C
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Vector Table Read Fault
Value Description
0
No bus fault has occurred on a vector table read.
1
A bus fault occurred on a vector table read.
This error is always handled by the hard fault handler.
When this bit is set, the PC value stacked for the exception return points
to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 42: Memory Management Fault Address (MMADDR), offset 0xD34
Note:
This register can only be accessed from privileged mode.
The MMADDR register contains the address of the location that generated a memory management
fault. When an unaligned access faults, the address in the MMADDR register is the actual address
that faulted. Because a single read or write instruction can be split into multiple aligned accesses,
the fault address can be any address in the range of the requested access size. Bits in the Memory
Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether
the value in the MMADDR register is valid (see page 159).
Memory Management Fault Address (MMADDR)
Base 0xE000.E000
Offset 0xD34
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
31:0
ADDR
R/W
-
R/W
-
Description
Fault Address
When the MMARV bit of MFAULTSTAT is set, this field holds the address
of the location that generated the memory management fault.
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Register 43: Bus Fault Address (FAULTADDR), offset 0xD38
Note:
This register can only be accessed from privileged mode.
The FAULTADDR register contains the address of the location that generated a bus fault. When
an unaligned access faults, the address in the FAULTADDR register is the one requested by the
instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid
(see page 159).
Bus Fault Address (FAULTADDR)
Base 0xE000.E000
Offset 0xD38
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
31:0
ADDR
R/W
-
R/W
-
Description
Fault Address
When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the
address of the location that generated the bus fault.
3.6
Memory Protection Unit (MPU) Register Descriptions
This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by
address offset.
The MPU registers can only be accessed from privileged mode.
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Register 44: MPU Type (MPUTYPE), offset 0xD90
Note:
This register can only be accessed from privileged mode.
The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it
supports.
MPU Type (MPUTYPE)
Base 0xE000.E000
Offset 0xD90
Type RO, reset 0x0000.0800
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
DREGION
Type
Reset
RO
0
RO
0
RO
0
RO
0
19
18
17
16
RO
0
IREGION
RO
0
RO
0
RO
0
RO
0
4
3
2
1
reserved
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
SEPARATE
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:16
IREGION
RO
0x00
Number of I Regions
This field indicates the number of supported MPU instruction regions.
This field always contains 0x00. The MPU memory map is unified and
is described by the DREGION field.
15:8
DREGION
RO
0x08
Number of D Regions
Value Description
0x08 Indicates there are eight supported MPU data regions.
7:1
reserved
RO
0x00
0
SEPARATE
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Separate or Unified MPU
Value Description
0
Indicates the MPU is unified.
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Register 45: MPU Control (MPUCTRL), offset 0xD94
Note:
This register can only be accessed from privileged mode.
The MPUCTRL register enables the MPU, enables the default memory map background region,
and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask
Register (FAULTMASK) escalated handlers.
When the ENABLE and PRIVDEFEN bits are both set:
■ For privileged accesses, the default memory map is as described in “Memory Model” on page 87.
Any access by privileged software that does not address an enabled memory region behaves
as defined by the default memory map.
■ Any access by unprivileged software that does not address an enabled memory region causes
a memory management fault.
Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless
of the value of the ENABLE bit.
When the ENABLE bit is set, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled,
then only privileged software can operate.
When the ENABLE bit is clear, the system uses the default memory map, which has the same
memory attributes as if the MPU is not implemented (see Table 2-5 on page 90 for more information).
The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always
permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set.
Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for
an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or
NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when
operating with these two priorities.
MPU Control (MPUCTRL)
Base 0xE000.E000
Offset 0xD94
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
PRIVDEFEN HFNMIENA
R/W
0
R/W
0
ENABLE
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
2
PRIVDEFEN
R/W
0
Description
MPU Default Region
This bit enables privileged software access to the default memory map.
Value Description
0
If the MPU is enabled, this bit disables use of the default memory
map. Any memory access to a location not covered by any
enabled region causes a fault.
1
If the MPU is enabled, this bit enables use of the default memory
map as a background region for privileged software accesses.
When this bit is set, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this default
map.
If the MPU is disabled, the processor ignores this bit.
1
HFNMIENA
R/W
0
MPU Enabled During Faults
This bit controls the operation of the MPU during hard fault, NMI, and
FAULTMASK handlers.
Value Description
0
The MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit.
1
The MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.
When the MPU is disabled and this bit is set, the resulting behavior is
unpredictable.
0
ENABLE
R/W
0
MPU Enable
Value Description
0
The MPU is disabled.
1
The MPU is enabled.
When the MPU is disabled and the HFNMIENA bit is set, the resulting
behavior is unpredictable.
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Register 46: MPU Region Number (MPUNUMBER), offset 0xD98
Note:
This register can only be accessed from privileged mode.
The MPUNUMBER register selects which memory region is referenced by the MPU Region Base
Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the
required region number should be written to this register before accessing the MPUBASE or the
MPUATTR register. However, the region number can be changed by writing to the MPUBASE
register with the VALID bit set (see page 172). This write updates the value of the REGION field.
MPU Region Number (MPUNUMBER)
Base 0xE000.E000
Offset 0xD98
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2:0
NUMBER
R/W
0x0
NUMBER
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MPU Region to Access
This field indicates the MPU region referenced by the MPUBASE and
MPUATTR registers. The MPU supports eight memory regions.
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Register 47: MPU Region Base Address (MPUBASE), offset 0xD9C
Register 48: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4
Register 49: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC
Register 50: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4
Note:
This register can only be accessed from privileged mode.
The MPUBASE register defines the base address of the MPU region selected by the MPU Region
Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To
change the current region number and update the MPUNUMBER register, write the MPUBASE
register with the VALID bit set.
The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size,
as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines
the value of N where:
N = Log2(Region size in bytes)
If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In
this case, the region occupies the complete memory map, and the base address is 0x0000.0000.
The base address is aligned to the size of the region. For example, a 64-KB region must be aligned
on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000.
MPU Region Base Address (MPUBASE)
Base 0xE000.E000
Offset 0xD9C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
VALID
reserved
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
WO
0
RO
0
ADDR
Type
Reset
ADDR
Type
Reset
R/W
0
Bit/Field
Name
Type
Reset
31:5
ADDR
R/W
0x0000.000
REGION
R/W
0
R/W
0
R/W
0
Description
Base Address Mask
Bits 31:N in this field contain the region base address. The value of N
depends on the region size, as shown above. The remaining bits (N-1):5
are reserved.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
4
VALID
WO
0
Description
Region Number Valid
Value Description
0
The MPUNUMBER register is not changed and the processor
updates the base address for the region specified in the
MPUNUMBER register and ignores the value of the REGION
field.
1
The MPUNUMBER register is updated with the value of the
REGION field and the base address is updated for the region
specified in the REGION field.
This bit is always read as 0.
3
reserved
RO
0
2:0
REGION
R/W
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Region Number
On a write, contains the value to be written to the MPUNUMBER register.
On a read, returns the current region number in the MPUNUMBER
register.
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Register 51: MPU Region Attribute and Size (MPUATTR), offset 0xDA0
Register 52: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
Register 53: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
Register 54: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
Note:
This register can only be accessed from privileged mode.
The MPUATTR register defines the region size and memory attributes of the MPU region specified
by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant
halfword holding the region attributes and the least-significant halfword holds the region size and
the region and subregion enable bits.
The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register
as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table
3-9 on page 174 gives example SIZE values with the corresponding region size and value of N in
the MPU Region Base Address (MPUBASE) register.
Table 3-9. Example SIZE Field Values
a
SIZE Encoding
Region Size
Value of N
Note
00100b (0x4)
32 B
5
Minimum permitted size
01001b (0x9)
1 KB
10
-
10011b (0x13)
1 MB
20
-
11101b (0x1D)
1 GB
30
-
11111b (0x1F)
4 GB
No valid ADDR field in MPUBASE; the Maximum possible size
region occupies the complete
memory map.
a. Refers to the N parameter in the MPUBASE register (see page 172).
MPU Region Attribute and Size (MPUATTR)
Base 0xE000.E000
Offset 0xDA0
Type R/W, reset 0x0000.0000
31
30
29
28
27
reserved
Type
Reset
26
25
24
23
AP
21
reserved
20
19
18
TEX
17
16
XN
reserved
S
C
B
RO
0
RO
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
SRD
Type
Reset
22
reserved
SIZE
174
R/W
0
ENABLE
R/W
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Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
XN
R/W
0
Instruction Access Disable
Value Description
0
Instruction fetches are enabled.
1
Instruction fetches are disabled.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26:24
AP
R/W
0
Access Privilege
For information on using this bit field, see Table 3-5 on page 118.
23:22
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21:19
TEX
R/W
0x0
Type Extension Mask
For information on using this bit field, see Table 3-3 on page 117.
18
S
R/W
0
Shareable
For information on using this bit, see Table 3-3 on page 117.
17
C
R/W
0
Cacheable
For information on using this bit, see Table 3-3 on page 117.
16
B
R/W
0
Bufferable
For information on using this bit, see Table 3-3 on page 117.
15:8
SRD
R/W
0x00
Subregion Disable Bits
Value Description
0
The corresponding subregion is enabled.
1
The corresponding subregion is disabled.
Region sizes of 128 bytes and less do not support subregions. When
writing the attributes for such a region, configure the SRD field as 0x00.
See the section called “Subregions” on page 116 for more information.
7:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:1
SIZE
R/W
0x0
Region Size Mask
The SIZE field defines the size of the MPU memory region specified by
the MPUNUMBER register. Refer to Table 3-9 on page 174 for more
information.
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Bit/Field
Name
Type
Reset
0
ENABLE
R/W
0
Description
Region Enable
Value Description
0
The region is disabled.
1
The region is enabled.
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4
JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into
the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
®
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core
by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM
TDO output while Stellaris JTAG instructions select the Stellaris TDO output. The multiplexer is
controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM,
Stellaris, and unimplemented JTAG instructions.
The Stellaris JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM
JTAG controller.
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4.1
Block Diagram
Figure 4-1. JTAG Module Block Diagram
TCK
TMS
TAP Controller
TDI
Instruction Register (IR)
BYPASS Data Register
TDO
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
Cortex-M3
Debug
Port
4.2
Signal Description
The following table lists the external signals of the JTAG/SWD controller and describes the function
of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however
note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals
are under commit protection and require a special process to be configured as GPIOs, see “Commit
Control” on page 435. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO
pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 450) is set to choose the JTAG/SWD function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 468) to assign the JTAG/SWD controller signals to the specified GPIO
port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 427.
Table 4-1. JTAG_SWD_SWO Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
SWCLK
80
PC0 (3)
I
TTL
JTAG/SWD CLK.
SWDIO
79
PC1 (3)
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
PC3 (3)
O
TTL
JTAG TDO and SWO.
TCK
80
PC0 (3)
I
TTL
JTAG/SWD CLK.
TDI
78
PC2 (3)
I
TTL
JTAG TDI.
TDO
77
PC3 (3)
O
TTL
JTAG TDO and SWO.
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Table 4-1. JTAG_SWD_SWO Signals (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
79
TMS
a
Pin Type
Buffer Type
I
TTL
PC1 (3)
Description
JTAG TMS and SWDIO.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 4-2. JTAG_SWD_SWO Signals (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
A9
PC0 (3)
I
TTL
JTAG/SWD CLK.
SWDIO
B9
PC1 (3)
I/O
TTL
JTAG TMS and SWDIO.
SWO
A10
PC3 (3)
O
TTL
JTAG TDO and SWO.
TCK
A9
PC0 (3)
I
TTL
JTAG/SWD CLK.
SWCLK
TDI
B8
PC2 (3)
I
TTL
JTAG TDI.
TDO
A10
PC3 (3)
O
TTL
JTAG TDO and SWO.
TMS
B9
PC1 (3)
I
TTL
JTAG TMS and SWDIO.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
4.3
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 178. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
The current state of the TAP controller depends on the sequence of values captured on TMS at the
rising edge of TCK. The TAP controller determines when the serial shift chains capture new data,
shift data from TDI towards TDO, and update the parallel load registers. The current state of the
TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register
(DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 4-4 on page 185 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 1223 for JTAG timing diagrams.
Note:
4.3.1
Of all the possible reset sources, only Power-On reset (POR) and the assertion of the RST
input have any effect on the JTAG module. The pin configurations are reset by both the
RST input and POR, whereas the internal JTAG logic is only reset with POR. See “Reset
Sources” on page 190 for more information on reset.
JTAG Interface Pins
The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their
associated state after a power-on reset or reset caused by the RST input are given in Table 4-3.
Detailed information on each pin follows. Refer to “General-Purpose Input/Outputs
(GPIOs)” on page 427 for information on how to reprogram the configuration of these pins.
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Table 4-3. JTAG Port Pins State after Power-On Reset or RST assertion
4.3.1.1
Pin Name
Data Direction
Internal Pull-Up
Internal Pull-Down
Drive Strength
Drive Value
TCK
Input
Enabled
Disabled
N/A
N/A
TMS
Input
Enabled
Disabled
N/A
N/A
TDI
Input
Enabled
Disabled
N/A
N/A
TDO
Output
Enabled
Disabled
2-mA driver
High-Z
Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks and to ensure that multiple JTAG TAP controllers that
are daisy-chained together can synchronously communicate serial test data between components.
During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When
necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0
or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data
Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset, assuring that no clocking
occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors
can be turned off to save internal power as long as the TCK pin is constantly being driven by an
external source (see page 456 and page 458).
4.3.1.2
Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be
entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1
expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
module and associated registers are reset to their default values. This procedure should be performed
to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety
in Figure 4-2 on page 181.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost (see page 456).
4.3.1.3
Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, may present this data to the proper shift register chain. Because the TDI pin is sampled
on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the
falling edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost (see page 456).
4.3.1.4
Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
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chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset, assuring that the pin
remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states (see page 456 and page 458).
4.3.2
JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 4-2. The TAP controller state machine
is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset
the JTAG module after the microcontroller has been powered on, the TMS input must be held HIGH
for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting
the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in
data, or idle during extended testing sequences. For detailed information on the function of the TAP
controller and the operations that occur in each state, please refer to IEEE Standard 1149.1.
Figure 4-2. Test Access Port State Machine
Test Logic Reset
1
0
Run Test Idle
0
Select DR Scan
1
Select IR Scan
1
0
1
Capture DR
1
Capture IR
0
0
Shift DR
Shift IR
0
1
Exit 1 DR
Exit 1 IR
1
Pause IR
0
1
Exit 2 DR
0
1
0
Exit 2 IR
1
1
Update DR
4.3.3
1
0
Pause DR
1
0
1
0
0
1
0
0
Update IR
1
0
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
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this information to be shifted out on TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 185.
4.3.4
Operational Considerations
Certain operational parameters must be considered when using the JTAG module. Because the
JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these
pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes is described below.
4.3.4.1
GPIO Functionality
When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0]
set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0]
set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors
(PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the
alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select
(GPIOAFSEL) register) on the JTAG/SWD pins. See page 450, page 456, page 458, and page 461.
It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in
the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins
to their GPIO functionality, the debugger may not have enough time to connect and halt the controller
before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part.
This issue can be avoided with a software routine that restores JTAG functionality based on an external
or software trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD
pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 450), GPIO Pull Up Select (GPIOPUR) register (see page 456), GPIO Pull-Down
Select (GPIOPDR) register (see page 458), and GPIO Digital Enable (GPIODEN) register (see
page 461) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 463)
has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 464)
have been set.
4.3.4.2
Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
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4.3.4.3
Recovering a "Locked" Microcontroller
Note:
Performing the sequence below restores the non-volatile registers discussed in “Non-Volatile
Register Programming” on page 327 to their factory default values. The mass erase of the
Flash memory caused by the sequence below occurs prior to the non-volatile registers
being restored.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug port unlock sequence that can be used to recover the
microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while
holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence
is:
1. Assert and hold the RST signal.
2. Apply power to the device.
3. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD
Switching” on page 184.
4. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG
Switching” on page 184.
5. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
6. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
7. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
8. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
9. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
10. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
11. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
12. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
13. Release the RST signal.
14. Wait 400 ms.
15. Power-cycle the microcontroller.
4.3.4.4
ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued
before the SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
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Stepping through this sequence of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Debug Interface V5 Architecture Specification.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This instance is the only one
where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to
the low probability of this sequence occurring during normal operation of the TAP controller, it should
not affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the microcontroller. The 16-bit
TMS/SWDIO command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted
LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The
complete switch sequence should consist of the following transactions on the TCK/SWCLK and
TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.
2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS/SWDIO.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in SWD mode before sending the switch sequence, the SWD goes into the line reset state.
To verify that the Debug Access Port (DAP) has switched to the Serial Wire Debug (SWD) operating
mode, perform a SWD READID operation. The ID value can be compared against the device's
known ID to verify the switch.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch command to the microcontroller. The 16-bit TMS/SWDIO
command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first.
This command can also be represented as 0xE73C when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.
2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS/SWDIO.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in JTAG mode before sending the switch sequence, the JTAG goes into the Test Logic Reset
state.
To verify that the Debug Access Port (DAP) has switched to the JTAG operating mode, set the
JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The
DR value can be compared against the device's known IDCODE to verify the switch.
4.4
Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
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application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. To return the pins to their JTAG functions,
enable the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register.
In addition to enabling the alternate functions, any other changes to the GPIO pad configurations
on the four JTAG pins (PC[3:0]) should be returned to their default settings.
4.5
Register Descriptions
The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are
not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within
the JTAG controller are all accessed serially through the TAP Controller. These registers include
the Instruction Register and the six Data Registers.
4.5.1
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated,
they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-4. A
detailed explanation of each instruction, along with its associated Data Register, follows.
Table 4-4. JTAG Instruction Register Commands
4.5.1.1
IR[3:0]
Instruction
Description
0x0
EXTEST
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
0x1
INTEST
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
0x2
SAMPLE / PRELOAD
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
0x8
ABORT
Shifts data into the ARM Debug Port Abort Register.
0xA
DPACC
Shifts data into and out of the ARM DP Access Register.
0xB
APACC
Shifts data into and out of the ARM AC Access Register.
0xE
IDCODE
Loads manufacturing information defined by the IEEE Standard 1149.1 into
the IDCODE chain and shifts it out.
0xF
BYPASS
Connects TDI to TDO through a single Shift Register chain.
All Others
Reserved
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. With tests
that drive known values out of the controller, this instruction can be used to verify connectivity. While
the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can
be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
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4.5.1.2
INTEST Instruction
The INTEST instruction is not associated with its own Data Register chain. Instead, the INTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. With tests that
drive known values into the controller, this instruction can be used for testing. It is important to note
that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable.
While the INTEST instruction is present in the Instruction Register, the Boundary Scan Data Register
can be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
4.5.1.3
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. See “Boundary Scan Data
Register” on page 188 for more information.
4.5.1.4
ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. See the “ABORT Data Register” on page 188 for more information.
4.5.1.5
DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. See “DPACC Data
Register” on page 188 for more information.
4.5.1.6
APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
See “APACC Data Register” on page 188 for more information.
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4.5.1.7
IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure input and output data streams. IDCODE is the default instruction loaded into the JTAG
Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is
entered. See “IDCODE Data Register” on page 187 for more information.
4.5.1.8
BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 187 for more
information.
4.5.2
Data Registers
The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE,
BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections.
4.5.2.1
IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-3. The standard requires that every JTAG-compliant microcontroller implement either the
IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically
configure themselves to work correctly with the Cortex-M3 during debug.
Figure 4-3. IDCODE Register Format
31
TDI
4.5.2.2
28 27
12 11
Version
Part Number
1 0
Manufacturer ID
1
TDO
BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-4. The standard requires that every JTAG-compliant microcontroller implement either the
BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
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Figure 4-4. BYPASS Register Format
0
0
TDI
4.5.2.3
TDO
Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting
with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each
GPIO pin has three associated digital signals that are included in the chain. These signals are input,
output, and output enable, and are arranged in that order as shown in the figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. The EXTEST instruction forces data out of the controller,
and the INTEST instruction forces data into the controller.
Figure 4-5. Boundary Scan Register Format
TDI
I
N
O
U
T
O
E
...
1st GPIO
4.5.2.4
I
N
O
U
T
mth GPIO
O
E
I
N
O
U
T
(m+1)th GPIO
O
E
...
I
N
O
U
T
O
E
TDO
GPIO nth
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.5.2.5
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.5.2.6
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
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5
System Control
System control configures the overall operation of the device and provides information about the
device. Configurable features include reset control, NMI operation, power control, clock control, and
low-power modes.
5.1
Signal Description
The following table lists the external signals of the System Control module and describes the function
of each. The NMI signal is the alternate function for the GPIO PB7 signal and functions as a GPIO
after reset. PB7 is under commit protection and requires a special process to be configured as any
alternate function or to subsequently return to the GPIO function, see “Commit Control” on page 435.
The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the
NMI signal. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 450)
should be set to choose the NMI function. The number in parentheses is the encoding that must be
programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 468) to assign
the NMI signal to the specified GPIO port pin. For more information on configuring GPIOs, see
“General-Purpose Input/Outputs (GPIOs)” on page 427. The remaining signals (with the word "fixed"
in the Pin Mux/Pin Assignment column) have a fixed pin assignment and function.
Table 5-1. System Control & Clocks Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
NMI
89
PB7 (4)
I
TTL
Non-maskable interrupt.
OSC0
48
fixed
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
49
fixed
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
64
fixed
I
TTL
System reset input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 5-2. System Control & Clocks Signals (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
NMI
A8
PB7 (4)
I
TTL
Non-maskable interrupt.
OSC0
L11
fixed
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
M11
fixed
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
H11
fixed
I
TTL
System reset input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
5.2
Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 190
■ Local control, such as reset (see “Reset Control” on page 190), power (see “Power
Control” on page 195) and clock control (see “Clock Control” on page 196)
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■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 203
5.2.1
Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, Flash memory size, and other features. See the DID0 (page 208), DID1
(page 237), DC0-DC9 (page 239) and NVMSTAT (page 259) registers.
5.2.2
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
5.2.2.1
Reset Sources
The LM3S9U90 microcontroller has six sources of reset:
1. Power-on reset (POR) (see page 191).
2. External reset input pin (RST) assertion (see page 191).
3. Internal brown-out (BOR) detector (see page 193).
4. Software-initiated reset (with the software reset registers) (see page 193).
5. A watchdog timer reset condition violation (see page 194).
6. MOSC failure (see page 195).
Table 5-3 provides a summary of results of the various reset operations.
Table 5-3. Reset Sources
Core Reset?
JTAG Reset?
On-Chip Peripherals Reset?
Power-On Reset
Reset Source
Yes
Yes
Yes
RST
Yes
Yes
Yes
Brown-Out Reset
Yes
Yes
Yes
Software System Request
Reset using the SYSRESREQ
bit in the APINT register.
Yes
Yes
Yes
Software System Request
Reset using the VECTRESET
bit in the APINT register.
Yes
No
No
Software Peripheral Reset
No
Yes
Yes
Watchdog Reset
Yes
Yes
Yes
MOSC Failure Reset
Yes
Yes
Yes
a
a. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
or an external reset is the cause, and then all the other bits in the RESC register are cleared except
for the POR or EXT indicator.
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At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM
Boot Loader or the application in Flash memory by using any GPIO signal as configured in the Boot
Configuration (BOOTCFG) register.
At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always
executed. The boot sequence executed from ROM is as follows:
1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is
mapped to address 0x0.
2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is
compared with the specified polarity. If the status matches the specified polarity, the ROM is
mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader.
3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and
if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and
execution continues out of the ROM Boot Loader.
4. If there is valid data at address 0x0000.0004, the stack pointer (SP) is loaded from Flash memory
at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004.
The user application begins executing.
For example, if the BOOTCFG register is written and committed with the value of 0x0000.3C01,
then PB7 is examined at reset to determine if the ROM Boot Loader should be executed. If PB7 is
Low, the core unconditionally begins executing the ROM boot loader. If PB7 is High, then the
application in Flash memory is executed if the reset vector at location 0x0000.0004 is not
0xFFFF.FFFF. Otherwise, the ROM boot loader is executed.
5.2.2.2
Power-On Reset (POR)
The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (VTH). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete (see “Power and Brown-Out” on page 1225). For
applications that require the use of an external reset signal to hold the microcontroller in reset longer
than the internal POR, the RST input may be used as discussed in “External RST Pin” on page 191.
The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller and when the
microcontroller wakes from hibernation. The Power-On Reset timing is shown in Figure
25-4 on page 1225.
5.2.2.3
External RST Pin
Note:
It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
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If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 192.
Figure 5-1. Basic RST Configuration
VDD
Stellaris®
RPU
RST
RPU = 0 to 100 kΩ
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 177). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted
(see “Reset” on page 1226).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 192.
Figure 5-2. External Circuitry to Extend Power-On Reset
VDD
Stellaris®
RPU
RST
C1
RPU = 1 kΩ to 100 kΩ
C1 = 1 nF to 10 µF
If the application requires the use of an external reset switch, Figure 5-3 on page 193 shows the
proper circuitry to use.
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Figure 5-3. Reset Circuit Controlled by Switch
VDD
Stellaris®
RPU
RST
C1
RS
Typical RPU = 10 kΩ
Typical RS = 470 Ω
C1 = 10 nF
The RPU and C1 components define the power-on delay.
The external reset timing is shown in Figure 25-7 on page 1226.
5.2.2.4
Brown-Out Reset (BOR)
The microcontroller provides a brown-out detection circuit that triggers if the power supply (VDD)
drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system
may generate an interrupt or a system reset. The default condition is to reset the microcontroller.
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset; if BORIOR is clear, an interrupt is generated. When a Brown-out condition occurs during a
Flash PROGRAM or ERASE operation, a full system reset is always triggered without regard to the
setting in the PBORCTL register.
The brown-out reset sequence is as follows:
1. When VDD drops below VBTH, an internal BOR condition is set.
2. If the BOR condition exists, an internal reset is asserted.
3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer,
the initial program counter, the first instruction designated by the program counter, and begins
execution.
4. The internal BOR condition is reset after 500 µs to prevent another BOR condition from being
set before software has a chance to investigate the original cause.
The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and
the reset is held active until the proper VDD level is restored. The RESC register can be examined
in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus
allowing software to determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 25-5 on page 1225.
5.2.2.5
Software Reset
Software can reset a specific peripheral or generate a reset to the entire microcontroller.
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Peripherals can be individually reset by software via three registers that control reset signals to each
on-chip peripheral (see the SRCRn registers, page 286). If the bit position corresponding to a
peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers
is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see
“System Control” on page 203).
The entire microcontroller, including the core, can be reset by software by setting the SYSRESREQ
bit in the Application Interrupt and Reset Control (APINT) register. The software-initiated system
reset sequence is as follows:
1. A software microcontroller reset is initiated by setting the SYSRESREQ bit.
2. An internal reset is asserted.
3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.
The core only can be reset by software by setting the VECTRESET bit in the APINT register. The
software-initiated core reset sequence is as follows:
1. A core reset is initiated by setting the VECTRESET bit.
2. An internal reset is asserted.
3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.
The software-initiated system reset timing is shown in Figure 25-8 on page 1226.
5.2.2.6
Watchdog Timer Reset
The Watchdog Timer module's function is to prevent system hangs. The LM3S9U90 microcontroller
has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run
off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module
operates in the same manner except that because the PIOSC watchdog timer module is in a different
clock domain, register accesses must have a time delay between them. The watchdog timer can
be configured to generate an interrupt to the microcontroller on its first time-out and to generate a
reset on its second time-out.
After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of
the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If
the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal
has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog
timer reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the microcontroller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
For more information on the Watchdog Timer module, see “Watchdog Timers” on page 604.
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The watchdog reset timing is shown in Figure 25-9 on page 1227.
5.2.3
Non-Maskable Interrupt
The microcontroller has three sources of non-maskable interrupt (NMI):
■ The assertion of the NMI signal
■ A main oscillator verification error
■ The NMISET bit in the Interrupt Control and State (INTCTRL) register in the Cortex™-M3 (see
page 142).
Software must check the cause of the interrupt in order to distinguish among the sources.
5.2.3.1
NMI Pin
The NMI signal is the alternate function for GPIO port pin PB7. The alternate function must be
enabled in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose
Input/Outputs (GPIOs)” on page 427. Note that enabling the NMI alternate function requires the use
of the GPIO lock and commit function just like the GPIO port pins associated with JTAG/SWD
functionality, see page 464. The active sense of the NMI signal is High; asserting the enabled NMI
signal above VIH initiates the NMI interrupt sequence.
5.2.3.2
Main Oscillator Verification Failure
The LM3S9U90 microcontroller provides a main oscillator verification circuit that generates an error
condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is
enabled and a failure occurs, a power-on reset is generated and control is transferred to the NMI
handler. The NMI handler is used to address the main oscillator verification failure because the
necessary code can be removed from the general reset handler, speeding up reset processing. The
detection circuit is enabled by setting the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. The main oscillator verification error is indicated in the main oscillator fail status (MOSCFAIL)
bit in the Reset Cause (RESC) register. The main oscillator verification circuit action is described
in more detail in “Main Oscillator Verification Circuit” on page 203.
5.2.4
Power Control
®
The Stellaris microcontroller provides an integrated LDO regulator that is used to provide power
to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture.
An external LDO may not be used.
Note:
VDDA must be supplied with a voltage that meets the specification in Table 25-2 on page 1222,
or the microcontroller does not function properly. VDDA is the supply for all of the analog
circuitry on the device, including the clock circuitry.
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Figure 5-4. Power Architecture
VDDC
Internal
Logic and PLL
VDDC
GND
GND
LDO
Low-Noise
LDO
+3.3V
VDD
GND
I/O Buffers
VDD
GND
VDDA
GNDA
Analog Circuits
VDDA
5.2.5
GNDA
Clock Control
System control determines the control of clocks in this part.
5.2.5.1
Fundamental Clock Sources
There are multiple clock sources for use in the microcontroller:
■ Precision Internal Oscillator (PIOSC). The precision internal oscillator is an on-chip clock
source that is the clock source the microcontroller uses during and following POR. It does not
require the use of any external components and provides a clock that is 16 MHz ±1% at room
temperature and ±3% across temperature. The PIOSC allows for a reduced system cost in
applications that require an accurate clock source. If the main oscillator is required, software
must enable the main oscillator following reset and allow the main oscillator to stabilize before
changing the clock reference. If the Hibernation Module clock source is a 32.768-kHz oscillator,
the precision internal oscillator can be trimmed by software based on a reference clock for
increased accuracy.
■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 3.579545 MHz to
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16.384 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz to 16.384 MHz. The single-ended clock source range is from DC
through the specified speed of the microcontroller. The supported crystals are listed in the XTAL
bit field in the RCC register (see page 219). Note that the MOSC provides the clock source for
the USB PLL and must be connected to a crystal or an oscillator.
■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator provides an operational frequency of
30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings
mode benefits from reduced internal switching and also allows the MOSC to be powered down.
■ Hibernation Module Clock Source. The Hibernation module can be clocked in one of two ways.
The first way is a 4.194304-MHz crystal connected to the XOSC0 and XOSC1 pins. This clock
signal is divided by 128 internally to produce the 32.768-kHz clock reference. The second way
is a 32.768-kHz oscillator connected to the XOSC0 pin. The 32.768-kHz oscillator can be used
for the system clock, thus eliminating the need for an additional crystal or oscillator. The
Hibernation module clock source is intended to provide the system with a real-time clock source
and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%).
The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz
(inclusive). Table 5-4 on page 197 shows how the various clock sources can be used in a system.
Table 5-4. Clock Source Options
5.2.5.2
Clock Source
Drive PLL?
Precision Internal Oscillator
Yes
Used as SysClk?
BYPASS = 0,
OSCSRC = 0x1
Yes
BYPASS = 1, OSCSRC = 0x1
Precision Internal Oscillator divide by 4 No
(4 MHz ± 1%)
-
Yes
BYPASS = 1, OSCSRC = 0x2
Main Oscillator
BYPASS = 0,
OSCSRC = 0x0
Yes
BYPASS = 1, OSCSRC = 0x0
Yes
Internal 30-kHz Oscillator
No
-
Yes
BYPASS = 1, OSCSRC = 0x3
Hibernation Module 32.768-kHz
Oscillator
No
-
Yes
BYPASS = 1, OSCSRC2 = 0x7
Hibernation Module 4.194304-MHz
Crystal
No
-
No
-
Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
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■ Crystal input selection
Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the
RCC register is required, include another register access after writing the RCC register
and before writing the RCC2 register.
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. When the PLL is enabled, the ADC clock
signal is automatically divided down to 16 MHz from the PLL output for proper ADC operation.
Note:
When the ADC module is in operation, the system clock must be at least 16 MHz. When
the USB module is in operation, MOSC must be the clock source, either with or without
using the PLL, and the system clock must be at least 30 MHz.
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Figure 5-5. Main Clock Tree
XTALa
USBPWRDN c
USB PLL
(480 MHz)
÷4
USB Clock
RXINT
RXFRAC
I2S Receive MCLK
TXINT
TXFRAC
I2S Transmit MCLK
USEPWMDIV a
PWMDW a
PWM Clock
XTALa
PWRDN b
MOSCDIS a
PLL
(400 MHz)
Main OSC
USESYSDIV a,d
DIV400 c
÷2
IOSCDIS
a
System Clock
Precision
Internal OSC
(16 MHz)
SYSDIV e
÷4
BYPASS
b,d
Internal OSC
(30 kHz)
Hibernation
OSC
(32.768 kHz)
PWRDN
ADC Clock
OSCSRC b,d
÷ 25
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2 bit, or
[SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set.
Note:
The figure above shows all features available on all Stellaris® Firestorm-class microcontrollers. Not all peripherals
may be available on this device.
Using the SYSDIV and SYSDIV2 Fields
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
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is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-4 on page 197.
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field
SYSDIV
0x0
Divisor
/1
a
®
Frequency (BYPASS=0) Frequency (BYPASS=1)
StellarisWare Parameter
reserved
SYSCTL_SYSDIV_1
Clock source frequency/1
0x1
/2
reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x2
/3
66.67 MHz
Clock source frequency/3
SYSCTL_SYSDIV_3
0x3
/4
50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x4
/5
40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
0x5
/6
33.33 MHz
Clock source frequency/6
SYSCTL_SYSDIV_6
0x6
/7
28.57 MHz
Clock source frequency/7
SYSCTL_SYSDIV_7
0x7
/8
25 MHz
Clock source frequency/8
SYSCTL_SYSDIV_8
0x8
/9
22.22 MHz
Clock source frequency/9
SYSCTL_SYSDIV_9
0x9
/10
20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
0xA
/11
18.18 MHz
Clock source frequency/11
SYSCTL_SYSDIV_11
0xB
/12
16.67 MHz
Clock source frequency/12
SYSCTL_SYSDIV_12
0xC
/13
15.38 MHz
Clock source frequency/13
SYSCTL_SYSDIV_13
0xD
/14
14.29 MHz
Clock source frequency/14
SYSCTL_SYSDIV_14
0xE
/15
13.33 MHz
Clock source frequency/15
SYSCTL_SYSDIV_15
0xF
/16
12.5 MHz (default)
Clock source frequency/16
SYSCTL_SYSDIV_16
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 5-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 5-4 on page 197.
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
SYSDIV2
Divisor
a
Frequency
(BYPASS2=0)
Frequency (BYPASS2=1)
StellarisWare Parameter
0x00
/1
reserved
Clock source frequency/1
SYSCTL_SYSDIV_1
0x01
/2
reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x02
/3
66.67 MHz
Clock source frequency/3
SYSCTL_SYSDIV_3
0x03
/4
50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x04
/5
40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
...
...
...
...
...
0x09
/10
20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
...
...
...
...
...
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Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
Divisor
SYSDIV2
0x3F
/64
a
Frequency
(BYPASS2=0)
Frequency (BYPASS2=1)
StellarisWare Parameter
3.125 MHz
Clock source frequency/64
SYSCTL_SYSDIV_64
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along
with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In
this situation, the divisor is equivalent to the (SYSDIV2 encoding with SYSDIV2LSB appended) plus
one. Table 5-7 shows the frequency choices when DIV400 is set. When the DIV400 bit is clear,
SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table
5-6 on page 200.
Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1
/2
reserved
-
/3
reserved
-
1
/4
reserved
-
0
/5
80 MHz
SYSCTL_SYSDIV_2_5
1
/6
66.67 MHz
SYSCTL_SYSDIV_3
0
/7
reserved
-
1
/8
50 MHz
SYSCTL_SYSDIV_4
0
/9
44.44 MHz
SYSCTL_SYSDIV_4_5
1
/10
40 MHz
SYSCTL_SYSDIV_5
...
...
...
...
0
/127
3.15 MHz
SYSCTL_SYSDIV_63_5
1
/128
3.125 MHz
SYSCTL_SYSDIV_64
0x00
reserved
0
0x01
0x02
0x03
0x04
...
0x3F
b
StellarisWare Parameter
SYSDIV2LSB
Divisor
a
Frequency (BYPASS2=0)
SYSDIV2
a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0.
b. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
5.2.5.3
Precision Internal Oscillator Operation (PIOSC)
The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC
must remain enabled as it is used for internal functions. The PIOSC can only be disabled during
Deep-Sleep mode. It can be powered down by setting the IOSCDIS bit in the RCC register.
The PIOSC generates a 16-MHz clock with a ±1% accuracy at room temperatures. Across the
extended temperature range, the accuracy is ±3%. At the factory, the PIOSC is set to 16 MHz at
room temperature, however, the frequency can be trimmed for other voltage or temperature conditions
using software in one of three ways:
■ Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator
Calibration (PIOSCCAL) register.
■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As
the UT value increases, the generated period increases. To commit a new UT value, first set the
UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within
a few clock periods and is glitch free.
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■ Automatic calibration using the Hibernation module with a functioning 32.768-kHz clock source:
Set the CAL bit in the PIOSCCAL register; the results of the calibration are shown in the RESULT
field in the Precision Internal Oscillator Statistic (PIOSCSTAT) register. After calibration is
complete, the PIOSC is trimmed using the trimmed value returned in the CT field.
5.2.5.4
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 16.384 MHz, otherwise,
the range of supported crystals is 1 to 16.384 MHz.
The XTAL bit in the RCC register (see page 219) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
5.2.5.5
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor, unless the DIV400 bit in the RCC2 register is set.
To configure the PIOSC to be the clock source for the main PLL, program the OSCRC2 field in the
Run-Mode Clock Configuration 2 (RCC2) register to be 0x1.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 223). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency. Table 25-8 on page 1228 shows the actual PLL frequency and error for
a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 219)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
5.2.5.6
USB PLL Frequency Configuration
The USB PLL is disabled by default during power-on reset and is enabled later by software. The
USB PLL must be enabled and running for proper USB function. The main oscillator is the only clock
reference for the USB PLL. The USB PLL is enabled by clearing the USBPWRDN bit of the RCC2
register. The XTAL bit field (Crystal Value) of the RCC register describes the available crystal choices.
The main oscillator must be connected to one of the following crystal values in order to correctly
generate the USB clock: 4, 5, 6, 8, 10, 12, or 16 MHz. Only these crystals provide the necessary
USB PLL VCO frequency to conform with the USB timing specifications.
5.2.5.7
PLL Modes
Both PLLs have two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 219 and page 226).
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5.2.5.8
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
25-7 on page 1227). During the relock time, the affected PLL is not usable as a clock reference.
Either PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter clocked by the system clock is used to measure the TREADY requirement. If the system
clock is the main oscillator and it is running off an 8.192 MHz or slower external oscillator clock, the
down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz). If the system clock is running off
the PIOSC or an external oscillator clock that is faster than 8.192 MHz, the down counter is set to
0x2400. Hardware is provided to keep the PLL from being used as a system clock until the TREADY
condition is met after one of the two changes above. It is the user's responsibility to have a stable
clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the microcontroller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
The USB PLL is not protected during the lock time (TREADY), and software should ensure that the
USB PLL has locked before using the interface. Software can use many methods to ensure the
TREADY period has passed, including periodically polling the USBPLLLRIS bit in the Raw Interrupt
Status (RIS) register, and enabling the USB PLL Lock interrupt.
5.2.5.9
Main Oscillator Verification Circuit
The clock control includes circuitry to ensure that the main oscillator is running at the appropriate
frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside
of the allowable band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, the following sequence is performed by the
hardware:
1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.
2. If the internal oscillator (PIOSC) is disabled, it is enabled.
3. The system clock is switched from the main oscillator to the PIOSC.
4. An internal power-on reset is initiated that lasts for 32 PIOSC periods.
5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence.
5.2.6
System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the microcontroller is in Run, Sleep, and
Deep-Sleep mode, respectively. These registers are located in the System Control register map
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starting at offsets 0x600, 0x700, and 0x800, respectively. There must be a delay of 3 system clocks
after a peripheral module clock is enabled in the RCGC register before any module registers are
accessed.
There are four levels of operation for the microcontroller defined as:
■ Run mode
■ Sleep mode
■ Deep-Sleep mode
■ Hibernate mode
The following sections describe the different modes in detail.
Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their Run mode configuration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
5.2.6.1
Run Mode
In Run mode, the microcontroller actively executes code. Run mode provides normal operation of
the processor and all of the peripherals that are currently enabled by the RCGCn registers. The
system clock can be any of the available clock sources including the PLL.
5.2.6.2
Sleep Mode
In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and
the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered
by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction. Any properly configured
interrupt event in the system brings the processor back into Run mode. See “Power
Management” on page 106 for more details.
Peripherals are clocked that are enabled in the SCGCn registers when auto-clock gating is enabled
(see the RCC register) or the RCGCn registers when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
5.2.6.3
Deep-Sleep Mode
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered on
request from the code. Deep-Sleep mode is entered by first setting the SLEEPDEEP bit in the System
Control (SYSCTRL) register (see page 148) and then executing a WFI instruction. Any properly
configured interrupt event in the system brings the processor back into Run mode. See “Power
Management” on page 106 for more details.
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The Cortex-M3 processor core and the memory subsystem are not clocked in Deep-Sleep mode.
Peripherals are clocked that are enabled in the DCGCn registers when auto-clock gating is enabled
(see the RCC register) or the RCGCn registers when auto-clock gating is disabled. The system
clock source is specified in the DSLPCLKCFG register. When the DSLPCLKCFG register is used,
the internal oscillator source is powered up, if necessary, and other clocks are powered down. If
the PLL is running at the time of the WFI instruction, hardware powers the PLL down and overrides
the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting
in the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep
mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the
PIOSC is used as the PLL reference clock source, it may continue to provide the clock during
Deep-Sleep. See page 230.
5.2.6.4
Hibernate Mode
In this mode, the power supplies are turned off to the main part of the microcontroller and only the
Hibernation module's circuitry is active. An external wake event or RTC event is required to bring
the microcontroller back to Run mode. The Cortex-M3 processor and peripherals outside of the
Hibernation module see a normal "power on" sequence and the processor starts running code.
Software can determine if the microcontroller has been restarted from Hibernate mode by inspecting
the Hibernation module registers. For more information on the operation of Hibernate mode, see
“Hibernation Module” on page 293.
5.3
Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register, thereby configuring the microcontroller to run off a "raw" clock source
and allowing for the new PLL configuration to be validated before switching the system clock
to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
5.4
Register Map
Table 5-8 on page 206 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note:
Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
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System Control
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 320.
Table 5-8. System Control Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
DID0
RO
-
Device Identification 0
208
0x004
DID1
RO
-
Device Identification 1
237
0x008
DC0
RO
0x017F.00BF
Device Capabilities 0
239
0x010
DC1
RO
-
Device Capabilities 1
240
0x014
DC2
RO
0x570F.5037
Device Capabilities 2
242
0x018
DC3
RO
0xBFFF.7FC0
Device Capabilities 3
244
0x01C
DC4
RO
0x5004.F1FF
Device Capabilities 4
246
0x020
DC5
RO
0x0000.0000
Device Capabilities 5
248
0x024
DC6
RO
0x0000.0013
Device Capabilities 6
249
0x028
DC7
RO
0xFFFF.FFFF
Device Capabilities 7
250
0x02C
DC8
RO
0xFFFF.FFFF
Device Capabilities 8 ADC Channels
254
0x030
PBORCTL
R/W
0x0000.0002
Brown-Out Reset Control
210
0x040
SRCR0
R/W
0x00000000
Software Reset Control 0
286
0x044
SRCR1
R/W
0x00000000
Software Reset Control 1
288
0x048
SRCR2
R/W
0x00000000
Software Reset Control 2
291
0x050
RIS
RO
0x0000.0000
Raw Interrupt Status
211
0x054
IMC
R/W
0x0000.0000
Interrupt Mask Control
213
0x058
MISC
R/W1C
0x0000.0000
Masked Interrupt Status and Clear
215
0x05C
RESC
R/W
-
Reset Cause
217
0x060
RCC
R/W
0x0780.3AD1
Run-Mode Clock Configuration
219
0x064
PLLCFG
RO
-
XTAL to PLL Translation
223
0x06C
GPIOHBCTL
R/W
0x0000.0000
GPIO High-Performance Bus Control
224
0x070
RCC2
R/W
0x07C0.6810
Run-Mode Clock Configuration 2
226
0x07C
MOSCCTL
R/W
0x0000.0000
Main Oscillator Control
229
0x100
RCGC0
R/W
0x00000040
Run Mode Clock Gating Control Register 0
260
0x104
RCGC1
R/W
0x00000000
Run Mode Clock Gating Control Register 1
268
0x108
RCGC2
R/W
0x00000000
Run Mode Clock Gating Control Register 2
277
0x110
SCGC0
R/W
0x00000040
Sleep Mode Clock Gating Control Register 0
263
0x114
SCGC1
R/W
0x00000000
Sleep Mode Clock Gating Control Register 1
271
0x118
SCGC2
R/W
0x00000000
Sleep Mode Clock Gating Control Register 2
280
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Table 5-8. System Control Register Map (continued)
Name
Type
Reset
0x120
DCGC0
R/W
0x00000040
Deep Sleep Mode Clock Gating Control Register 0
266
0x124
DCGC1
R/W
0x00000000
Deep-Sleep Mode Clock Gating Control Register 1
274
0x128
DCGC2
R/W
0x00000000
Deep Sleep Mode Clock Gating Control Register 2
283
0x144
DSLPCLKCFG
R/W
0x0780.0000
Deep Sleep Clock Configuration
230
0x150
PIOSCCAL
R/W
0x0000.0000
Precision Internal Oscillator Calibration
232
0x154
PIOSCSTAT
RO
0x0000.0040
Precision Internal Oscillator Statistics
234
0x170
I2SMCLKCFG
R/W
0x0000.0000
I2S MCLK Configuration
235
0x190
DC9
RO
0x00FF.00FF
Device Capabilities 9 ADC Digital Comparators
257
0x1A0
NVMSTAT
RO
0x0000.0001
Non-Volatile Memory Information
259
5.5
Description
See
page
Offset
Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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System Control
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the microcontroller. Each microcontroller is uniquely identified
by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1
register.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset 31
30
reserved
Type
Reset
29
28
27
26
VER
25
24
23
22
21
20
reserved
18
17
16
CLASS
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
MAJOR
Type
Reset
19
MINOR
Bit/Field
Name
Type
Reset
31
reserved
RO
0
30:28
VER
RO
0x1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x1
Second version of the DID0 register format.
27:24
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:16
CLASS
RO
0x06
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all microcontrollers in a particular product line.
The CLASS field value is changed for new product lines, for changes in
fab process (for example, a remap or shrink), or any case where the
MAJOR or MINOR fields require differentiation from prior microcontrollers.
The value of the CLASS field is encoded as follows (all other encodings
are reserved):
Value Description
0x06 Stellaris® Firestorm-class microcontrollers
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Bit/Field
Name
Type
Reset
15:8
MAJOR
RO
-
Description
Major Revision
This field specifies the major revision number of the microcontroller.
The major revision reflects changes to base layers of the design. The
major revision number is indicated in the part number as a letter (A for
first revision, B for second, and so on). This field is encoded as follows:
Value Description
0x0
Revision A (initial device)
0x1
Revision B (first base layer revision)
0x2
Revision C (second base layer revision)
and so on.
7:0
MINOR
RO
-
Minor Revision
This field specifies the minor revision number of the microcontroller.
The minor revision reflects changes to the metal layers of the design.
The MINOR field value is reset when the MAJOR field is changed. This
field is numeric and is encoded as follows:
Value Description
0x0
Initial device, or a major revision update.
0x1
First metal layer change.
0x2
Second metal layer change.
and so on.
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Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.0002
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
BORIOR reserved
R/W
1
RO
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BORIOR
R/W
1
BOR Interrupt or Reset
Value Description
0
reserved
RO
0
0
A Brown Out Event causes an interrupt to be generated to the
interrupt controller.
1
A Brown Out Event causes a reset of the microcontroller.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 3: Raw Interrupt Status (RIS), offset 0x050
This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt
controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1
to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt
status bit.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
BORRIS
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MOSCPUPRIS USBPLLLRIS
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
MOSCPUPRIS
RO
0
RO
0
RO
0
PLLLRIS
RO
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MOSC Power Up Raw Interrupt Status
Value Description
1
Sufficient time has passed for the MOSC to reach the expected
frequency. The value for this power-up time is indicated by
TMOSC_START.
0
Sufficient time has not passed for the MOSC to reach the
expected frequency.
This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC
register.
7
USBPLLLRIS
RO
0
USB PLL Lock Raw Interrupt Status
Value Description
1
The USB PLL timer has reached TREADY indicating that sufficient
time has passed for the USB PLL to lock.
0
The USB PLL timer has not reached TREADY.
This bit is cleared by writing a 1 to the USBPLLLMIS bit in the MISC
register.
6
PLLLRIS
RO
0
PLL Lock Raw Interrupt Status
Value Description
1
The PLL timer has reached TREADY indicating that sufficient time
has passed for the PLL to lock.
0
The PLL timer has not reached TREADY.
This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register.
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System Control
Bit/Field
Name
Type
Reset
5:2
reserved
RO
0x0
1
BORRIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Brown-Out Reset Raw Interrupt Status
Value Description
1
A brown-out condition is currently active.
0
A brown-out condition is not currently active.
Note the BORIOR bit in the PBORCTL register must be cleared to cause
an interrupt due to a Brown Out Event.
This bit is cleared by writing a 1 to the BORMIS bit in the MISC register.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 4: Interrupt Mask Control (IMC), offset 0x054
This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by
a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the
corresponding bit in this register is set.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
BORIM
reserved
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MOSCPUPIM USBPLLLIM
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
MOSCPUPIM
R/W
0
R/W
0
R/W
0
PLLLIM
R/W
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MOSC Power Up Interrupt Mask
Value Description
7
USBPLLLIM
R/W
0
1
An interrupt is sent to the interrupt controller when the
MOSCPUPRIS bit in the RIS register is set.
0
The MOSCPUPRIS interrupt is suppressed and not sent to the
interrupt controller.
USB PLL Lock Interrupt Mask
Value Description
6
PLLLIM
R/W
0
1
An interrupt is sent to the interrupt controller when the
USBPLLLRIS bit in the RIS register is set.
0
The USBPLLLRIS interrupt is suppressed and not sent to the
interrupt controller.
PLL Lock Interrupt Mask
Value Description
5:2
reserved
RO
0x0
1
An interrupt is sent to the interrupt controller when the PLLLRIS
bit in the RIS register is set.
0
The PLLLRIS interrupt is suppressed and not sent to the
interrupt controller.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
1
BORIM
R/W
0
Description
Brown-Out Reset Interrupt Mask
Value Description
0
reserved
RO
0
1
An interrupt is sent to the interrupt controller when the BORRIS
bit in the RIS register is set.
0
The BORRIS interrupt is suppressed and not sent to the interrupt
controller.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt in the
Raw Interrupt Status (RIS) register. All of the bits are R/W1C, thus writing a 1 to a bit clears the
corresponding raw interrupt bit in the RIS register (see page 211).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MOSCPUPMIS USBPLLLMIS
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
MOSCPUPMIS
R/W1C
0
R/W1C
0
R/W1C
0
PLLLMIS
R/W1C
0
reserved
BORMIS reserved
R/W1C
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MOSC Power Up Masked Interrupt Status
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the MOSC PLL
to lock.
Writing a 1 to this bit clears it and also the MOSCPUPRIS bit in
the RIS register.
0
When read, a 0 indicates that sufficient time has not passed for
the MOSC PLL to lock.
A write of 0 has no effect on the state of this bit.
7
USBPLLLMIS
R/W1C
0
USB PLL Lock Masked Interrupt Status
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the USB PLL
to lock.
Writing a 1 to this bit clears it and also the USBPLLLRIS bit in
the RIS register.
0
When read, a 0 indicates that sufficient time has not passed for
the USB PLL to lock.
A write of 0 has no effect on the state of this bit.
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System Control
Bit/Field
Name
Type
Reset
6
PLLLMIS
R/W1C
0
Description
PLL Lock Masked Interrupt Status
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the PLL to lock.
Writing a 1 to this bit clears it and also the PLLLRIS bit in the
RIS register.
0
When read, a 0 indicates that sufficient time has not passed for
the PLL to lock.
A write of 0 has no effect on the state of this bit.
5:2
reserved
RO
0x0
1
BORMIS
R/W1C
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
BOR Masked Interrupt Status
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because of a brown-out condition.
Writing a 1 to this bit clears it and also the BORRIS bit in the
RIS register.
0
When read, a 0 indicates that a brown-out condition has not
occurred.
A write of 0 has no effect on the state of this bit.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 6: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when a power- on reset or an external reset is
the cause, in which case, all bits other than POR or EXT in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset 31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
-
9
8
7
6
5
4
3
2
1
0
WDT1
SW
WDT0
BOR
POR
EXT
RO
0
RO
0
RO
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
MOSCFAIL
reserved
Type
Reset
RO
0
16
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
MOSCFAIL
R/W
-
MOSC Failure Reset
Value Description
1
When read, this bit indicates that the MOSC circuit was enabled
for clock validation and failed, generating a reset event.
0
When read, this bit indicates that a MOSC failure has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
15:6
reserved
RO
0x00
5
WDT1
R/W
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Timer 1 Reset
Value Description
1
When read, this bit indicates that Watchdog Timer 1 timed out
and generated a reset.
0
When read, this bit indicates that Watchdog Timer 1 has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
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Bit/Field
Name
Type
Reset
4
SW
R/W
-
Description
Software Reset
Value Description
1
When read, this bit indicates that a software reset has caused
a reset event.
0
When read, this bit indicates that a software reset has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
3
WDT0
R/W
-
Watchdog Timer 0 Reset
Value Description
1
When read, this bit indicates that Watchdog Timer 0 timed out
and generated a reset.
0
When read, this bit indicates that Watchdog Timer 0 has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
2
BOR
R/W
-
Brown-Out Reset
Value Description
1
When read, this bit indicates that a brown-out reset has caused
a reset event.
0
When read, this bit indicates that a brown-out reset has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1
POR
R/W
-
Power-On Reset
Value Description
1
When read, this bit indicates that a power-on reset has caused
a reset event.
0
When read, this bit indicates that a power-on reset has not
generated a reset.
Writing a 0 to this bit clears it.
0
EXT
R/W
-
External Reset
Value Description
1
When read, this bit indicates that an external reset (RST
assertion) has caused a reset event.
0
When read, this bit indicates that an external reset (RST
assertion) has not caused a reset event since the previous
power-on reset.
Writing a 0 to this bit clears it.
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Register 7: Run-Mode Clock Configuration (RCC), offset 0x060
The bits in this register configure the system clock and oscillators.
Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the
RCC register is required, include another register access after writing the RCC register
and before writing the RCC2 register.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x0780.3AD1
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
12
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
27
26
25
24
23
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
11
10
9
8
R/W
0
R/W
1
ACG
PWRDN
reserved BYPASS
R/W
1
RO
1
21
20
19
R/W
0
RO
0
RO
0
RO
0
7
6
5
4
3
R/W
1
R/W
1
R/W
0
R/W
1
RO
0
SYSDIV
22
Bit/Field
Name
Type
Reset
31:28
reserved
RO
0x0
27
ACG
R/W
0
R/W
0
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
USESYSDIV
XTAL
R/W
1
18
OSCSRC
reserved
RO
0
IOSCDIS MOSCDIS
R/W
0
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the microcontroller enters a Sleep
or Deep-Sleep mode (respectively).
Value Description
1
The SCGCn or DCGCn registers are used to control the clocks
distributed to the peripherals when the microcontroller is in a
sleep mode. The SCGCn and DCGCn registers allow unused
peripherals to consume less power when the microcontroller is
in a sleep mode.
0
The Run-Mode Clock Gating Control (RCGCn) registers are
used when the microcontroller enters a sleep mode.
The RCGCn registers are always used to control the clocks in Run
mode.
26:23
SYSDIV
R/W
0xF
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-5 on page 200 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 240), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
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System Control
Bit/Field
Name
Type
Reset
22
USESYSDIV
R/W
0
Description
Enable System Clock Divider
Value Description
1
The system clock divider is the source for the system clock. The
system clock divider is forced to be used when the PLL is
selected as the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2
field in the RCC2 register is used as the system clock divider
rather than the SYSDIV field in this register.
0
The system clock is used undivided.
21:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
PWRDN
R/W
1
PLL Power Down
Value Description
1
The PLL is powered down. Care must be taken to ensure that
another clock source is functioning and that the BYPASS bit is
set before setting this bit.
0
The PLL is operating normally.
12
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
BYPASS
R/W
1
PLL Bypass
Value Description
1
The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV.
0
The system clock is the PLL output clock divided by the divisor
specified by SYSDIV.
See Table 5-5 on page 200 for programming guidelines.
Note:
The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
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Bit/Field
Name
Type
Reset
Description
10:6
XTAL
R/W
0x0B
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below. Depending on the crystal used,
the PLL frequency may not be exactly 400 MHz, see Table
25-8 on page 1228 for more information.
Frequencies that may be used with the USB interface are indicated in
the table. To function within the clocking requirements of the USB
specification, a crystal of 4, 5, 6, 8, 10, 12, or 16 MHz must be used.
Value Crystal Frequency (MHz) Not Crystal Frequency (MHz) Using
Using the PLL
the PLL
0x00
1.000 MHz
reserved
0x01
1.8432 MHz
reserved
0x02
2.000 MHz
reserved
0x03
2.4576 MHz
0x04
reserved
3.579545 MHz
0x05
3.6864 MHz
0x06
4 MHz (USB)
0x07
4.096 MHz
0x08
4.9152 MHz
0x09
5 MHz (USB)
0x0A
5.12 MHz
0x0B
6 MHz (reset value)(USB)
0x0C
6.144 MHz
0x0D
7.3728 MHz
0x0E
8 MHz (USB)
0x0F
8.192 MHz
0x10
10.0 MHz (USB)
0x11
12.0 MHz (USB)
0x12
12.288 MHz
0x13
13.56 MHz
0x14
14.31818 MHz
0x15
16.0 MHz (USB)
0x16
16.384 MHz
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Bit/Field
Name
Type
Reset
5:4
OSCSRC
R/W
0x1
Description
Oscillator Source
Selects the input source for the OSC. The values are:
Value Input Source
0x0
MOSC
Main oscillator
0x1
PIOSC
Precision internal oscillator
(default)
0x2
PIOSC/4
Precision internal oscillator / 4
0x3
30 kHz
30-kHz internal oscillator
For additional oscillator sources, see the RCC2 register.
3:2
reserved
RO
0x0
1
IOSCDIS
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Precision Internal Oscillator Disable
Value Description
0
MOSCDIS
R/W
1
1
The precision internal oscillator (PIOSC) is disabled.
0
The precision internal oscillator is enabled.
Main Oscillator Disable
Value Description
1
The main oscillator is disabled (default).
0
The main oscillator is enabled.
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Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 219).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
-
RO
-
RO
-
RO
-
RO
-
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
F
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0x0000.0
13:5
F
RO
-
R
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL F Value
This field specifies the value supplied to the PLL’s F input.
4:0
R
RO
-
PLL R Value
This field specifies the value supplied to the PLL’s R input.
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System Control
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C
This register controls which internal bus is used to access each GPIO port. When a bit is clear, the
corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and
through the APB memory aperture. When a bit is set, the corresponding port is accessed across
the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each
GPIO port can be individually configured to use AHB or APB, but may be accessed only through
one aperture. The AHB bus provides better back-to-back access performance than the APB bus.
The address aperture in the memory map changes for the ports that are enabled for AHB access
(see Table 9-7 on page 438).
GPIO High-Performance Bus Control (GPIOHBCTL)
Base 0x400F.E000
Offset 0x06C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.0
8
PORTJ
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port J Advanced High-Performance Bus
This bit defines the memory aperture for Port J.
Value Description
7
PORTH
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port H Advanced High-Performance Bus
This bit defines the memory aperture for Port H.
Value Description
6
PORTG
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port G Advanced High-Performance Bus
This bit defines the memory aperture for Port G.
Value Description
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
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Bit/Field
Name
Type
Reset
5
PORTF
R/W
0
Description
Port F Advanced High-Performance Bus
This bit defines the memory aperture for Port F.
Value Description
4
PORTE
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port E Advanced High-Performance Bus
This bit defines the memory aperture for Port E.
Value Description
3
PORTD
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port D Advanced High-Performance Bus
This bit defines the memory aperture for Port D.
Value Description
2
PORTC
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port C Advanced High-Performance Bus
This bit defines the memory aperture for Port C.
Value Description
1
PORTB
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port B Advanced High-Performance Bus
This bit defines the memory aperture for Port B.
Value Description
0
PORTA
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port A Advanced High-Performance Bus
This bit defines the memory aperture for Port A.
Value Description
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
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System Control
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields, as shown in Table 5-9, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.
Table 5-9. RCC2 Fields that Override RCC Fields
RCC2 Field...
Overrides RCC Field
SYSDIV2, bits[28:23]
SYSDIV, bits[26:23]
PWRDN2, bit[13]
PWRDN, bit[13]
BYPASS2, bit[11]
BYPASS, bit[11]
OSCSRC2, bits[6:4]
OSCSRC, bits[5:4]
Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the
RCC register is required, include another register access after writing the RCC register
and before writing the RCC2 register.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x07C0.6810
31
30
USERCC2 DIV400
Type
Reset
29
28
27
26
reserved
25
23
22
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
RO
0
R/W
1
R/W
1
RO
0
reserved
R/W
1
RO
0
21
20
19
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31
USERCC2
R/W
0
Use RCC2
R/W
0
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
0
RO
0
OSCSRC2
RO
0
18
reserved
SYSDIV2LSB
reserved USBPWRDN PWRDN2 reserved BYPASS2
Type
Reset
24
SYSDIV2
R/W
0
reserved
R/W
1
RO
0
RO
0
Value Description
30
DIV400
R/W
0
1
The RCC2 register fields override the RCC register fields.
0
The RCC register fields are used, and the fields in RCC2 are
ignored.
Divide PLL as 400 MHz vs. 200 MHz
This bit, along with the SYSDIV2LSB bit, allows additional frequency
choices.
Value Description
1
Append the SYSDIV2LSB bit to the SYSDIV2 field to create a
7 bit divisor using the 400 MHz PLL output, see Table
5-7 on page 201.
0
Use SYSDIV2 as is and apply to 200 MHz predivided PLL
output. See Table 5-6 on page 200 for programming guidelines.
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Bit/Field
Name
Type
Reset
29
reserved
RO
0x0
28:23
SYSDIV2
R/W
0x0F
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divisor 2
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS2
bit is configured). SYSDIV2 is used for the divisor when both the
USESYSDIV bit in the RCC register and the USERCC2 bit in this register
are set. See Table 5-6 on page 200 for programming guidelines.
22
SYSDIV2LSB
R/W
1
Additional LSB for SYSDIV2
When DIV400 is set, this bit becomes the LSB of SYSDIV2. If DIV400
is clear, this bit is not used. See Table 5-6 on page 200 for programming
guidelines.
This bit can only be set or cleared when DIV400 is set.
21:15
reserved
RO
0x0
14
USBPWRDN
R/W
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power-Down USB PLL
Value Description
13
PWRDN2
R/W
1
1
The USB PLL is powered down.
0
The USB PLL operates normally.
Power-Down PLL 2
Value Description
1
The PLL is powered down.
0
The PLL operates normally.
12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
BYPASS2
R/W
1
PLL Bypass 2
Value Description
1
The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV2.
0
The system clock is the PLL output clock divided by the divisor
specified by SYSDIV2.
See Table 5-6 on page 200 for programming guidelines.
Note:
10:7
reserved
RO
0x0
The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
6:4
OSCSRC2
R/W
0x1
Description
Oscillator Source 2
Selects the input source for the OSC. The values are:
Value
Description
0x0
MOSC
Main oscillator
0x1
PIOSC
Precision internal oscillator
0x2
PIOSC/4
Precision internal oscillator / 4
0x3
30 kHz
30-kHz internal oscillator
0x4-0x6 Reserved
0x7
32.768 kHz
32.768-kHz external oscillator
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C
This register provides the ability to enable the MOSC clock verification circuit. When enabled, this
circuit monitors the frequency of the MOSC to verify that the oscillator is operating within specified
limits. If the clock goes invalid after being enabled, the microcontroller issues a power-on reset and
reboots to the NMI handler.
Main Oscillator Control (MOSCCTL)
Base 0x400F.E000
Offset 0x07C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
CVAL
R/W
0
RO
0
CVAL
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Validation for MOSC
Value Description
1
The MOSC monitor circuit is enabled.
0
The MOSC monitor circuit is disabled.
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Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31
30
29
28
27
26
reserved
Type
Reset
25
24
23
22
21
20
DSDIVORIDE
18
17
16
reserved
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
19
DSOSCSRC
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0x0
28:23
DSDIVORIDE
R/W
0x0F
R/W
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Divider Field Override
If Deep-Sleep mode is enabled when the PLL is running, the PLL is
disabled. This 6-bit field contains a system divider field that overrides
the SYSDIV field in the RCC register or the SYSDIV2 field in the RCC2
register during Deep Sleep. This divider is applied to the source selected
by the DSOSCSRC field.
Value Description
0x0
/1
0x1
/2
0x2
/3
0x3
/4
...
...
0x3F /64
22:7
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
6:4
DSOSCSRC
R/W
0x0
Description
Clock Source
Specifies the clock source during Deep-Sleep mode.
Value
Description
0x0
MOSC
Use the main oscillator as the source.
Note:
0x1
If the PIOSC is being used as the clock reference
for the PLL, the PIOSC is the clock source instead
of MOSC in Deep-Sleep mode.
PIOSC
Use the precision internal 16-MHz oscillator as the source.
0x2
Reserved
0x3
30 kHz
Use the 30-kHz internal oscillator as the source.
0x4-0x6 Reserved
0x7
32.768 kHz
Use the Hibernation module 32.768-kHz external oscillator
as the source.
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150
This register provides the ability to update or recalibrate the precision internal oscillator. Note that
a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be
able to calibrate the PIOSC.
Precision Internal Oscillator Calibration (PIOSCCAL)
Base 0x400F.E000
Offset 0x150
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
UTEN
Type
Reset
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
reserved
Type
Reset
23
RO
0
CAL
R/W
0
Bit/Field
Name
Type
Reset
31
UTEN
R/W
0
UPDATE reserved
R/W
0
RO
0
UT
Description
Use User Trim Value
Value Description
30:10
reserved
RO
0x0000
9
CAL
R/W
0
1
The trim value in bits[6:0] of this register are used for any update
trim operation.
0
The factory calibration value is used for an update trim operation.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Start Calibration
Value Description
1
Starts a new calibration of the PIOSC. Results are in the
PIOSCSTAT register. The resulting trim value from the operation
is active in the PIOSC after the calibration completes. The result
overrides any previous update trim operation whether the
calibration passes or fails.
0
No action.
This bit is auto-cleared after it is set.
8
UPDATE
R/W
0
Update Trim
Value Description
1
Updates the PIOSC trim value with the UT bit or the DT bit in
the PIOSCSTAT register. Used with UTEN.
0
No action.
This bit is auto-cleared after the update.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
6:0
UT
R/W
0x0
Description
User Trim Value
User trim value that can be loaded into the PIOSC.
Refer to “Main PLL Frequency Configuration” on page 202 for more
information on calibrating the PIOSC.
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Register 14: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154
This register provides the user information on the PIOSC calibration. Note that a 32.768-kHz oscillator
must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC.
Precision Internal Oscillator Statistics (PIOSCSTAT)
Base 0x400F.E000
Offset 0x154
Type RO, reset 0x0000.0040
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
DT
reserved
Type
Reset
RO
0
RESULT
reserved
RO
0
RO
0
CT
Bit/Field
Name
Type
Reset
Description
31:23
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:16
DT
RO
-
Default Trim Value
This field contains the default trim value. This value is loaded into the
PIOSC after every full power-up.
15:10
reserved
RO
0x0
9:8
RESULT
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Calibration Result
Value Description
7
reserved
RO
0
6:0
CT
RO
0x40
0x0
Calibration has not been attempted.
0x1
The last calibration operation completed to meet 1% accuracy.
0x2
The last calibration operation failed to meet 1% accuracy.
0x3
Reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Calibration Trim Value
This field contains the trim value from the last calibration operation. After
factory calibration CT and DT are the same.
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Register 15: I2S MCLK Configuration (I2SMCLKCFG), offset 0x170
This register configures the receive and transmit fractional clock dividers for the for the I2S master
transmit and receive clocks (I2S0TXMCLK and I2S0RXMCLK). Varying the integer and fractional
inputs for the clocks allows greater accuracy in hitting the target I2S clock frequencies. Refer to
“Clock Control” on page 858 for combinations of the TXI and TXF bits and the RXI and RXF bits that
provide MCLK frequencies within acceptable error limits.
I2S MCLK Configuration (I2SMCLKCFG)
Base 0x400F.E000
Offset 0x170
Type R/W, reset 0x0000.0000
Type
Reset
Type
Reset
31
30
RXEN
reserved
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
12
11
10
9
15
14
TXEN
reserved
R/W
0
RO
0
29
28
27
26
25
24
23
22
21
20
19
18
RXI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
TXI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31
RXEN
R/W
0
17
16
R/W
0
R/W
0
1
0
R/W
0
R/W
0
RXF
TXF
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
RX Clock Enable
Value Description
1
The I2S receive clock generator is enabled.
0
The I2S receive clock generator is disabled.
If the RXSLV bit in the I2S Module Configuration (I2SCFG)
register is set, then the I2S0RXMCLK must be externally
generated.
30
reserved
RO
0
29:20
RXI
R/W
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RX Clock Integer Input
This field contains the integer input for the receive clock generator.
19:16
RXF
R/W
0x0
RX Clock Fractional Input
This field contains the fractional input for the receive clock generator.
15
TXEN
R/W
0
TX Clock Enable
Value Description
1
The I2S transmit clock generator is enabled.
0
The I2S transmit clock generator is disabled.
If the TXSLV bit in the I2S Module Configuration (I2SCFG)
register is set, then the I2S0TXMCLK must be externally
generated.
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Bit/Field
Name
Type
Reset
14
reserved
RO
0
13:4
TXI
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
TX Clock Integer Input
This field contains the integer input for the transmit clock generator.
3:0
TXF
R/W
0x0
TX Clock Fractional Input
This field contains the fractional input for the transmit clock generator.
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Register 16: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the
DID0 register and the PARTNO field in the DID1 register.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset 31
30
29
28
27
26
RO
0
15
25
24
23
22
21
20
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
14
13
12
11
10
9
8
7
6
5
4
RO
0
RO
0
RO
0
RO
0
RO
0
RO
-
RO
-
RO
-
VER
Type
Reset
FAM
PINCOUNT
Type
Reset
RO
0
RO
1
18
17
16
RO
1
RO
1
RO
0
RO
1
3
2
1
0
PARTNO
reserved
RO
0
19
TEMP
Bit/Field
Name
Type
Reset
31:28
VER
RO
0x1
RO
-
PKG
ROHS
RO
-
RO
1
QUAL
RO
-
RO
-
Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x1
27:24
FAM
RO
0x0
Second version of the DID1 register format.
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
0x0
23:16
PARTNO
RO
0x7D
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x7D LM3S9U90
15:13
PINCOUNT
RO
0x2
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
0x2
100-pin package
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Bit/Field
Name
Type
Reset
Description
12:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
TEMP
RO
-
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
4:3
PKG
RO
-
0x0
Commercial temperature range (0°C to 70°C)
0x1
Industrial temperature range (-40°C to 85°C)
0x2
Extended temperature range (-40°C to 105°C)
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
2
ROHS
RO
1
0x0
SOIC package
0x1
LQFP package
0x2
BGA package
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
1:0
QUAL
RO
-
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0
Engineering Sample (unqualified)
0x1
Pilot Production (unqualified)
0x2
Fully Qualified
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Register 17: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x017F.00BF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
SRAMSZ
Type
Reset
FLASHSZ
Type
Reset
RO
1
Bit/Field
Name
Type
Reset
Description
31:16
SRAMSZ
RO
0x017F
SRAM Size
Indicates the size of the on-chip SRAM memory.
Value
Description
0x017F 96 KB of SRAM
15:0
FLASHSZ
RO
0x00BF
Flash Size
Indicates the size of the on-chip flash memory.
Value
Description
0x00BF 384 KB of Flash
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Register 18: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 31
30
29
reserved
Type
Reset
28
WDT1
26
24
23
22
21
20
19
18
16
CAN1
CAN0
ADC1
ADC0
RO
0
RO
1
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MPU
HIB
TEMPSNS
PLL
WDT0
SWO
SWD
JTAG
RO
-
RO
-
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
-
MAXADC1SPD
MAXADC0SPD
RO
1
RO
1
RO
1
RO
1
reserved
17
RO
0
RO
-
reserved
25
RO
0
MINSYSDIV
Type
Reset
27
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
RO
1
Watchdog Timer 1 Present
When set, indicates that watchdog timer 1 is present.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
RO
1
CAN Module 1 Present
When set, indicates that CAN unit 1 is present.
24
CAN0
RO
1
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
23:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
ADC1
RO
1
ADC Module 1 Present
When set, indicates that ADC module 1 is present.
16
ADC0
RO
1
ADC Module 0 Present
When set, indicates that ADC module 0 is present
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Bit/Field
Name
Type
Reset
15:12
MINSYSDIV
RO
-
Description
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
11:10
MAXADC1SPD
RO
0x3
0x1
Specifies an 80-MHz CPU clock with a PLL divider of 2.5.
0x2
Specifies a 66.67-MHz CPU clock with a PLL divider of 3.
0x3
Specifies a 50-MHz CPU clock with a PLL divider of 4.
0x7
Specifies a 25-MHz clock with a PLL divider of 8.
0x9
Specifies a 20-MHz clock with a PLL divider of 10.
Max ADC1 Speed
This field indicates the maximum rate at which the ADC samples data.
Value Description
0x3
9:8
MAXADC0SPD
RO
0x3
1M samples/second
Max ADC0 Speed
This field indicates the maximum rate at which the ADC samples data.
Value Description
0x3
7
MPU
RO
1
1M samples/second
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the "Cortex-M3 Peripherals" chapter for details
on the MPU.
6
HIB
RO
1
Hibernation Module Present
When set, indicates that the Hibernation module is present.
5
TEMPSNS
RO
1
Temp Sensor Present
When set, indicates that the on-chip temperature sensor is present.
4
PLL
RO
1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
3
WDT0
RO
1
Watchdog Timer 0 Present
When set, indicates that watchdog timer 0 is present.
2
SWO
RO
1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
1
SWD
RO
1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
0
JTAG
RO
1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
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Register 19: Device Capabilities 2 (DC2), offset 0x014
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x570F.5037
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
23
22
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
RO
1
RO
0
RO
1
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
reserved
I2C1
reserved
I2C0
RO
0
RO
1
RO
0
RO
1
RO
0
RO
0
RO
0
21
20
19
18
17
16
RO
1
RO
0
RO
0
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
RO
1
RO
1
RO
1
RO
1
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
SSI1
SSI0
reserved
UART2
UART1
UART0
RO
1
RO
1
RO
0
RO
1
RO
1
RO
1
reserved
reserved
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
RO
1
EPI Module 0 Present
When set, indicates that EPI module 0 is present.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
RO
1
I2S Module 0 Present
When set, indicates that I2S module 0 is present.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
COMP2
RO
1
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
25
COMP1
RO
1
Analog Comparator 1 Present
When set, indicates that analog comparator 1 is present.
24
COMP0
RO
1
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
RO
1
Timer Module 3 Present
When set, indicates that General-Purpose Timer module 3 is present.
18
TIMER2
RO
1
Timer Module 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
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Bit/Field
Name
Type
Reset
17
TIMER1
RO
1
Description
Timer Module 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
16
TIMER0
RO
1
Timer Module 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
RO
1
I2C Module 1 Present
When set, indicates that I2C module 1 is present.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
RO
1
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
RO
1
SSI Module 1 Present
When set, indicates that SSI module 1 is present.
4
SSI0
RO
1
SSI Module 0 Present
When set, indicates that SSI module 0 is present.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
RO
1
UART Module 2 Present
When set, indicates that UART module 2 is present.
1
UART1
RO
1
UART Module 1 Present
When set, indicates that UART module 1 is present.
0
UART0
RO
1
UART Module 0 Present
When set, indicates that UART module 0 is present.
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Register 20: Device Capabilities 3 (DC3), offset 0x018
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0xBFFF.7FC0
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
32KHZ
reserved
CCP5
CCP4
CCP3
CCP2
CCP1
CCP0
RO
1
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
C2O
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
C2PLUS C2MINUS
RO
1
RO
1
C1O
C1PLUS C1MINUS
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31
32KHZ
RO
1
C0O
RO
1
23
22
21
20
19
18
17
16
ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0
C0PLUS C0MINUS
RO
1
RO
1
reserved
Description
32KHz Input Clock Available
When set, indicates an even CCP pin is present and can be used as a
32-KHz input clock.
30
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29
CCP5
RO
1
CCP5 Pin Present
When set, indicates that Capture/Compare/PWM pin 5 is present.
28
CCP4
RO
1
CCP4 Pin Present
When set, indicates that Capture/Compare/PWM pin 4 is present.
27
CCP3
RO
1
CCP3 Pin Present
When set, indicates that Capture/Compare/PWM pin 3 is present.
26
CCP2
RO
1
CCP2 Pin Present
When set, indicates that Capture/Compare/PWM pin 2 is present.
25
CCP1
RO
1
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
24
CCP0
RO
1
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
23
ADC0AIN7
RO
1
ADC Module 0 AIN7 Pin Present
When set, indicates that ADC module 0 input pin 7 is present.
22
ADC0AIN6
RO
1
ADC Module 0 AIN6 Pin Present
When set, indicates that ADC module 0 input pin 6 is present.
21
ADC0AIN5
RO
1
ADC Module 0 AIN5 Pin Present
When set, indicates that ADC module 0 input pin 5 is present.
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Bit/Field
Name
Type
Reset
20
ADC0AIN4
RO
1
Description
ADC Module 0 AIN4 Pin Present
When set, indicates that ADC module 0 input pin 4 is present.
19
ADC0AIN3
RO
1
ADC Module 0 AIN3 Pin Present
When set, indicates that ADC module 0 input pin 3 is present.
18
ADC0AIN2
RO
1
ADC Module 0 AIN2 Pin Present
When set, indicates that ADC module 0 input pin 2 is present.
17
ADC0AIN1
RO
1
ADC Module 0 AIN1 Pin Present
When set, indicates that ADC module 0 input pin 1 is present.
16
ADC0AIN0
RO
1
ADC Module 0 AIN0 Pin Present
When set, indicates that ADC module 0 input pin 0 is present.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
C2O
RO
1
C2o Pin Present
When set, indicates that the analog comparator 2 output pin is present.
13
C2PLUS
RO
1
C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
12
C2MINUS
RO
1
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
11
C1O
RO
1
C1o Pin Present
When set, indicates that the analog comparator 1 output pin is present.
10
C1PLUS
RO
1
C1+ Pin Present
When set, indicates that the analog comparator 1 (+) input pin is present.
9
C1MINUS
RO
1
C1- Pin Present
When set, indicates that the analog comparator 1 (-) input pin is present.
8
C0O
RO
1
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
7
C0PLUS
RO
1
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
6
C0MINUS
RO
1
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
5:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 21: Device Capabilities 4 (DC4), offset 0x01C
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x5004.F1FF
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
reserved
EPHY0
reserved
EMAC0
RO
0
RO
1
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
CCP7
RO
1
CCP6
UDMA
ROM
RO
1
RO
1
RO
1
23
22
21
20
19
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
8
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
reserved
RO
0
RO
0
RO
0
18
17
PICAL
16
reserved
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
RO
1
Ethernet PHY Layer 0 Present
When set, indicates that Ethernet PHY layer 0 is present.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
RO
1
Ethernet MAC Layer 0 Present
When set, indicates that Ethernet MAC layer 0 is present.
27:19
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
18
PICAL
RO
1
PIOSC Calibrate
When set, indicates that the PIOSC can be calibrated.
17:16
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15
CCP7
RO
1
CCP7 Pin Present
When set, indicates that Capture/Compare/PWM pin 7 is present.
14
CCP6
RO
1
CCP6 Pin Present
When set, indicates that Capture/Compare/PWM pin 6 is present.
13
UDMA
RO
1
Micro-DMA Module Present
When set, indicates that the micro-DMA module present.
12
ROM
RO
1
Internal Code ROM Present
When set, indicates that internal code ROM is present.
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Bit/Field
Name
Type
Reset
Description
11:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
RO
1
GPIO Port J Present
When set, indicates that GPIO Port J is present.
7
GPIOH
RO
1
GPIO Port H Present
When set, indicates that GPIO Port H is present.
6
GPIOG
RO
1
GPIO Port G Present
When set, indicates that GPIO Port G is present.
5
GPIOF
RO
1
GPIO Port F Present
When set, indicates that GPIO Port F is present.
4
GPIOE
RO
1
GPIO Port E Present
When set, indicates that GPIO Port E is present.
3
GPIOD
RO
1
GPIO Port D Present
When set, indicates that GPIO Port D is present.
2
GPIOC
RO
1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
1
GPIOB
RO
1
GPIO Port B Present
When set, indicates that GPIO Port B is present.
0
GPIOA
RO
1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
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Register 22: Device Capabilities 5 (DC5), offset 0x020
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 5 (DC5)
Base 0x400F.E000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:0
reserved
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 23: Device Capabilities 6 (DC6), offset 0x024
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 6 (DC6)
Base 0x400F.E000
Offset 0x024
Type RO, reset 0x0000.0013
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
USB0PHY
RO
1
reserved
RO
0
USB0
RO
1
Bit/Field
Name
Type
Reset
Description
31:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
USB0PHY
RO
1
USB Module 0 PHY Present
When set, indicates that the USB module 0 PHY is present.
3:2
reserved
RO
0
1:0
USB0
RO
0x3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Module 0 Present
Thie field indicates that USB module 0 is present and specifies its
capability.
Value Description
0x3
USB0 is OTG.
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Register 24: Device Capabilities 7 (DC7), offset 0x028
This register is predefined by the part and can be used to verify uDMA channel features. A 1 indicates
the channel is available on this device; a 0 that the channel is only available on other devices in the
family. Most channels have primary and secondary assignments. If the primary function is not
available on this microcontroller, the secondary function becomes the primary function. If the
secondary function is not available, the primary function is the only option.
Device Capabilities 7 (DC7)
Base 0x400F.E000
Offset 0x028
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 DMACH3 DMACH2 DMACH1 DMACH0
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31
reserved
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
Reserved
Reserved for uDMA channel 31.
30
DMACH30
RO
1
SW
When set, indicates uDMA channel 30 is available for software transfers.
29
DMACH29
RO
1
I2S0_TX / CAN1_TX
When set, indicates uDMA channel 29 is available and connected to
the transmit path of I2S module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of CAN module 1 transmit.
28
DMACH28
RO
1
I2S0_RX / CAN1_RX
When set, indicates uDMA channel 28 is available and connected to
the receive path of I2S module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of CAN module 1 receive.
27
DMACH27
RO
1
CAN1_TX / ADC1_SS3
When set, indicates uDMA channel 27 is available and connected to
the transmit path of CAN module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of ADC module 1 Sample Sequencer
3.
26
DMACH26
RO
1
CAN1_RX / ADC1_SS2
When set, indicates uDMA channel 26 is available and connected to
the receive path of CAN module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of ADC module 1 Sample Sequencer
2.
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Bit/Field
Name
Type
Reset
25
DMACH25
RO
1
Description
SSI1_TX / ADC1_SS1
When set, indicates uDMA channel 25 is available and connected to
the transmit path of SSI module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of ADC module 1 Sample Sequencer
1.
24
DMACH24
RO
1
SSI1_RX / ADC1_SS0
When set, indicates uDMA channel 24 is available and connected to
the receive path of SSI module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of ADC module 1 Sample Sequencer
0.
23
DMACH23
RO
1
UART1_TX / CAN2_TX
When set, indicates uDMA channel 23 is available and connected to
the transmit path of UART module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of CAN module 2 transmit.
22
DMACH22
RO
1
UART1_RX / CAN2_RX
When set, indicates uDMA channel 22 is available and connected to
the receive path of UART module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of CAN module 2 receive.
21
DMACH21
RO
1
Timer1B / EPI0_WFIFO
When set, indicates uDMA channel 21 is available and connected to
Timer 1B. If the corresponding bit in the DMACHASGN register is set,
the channel is connected instead to the secondary channel assignment
of EPI module 0 write FIFO (WRIFO).
20
DMACH20
RO
1
Timer1A / EPI0_NBRFIFO
When set, indicates uDMA channel 20 is available and connected to
Timer 1A. If the corresponding bit in the DMACHASGN register is set,
the channel is connected instead to the secondary channel assignment
of EPI module 0 non-blocking read FIFO (NBRFIFO).
19
DMACH19
RO
1
Timer0B / Timer1B
When set, indicates uDMA channel 19 is available and connected to
Timer 0B. If the corresponding bit in the DMACHASGN register is set,
the channel is connected instead to the secondary channel assignment
of Timer 1B.
18
DMACH18
RO
1
Timer0A / Timer1A
When set, indicates uDMA channel 18 is available and connected to
Timer 0A. If the corresponding bit in the DMACHASGN register is set,
the channel is connected instead to the secondary channel assignment
of Timer 1A.
17
DMACH17
RO
1
ADC0_SS3
When set, indicates uDMA channel 17 is available and connected to
ADC module 0 Sample Sequencer 3.
16
DMACH16
RO
1
ADC0_SS2
When set, indicates uDMA channel 16 is available and connected to
ADC module 0 Sample Sequencer 2.
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Bit/Field
Name
Type
Reset
15
DMACH15
RO
1
Description
ADC0_SS1 / Timer2B
When set, indicates uDMA channel 15 is available and connected to
ADC module 0 Sample Sequencer 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2B.
14
DMACH14
RO
1
ADC0_SS0 / Timer2A
When set, indicates uDMA channel 14 is available and connected to
ADC module 0 Sample Sequencer 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2A.
13
DMACH13
RO
1
CAN0_TX / UART2_TX
When set, indicates uDMA channel 13 is available and connected to
the transmit path of CAN module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 2 transmit.
12
DMACH12
RO
1
CAN0_RX / UART2_RX
When set, indicates uDMA channel 12 is available and connected to
the receive path of CAN module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 2 receive.
11
DMACH11
RO
1
SSI0_TX / SSI1_TX
When set, indicates uDMA channel 11 is available and connected to
the transmit path of SSI module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of SSI module 1 transmit.
10
DMACH10
RO
1
SSI0_RX / SSI1_RX
When set, indicates uDMA channel 10 is available and connected to
the receive path of SSI module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of SSI module 1 receive.
9
DMACH9
RO
1
UART0_TX / UART1_TX
When set, indicates uDMA channel 9 is available and connected to the
transmit path of UART module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 1 transmit.
8
DMACH8
RO
1
UART0_RX / UART1_RX
When set, indicates uDMA channel 8 is available and connected to the
receive path of UART module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 1 receive.
7
DMACH7
RO
1
ETH_TX / Timer2B
When set, indicates uDMA channel 7 is available and connected to the
transmit path of the Ethernet module. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2B.
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Bit/Field
Name
Type
Reset
6
DMACH6
RO
1
Description
ETH_RX / Timer2A
When set, indicates uDMA channel 6 is available and connected to the
receive path of the Ethernet module. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2A.
5
DMACH5
RO
1
USB_EP3_TX / Timer2B
When set, indicates uDMA channel 5 is available and connected to the
transmit path of USB endpoint 3. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2B.
4
DMACH4
RO
1
USB_EP3_RX / Timer2A
When set, indicates uDMA channel 4 is available and connected to the
receive path of USB endpoint 3. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2A.
3
DMACH3
RO
1
USB_EP2_TX / Timer3B
When set, indicates uDMA channel 3 is available and connected to the
transmit path of USB endpoint 2. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 3B.
2
DMACH2
RO
1
USB_EP2_RX / Timer3A
When set, indicates uDMA channel 2 is available and connected to the
receive path of USB endpoint 2. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 3A.
1
DMACH1
RO
1
USB_EP1_TX / UART2_TX
When set, indicates uDMA channel 1 is available and connected to the
transmit path of USB endpoint 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 2 transmit.
0
DMACH0
RO
1
USB_EP1_RX / UART2_RX
When set, indicates uDMA channel 0 is available and connected to the
receive path of USB endpoint 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 2 receive.
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Register 25: Device Capabilities 8 ADC Channels (DC8), offset 0x02C
This register is predefined by the part and can be used to verify features.
Device Capabilities 8 ADC Channels (DC8)
Base 0x400F.E000
Offset 0x02C
Type RO, reset 0xFFFF.FFFF
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADC1AIN15
ADC1AIN14
ADC1AIN13
ADC1AIN12
ADC1AIN11
ADC1AIN10
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADC0AIN15
ADC0AIN14
ADC0AIN13
ADC0AIN12
ADC0AIN11
ADC0AIN10
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
ADC1AIN9 ADC1AIN8 ADC1AIN7 ADC1AIN6 ADC1AIN5 ADC1AIN4 ADC1AIN3 ADC1AIN2 ADC1AIN1 ADC1AIN0
ADC0AIN9 ADC0AIN8 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0
RO
1
Bit/Field
Name
Type
Reset
31
ADC1AIN15
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
ADC Module 1 AIN15 Pin Present
When set, indicates that ADC module 1 input pin 15 is present.
30
ADC1AIN14
RO
1
ADC Module 1 AIN14 Pin Present
When set, indicates that ADC module 1 input pin 14 is present.
29
ADC1AIN13
RO
1
ADC Module 1 AIN13 Pin Present
When set, indicates that ADC module 1 input pin 13 is present.
28
ADC1AIN12
RO
1
ADC Module 1 AIN12 Pin Present
When set, indicates that ADC module 1 input pin 12 is present.
27
ADC1AIN11
RO
1
ADC Module 1 AIN11 Pin Present
When set, indicates that ADC module 1 input pin 11 is present.
26
ADC1AIN10
RO
1
ADC Module 1 AIN10 Pin Present
When set, indicates that ADC module 1 input pin 10 is present.
25
ADC1AIN9
RO
1
ADC Module 1 AIN9 Pin Present
When set, indicates that ADC module 1 input pin 9 is present.
24
ADC1AIN8
RO
1
ADC Module 1 AIN8 Pin Present
When set, indicates that ADC module 1 input pin 8 is present.
23
ADC1AIN7
RO
1
ADC Module 1 AIN7 Pin Present
When set, indicates that ADC module 1 input pin 7 is present.
22
ADC1AIN6
RO
1
ADC Module 1 AIN6 Pin Present
When set, indicates that ADC module 1 input pin 6 is present.
21
ADC1AIN5
RO
1
ADC Module 1 AIN5 Pin Present
When set, indicates that ADC module 1 input pin 5 is present.
20
ADC1AIN4
RO
1
ADC Module 1 AIN4 Pin Present
When set, indicates that ADC module 1 input pin 4 is present.
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Bit/Field
Name
Type
Reset
19
ADC1AIN3
RO
1
Description
ADC Module 1 AIN3 Pin Present
When set, indicates that ADC module 1 input pin 3 is present.
18
ADC1AIN2
RO
1
ADC Module 1 AIN2 Pin Present
When set, indicates that ADC module 1 input pin 2 is present.
17
ADC1AIN1
RO
1
ADC Module 1 AIN1 Pin Present
When set, indicates that ADC module 1 input pin 1 is present.
16
ADC1AIN0
RO
1
ADC Module 1 AIN0 Pin Present
When set, indicates that ADC module 1 input pin 0 is present.
15
ADC0AIN15
RO
1
ADC Module 0 AIN15 Pin Present
When set, indicates that ADC module 0 input pin 15 is present.
14
ADC0AIN14
RO
1
ADC Module 0 AIN14 Pin Present
When set, indicates that ADC module 0 input pin 14 is present.
13
ADC0AIN13
RO
1
ADC Module 0 AIN13 Pin Present
When set, indicates that ADC module 0 input pin 13 is present.
12
ADC0AIN12
RO
1
ADC Module 0 AIN12 Pin Present
When set, indicates that ADC module 0 input pin 12 is present.
11
ADC0AIN11
RO
1
ADC Module 0 AIN11 Pin Present
When set, indicates that ADC module 0 input pin 11 is present.
10
ADC0AIN10
RO
1
ADC Module 0 AIN10 Pin Present
When set, indicates that ADC module 0 input pin 10 is present.
9
ADC0AIN9
RO
1
ADC Module 0 AIN9 Pin Present
When set, indicates that ADC module 0 input pin 9 is present.
8
ADC0AIN8
RO
1
ADC Module 0 AIN8 Pin Present
When set, indicates that ADC module 0 input pin 8 is present.
7
ADC0AIN7
RO
1
ADC Module 0 AIN7 Pin Present
When set, indicates that ADC module 0 input pin 7 is present.
6
ADC0AIN6
RO
1
ADC Module 0 AIN6 Pin Present
When set, indicates that ADC module 0 input pin 6 is present.
5
ADC0AIN5
RO
1
ADC Module 0 AIN5 Pin Present
When set, indicates that ADC module 0 input pin 5 is present.
4
ADC0AIN4
RO
1
ADC Module 0 AIN4 Pin Present
When set, indicates that ADC module 0 input pin 4 is present.
3
ADC0AIN3
RO
1
ADC Module 0 AIN3 Pin Present
When set, indicates that ADC module 0 input pin 3 is present.
2
ADC0AIN2
RO
1
ADC Module 0 AIN2 Pin Present
When set, indicates that ADC module 0 input pin 2 is present.
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Bit/Field
Name
Type
Reset
1
ADC0AIN1
RO
1
Description
ADC Module 0 AIN1 Pin Present
When set, indicates that ADC module 0 input pin 1 is present.
0
ADC0AIN0
RO
1
ADC Module 0 AIN0 Pin Present
When set, indicates that ADC module 0 input pin 0 is present.
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Register 26: Device Capabilities 9 ADC Digital Comparators (DC9), offset
0x190
This register is predefined by the part and can be used to verify features.
Device Capabilities 9 ADC Digital Comparators (DC9)
Base 0x400F.E000
Offset 0x190
Type RO, reset 0x00FF.00FF
31
30
29
28
27
26
25
24
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
ADC1DC7 ADC1DC6 ADC1DC5 ADC1DC4 ADC1DC3 ADC1DC2 ADC1DC1 ADC1DC0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
ADC0DC7 ADC0DC6 ADC0DC5 ADC0DC4 ADC0DC3 ADC0DC2 ADC0DC1 ADC0DC0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23
ADC1DC7
RO
1
ADC1 DC7 Present
When set, indicates that ADC module 1 Digital Comparator 7 is present.
22
ADC1DC6
RO
1
ADC1 DC6 Present
When set, indicates that ADC module 1 Digital Comparator 6 is present.
21
ADC1DC5
RO
1
ADC1 DC5 Present
When set, indicates that ADC module 1 Digital Comparator 5 is present.
20
ADC1DC4
RO
1
ADC1 DC4 Present
When set, indicates that ADC module 1 Digital Comparator 4 is present.
19
ADC1DC3
RO
1
ADC1 DC3 Present
When set, indicates that ADC module 1 Digital Comparator 3 is present.
18
ADC1DC2
RO
1
ADC1 DC2 Present
When set, indicates that ADC module 1 Digital Comparator 2 is present.
17
ADC1DC1
RO
1
ADC1 DC1 Present
When set, indicates that ADC module 1 Digital Comparator 1 is present.
16
ADC1DC0
RO
1
ADC1 DC0 Present
When set, indicates that ADC module 1 Digital Comparator 0 is present.
15:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
ADC0DC7
RO
1
ADC0 DC7 Present
When set, indicates that ADC module 0 Digital Comparator 7 is present.
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Bit/Field
Name
Type
Reset
6
ADC0DC6
RO
1
Description
ADC0 DC6 Present
When set, indicates that ADC module 0 Digital Comparator 6 is present.
5
ADC0DC5
RO
1
ADC0 DC5 Present
When set, indicates that ADC module 0 Digital Comparator 5 is present.
4
ADC0DC4
RO
1
ADC0 DC4 Present
When set, indicates that ADC module 0 Digital Comparator 4 is present.
3
ADC0DC3
RO
1
ADC0 DC3 Present
When set, indicates that ADC module 0 Digital Comparator 3 is present.
2
ADC0DC2
RO
1
ADC0 DC2 Present
When set, indicates that ADC module 0 Digital Comparator 2 is present.
1
ADC0DC1
RO
1
ADC0 DC1 Present
When set, indicates that ADC module 0 Digital Comparator 1 is present.
0
ADC0DC0
RO
1
ADC0 DC0 Present
When set, indicates that ADC module 0 Digital Comparator 0 is present.
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Register 27: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0
This register is predefined by the part and can be used to verify features.
Non-Volatile Memory Information (NVMSTAT)
Base 0x400F.E000
Offset 0x1A0
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
FWB
RO
1
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
FWB
RO
1
32 Word Flash Write Buffer Active
When set, indicates that the 32 word Flash memory write buffer feature
is active.
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Register 28: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31
30
29
reserved
Type
Reset
28
WDT1
26
24
23
22
21
20
19
18
16
CAN1
CAN0
ADC1
ADC0
RO
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
MAXADC1SPD
MAXADC0SPD
R/W
0
R/W
0
R/W
0
R/W
0
reserved
17
RO
0
RO
0
reserved
25
RO
0
reserved
Type
Reset
27
reserved
HIB
RO
0
R/W
1
reserved
RO
0
RO
0
WDT0
R/W
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
R/W
0
WDT1 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 1. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
R/W
0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
24
CAN0
R/W
0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Bit/Field
Name
Type
Reset
Description
23:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
ADC1
R/W
0
ADC1 Clock Gating Control
This bit controls the clock gating for SAR ADC module 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
16
ADC0
R/W
0
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10
MAXADC1SPD
R/W
0
ADC1 Sample Speed
This field sets the rate at which ADC module 1 samples data. You cannot
set the rate higher than the maximum rate. You can set the sample rate
by setting the MAXADC1SPD bit as follows (all other encodings are
reserved):
Value Description
9:8
MAXADC0SPD
R/W
0
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
ADC0 Sample Speed
This field sets the rate at which ADC0 samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADC0SPD bit as follows (all other encodings are reserved):
Value Description
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
HIB
R/W
1
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
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Bit/Field
Name
Type
Reset
Description
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
R/W
0
WDT0 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 0. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 29: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31
30
29
reserved
Type
Reset
28
WDT1
RO
0
RO
0
RO
0
R/W
0
15
14
13
12
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
27
26
reserved
RO
0
RO
0
11
10
25
24
CAN1
CAN0
R/W
0
R/W
0
9
8
MAXADC1SPD
MAXADC0SPD
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
reserved
RO
0
RO
0
RO
0
RO
0
5
4
7
6
reserved
HIB
RO
0
R/W
1
reserved
RO
0
RO
0
RO
0
RO
0
3
2
WDT0
R/W
0
17
16
ADC1
ADC0
R/W
0
R/W
0
1
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
R/W
0
WDT1 Clock Gating Control
This bit controls the clock gating for Watchdog Timer module 1. If set,
the module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
R/W
0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
24
CAN0
R/W
0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Bit/Field
Name
Type
Reset
Description
23:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
ADC1
R/W
0
ADC1 Clock Gating Control
This bit controls the clock gating for ADC module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
16
ADC0
R/W
0
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10
MAXADC1SPD
R/W
0
ADC1 Sample Speed
This field sets the rate at which ADC module 1 samples data. You cannot
set the rate higher than the maximum rate. You can set the sample rate
by setting the MAXADC1SPD bit as follows (all other encodings are
reserved):
Value Description
9:8
MAXADC0SPD
R/W
0
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
ADC0 Sample Speed
This field sets the rate at which ADC module 0 samples data. You cannot
set the rate higher than the maximum rate. You can set the sample rate
by setting the MAXADC0SPD bit as follows (all other encodings are
reserved):
Value Description
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
HIB
R/W
1
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
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Bit/Field
Name
Type
Reset
Description
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
R/W
0
WDT0 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 0. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 30: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31
30
29
reserved
Type
Reset
28
WDT1
RO
0
RO
0
RO
0
R/W
0
15
14
13
12
27
26
reserved
25
24
CAN1
CAN0
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
11
10
9
8
7
RO
0
RO
0
RO
0
20
RO
0
RO
0
RO
0
6
5
4
HIB
RO
0
21
19
18
reserved
reserved
Type
Reset
22
RO
0
R/W
1
reserved
RO
0
RO
0
RO
0
RO
0
3
2
WDT0
R/W
0
17
16
ADC1
ADC0
R/W
0
R/W
0
1
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
R/W
0
WDT1 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 1. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
R/W
0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
24
CAN0
R/W
0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Bit/Field
Name
Type
Reset
Description
23:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
ADC1
R/W
0
ADC1 Clock Gating Control
This bit controls the clock gating for ADC module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
16
ADC0
R/W
0
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
HIB
R/W
1
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
R/W
0
WDT0 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 0. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 31: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
23
22
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
RO
0
RO
0
RO
0
21
20
19
18
17
16
R/W
0
RO
0
RO
0
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
SSI1
SSI0
reserved
UART2
UART1
UART0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
reserved
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
R/W
0
EPI0 Clock Gating
This bit controls the clock gating for EPI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
R/W
0
I2S0 Clock Gating
This bit controls the clock gating for I2S module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
26
COMP2
R/W
0
Description
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
25
COMP1
R/W
0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
17
TIMER1
R/W
0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Bit/Field
Name
Type
Reset
Description
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
R/W
0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
1
UART1
R/W
0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0
UART0
R/W
0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Register 32: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
11
10
9
8
7
6
15
14
13
12
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
23
22
reserved
RO
0
RO
0
RO
0
RO
0
21
20
reserved
RO
0
RO
0
RO
0
RO
0
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
0
SSI1
SSI0
reserved
UART2
UART1
UART0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
R/W
0
EPI0 Clock Gating
This bit controls the clock gating for EPI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
R/W
0
I2S0 Clock Gating
This bit controls the clock gating for I2S module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
26
COMP2
R/W
0
Description
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
25
COMP1
R/W
0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
17
TIMER1
R/W
0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Bit/Field
Name
Type
Reset
Description
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
R/W
0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
1
UART1
R/W
0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0
UART0
R/W
0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Register 33: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
11
10
9
8
7
6
15
14
13
12
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
23
22
reserved
RO
0
RO
0
RO
0
RO
0
21
20
reserved
RO
0
RO
0
RO
0
RO
0
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
0
SSI1
SSI0
reserved
UART2
UART1
UART0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
R/W
0
EPI0 Clock Gating
This bit controls the clock gating for EPI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
R/W
0
I2S0 Clock Gating
This bit controls the clock gating for I2S module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
26
COMP2
R/W
0
Description
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
25
COMP1
R/W
0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
17
TIMER1
R/W
0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Bit/Field
Name
Type
Reset
Description
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
R/W
0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
1
UART1
R/W
0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0
UART0
R/W
0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Register 34: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
15
14
13
reserved
Type
Reset
RO
0
RO
0
27
26
25
24
23
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
12
11
10
9
8
RO
0
RO
0
UDMA
R/W
0
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
reserved
RO
0
RO
0
16
USB0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
27:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
16
USB0
R/W
0
Description
USB0 Clock Gating Control
This bit controls the clock gating for USB module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
12:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
R/W
0
Port J Clock Gating Control
This bit controls the clock gating for Port J. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
7
GPIOH
R/W
0
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
6
GPIOG
R/W
0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
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Bit/Field
Name
Type
Reset
2
GPIOC
R/W
0
Description
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
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System Control
Register 35: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
R/W
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
reserved
Type
Reset
RO
0
RO
0
UDMA
R/W
0
27
26
25
23
22
21
20
19
18
17
reserved
reserved
RO
0
24
RO
0
RO
0
RO
0
RO
0
RO
0
16
USB0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
8
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
27:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
16
USB0
R/W
0
Description
USB0 Clock Gating Control
This bit controls the clock gating for USB module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
12:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
R/W
0
Port J Clock Gating Control
This bit controls the clock gating for Port J. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
7
GPIOH
R/W
0
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
6
GPIOG
R/W
0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
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System Control
Bit/Field
Name
Type
Reset
2
GPIOC
R/W
0
Description
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
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Register 36: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
R/W
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
reserved
Type
Reset
RO
0
RO
0
UDMA
R/W
0
27
26
25
23
22
21
20
19
18
17
reserved
reserved
RO
0
24
RO
0
RO
0
RO
0
RO
0
RO
0
16
USB0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
8
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
27:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
16
USB0
R/W
0
Description
USB0 Clock Gating Control
This bit controls the clock gating for USB module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
12:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
R/W
0
Port J Clock Gating Control
This bit controls the clock gating for Port J. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
7
GPIOH
R/W
0
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
6
GPIOG
R/W
0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
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Bit/Field
Name
Type
Reset
2
GPIOC
R/W
0
Description
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
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Register 37: Software Reset Control 0 (SRCR0), offset 0x040
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31
30
29
reserved
Type
Reset
28
WDT1
27
26
reserved
25
24
23
22
21
19
18
reserved
17
16
CAN1
CAN0
ADC1
ADC0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
reserved
Type
Reset
20
HIB
RO
0
reserved
RO
0
RO
0
WDT0
R/W
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
R/W
0
WDT1 Reset Control
When this bit is set, Watchdog Timer module 1 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
R/W
0
CAN1 Reset Control
When this bit is set, CAN module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
24
CAN0
R/W
0
CAN0 Reset Control
When this bit is set, CAN module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
23:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
ADC1
R/W
0
ADC1 Reset Control
When this bit is set, ADC module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
16
ADC0
R/W
0
ADC0 Reset Control
When this bit is set, ADC module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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Bit/Field
Name
Type
Reset
Description
15:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
HIB
R/W
0
HIB Reset Control
When this bit is set, the Hibernation module is reset. All internal data is
lost and the registers are returned to their reset states.This bit must be
manually cleared after being set.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
R/W
0
WDT0 Reset Control
When this bit is set, Watchdog Timer module 0 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 38: Software Reset Control 1 (SRCR1), offset 0x044
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
23
22
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
RO
0
RO
0
RO
0
21
20
19
18
17
16
R/W
0
RO
0
RO
0
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
SSI1
SSI0
reserved
UART2
UART1
UART0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
reserved
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
R/W
0
EPI0 Reset Control
When this bit is set, EPI module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
R/W
0
I2S0 Reset Control
When this bit is set, I2S module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
COMP2
R/W
0
Analog Comp 2 Reset Control
When this bit is set, Analog Comparator module 2 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
25
COMP1
R/W
0
Analog Comp 1 Reset Control
When this bit is set, Analog Comparator module 1 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
24
COMP0
R/W
0
Analog Comp 0 Reset Control
When this bit is set, Analog Comparator module 0 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
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Bit/Field
Name
Type
Reset
Description
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Reset Control
Timer 3 Reset Control. When this bit is set, General-Purpose Timer
module 3 is reset. All internal data is lost and the registers are returned
to their reset states. This bit must be manually cleared after being set.
18
TIMER2
R/W
0
Timer 2 Reset Control
When this bit is set, General-Purpose Timer module 2 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
17
TIMER1
R/W
0
Timer 1 Reset Control
When this bit is set, General-Purpose Timer module 1 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
16
TIMER0
R/W
0
Timer 0 Reset Control
When this bit is set, General-Purpose Timer module 0 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Reset Control
When this bit is set, I2C module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Reset Control
When this bit is set, I2C module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Reset Control
When this bit is set, SSI module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
4
SSI0
R/W
0
SSI0 Reset Control
When this bit is set, SSI module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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Bit/Field
Name
Type
Reset
Description
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
R/W
0
UART2 Reset Control
When this bit is set, UART module 2 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
1
UART1
R/W
0
UART1 Reset Control
When this bit is set, UART module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
0
UART0
R/W
0
UART0 Reset Control
When this bit is set, UART module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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Register 39: Software Reset Control 2 (SRCR2), offset 0x048
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
15
14
13
reserved
Type
Reset
RO
0
RO
0
27
26
25
24
23
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
12
11
10
9
8
RO
0
RO
0
UDMA
R/W
0
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
reserved
RO
0
RO
0
16
USB0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Reset Control
When this bit is set, Ethernet PHY layer 0 is reset. All internal data is
lost and the registers are returned to their reset states. This bit must be
manually cleared after being set.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Reset Control
When this bit is set, Ethernet MAC layer 0 is reset. All internal data is
lost and the registers are returned to their reset states. This bit must be
manually cleared after being set.
27:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
USB0
R/W
0
USB0 Reset Control
When this bit is set, USB module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
Micro-DMA Reset Control
When this bit is set, uDMA module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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Bit/Field
Name
Type
Reset
Description
12:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
R/W
0
Port J Reset Control
When this bit is set, Port J module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
7
GPIOH
R/W
0
Port H Reset Control
When this bit is set, Port H module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
6
GPIOG
R/W
0
Port G Reset Control
When this bit is set, Port G module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
5
GPIOF
R/W
0
Port F Reset Control
When this bit is set, Port F module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
4
GPIOE
R/W
0
Port E Reset Control
When this bit is set, Port E module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
3
GPIOD
R/W
0
Port D Reset Control
When this bit is set, Port D module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
2
GPIOC
R/W
0
Port C Reset Control
When this bit is set, Port C module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
1
GPIOB
R/W
0
Port B Reset Control
When this bit is set, Port B module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
0
GPIOA
R/W
0
Port A Reset Control
When this bit is set, Port A module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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6
Hibernation Module
The Hibernation Module manages removal and restoration of power to provide a means for reducing
power consumption. When the processor and peripherals are idle, power can be completely removed
with only the Hibernation module remaining powered. Power can be restored based on an external
signal or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can
be independently supplied from a battery or an auxiliary power supply.
The Hibernation module has the following features:
■ 32-bit real-time counter (RTC)
– Two 32-bit RTC match registers for timed wake-up and interrupt generation
– RTC predivider trim for making fine adjustments to the clock rate
■ Two mechanisms for power control
– System power control using discrete external regulator
– On-chip power control using internal switches under register control
■ Dedicated pin for waking using an external signal
■ RTC operational and hibernation memory valid as long as VBAT is valid
■ Low-battery detection, signaling, and interrupt generation
■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal; 32.768-kHz
external oscillator can be used for main controller clock
■ 64 32-bit words of battery-backed memory to save state during hibernation
■ Programmable interrupts for RTC match, external wake, and low battery events
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6.1
Block Diagram
Figure 6-1. Hibernation Module Block Diagram
HIBCTL.CLK32EN
XOSC0
Interrupts
HIBIM
HIBRIS
HIBMIS
HIBIC
Pre-Divider
XOSC1
HIBRTCT
/128
HIBCTL.CLKSEL
Battery-Backed
Memory
64 words
HIBDATA
RTC
HIBRTCC
HIBRTCLD
HIBRTCM0
HIBRTCM1
Clock Source for
System Clock
Interrupts
to CPU
MATCH0/1
HIBCTL.RTCEN
WAKE
LOWBAT
Power
Sequence
Logic
Low Battery
Detect
VBAT
HIBCTL.LOWBATEN
HIB
HIBCTL.PWRCUT
HIBCTL.RTCWEN
HIBCTL.PINWEN
HIBCTL.VABORT
HIBCTL.HIBREQ
6.2
Signal Description
The following table lists the external signals of the Hibernation module and describes the function
of each. These signals have dedicated functions and are not alternate functions for any GPIO signals.
Table 6-1. Hibernate Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
HIB
51
fixed
O
OD
An output that indicates the processor is in
Hibernate mode.
VBAT
55
fixed
-
Power
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
WAKE
50
fixed
I
TTL
An external input that brings the processor out of
Hibernate mode when asserted.
XOSC0
52
fixed
I
Analog
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a 4.194304-MHz crystal or a 32.768-kHz
oscillator for the Hibernation module RTC. See the
CLKSEL bit in the HIBCTL register.
XOSC1
53
fixed
O
Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
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Table 6-2. Hibernate Signals (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
HIB
M12
fixed
O
OD
An output that indicates the processor is in
Hibernate mode.
VBAT
L12
fixed
-
Power
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
WAKE
M10
fixed
I
TTL
An external input that brings the processor out of
Hibernate mode when asserted.
XOSC0
K11
fixed
I
Analog
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a 4.194304-MHz crystal or a 32.768-kHz
oscillator for the Hibernation module RTC. See the
CLKSEL bit in the HIBCTL register.
XOSC1
K12
fixed
O
Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
6.3
Functional Description
The Hibernation module provides two mechanisms for power control:
■ The first mechanism controls the power to the microcontroller with a control signal (HIB) that
signals an external voltage regulator to turn on or off.
■ The second mechanism uses internal switches to control power to the Cortex-M3 as well as to
most analog and digital functions while retaining I/O pin power (VDD3ON mode).
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage
source (VBAT). The Hibernation module also has an independent clock source to maintain a real-time
clock (RTC) when the system clock is powered down.
Once in hibernation, the module signals an external voltage regulator to turn the power back on
when an external pin (WAKE) is asserted or when the internal RTC reaches a certain value. The
Hibernation module can also detect when the battery voltage is low and optionally prevent hibernation
when this occurs.
When waking from hibernation, the HIB signal is deasserted. The return of VDD causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TIRPOR).
6.3.1
Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is tHIB_REG_ACCESS, therefore
software must guarantee that this delay is inserted between back-to-back writes to certain Hibernation
registers or between a write followed by a read to those same registers. Software may make use
of the WRC bit in the Hibernation Control (HIBCTL) register to ensure that the required timing gap
has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to
software that another write or read may be started safely. Software should poll HIBCTL for WRC=1
prior to accessing any affected register. The following registers are subject to this timing restriction:
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■ Hibernation RTC Counter (HIBRTCC)
■ Hibernation RTC Match 0 (HIBRTCM0)
■ Hibernation RTC Match 1 (HIBRTCM1)
■ Hibernation RTC Load (HIBRTCLD)
■ Hibernation RTC Trim (HIBRTCT)
■ Hibernation Data (HIBDATA)
Back-to-back reads from Hibernation module registers have no timing restrictions. Reads are
performed at the full peripheral clock rate.
6.3.2
Hibernation Clock Source
In systems where the Hibernation module is used to put the microcontroller into hibernation, the
module must be clocked by an external source that is independent from the main system clock,
even if the RTC feature is not used. An external oscillator or crystal is used for this purpose. To use
a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is
divided by 128 internally to produce a 32.768-kHz Hibernation clock reference. Alternatively, a
32.768-kHz oscillator can be connected to the XOSC0 pin, leaving XOSC1 unconnected. Care must
be taken that the voltage amplitude of the 32.768-kHz oscillator is less than VBAT, otherwise, the
Hibernation module may draw power from the oscillator and not VBAT during hibernation. See Figure
6-2 on page 297 and Figure 6-3 on page 297.
The Hibernation clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The
type of clock source is selected by clearing the CLKSEL bit for a 4.194304-MHz crystal and setting
the CLKSEL bit for a 32.768-kHz oscillator. If a crystal is used for the clock source, the software
must leave a delay of tHIBOSC_START after writing to the CLK32EN bit and before any other accesses
to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an
oscillator is used for the clock source, no delay is needed.
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Figure 6-2. Using a Crystal as the Hibernation Clock Source
Stellaris® Microcontroller
Regulator
or Switch
Input
Voltage
IN
OUT
VDD
EN
XOSC0
X1
RL
XOSC1
C1
C2
HIB
WAKE
RPU1
Open drain
external wake
up circuit
Note:
VBAT
GND
3V
Battery
RPU2
X1 = Crystal frequency is fXOSC_XTAL.
C1,2 = Capacitor value derived from crystal vendor load capacitance specifications.
RL = Load resistor is RXOSC_LOAD.
RPU1 = Pull-up resistor 1 (value and voltage source (VBAT or Input Voltage) determined by regulator
or switch enable input characteristics).
RPU2 = Pull-up resistor 2 is 200 kΩ
See “Hibernation Clock Source Specifications” on page 1229 for specific parameter values.
Figure 6-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode
Stellaris® Microcontroller
Regulator
Input
Voltage
IN
OUT
VDD
Clock
Source
XOSC0
(fEXT_OSC)
N.C.
XOSC1
HIB
WAKE
Open drain
external wake
up circuit
Note:
6.3.3
VBAT
GND
RPU
3V
Battery
RPU = Pull-up resistor is 1 MΩ
System Implementation
Several different system configurations are possible when using the Hibernation module:
■ Using a single battery source, where the battery provides both VDD and VBAT.
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■ Using the VDD3ON mode, where VDD continues to be powered in hibernation, allowing the GPIO
pins to retain their states, as shown in Figure 6-3 on page 297. In this mode, VDDC is powered off
internally.
■ Using separate sources for VDD and VBAT, as shown in Figure 6-2 on page 297.
■ Using a regulator to provide both VDD and VBAT with a switch enabled by HIB to remove VDD
during hibernation.
Adding external capacitance to the VBAT supply reduces the accuracy of the low-battery measurement
and should be avoided if possible. The diagrams referenced in this section only show the connection
to the Hibernation pins and not to the full system.
If the application does not require the use of the Hibernation module, refer to “Connections for
Unused Signals” on page 1218. In this situation, the HIB bit in the Run Mode Clock Gating Control
Register 0 (RCGC0) register must be cleared, disabling the system clock to the Hibernation module
and Hibernation module registers are not accessible.
6.3.4
Battery Management
Important: System-level factors may affect the accuracy of the low battery detect circuit. The
designer should consider battery type, discharge characteristics, and a test load during
battery voltage measurements.
The Hibernation module can be independently powered by a battery or an auxiliary power source
using the VBAT pin. The module can monitor the voltage level of the battery and detect when the
voltage drops below VLOWBAT. The module can also be configured so that it does not go into Hibernate
mode if the battery voltage drops below this threshold. Battery voltage is not measured while in
Hibernate mode.
The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN
bit of the HIBCTL register. In this configuration, the LOWBAT bit of the Hibernation Raw Interrupt
Status (HIBRIS) register is set when the battery level is low. If the VABORT bit in the HIBCTL register
is also set, then the module is prevented from entering Hibernate mode when a low battery is
detected. The module can also be configured to generate an interrupt for the low-battery condition
(see “Interrupts and Status” on page 300).
Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher
voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under
nominal conditions or else the Hibernation module draws power from the battery even when VDD is
available.
6.3.5
Real-Time Clock
The Hibernation module includes a 32-bit counter that increments once per second with the proper
configuration (see “Hibernation Clock Source” on page 296). The 32.768-kHz clock signal, either
directly from the 32.768-kHz oscillator or from the 4.194304-MHz crystal divided by 128, is fed into
a predivider register that counts down the 32.768-kHz clock ticks to achieve a once per second
clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock source
by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and
is used for one second out of every 64 seconds to divide the input clock. This configuration allows
the software to make fine corrections to the clock rate by adjusting the predivider trim register up
or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down
the RTC rate and down from 0x7FFF in order to speed up the RTC rate.
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The Hibernation module includes two 32-bit match registers that are compared to the value of the
RTC counter. The match registers can be used to wake the processor from Hibernate mode or to
generate an interrupt to the processor if it is not in hibernation.
The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be
set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading
and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust
the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1
registers. The RTC can be configured to generate interrupts by using the interrupt registers (see
“Interrupts and Status” on page 300). As long as the RTC is enabled and a valid VBAT is present, the
RTC continues counting, regardless of whether VDD is present or if the part is in hibernation.
6.3.6
Battery-Backed Memory
The Hibernation module contains 64 32-bit words of memory that are powered from the battery or
auxiliary power supply and therefore retained during hibernation. The processor software can save
state information in this memory prior to hibernation and recover the state upon waking. The
battery-backed memory can be accessed through the HIBDATA registers. If both VDD and VBAT are
removed, the contents of the HIBDATA registers are not retained.
6.3.7
Power Control Using HIB
Important: The Hibernation Module requires special system implementation considerations when
using HIB to control power, as it is intended to power-down all other sections of the
microcontroller. All system signals and power supplies that connect to the chip must
be driven to 0 VDC or powered down with the same regulator controlled by HIB.
The Hibernation module controls power to the microcontroller through the use of the HIB pin which
is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V to the
microcontroller and other circuits. When the HIB signal is asserted by the Hibernation module, the
external regulator is turned off and no longer powers the microcontroller and any parts of the system
that are powered by the regulator. The Hibernation module remains powered from the VBAT supply
(which could be a battery or an auxiliary power source) until a Wake event. Power to the
microcontroller is restored by deasserting the HIB signal, which causes the external regulator to
turn power back on to the chip.
6.3.8
Power Control Using VDD3ON Mode
The Hibernation module may also be configured to cut power to all internal modules. While in this
state, all pins are configured as inputs. In the VDD3ON mode, the regulator should maintain 3.3 V
power to the microcontroller during Hibernate. This power control mode is enabled by setting the
VDD3ON bit in HIBCTL.
6.3.9
Initiating Hibernate
Hibernate mode is initiated when the HIBREQ bit of the HIBCTL register is set. If a wake-up condition
has not been configured using the PINWEN or RTCWEN bits in the HIBCTL register, the hibernation
request is ignored. If a Flash memory write operation is in progress when the HIBREQ bit is set, an
interlock feature holds off the transition into Hibernate mode until the write has completed.
6.3.10
Waking from Hibernate
The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN
bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Note
that the WAKE pin uses the Hibernation module's internal power supply as the logic 1 reference.
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Upon either external wake-up or RTC match, the Hibernation module delays coming out of hibernation
until VDD is above the minimum specified voltage, see Table 25-2 on page 1222.
When the Hibernation module wakes, the microcontroller performs a normal power-on reset. Note
that this reset does not reset the Hibernation module, but does reset the rest of the microcontroller.
Software can detect that the power-on was due to a wake from hibernation by examining the raw
interrupt status register (see “Interrupts and Status” on page 300) and by looking for state data in
the battery-backed memory (see “Battery-Backed Memory” on page 299).
6.3.11
Interrupts and Status
The Hibernation module can generate interrupts when the following conditions occur:
■ Assertion of WAKE pin
■ RTC match
■ Low battery detected
All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate
module can only generate a single interrupt request to the controller at any given time. The software
interrupt handler can service multiple interrupt events by reading the Hibernation Masked Interrupt
Status (HIBMIS) register. Software can also read the status of the Hibernation module at any time
by reading the HIBRIS register which shows all of the pending events. This register can be used
after waking from hibernation to see if the wake condition was caused by the WAKE signal or the
RTC match.
The events that can trigger an interrupt are configured by setting the appropriate bits in the
Hibernation Interrupt Mask (HIBIM) register. Pending interrupts can be cleared by writing the
corresponding bit in the Hibernation Interrupt Clear (HIBIC) register.
6.4
Initialization and Configuration
The Hibernation module has several different configurations. The following sections show the
recommended programming sequence for various scenarios. The examples below assume that a
32.768-kHz oscillator is used, and thus always set the CLKSEL bit of the HIBCTL register. If a
4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the Hibernation
module runs at 32.768 kHz and is asynchronous to the rest of the microcontroller, which is run off
the system clock, software must allow a delay of tHIB_REG_ACCESS after writes to certain registers
(see “Register Access Timing” on page 295). The registers that require a delay are listed in a note
in “Register Map” on page 302 as well as in each register description.
6.4.1
Initialization
The Hibernation module comes out of reset with the system clock enabled to the module, but if the
system clock to the module has been disabled, then it must be re-enabled, even if the RTC feature
is not used. See page 260.
If a 4.194304-MHz crystal is used as the Hibernation module clock source, perform the following
step:
1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128
input path.
If a 32.678-kHz single-ended oscillator is used as the Hibernation module clock source, then perform
the following steps:
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1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input and bypass the
on-chip oscillator.
2. No delay is necessary.
The above steps are only necessary when the entire system is initialized for the first time. If the
microcontroller has been in hibernation, then the Hibernation module has already been powered
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.
Table 6-3 on page 301 illustrates how the clocks function with various bit setting both in normal
operation and in hibernation.
Table 6-3. Hibernation Module Clock Operation
CLK32EN PINWEN RTCWEN CLKSEL RTCEN Result Normal Operation
6.4.2
Result Hibernation
0
X
X
X
X
Hibernation module disabled
Hibernation module disabled
1
0
0
0
1
RTC match capability enabled.
Module clocked from
4.184304-MHz crystal.
No hibernation
1
0
0
1
1
RTC match capability enabled.
Module clocked from 32.768-kHz
oscillator.
No hibernation
1
0
1
X
1
Module clocked from selected
source
RTC match for wake-up event
1
1
0
X
0
Module clocked from selected
source
Clock is powered down during
hibernation and powered up again
on external wake-up event.
1
1
0
X
1
Module clocked from selected
source
Clock is powered up during
hibernation for RTC. Wake up on
external event.
1
1
1
X
1
Module clocked from selected
source
RTC match or external wake-up
event, whichever occurs first.
RTC Match Functionality (No Hibernation)
Use the following steps to implement the RTC match functionality of the Hibernation module:
1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the
HIBIM register at offset 0x014.
4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.
6.4.3
RTC Match/Wake-Up from Hibernation
Use the following steps to implement the RTC match and wake-up functionality of the Hibernation
module:
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
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3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
6.4.4
External Wake-Up from Hibernation
Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
Note that in this mode, if the RTC is disabled, then the Hibernation clock source is powered down
during Hibernate mode and is powered up again on the external wake event to save power during
hibernation. If the RTC is enabled before hibernation, it continues to operate during hibernation.
6.4.5
RTC or External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
6.5
Register Map
Table 6-4 on page 303 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000. Note that the system clock to the Hibernation module must
be enabled before the registers can be programmed (see page 260). There must be a delay of 3
system clocks after the Hibernation module clock is enabled before any Hibernation module registers
are accessed.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 295.
Important: The Hibernation module registers are reset under two conditions:
1. A system reset when the RTCEN and the PINWEN bits in the HIBCTL register are
both cleared.
2. A cold POR, when both the VDD and VBAT supplies are removed.
Any other reset condition is ignored by the Hibernation module.
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Table 6-4. Hibernation Module Register Map
Offset
Name
0x000
Reset
HIBRTCC
RO
0x0000.0000
Hibernation RTC Counter
304
0x004
HIBRTCM0
R/W
0xFFFF.FFFF
Hibernation RTC Match 0
305
0x008
HIBRTCM1
R/W
0xFFFF.FFFF
Hibernation RTC Match 1
306
0x00C
HIBRTCLD
R/W
0xFFFF.FFFF
Hibernation RTC Load
307
0x010
HIBCTL
R/W
0x8000.0000
Hibernation Control
308
0x014
HIBIM
R/W
0x0000.0000
Hibernation Interrupt Mask
311
0x018
HIBRIS
RO
0x0000.0000
Hibernation Raw Interrupt Status
313
0x01C
HIBMIS
RO
0x0000.0000
Hibernation Masked Interrupt Status
315
0x020
HIBIC
R/W1C
0x0000.0000
Hibernation Interrupt Clear
317
0x024
HIBRTCT
R/W
0x0000.7FFF
Hibernation RTC Trim
318
0x0300x12C
HIBDATA
R/W
-
Hibernation Data
319
6.6
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.
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Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000
This register is the current 32-bit value of the RTC counter.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 295.
Hibernation RTC Counter (HIBRTCC)
Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RTCC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RTCC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
31:0
RTCC
RO
RO
0
Reset
RO
0
Description
0x0000.0000 RTC Counter
A read returns the 32-bit counter value, which represents the seconds
elapsed since the RTC was enabled. This register is read-only. To
change the value, use the HIBRTCLD register.
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Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit match 0 register for the RTC counter.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 295.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCM0
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
RTCM0
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
RTCM0
R/W
R/W
1
Reset
R/W
1
Description
0xFFFF.FFFF RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
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Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008
This register is the 32-bit match 1 register for the RTC counter.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 295.
Hibernation RTC Match 1 (HIBRTCM1)
Base 0x400F.C000
Offset 0x008
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCM1
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
RTCM1
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
RTCM1
R/W
R/W
1
Reset
R/W
1
Description
0xFFFF.FFFF RTC Match 1
A write loads the value into the RTC match register.
A read returns the current match value.
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Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C
This register is used to load a 32-bit value loaded into the RTC counter. The load occurs immediately
upon this register being written.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 295.
Hibernation RTC Load (HIBRTCLD)
Base 0x400F.C000
Offset 0x00C
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCLD
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
RTCLD
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
RTCLD
R/W
R/W
1
Reset
R/W
1
Description
0xFFFF.FFFF RTC Load
A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.
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Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module. This register must be written last
before a hibernate event is issued. Writes to other registers after the HIBREQ bit is set are not
guaranteed to complete before hibernation is entered.
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x8000.0000
31
30
29
28
27
26
25
24
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WRC
Type
Reset
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
HIBREQ
RTCEN
R/W
0
R/W
0
reserved
reserved
Type
Reset
23
RO
0
VDD3ON VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL
Bit/Field
Name
Type
Reset
31
WRC
RO
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Write Complete/Capable
Value Description
0
The interface is processing a prior write and is busy. Any write
operation that is attempted while WRC is 0 results in
undetermined behavior.
1
The interface is ready to accept a write.
Software must poll this bit between write requests and defer writes until
WRC=1 to ensure proper operation.
The bit name WRC means "Write Complete," which is the normal use of
the bit (between write accesses). However, because the bit is set
out-of-reset, the name can also mean "Write Capable" which simply
indicates that the interface may be written to by software. This difference
may be exploited by software at reset time to detect which method of
programming is appropriate: 0 = software delay loops required; 1 = WRC
paced available.
30:9
reserved
RO
0x000
8
VDD3ON
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VDD Powered
Value Description
1
The internal switches control the power to the on-chip modules
(VDD3ON mode).
0
The internal switches are not used. The HIB signal should be
used to control an external switch or regulator.
Note that regardless of the status of the VDD3ON bit, the HIB signal is
asserted during Hibernate mode. Thus, when VDD3ON is set, the HIB
signal should not be connected to the 3.3V regulator, and the 3.3V power
source should remain connected.
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Bit/Field
Name
Type
Reset
7
VABORT
R/W
0
6
CLK32EN
R/W
0
Description
Power Cut Abort Enable
Value
Description
1
When this bit is set, the battery voltage level is checked
before entering hibernation. If VBAT is less than VLOWBAT,
the microcontroller does not go into hibernation.
0
The microcontroller goes into hibernation regardless of the
voltage level of the battery.
Clocking Enable
This bit must be enabled to use the Hibernation module.
5
4
3
2
LOWBATEN
PINWEN
RTCWEN
CLKSEL
R/W
R/W
R/W
R/W
0
0
0
0
Value
Description
1
The Hibernation module clock source is enabled.
0
The Hibernation module clock source is disabled.
Low Battery Monitoring Enable
Value
Description
1
Low battery voltage detection is enabled. When this bit is
set, the battery voltage level is checked before entering
hibernation. If VBAT is less than VLOWBAT, the LOWBAT bit
in the HIBRIS register is set.
0
Low battery monitoring is disabled.
External WAKE Pin Enable
Value
Description
1
An assertion of the WAKE pin takes the microcontroller
out of hibernation.
0
The status of the WAKE pin has no effect on hibernation.
RTC Wake-up Enable
Value
Description
1
An RTC match event (the value the HIBRTCC register
matches the value of the HIBRTCM0 or HIBRTCM1
register) takes the microcontroller out of hibernation.
0
An RTC match event has no effect on hibernation.
Hibernation Module Clock Select
Value
Description
1
Use raw output. Use this value for a 32.768-kHz
oscillator.
0
Use Divide-by-128 output. Use this value for a
4.194304-MHz crystal.
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Bit/Field
Name
Type
Reset
1
HIBREQ
R/W
0
Description
Hibernation Request
Value
Description
1
Set this bit to initiate hibernation.
0
No hibernation request.
After a wake-up event, this bit is automatically cleared by hardware.
A hibernation request is ignored if both the PINWEN and RTCWEN bits
are clear.
0
RTCEN
R/W
0
RTC Timer Enable
Value
Description
1
The Hibernation module RTC is enabled.
0
The Hibernation module RTC is disabled.
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Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources. Each bit in
this register masks the corresponding bit in the Hibernation Raw Interrupt Status (HIBRIS) register.
If a bit is unmasked, the interrupt is sent to the interrupt controller. If the bit is masked, the interrupt
is not sent to the interrupt controller.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
EXTW
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
EXTW
R/W
0
R/W
0
LOWBAT RTCALT1 RTCALT0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Interrupt Mask
Value Description
2
LOWBAT
R/W
0
1
An interrupt is sent to the interrupt controller when the EXTW bit
in the HIBRIS register is set.
0
The EXTW interrupt is suppressed and not sent to the interrupt
controller.
Low Battery Voltage Interrupt Mask
Value Description
1
RTCALT1
R/W
0
1
An interrupt is sent to the interrupt controller when the LOWBAT
bit in the HIBRIS register is set.
0
The LOWBAT interrupt is suppressed and not sent to the interrupt
controller.
RTC Alert 1 Interrupt Mask
Value Description
1
An interrupt is sent to the interrupt controller when the RTCALT1
bit in the HIBRIS register is set.
0
The RTCALT1 interrupt is suppressed and not sent to the
interrupt controller.
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Bit/Field
Name
Type
Reset
0
RTCALT0
R/W
0
Description
RTC Alert 0 Interrupt Mask
Value Description
1
An interrupt is sent to the interrupt controller when the RTCALT0
bit in the HIBRIS register is set.
0
The RTCALT0 interrupt is suppressed and not sent to the
interrupt controller.
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Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018
This register is the raw interrupt status for the Hibernation module interrupt sources. Each bit can
be masked by clearing the corresponding bit in the HIBIM register. When a bit is masked, the
interrupt is not sent to the interrupt controller. Bits in this register are cleared by writing a 1 to the
corresponding bit in the Hibernation Interrupt Clear (HIBIC) register or by entering hibernation.
Hibernation Raw Interrupt Status (HIBRIS)
Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
EXTW
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
EXTW
RO
0
RO
0
LOWBAT RTCALT1 RTCALT0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Raw Interrupt Status
Value Description
1
The WAKE pin has been asserted.
0
The WAKE pin has not been asserted.
This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.
2
LOWBAT
RO
0
Low Battery Voltage Raw Interrupt Status
Value Description
1
The battery voltage dropped below VLOWBAT.
0
The battery voltage has not dropped below VLOWBAT.
This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.
1
RTCALT1
RO
0
RTC Alert 1 Raw Interrupt Status
Value Description
1
The value of the HIBRTCC register matches the value in the
HIBRTCM1 register.
0
No match
This bit is cleared by writing a 1 to the RTCALT1 bit in the HIBIC register.
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Bit/Field
Name
Type
Reset
0
RTCALT0
RO
0
Description
RTC Alert 0 Raw Interrupt Status
Value Description
1
The value of the HIBRTCC register matches the value in the
HIBRTCM0 register.
0
No match
This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register.
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Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources. Bits in this
register are the AND of the corresponding bits in the HIBRIS and HIBIM registers. When both
corresponding bits are set, the bit in this register is set, and the interrupt is sent to the interrupt
controller.
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
EXTW
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
EXTW
RO
0
RO
0
LOWBAT RTCALT1 RTCALT0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to a WAKE pin
assertion.
0
An external wake-up interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.
2
LOWBAT
RO
0
Low Battery Voltage Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to a low battery voltage
condition.
0
A low battery voltage interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.
1
RTCALT1
RO
0
RTC Alert 1 Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to an RTC match.
0
An RTC match interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RTCALT1 bit in the HIBIC register.
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Bit/Field
Name
Type
Reset
0
RTCALT0
RO
0
Description
RTC Alert 0 Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to an RTC match.
0
An RTC match interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register.
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Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Writing a 1 to a bit clears the corresponding interrupt in the HIBRIS register.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
EXTW
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
EXTW
R/W1C
0
LOWBAT RTCALT1 RTCALT0
R/W1C
0
R/W1C
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Masked Interrupt Clear
Writing a 1 to this bit clears the EXTW bit in the HIBRIS and HIBMIS
registers.
Reads return an indeterminate value.
2
LOWBAT
R/W1C
0
Low Battery Voltage Masked Interrupt Clear
Writing a 1 to this bit clears the LOWBAT bit in the HIBRIS and HIBMIS
registers.
Reads return an indeterminate value.
1
RTCALT1
R/W1C
0
RTC Alert1 Masked Interrupt Clear
Writing a 1 to this bit clears the RTCALT1 bit in the HIBRIS and HIBMIS
registers.
Reads return an indeterminate value.
0
RTCALT0
R/W1C
0
RTC Alert0 Masked Interrupt Clear
Writing a 1 to this bit clears the RTCALT0 bit in the HIBRIS and HIBMIS
registers.
Reads return an indeterminate value.
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Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024
This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles, where N is the number of clock cycles to add or subtract every 63 seconds.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 295.
Hibernation RTC Trim (HIBRTCT)
Base 0x400F.C000
Offset 0x024
Type R/W, reset 0x0000.7FFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
TRIM
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TRIM
R/W
0x7FFF
RTC Trim Value
This value is loaded into the RTC predivider every 64 seconds. It is used
to adjust the RTC rate to account for drift and inaccuracy in the clock
source. Compensation can be adjusted by software by moving the default
value of 0x7FFF up or down. Moving the value up slows down the RTC
and moving the value down speeds up the RTC.
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Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C
This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store state information and does not lose power during a power cut
operation as long as a battery is present.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 295.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
RTD
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
RTD
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
31:0
RTD
R/W
-
R/W
-
Description
Hibernation Module NV Data
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Internal Memory
7
Internal Memory
The LM3S9U90 microcontroller comes with 96 KB of bit-banded SRAM, internal ROM,and 384 KB
of Flash memory. The Flash memory controller provides a user-friendly interface, making Flash
memory programming a simple task. Flash memory protection can be applied to the Flash memory
on a 2-KB block basis.
7.1
Block Diagram
Figure 7-1 on page 320 illustrates the internal memory blocks and control logic. The dashed boxes
in the figure indicate registers residing in the System Control module.
Figure 7-1. Internal Memory Block Diagram
ROM Control
ROM Array
RMCTL
Flash Control
Icode Bus
Cortex-M3
FMA
FMD
FMC
FCRIS
FCIM
FCMISC
Dcode Bus
Flash Array
System
Bus
Flash Write Buffer
FMC2
FWBVAL
FWBn
32 words
Flash Protection
Bridge
FMPREn
FMPRE
FMPPEn
FMPPE
User
Registers
Flash
Timing
BOOTCFG
USECRL
USER_REG0
USER_REG1
USER_REG2
USER_REG3
SRAM Array
7.2
Functional Description
This section describes the functionality of the SRAM, ROM, and Flash memories.
Note:
The μDMA controller can transfer data to and from the on-chip SRAM. However, because
the Flash memory and ROM are located on a separate internal bus, it is not possible to
transfer data from the Flash memory or ROM with the μDMA controller.
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7.2.1
SRAM
®
The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM provides
bit-banding technology in the processor. With a bit-band-enabled processor, certain regions in the
memory map (SRAM and peripheral space) can use address aliases to access individual bits in a
single, atomic operation. The bit-band base is located at address 0x2200.0000.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see “Bit-Banding” on page 92.
Note:
7.2.2
The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays).
The banks are partitioned such that one bank contains all even words (the even bank) and
the other contains all odd words (the odd bank). A write access that is followed immediately
by a read access to the same bank incurs a stall of a single clock cycle. However, a write
to one bank followed by a read of the other bank can occur in successive clock cycles
without incurring any delay.
ROM
The internal ROM of the Stellaris device is located at address 0x0100.0000 of the device memory
map. Detailed information on the ROM contents can be found in the Stellaris® ROM User’s Guide.
The ROM contains the following components:
■ Stellaris Boot Loader and vector table
■ Stellaris Peripheral Driver Library (DriverLib) release for product-specific peripherals and interfaces
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error detection functionality
The boot loader is used as an initial program loader (when the Flash memory is empty) as well as
an application-initiated firmware upgrade mechanism (by calling back to the boot loader). The
Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory
requirements and freeing the Flash memory to be used for other purposes (such as additional
features in the application). Advance Encryption Standard (AES) is a publicly defined encryption
standard used by the U.S. Government and Cyclic Redundancy Check (CRC) is a technique to
validate a span of data has the same contents as when previously checked.
7.2.2.1
Boot Loader Overview
The Stellaris Boot Loader is used to download code to the Flash memory of a device without the
use of a debug interface. When the core is reset, the user has the opportunity to direct the core to
execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal in Ports
A-H as configured in the Boot Configuration (BOOTCFG) register.
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Internal Memory
At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always
executed. The boot sequence executed from ROM is as follows:
1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is
mapped to address 0x0.
2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is
compared with the specified polarity. If the status matches the specified polarity, the ROM is
mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader.
3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and
if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and
execution continues out of the ROM Boot Loader.
4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded
from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from
address 0x0000.0004. The user application begins executing.
The boot loader uses a simple packet interface to provide synchronous communication with the
device. The speed of the boot loader is determined by the internal oscillator (PIOSC) frequency as
it does not enable the PLL. The following serial interfaces can be used:
■ UART0
■ SSI0
■ I2C0
■ Ethernet
For simplicity, both the data format and communication protocol are identical for all serial interfaces.
Note:
The Flash-memory-resident version of the Boot Loader also supports CAN and USB.
See the Stellaris® Boot Loader User's Guide for information on the boot loader software.
7.2.2.2
Stellaris Peripheral Driver Library
The Stellaris Peripheral Driver Library contains a file called driverlib/rom.h that assists with
calling the peripheral driver library functions in the ROM. The detailed description of each function
is available in the Stellaris® ROM User’s Guide. See the "Using the ROM" chapter of the Stellaris®
Peripheral Driver Library User's Guide for more details on calling the ROM functions and using
driverlib/rom.h.
A table at the beginning of the ROM points to the entry points for the APIs that are provided in the
ROM. Accessing the API through these tables provides scalability; while the API locations may
change in future versions of the ROM, the API tables will not. The tables are split into two levels;
the main table contains one pointer per peripheral which points to a secondary table that contains
one pointer per API that is associated with that peripheral. The main table is located at 0x0100.0010,
right after the Cortex-M3 vector table in the ROM.
DriverLib functions are described in detail in the Stellaris® Peripheral Driver Library User's Guide.
Additional APIs are available for graphics and USB functions, but are not preloaded into ROM. The
Stellaris Graphics Library provides a set of graphics primitives and a widget set for creating graphical
user interfaces on Stellaris microcontroller-based boards that have a graphical display (for more
information, see the Stellaris® Graphics Library User's Guide). The Stellaris USB Library is a set
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of data types and functions for creating USB Device, Host or On-The-Go (OTG) applications on
Stellaris microcontroller-based boards (for more information, see the Stellaris® USB Library User's
Guide).
7.2.2.3
Advanced Encryption Standard (AES) Cryptography Tables
AES is a strong encryption method with reasonable performance and size. AES is fast in both
hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for
applications that can use pre-arranged keys, such as setup during manufacturing or configuration.
Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the
forward S-box substitution table, the second is the reverse S-box substitution table, the third is the
forward polynomial table, and the final is the reverse polynomial table. See the Stellaris® ROM
User’s Guide for more information on AES.
7.2.2.4
Cyclic Redundancy Check (CRC) Error Detection
The CRC technique can be used to validate correct receipt of messages (nothing lost or modified
in transit), to validate data after decompression, to validate that Flash memory contents have not
been changed, and for other cases where the data needs to be validated. A CRC is preferred over
a simple checksum (e.g. XOR all bits) because it catches changes more readily. See the Stellaris®
ROM User’s Guide for more information on CRC.
7.2.3
Flash Memory
At system clock speeds of 50 MHz and below, the Flash memory is read in a single cycle. The Flash
memory is organized as a set of 1-KB blocks that can be individually erased. An individual 32-bit
word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability
to concurrently program 32 continuous words in Flash memory. Erasing a block causes the entire
contents of the block to be reset to all 1s. The 1-KB blocks are paired into sets of 2-KB blocks that
can be individually protected. The protection allows blocks to be marked as read-only or execute-only,
providing different levels of code protection. Read-only blocks cannot be erased or programmed,
protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased
or programmed and can only be read by the controller instruction fetch mechanism, protecting the
contents of those blocks from being read by either the controller or by a debugger.
Caution – The Stellaris Flash memory array has ECC which uses a test port into the Flash memory to
continually scan the array for ECC errors and to correct any that are detected. This operation is
transparent to the microcontroller. The BIST must scan the entire memory array occasionally to ensure
integrity, taking about five minutes to do so. In systems where the microcontroller is frequently powered
for less than five minutes, power should be removed from the microcontroller in a controlled manner
to ensure proper operation. This controlled manner can either be through entering Hibernate mode or
software can request permission to power down the part using the USDREQ bit in the Flash Control
(FCTL) register and wait to receive an acknowledge from the USDACK bit prior to removing power. If
the microcontroller is powered down using this controlled method, the BIST engine keeps track of
where it was in the memory array and it always scans the complete array after any aggregate of five
minutes powered-on, regardless of the number of intervening power cycles. If the microcontroller is
powered down before five minutes of being powered up, BIST starts again from wherever it left off
before the last controlled power-down or from 0 if there never was a controlled power down. An
occasional short power down is not a concern, but the microcontroller should not always be powered
down frequently in an uncontrolled manner. The microcontroller can be power-cycled as frequently
as necessary if it is powered-down in a controlled manner.
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7.2.3.1
Prefetch Buffer
The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency
is greater than 50 MHz. In this mode, the Flash memory operates at half of the system clock. The
prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait
states while code is executing linearly. The fetch buffer includes a branch speculation mechanism
that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short
loop branches often stay in the buffer. As a result, some branches can be executed with no wait
states. Other branches incur a single wait state.
7.2.3.2
Flash Memory Protection
The user is provided two forms of Flash memory protection per 2-KB Flash memory block in six
pairs of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per
policy per block) in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If a bit is set, the corresponding block
may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be
changed.
■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
The policies may be combined as shown in Table 7-1 on page 324.
Table 7-1. Flash Memory Protection Policy Combinations
FMPPEn
FMPREn
0
0
Protection
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
1
0
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
0
1
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
1
1
No protection. The block may be written, erased, executed or read.
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases. Note that if a
FMPREn bit is cleared, all read accesses to the Flash memory block are disallowed, including any
data accesses. Care must be taken not to store required data in a Flash memory block that has the
associated FMPREn bit cleared.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are effective immediately, but are not
permanent until the register is committed (saved), at which point the bit change is permanent. If a
bit is changed from a 1 to a 0 and not committed, it may be restored by executing any type of reset
sequence. The changes are committed using the Flash Memory Control (FMC) register. Details
on programming these bits are discussed in “Non-Volatile Register Programming” on page 327.
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7.2.3.3
Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 337) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 336).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 338).
7.2.3.4
Flash Memory Programming
The Stellaris devices provide a user-friendly interface for Flash memory programming. All
erase/program operations are handled via three registers: Flash Memory Address (FMA), Flash
Memory Data (FMD), and Flash Memory Control (FMC). Note that if the debug capabilities of the
microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be
performed in order to reactivate the debug module. See “Recovering a "Locked"
Microcontroller” on page 183.
During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory
is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation
is complete. If instruction execution is required during a Flash memory operation, the code that is
executing must be placed in SRAM and executed from there while the flash operation is in progress.
Caution – The Flash memory is divided into sectors of electrically separated address ranges of 4 KB
each, aligned on 4 KB boundaries. Erase/program operations on a 1-KB page have an electrical effect
on the other three 1-KB pages within the sector. A specific 1-KB page must be erased after 6 total
erase/program cycles occur to the other pages within its 4-KB sector. The following sequence of operations
on a 4-KB sector of Flash memory (Page 0..3) provides an example:
■ Page 3 is erase and programmed with values.
■ Page 0, Page 1, and Page 2 are erased and then programmed with values. At this point Page 3 has
been affected by 3 erase/program cycles.
■ Page 0, Page 1, and Page 2 are again erased and then programmed with values. At this point Page
3 has been affected by 6 erase/program cycles.
■ If the contents of Page 3 must continue to be valid, Page 3 must be erased and reprogrammed before
any other page in this sector has another erase or program operation.
To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
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3. Write the Flash memory write key and the WRITE bit (a value of 0xA442.0001) to the FMC
register.
4. Poll the FMC register until the WRITE bit is cleared.
Important: To ensure proper operation, two writes to the same word must be separated by an
ERASE. The following two sequences are allowed:
■ ERASE -> PROGRAM value -> PROGRAM 0x0000.0000
■ ERASE -> PROGRAM value -> ERASE
The following sequence is NOT allowed:
■ ERASE -> PROGRAM value -> PROGRAM value
To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the Flash memory write key and the ERASE bit (a value of 0xA442.0002) to the FMC
register.
3. Poll the FMC register until the ERASE bit is cleared or, alternatively, enable the programming
interrupt using the PMASK bit in the FCIM register.
To perform a mass erase of the Flash memory
1. Write the Flash memory write key and the MERASE bit (a value of 0xA442.0004) to the FMC
register.
2. Poll the FMC register until the MERASE bit is cleared or, alternatively, enable the programming
interrupt using the PMASK bit in the FCIM register.
7.2.3.5
32-Word Flash Memory Write Buffer
A 32-word write buffer provides the capability to perform faster write accesses to the Flash memory
by concurrently programing 32 words with a single buffered Flash memory write operation. The
buffered Flash memory write operation takes the same amount of time as the single word write
operation controlled by bit 0 in the FMC register. The data for the buffered write is written to the
Flash Write Buffer (FWBn) registers.
The registers are 32-word aligned with Flash memory, and therefore the register FWB0 corresponds
with the address in FMA where bits [6:0] of FMA are all 0. FWB1 corresponds with the address in
FMA + 0x4 and so on. Only the FWBn registers that have been updated since the previous buffered
Flash memory write operation are written. The Flash Write Buffer Valid (FWBVAL) register shows
which registers have been written since the last buffered Flash memory write operation. This register
contains a bit for each of the 32 FWBn registers, where bit[n] of FWBVAL corresponds to FWBn.
The FWBn register has been updated if the corresponding bit in the FWBVAL register is set.
To program 32 words with a single buffered Flash memory write operation
1. Write the source data to the FWBn registers.
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2. Write the target address to the FMA register. This must be a 32-word aligned address (that is,
bits [6:0] in FMA must be 0s).
3. Write the Flash memory write key and the WRBUF bit (a value of 0xA442.0001) to the FMC2
register.
4. Poll the FMC2 register until the WRBUF bit is cleared or wait for the PMIS interrupt to be signaled.
7.2.3.6
Non-Volatile Register Programming
Note:
The Boot Configuration (BOOTCFG) register requires a POR before the committed
changes take effect.
This section discusses how to update the registers shown in Table 7-2 on page 328 that are resident
within the Flash memory itself. These registers exist in a separate space from the main Flash memory
array and are not affected by an ERASE or MASS ERASE operation. With the exception of the Boot
Configuration (BOOTCFG) register, the settings in these registers can be written, their functions
verified, and their values read back before they are committed, at which point they become
non-volatile. If a value in one of these registers has not been committed, any type of reset restores
the last committed value or the default value if the register has never been committed. Once the
register contents are committed, the only way to restore the factory default values is to perform the
sequence described in “Recovering a "Locked" Microcontroller” on page 183.
To write to a non-volatile register:
■ Bits can only be changed from 1 to 0.
■ For all registers except the BOOTCFG register, write the data to the register address provided
in the register description. For the BOOTCFG register, write the data to the FMD register.
■ The registers can be read to verify their contents. To verify what is to be stored in the BOOTCFG
register, read the FMD register. Reading the BOOTCFG register returns the previously committed
value or the default value if the register has never been committed.
■ The new values are effectively immediately for all registers except BOOTCFG, as the new value
for the register is not stored in the register until it has been committed.
■ Prior to committing the register value, any type of reset restores the last committed value or the
default value if the register has never been committed.
To commit a new value to a non-volatile register:
■ Write the data as described above.
■ Write to the FMA register the value shown in Table 7-2 on page 328.
■ Write the Flash memory write key and set the COMT bit in the FMC register. These values must
be written to the FMC register at the same time.
■ Committing a non-volatile register has the same timing as a write to regular Flash memory,
defined by TPROG, as shown in Table 25-20 on page 1232. Software can poll the COMT bit in the
FMC register to determine when the operation is complete, or an interrupt can be enabled by
setting the PMASK bit in the FCIM register.
■ When committing the BOOTCFG register, the INVDRIS bit in the FCRIS register is set if a bit
that has already been committed as a 0 is attempted to be committed as a 1.
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■ Once the value has been committed, any type of reset has no effect on the register contents.
■ Changes to the BOOTCFG register are effective after the next reset.
■ The NW bit in the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and BOOTCFG
registers is cleared when the register is committed. Once this bit is cleared, additional changes
to the register are not allowed.
Important: After being committed, these registers can only be restored to their factory default values
by performing the sequence described in “Recovering a "Locked"
Microcontroller” on page 183. The mass erase of the main Flash memory array caused
by the sequence is performed prior to restoring these registers.
Table 7-2. User-Programmable Flash Memory Resident Registers
Register to be Committed
7.3
FMA Value
Data Source
FMPRE0
0x0000.0000
FMPRE0
FMPRE1
0x0000.0002
FMPRE1
FMPRE2
0x0000.0004
FMPRE2
FMPRE3
0x0000.0006
FMPRE3
FMPRE4
0x0000.0008
FMPRE4
FMPRE5
0x0000.000A
FMPRE5
FMPPE0
0x0000.0001
FMPPE0
FMPPE1
0x0000.0003
FMPPE1
FMPPE2
0x0000.0005
FMPPE2
FMPPE3
0x0000.0007
FMPPE3
FMPRE4
0x0000.0009
FMPRE4
FMPRE5
0x0000.000B
FMPRE5
USER_REG0
0x8000.0000
USER_REG0
USER_REG1
0x8000.0001
USER_REG1
USER_REG2
0x8000.0002
USER_REG2
USER_REG3
0x8000.0003
USER_REG3
BOOTCFG
0x7510.0000
FMD
Register Map
Table 7-3 on page 328 lists the ROM Controller register and the Flash memory and control registers.
The offset listed is a hexadecimal increment to the register's address. The Flash memory register
offsets are relative to the Flash memory control base address of 0x400F.D000. The ROM and Flash
memory protection register offsets are relative to the System Control base address of 0x400F.E000.
Table 7-3. Flash Register Map
Offset
Name
Type
Reset
Description
See
page
Flash Memory Registers (Flash Control Offset)
0x000
FMA
R/W
0x0000.0000
Flash Memory Address
331
0x004
FMD
R/W
0x0000.0000
Flash Memory Data
332
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Table 7-3. Flash Register Map (continued)
Description
See
page
Offset
Name
Type
Reset
0x008
FMC
R/W
0x0000.0000
Flash Memory Control
333
0x00C
FCRIS
RO
0x0000.0000
Flash Controller Raw Interrupt Status
336
0x010
FCIM
R/W
0x0000.0000
Flash Controller Interrupt Mask
337
0x014
FCMISC
R/W1C
0x0000.0000
Flash Controller Masked Interrupt Status and Clear
338
0x020
FMC2
R/W
0x0000.0000
Flash Memory Control 2
339
0x030
FWBVAL
R/W
0x0000.0000
Flash Write Buffer Valid
340
0x0F8
FCTL
R/W
0x0000.0000
Flash Control
341
0x100 0x17C
FWBn
R/W
0x0000.0000
Flash Write Buffer n
342
ROM Control
343
Memory Registers (System Control Offset)
0x0F0
RMCTL
R/W1C
-
0x130
FMPRE0
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
344
0x200
FMPRE0
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
344
0x134
FMPPE0
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
345
0x400
FMPPE0
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
345
0x1D0
BOOTCFG
R/W
0xFFFF.FFFE
Boot Configuration
346
0x1E0
USER_REG0
R/W
0xFFFF.FFFF
User Register 0
348
0x1E4
USER_REG1
R/W
0xFFFF.FFFF
User Register 1
349
0x1E8
USER_REG2
R/W
0xFFFF.FFFF
User Register 2
350
0x1EC
USER_REG3
R/W
0xFFFF.FFFF
User Register 3
351
0x204
FMPRE1
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 1
352
0x208
FMPRE2
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 2
353
0x20C
FMPRE3
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 3
354
0x210
FMPRE4
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 4
355
0x214
FMPRE5
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 5
356
0x218
FMPRE6
R/W
0x0000.0000
Flash Memory Protection Read Enable 6
357
0x21C
FMPRE7
R/W
0x0000.0000
Flash Memory Protection Read Enable 7
358
0x404
FMPPE1
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 1
359
0x408
FMPPE2
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 2
360
0x40C
FMPPE3
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 3
361
0x410
FMPPE4
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 4
362
0x414
FMPPE5
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 5
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Table 7-3. Flash Register Map (continued)
See
page
Offset
Name
Type
Reset
0x418
FMPPE6
R/W
0x0000.0000
Flash Memory Protection Program Enable 6
364
0x41C
FMPPE7
R/W
0x0000.0000
Flash Memory Protection Program Enable 7
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7.4
Description
Flash Memory Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned CPU byte address
and specifies which block is erased. Note that the alignment requirements must be met by software
or the results of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
25
24
23
22
21
20
19
18
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
17
16
OFFSET
OFFSET
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:19
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
18:0
OFFSET
R/W
0x0
Address Offset
Address offset in Flash memory where operation is performed, except
for non-volatile registers (see “Non-Volatile Register
Programming” on page 327 for details on values for this field).
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Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
31:0
DATA
R/W
Reset
Description
0x0000.0000 Data Value
Data value for write operation.
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Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the Flash memory controller initiates the appropriate access cycle for
the location specified by the Flash Memory Address (FMA) register (see page 331). If the access
is a write access, the data contained in the Flash Memory Data (FMD) register (see page 332) is
written to the specified address.
This register must be the final register written and initiates the memory operation. The four control
bits in the lower byte of this register are used to initiate memory operations.
Care must be taken not to set multiple control bits as the results of such an operation are
unpredictable.
Caution – If any of bits [15:4] are written to 1, the device may become inoperable. These bits should
always be written to 0. In all registers, the value of a reserved bit should be preserved across a
read-modify-write operation.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
COMT
MERASE
ERASE
WRITE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
WRKEY
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:16
WRKEY
WO
0x0000
Description
Flash Memory Write Key
This field contains a write key, which is used to minimize the incidence
of accidental Flash memory writes. The value 0xA442 must be written
into this field for a Flash memory write to occur. Writes to the FMC
register without this WRKEY value are ignored. A read of this field returns
the value 0.
15:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
3
COMT
R/W
0
Description
Commit Register Value
This bit is used to commit writes to Flash-memory-resident registers
and to monitor the progress of that process.
Value Description
1
Set this bit to commit (write) the register value to a
Flash-memory-resident register.
When read, a 1 indicates that the previous commit access is
not complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous commit access is
complete.
See “Non-Volatile Register Programming” on page 327 for more
information on programming Flash-memory-resident registers.
2
MERASE
R/W
0
Mass Erase Flash Memory
This bit is used to mass erase the Flash main memory and to monitor
the progress of that process.
Value Description
1
Set this bit to erase the Flash main memory.
When read, a 1 indicates that the previous mass erase access
is not complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous mass erase access
is complete.
For information on erase time, see “Flash Memory” on page 1232.
1
ERASE
R/W
0
Erase a Page of Flash Memory
This bit is used to erase a page of Flash memory and to monitor the
progress of that process.
Value Description
1
Set this bit to erase the Flash memory page specified by the
contents of the FMA register.
When read, a 1 indicates that the previous page erase access
is not complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous page erase access
is complete.
For information on erase time, see “Flash Memory” on page 1232.
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Bit/Field
Name
Type
Reset
0
WRITE
R/W
0
Description
Write a Word into Flash Memory
This bit is used to write a word into Flash memory and to monitor the
progress of that process.
Value Description
1
Set this bit to write the data stored in the FMD register into the
Flash memory location specified by the contents of the FMA
register.
When read, a 1 indicates that the write update access is not
complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous write update access
is complete.
For information on programming time, see “Flash Memory” on page 1232.
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Internal Memory
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the Flash memory controller has an interrupt condition. An interrupt is
sent to the interrupt controller only if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PRIS
ARIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
PRIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or erase
actions generated through the FMC or FMC2 register bits (see page 333
and page 339).
Value Description
1
The programming or erase cycle has completed.
0
The programming or erase cycle has not completed.
This status is sent to the interrupt controller when the PMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register.
0
ARIS
RO
0
Access Raw Interrupt Status
Value Description
1
A program or erase action was attempted on a block of Flash
memory that contradicts the protection policy for that block as
set in the FMPPEn registers.
0
No access has tried to improperly program or erase the Flash
memory.
This status is sent to the interrupt controller when the AMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register.
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Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the Flash memory controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PMASK
AMASK
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
PMASK
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the interrupt controller.
Value Description
0
AMASK
R/W
0
1
An interrupt is sent to the interrupt controller when the PRIS bit
is set.
0
The PRIS interrupt is suppressed and not sent to the interrupt
controller.
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
interrupt controller.
Value Description
1
An interrupt is sent to the interrupt controller when the ARIS bit
is set.
0
The ARIS interrupt is suppressed and not sent to the interrupt
controller.
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Internal Memory
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
PMISC
R/W1C
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
PMISC
AMISC
R/W1C
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Masked Interrupt Status and Clear
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
FCRIS register (see page 336).
0
When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
AMISC
R/W1C
0
Access Masked Interrupt Status and Clear
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because a program or erase action was attempted on
a block of Flash memory that contradicts the protection policy
for that block as set in the FMPPEn registers.
Writing a 1 to this bit clears AMISC and also the ARIS bit in the
FCRIS register (see page 336).
0
When read, a 0 indicates that no improper accesses have
occurred.
A write of 0 has no effect on the state of this bit.
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Register 7: Flash Memory Control 2 (FMC2), offset 0x020
When this register is written, the Flash memory controller initiates the appropriate access cycle for
the location specified by the Flash Memory Address (FMA) register (see page 331). If the access
is a write access, the data contained in the Flash Write Buffer (FWB) registers is written.
This register must be the final register written as it initiates the memory operation.
Flash Memory Control 2 (FMC2)
Base 0x400F.D000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
8
7
6
5
4
3
2
1
WRKEY
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:16
WRKEY
WO
0x0000
RO
0
0
WRBUF
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Description
Flash Memory Write Key
This field contains a write key, which is used to minimize the incidence
of accidental Flash memory writes. The value 0xA442 must be written
into this field for a write to occur. Writes to the FMC2 register without
this WRKEY value are ignored. A read of this field returns the value 0.
15:1
reserved
RO
0x000
0
WRBUF
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Buffered Flash Memory Write
This bit is used to start a buffered write to Flash memory.
Value Description
1
Set this bit to write the data stored in the FWBn registers to the
location specified by the contents of the FMA register.
When read, a 1 indicates that the previous buffered Flash
memory write access is not complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous buffered Flash
memory write access is complete.
For information on programming time, see “Flash Memory” on page 1232.
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Internal Memory
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030
This register provides a bitwise status of which FWBn registers have been written by the processor
since the last write of the Flash memory write buffer. The entries with a 1 are written on the next
write of the Flash memory write buffer. This register is cleared after the write operation by hardware.
A protection violation on the write operation also clears this status.
Software can program the same 32 words to various Flash memory locations by setting the FWB[n]
bits after they are cleared by the write operation. The next write operation then uses the same data
as the previous one. In addition, if a FWBn register change should not be written to Flash memory,
software can clear the corresponding FWB[n] bit to preserve the existing data when the next write
operation occurs.
Flash Write Buffer Valid (FWBVAL)
Base 0x400F.D000
Offset 0x030
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FWB[n]
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
FWB[n]
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:0
FWB[n]
R/W
0x0
R/W
0
Description
Flash Memory Write Buffer
Value Description
1
The corresponding FWBn register has been updated since the
last buffer write operation and is ready to be written to Flash
memory.
0
The corresponding FWBn register has no new data to be written.
Bit 0 corresponds to FWB0, offset 0x100, and bit 31 corresponds to
FWB31, offset 0x13C.
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Register 9: Flash Control (FCTL), offset 0x0F8
This register is used to ensure that the microcontroller is powered down in a controlled fashion in
systems where power is cycled more frequently than once every five minutes. The USDREQ bit
should be set to indicate that power is going to be turned off. Software should poll the USDACK bit
to determine when it is acceptable to power down.
Note that this power-down process is not required if the microcontroller enters Hibernate mode prior
to power being removed.
Flash Control (FCTL)
Base 0x400F.D000
Offset 0x0F8
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
USDACK
RO
0
USDACK USDREQ
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
User Shut Down Acknowledge
Value Description
1
The microcontroller can be powered down.
0
The microcontroller cannot yet be powered down.
This bit should be set within 50 ms of setting the USDREQ bit.
0
USDREQ
R/W
0
User Shut Down Request
Value Description
1
Requests permission to power down the microcontroller.
0
No effect.
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Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C
These 32 registers hold the contents of the data to be written into the Flash memory on a buffered
Flash memory write operation. The offset selects one of the 32-bit registers. Only FWBn registers
that have been updated since the preceding buffered Flash memory write operation are written into
the Flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or
2 words. The FWBn registers are written into the Flash memory with the FWB0 register corresponding
to the address contained in FMA. FWB1 is written to the address FMA+0x4 etc. Note that only data
bits that are 0 result in the Flash memory being modified. A data bit that is 1 leaves the content of
the Flash memory bit at its previous value.
Flash Write Buffer n (FWBn)
Base 0x400F.D000
Offset 0x100 - 0x17C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
31:0
DATA
R/W
Reset
Description
0x0000.0000 Data
Data to be written into the Flash memory.
7.5
Memory Register Descriptions (System Control Offset)
The remainder of this section lists and describes the registers that reside in the System Control
address space, in numerical order by address offset. Registers in this section are relative to the
System Control base address of 0x400F.E000.
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Register 11: ROM Control (RMCTL), offset 0x0F0
This register provides control of the ROM controller state. This register offset is relative to the System
Control base address of 0x400F.E000.
At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always
executed. The boot sequence executed from ROM is as follows:
1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is
mapped to address 0x0.
2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is
compared with the specified polarity. If the status matches the specified polarity, the ROM is
mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader.
3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and
if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and
execution continues out of the ROM Boot Loader.
4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded
from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from
address 0x0000.0004. The user application begins executing.
ROM Control (RMCTL)
Base 0x400F.E000
Offset 0x0F0
Type R/W1C, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
BA
R/W1C
1
RO
0
0
BA
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Boot Alias
Value Description
1
The microcontroller's ROM appears at address 0x0.
0
The Flash memory is at address 0x0.
This bit is cleared by writing a 1 to this bit position.
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Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note:
This register is aliased for backwards compatability.
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
For additional information, see “Flash Memory Protection” on page 324.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.E000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
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Register 13: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note:
This register is aliased for backwards compatability.
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
For additional information, see “Flash Memory Protection” on page 324.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.E000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PROG_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
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Internal Memory
Register 14: Boot Configuration (BOOTCFG), offset 0x1D0
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides configuration of a GPIO pin to enable the ROM Boot Loader as well as a
write-once mechanism to disable external debugger access to the device. Upon reset, the user has
the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory
by using any GPIO signal from Ports A-H as configured by the bits in this register. If the EN bit is
set or the specified pin does not have the required polarity, the system control module checks
address 0x000.0004 to see if the Flash memory has a valid reset vector. If the data at address
0x0000.0004 is 0xFFFF.FFFF, then it is assumed that the Flash memory has not yet been
programmed, and the core executes the ROM Boot Loader. The DBG0 bit (bit 0) is set to 0 from
the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Clearing the
DBG1 bit disables any external debugger access to the device permanently, starting with the next
power-up cycle of the device. The NW bit (bit 31) indicates that the register has not yet been
committed and is controlled through hardware to ensure that the register is only committed once.
Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies
to power-on reset; any other type of reset does not affect this register. Once committed, the only
way to restore the factory default value of this register is to perform the sequence detailed in
“Recovering a "Locked" Microcontroller” on page 183.
Boot Configuration (BOOTCFG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31
30
29
28
27
26
25
24
NW
Type
Reset
R/W
1
15
RO
1
RO
1
RO
1
14
13
12
PORT
Type
Reset
R/W
1
23
22
21
20
19
18
17
16
RO
1
RO
1
reserved
R/W
1
RO
1
RO
1
11
10
PIN
R/W
1
R/W
1
R/W
1
R/W
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
9
8
POL
EN
R/W
1
R/W
1
reserved
RO
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
RO
1
RO
1
RO
1
RO
1
RO
1
1
0
DBG1
DBG0
R/W
1
R/W
0
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:16
reserved
RO
0x7FFF
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
15:13
PORT
R/W
0x7
Description
Boot GPIO Port
This field selects the port of the GPIO port pin that enables the ROM
boot loader at reset.
Value Description
12:10
PIN
R/W
0x7
0x0
Port A
0x1
Port B
0x2
Port C
0x3
Port D
0x4
Port E
0x5
Port F
0x6
Port G
0x7
Port H
Boot GPIO Pin
This field selects the pin number of the GPIO port pin that enables the
ROM boot loader at reset.
Value Description
9
POL
R/W
0x1
0x0
Pin 0
0x1
Pin 1
0x2
Pin 2
0x3
Pin 3
0x4
Pin 4
0x5
Pin 5
0x6
Pin 6
0x7
Pin 7
Boot GPIO Polarity
When set, this bit selects a high level for the GPIO port pin to enable
the ROM boot loader at reset. When clear, this bit selects a low level
for the GPIO port pin.
8
EN
R/W
0x1
Boot GPIO Enable
Clearing this bit enables the use of a GPIO pin to enable the ROM Boot
Loader at reset. When this bit is set, the contents of address
0x0000.0004 are checked to see if the Flash memory has been
programmed. If the contents are not 0xFFFF.FFFF, the core executes
out of Flash memory. If the Flash has not been programmed, the core
executes out of ROM.
7:2
reserved
RO
0x3F
1
DBG1
R/W
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0
DBG0
R/W
0x0
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
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Internal Memory
Register 15: User Register 0 (USER_REG0), offset 0x1E0
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. Once committed, the only way to restore
the factory default value of this register is to perform the sequence detailed in “Recovering a "Locked"
Microcontroller” on page 183.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
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Register 16: User Register 1 (USER_REG1), offset 0x1E4
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
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Internal Memory
Register 17: User Register 2 (USER_REG2), offset 0x1E8
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 2 (USER_REG2)
Base 0x400F.E000
Offset 0x1E8
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
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Register 18: User Register 3 (USER_REG3), offset 0x1EC
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 3 (USER_REG3)
Base 0x400F.E000
Offset 0x1EC
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
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Internal Memory
Register 19: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but
software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
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Register 20: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 129 to 192 KB.
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Internal Memory
Register 21: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 193 to 256 KB.
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Stellaris LM3S9U90 Microcontroller
Register 22: Flash Memory Protection Read Enable 4 (FMPRE4), offset 0x210
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Read Enable 4 (FMPRE4)
Base 0x400F.E000
Offset 0x210
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 257 to 320 KB.
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Internal Memory
Register 23: Flash Memory Protection Read Enable 5 (FMPRE5), offset 0x214
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Read Enable 5 (FMPRE5)
Base 0x400F.E000
Offset 0x214
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 321 to 384 KB.
356
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Register 24: Flash Memory Protection Read Enable 6 (FMPRE6), offset 0x218
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Read Enable 6 (FMPRE6)
Base 0x400F.E000
Offset 0x218
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
0
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in Table 7-1 on page 324.
Value
Description
0x00000000 Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 385 to 448 KB.
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Internal Memory
Register 25: Flash Memory Protection Read Enable 7 (FMPRE7), offset 0x21C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Read Enable 7 (FMPRE7)
Base 0x400F.E000
Offset 0x21C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
0
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in Table 7-1 on page 324.
Value
Description
0x00000000 Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 449 to 512 KB.
358
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Stellaris LM3S9U90 Microcontroller
Register 26: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but
software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
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Internal Memory
Register 27: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 129 to 192 KB.
360
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®
Stellaris LM3S9U90 Microcontroller
Register 28: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 193 to 256 KB.
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Internal Memory
Register 29: Flash Memory Protection Program Enable 4 (FMPPE4), offset
0x410
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Program Enable 4 (FMPPE4)
Base 0x400F.E000
Offset 0x410
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 257 to 320 KB.
362
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®
Stellaris LM3S9U90 Microcontroller
Register 30: Flash Memory Protection Program Enable 5 (FMPPE5), offset
0x414
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Program Enable 5 (FMPPE5)
Base 0x400F.E000
Offset 0x414
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in Table 7-1 on page 324.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 321 to 384 KB.
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Internal Memory
Register 31: Flash Memory Protection Program Enable 6 (FMPPE6), offset
0x418
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Program Enable 6 (FMPPE6)
Base 0x400F.E000
Offset 0x418
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in Table 7-1 on page 324.
Value
Description
0x00000000 Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 385 to 448 KB.
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Register 32: Flash Memory Protection Program Enable 7 (FMPPE7), offset
0x41C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 183.
If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes,
but software should not rely on these bits to be zero. For additional information, see “Flash Memory
Protection” on page 324.
Flash Memory Protection Program Enable 7 (FMPPE7)
Base 0x400F.E000
Offset 0x41C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in Table 7-1 on page 324.
Value
Description
0x00000000 Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 449 to 512 KB.
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8
Micro Direct Memory Access (μDMA)
The LM3S9U90 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex™-M3 processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
®
®
■ ARM PrimeCell 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single
request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– Primary and secondary channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable priority scheme
– Optional software-initiated requests for any channel
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Transfer size is programmable in binary steps from 1 to 1024
■ Source and destination address increment size of byte, half-word, word, or no increment
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■ Maskable peripheral requests
■ Interrupt on transfer completion, with a separate interrupt per channel
8.1
Block Diagram
Figure 8-1. μDMA Block Diagram
uDMA
Controller
DMA error
System Memory
CH Control Table
Peripheral
DMA Channel 0
•
•
•
Peripheral
DMA Channel N-1
Nested
Vectored
Interrupt
Controller
(NVIC)
IRQ
General
Peripheral N
Registers
request
done
request
done
request
done
DMASTAT
DMACFG
DMACTLBASE
DMAALTBASE
DMAWAITSTAT
DMASWREQ
DMAUSEBURSTSET
DMAUSEBURSTCLR
DMAREQMASKSET
DMAREQMASKCLR
DMAENASET
DMAENACLR
DMAALTSET
DMAALTCLR
DMAPRIOSET
DMAPRIOCLR
DMAERRCLR
DMACHASGN
DMACHIS
DMASRCENDP
DMADSTENDP
DMACHCTRL
•
•
•
DMASRCENDP
DMADSTENDP
DMACHCTRL
Transfer Buffers
Used by µDMA
ARM
Cortex-M3
8.2
Functional Description
The μDMA controller is a flexible and highly configurable DMA controller designed to work efficiently
with the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address
increment schemes, multiple levels of priority among DMA channels, and several transfer modes
to allow for sophisticated programmed data transfers. The μDMA controller's usage of the bus is
always subordinate to the processor core, so it never holds up a bus transaction by the processor.
Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth
it provides is essentially free, with no impact on the rest of the system. The bus architecture has
been optimized to greatly enhance the ability of the processor core and the μDMA controller to
efficiently share the on-chip bus, thus improving performance. The optimizations include RAM
striping and peripheral bus segmentation, which in many cases allow both the processor core and
the μDMA controller to access the bus and perform simultaneous data transfers.
The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash
memory and ROM are located on a separate internal bus, it is not possible to transfer data from the
Flash memory or ROM with the μDMA controller.
Each peripheral function that is supported has a dedicated channel on the μDMA controller that can
be configured independently. The μDMA controller implements a unique configuration method using
channel control structures that are maintained in system memory by the processor. While simple
transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that
allow the μDMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part
of a single transfer request. The μDMA controller also supports the use of ping-pong buffering to
accommodate constant streaming of data to or from a peripheral.
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Each channel also has a configurable arbitration size. The arbitration size is the number of items
that are transferred in a burst before the μDMA controller rearbitrates for channel priority. Using the
arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral
each time it makes a μDMA service request.
8.2.1
Channel Assignments
μDMA channels 0-31 are assigned to peripherals according to the following table. The DMA Channel
Assignment (DMACHASGN) register (see page 416) can be used to specify the primary or secondary
assignment. If the primary function is not available on this microcontroller, the secondary function
becomes the primary function. If the secondary function is not available, the primary function is the
only option.
Note:
Channels noted in the table as "Available for software" may be assigned to peripherals in
the future. However, they are currently available for software use. Channel 30 is dedicated
for software use.
The USB endpoints mapped to μDMA channels 0-3 can be changed with the USBDMASEL
register (see page 1137).
Because of the way the μDMA controller interacts with peripherals, the μDMA channel for
the peripheral must be enabled in order for the μDMA controller to be able to read and write
the peripheral registers, even if a different μDMA channel is used to perform the μDMA
transfer. To minimize confusion and chance of software errors, it is best practice to use a
peripheral's μDMA channel for performing all μDMA transfers for that peripheral, even if it
is processor-triggered and using AUTO mode, which could be considered a software transfer.
Note that if the software channel is used, interrupts occur on the dedicated μDMA interrupt
vector. If the peripheral channel is used, then the interrupt occurs on the interrupt vector
for the peripheral.
Table 8-1. μDMA Channel Assignments
μDMA Channel
Primary Assignment
Secondary Assignment
0
USB Endpoint 1 Receive
UART2 Receive
1
USB Endpoint 1 Transmit
UART2 Transmit
2
USB Endpoint 2 Receive
General-Purpose Timer 3A
3
USB Endpoint 2 Transmit
General-Purpose Timer 3B
4
USB Endpoint 3 Receive
General-Purpose Timer 2A
5
USB Endpoint 3 Transmit
General-Purpose Timer 2B
6
Ethernet Receive
General-Purpose Timer 2A
7
Ethernet Transmit
General-Purpose Timer 2B
8
UART0 Receive
UART1 Receive
9
UART0 Transmit
UART1 Transmit
10
SSI0 Receive
SSI1 Receive
11
SSI0 Transmit
SSI1 Transmit
12
Available for software
UART2 Receive
13
Available for software
UART2 Transmit
14
ADC0 Sample Sequencer 0
General-Purpose Timer 2A
15
ADC0 Sample Sequencer 1
General-Purpose Timer 2B
16
ADC0 Sample Sequencer 2
Available for software
17
ADC0 Sample Sequencer 3
Available for software
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Table 8-1. μDMA Channel Assignments (continued)
μDMA Channel
8.2.2
Primary Assignment
Secondary Assignment
18
General-Purpose Timer 0A
General-Purpose Timer 1A
19
General-Purpose Timer 0B
General-Purpose Timer 1B
20
General-Purpose Timer 1A
EPI0 NBRFIFO
21
General-Purpose Timer 1B
EPI0 WFIFO
22
UART1 Receive
Available for software
23
UART1 Transmit
Available for software
24
SSI1 Receive
ADC1 Sample Sequencer 0
25
SSI1 Transmit
ADC1 Sample Sequencer 1
26
Available for software
ADC1 Sample Sequencer 2
27
Available for software
ADC1 Sample Sequencer 3
28
I2S0 Receive
Available for software
29
I2S0
Available for software
30
Dedicated for software use
31
Reserved
Transmit
Priority
The μDMA controller assigns priority to each channel based on the channel number and the priority
level bit for the channel. Channel number 0 has the highest priority and as the channel number
increases, the priority of a channel decreases. Each channel has a priority level bit to provide two
levels of priority: default priority and high priority. If the priority level bit is set, then that channel has
higher priority than all other channels at default priority. If multiple channels are set for high priority,
then the channel number is used to determine relative priority among all the high priority channels.
The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET)
register and cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register.
8.2.3
Arbitration Size
When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels
making a request and services the μDMA channel with the highest priority. Once a transfer begins,
it continues for a selectable number of transfers before rearbitrating among the requesting channels
again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers.
After the μDMA controller transfers the number of items specified by the arbitration size, it then
checks among all the channels making a request and services the channel with the highest priority.
If a lower priority μDMA channel uses a large arbitration size, the latency for higher priority channels
is increased because the μDMA controller completes the lower priority burst before checking for
higher priority requests. Therefore, lower priority channels should not use a large arbitration size
for best response on high priority channels.
The arbitration size can also be thought of as a burst size. It is the maximum number of items that
are transferred at any one time in a burst. Here, the term arbitration refers to determination of μDMA
channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the
processor always takes priority. Furthermore, the μDMA controller is held off whenever the processor
must perform a bus transaction on the same bus, even in the middle of a burst transfer.
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8.2.4
Request Types
The μDMA controller responds to two types of requests from a peripheral: single or burst. Each
peripheral may support either or both types of requests. A single request means that the peripheral
is ready to transfer one item, while a burst request means that the peripheral is ready to transfer
multiple items.
The μDMA controller responds differently depending on whether the peripheral is making a single
request or a burst request. If both are asserted, and the μDMA channel has been set up for a burst
transfer, then the burst request takes precedence. See Table 8-2 on page 370, which shows how
each peripheral supports the two request types.
Table 8-2. Request Type Support
8.2.4.1
Peripheral
Single Request Signal
Burst Request Signal
ADC
None
Sequencer IE bit
EPI WFIFO
None
WFIFO Level (configurable)
EPI NBRFIFO
None
NBRFIFO Level (configurable)
Ethernet TX
TX FIFO empty
None
Ethernet RX
RX packet received
None
General-Purpose Timer
None
Trigger event
I2S
TX
None
FIFO service request
I2S RX
None
FIFO service request
SSI TX
TX FIFO Not Full
TX FIFO Level (fixed at 4)
SSI RX
RX FIFO Not Empty
RX FIFO Level (fixed at 4)
UART TX
TX FIFO Not Full
TX FIFO Level (configurable)
UART RX
RX FIFO Not Empty
RX FIFO Level (configurable)
USB TX
None
FIFO TXRDY
USB RX
None
FIFO RXRDY
Single Request
When a single request is detected, and not a burst request, the μDMA controller transfers one item
and then stops to wait for another request.
8.2.4.2
Burst Request
When a burst request is detected, the μDMA controller transfers the number of items that is the
lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration
size should be the same as the number of data items that the peripheral can accommodate when
making a burst request. For example, the UART generates a burst request based on the FIFO trigger
level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer
when the trigger level is reached. A burst transfer runs to completion once it is started, and cannot
be interrupted, even by a higher priority channel. Burst transfers complete in a shorter time than the
same number of non-burst transfers.
It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps
the nature of the data is such that it only makes sense when transferred together as a single unit
rather than one piece at a time. The single request can be disabled by using the DMA Channel
Useburst Set (DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the
μDMA controller only responds to burst requests for that channel.
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8.2.5
Channel Configuration
The μDMA controller uses an area of system memory to store a set of channel control structures
in a table. The control table may have one or two entries for each μDMA channel. Each entry in the
table structure contains source and destination pointers, transfer size, and transfer mode. The
control table can be located anywhere in system memory, but it must be contiguous and aligned on
a 1024-byte boundary.
Table 8-3 on page 371 shows the layout in memory of the channel control table. Each channel may
have one or two control structures in the control table: a primary control structure and an optional
alternate control structure. The table is organized so that all of the primary entries are in the first
half of the table, and all the alternate structures are in the second half of the table. The primary entry
is used for simple transfer modes where transfers can be reconfigured and restarted after each
transfer is complete. In this case, the alternate control structures are not used and therefore only
the first half of the table must be allocated in memory; the second half of the control table is not
necessary, and that memory can be used for something else. If a more complex transfer mode is
used such as ping-pong or scatter-gather, then the alternate control structure is also used and
memory space should be allocated for the entire table.
Any unused memory in the control table may be used by the application. This includes the control
structures for any channels that are unused by the application as well as the unused control word
for each channel.
Table 8-3. Control Structure Memory Map
Offset
Channel
0x0
0, Primary
0x10
1, Primary
...
...
0x1F0
31, Primary
0x200
0, Alternate
0x210
1, Alternate
...
0x3F0
...
31, Alternate
Table 8-4 shows an individual control structure entry in the control table. Each entry is aligned on
a 16-byte boundary. The entry contains four long words: the source end pointer, the destination end
pointer, the control word, and an unused entry. The end pointers point to the ending address of the
transfer and are inclusive. If the source or destination is non-incrementing (as for a peripheral
register), then the pointer should point to the transfer address.
Table 8-4. Channel Control Structure
Offset
Description
0x000
Source End Pointer
0x004
Destination End Pointer
0x008
Control Word
0x00C
Unused
The control word contains the following fields:
■ Source and destination data sizes
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■ Source and destination address increment size
■ Number of transfers before bus arbitration
■ Total number of items to transfer
■ Useburst flag
■ Transfer mode
The control word and each field are described in detail in “μDMA Channel Control
Structure” on page 390. The μDMA controller updates the transfer size and transfer mode fields as
the transfer is performed. At the end of a transfer, the transfer size indicates 0, and the transfer
mode indicates "stopped." Because the control word is modified by the μDMA controller, it must be
reconfigured before each new transfer. The source and destination end pointers are not modified,
so they can be left unchanged if the source or destination addresses remain the same.
Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the
DMA Channel Enable Set (DMAENASET) register. A channel can be disabled by setting the
channel bit in the DMA Channel Enable Clear (DMAENACLR) register. At the end of a complete
μDMA transfer, the controller automatically disables the channel.
8.2.6
Transfer Modes
The μDMA controller supports several transfer modes. Two of the modes support simple one-time
transfers. Several complex modes support a continuous flow of data.
8.2.6.1
Stop Mode
While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word.
When the mode field has this value, the μDMA controller does not perform any transfers and disables
the channel if it is enabled. At the end of a transfer, the μDMA controller updates the control word
to set the mode to Stop.
8.2.6.2
Basic Mode
In Basic mode, the μDMA controller performs transfers as long as there are more items to transfer,
and a transfer request is present. This mode is used with peripherals that assert a μDMA request
signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any
situation where the request is momentary even though the entire transfer should be completed. For
example, a software-initiated transfer creates a momentary request, and in Basic mode, only the
number of transfers specified by the ARBSIZE field in the DMA Channel Control Word (DMACHCTL)
register is transferred on a software request, even if there is more data to transfer.
When all of the items have been transferred using Basic mode, the μDMA controller sets the mode
for that channel to Stop.
8.2.6.3
Auto Mode
Auto mode is similar to Basic mode, except that once a transfer request is received, the transfer
runs to completion, even if the μDMA request is removed. This mode is suitable for software-triggered
transfers. Generally, Auto mode is not used with a peripheral.
When all the items have been transferred using Auto mode, the μDMA controller sets the mode for
that channel to Stop.
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8.2.6.4
Ping-Pong
Ping-Pong mode is used to support a continuous data flow to or from a peripheral. To use Ping-Pong
mode, both the primary and alternate data structures must be implemented. Both structures are set
up by the processor for data transfer between memory and a peripheral. The transfer is started
using the primary control structure. When the transfer using the primary control structure is complete,
the μDMA controller reads the alternate control structure for that channel to continue the transfer.
Each time this happens, an interrupt is generated, and the processor can reload the control structure
for the just-completed transfer. Data flow can continue indefinitely this way, using the primary and
alternate control structures to switch back and forth between buffers as the data flows to or from
the peripheral.
Refer to Figure 8-2 on page 374 for an example showing operation in Ping-Pong mode.
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Figure 8-2. Example of Ping-Pong μDMA Transaction
µDMA Controller
SOURCE
DEST
CONTROL
Unused
transfers using BUFFER A
transfer continues using alternate
Primary Structure
Cortex-M3 Processor
SOURCE
DEST
CONTROL
Unused
Pe
rip
he
ral
/µD
M
AI
nte
rru
p
t
transfers using BUFFER B
Time
SOURCE
DEST
CONTROL
Unused
Pe
Alternate Structure
8.2.6.5
SOURCE
DEST
CONTROL
Unused
rip
he
ral
/µD
M
AI
nte
transfers using BUFFER A
rru
pt
BUFFER A
· Process data in BUFFER B
· Reload alternate structure
transfer continues using alternate
Primary Structure
BUFFER B
· Process data in BUFFER A
· Reload primary structure
transfer continues using primary
Alternate Structure
BUFFER A
Pe
rip
he
ral
/µD
M
AI
nte
transfers using BUFFER B
rru
pt
BUFFER B
· Process data in BUFFER B
· Reload alternate structure
Memory Scatter-Gather
Memory Scatter-Gather mode is a complex mode used when data must be transferred to or from
varied locations in memory instead of a set of contiguous locations in a memory buffer. For example,
a gather μDMA operation could be used to selectively read the payload of several stored packets
of a communication protocol and store them together in sequence in a memory buffer.
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In Memory Scatter-Gather mode, the primary control structure is used to program the alternate
control structure from a table in memory. The table is set up by the processor software and contains
a list of control structures, each containing the source and destination end pointers, and the control
word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode.
Each entry in the table is copied in turn to the alternate structure where it is then executed. The
μDMA controller alternates between using the primary control structure to copy the next transfer
instruction from the list and then executing the new transfer instruction. The end of the list is marked
by programming the control word for the last entry to use Auto transfer mode. Once the last transfer
is performed using Auto mode, the μDMA controller stops. A completion interrupt is generated only
after the last transfer. It is possible to loop the list by having the last entry copy the primary control
structure to point back to the beginning of the list (or to a new list). It is also possible to trigger a set
of other channels to perform a transfer, either directly, by programming a write to the software trigger
for another channel, or indirectly, by causing a peripheral action that results in a μDMA request.
By programming the μDMA controller using this method, a set of up to 256 arbitrary transfers can
be performed based on a single μDMA request.
Refer to Figure 8-3 on page 376 and Figure 8-4 on page 377, which show an example of operation
in Memory Scatter-Gather mode. This example shows a gather operation, where data in three
separate buffers in memory is copied together into one buffer. Figure 8-3 on page 376 shows how
the application sets up a μDMA task list in memory that is used by the controller to perform three
sets of copy operations from different locations in memory. The primary control structure for the
channel that is used for the operation is configured to copy from the task list to the alternate control
structure.
Figure 8-4 on page 377 shows the sequence as the μDMA controller performs the three sets of copy
operations. First, using the primary control structure, the μDMA controller loads the alternate control
structure with task A. It then performs the copy operation specified by task A, copying the data from
the source buffer A to the destination buffer. Next, the μDMA controller again uses the primary
control structure to load task B into the alternate control structure, and then performs the B operation
with the alternate control structure. The process is repeated for task C.
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Figure 8-3. Memory Scatter-Gather, Setup and Configuration
1
2
3
Source and Destination
Buffer in Memory
Task List in Memory
Channel Control
Table in Memory
4 WORDS (SRC A)
SRC
A
DST
ITEMS=4
16 WORDS (SRC B)
SRC
Unused
DST
SRC
ITEMS=12
DST
B
“TASK” A
ITEMS=16
Channel Primary
Control Structure
“TASK” B
Unused
SRC
DST
ITEMS=1
“TASK” C
Unused
SRC
DST
Channel Alternate
Control Structure
ITEMS=n
1 WORD (SRC C)
C
4 (DEST A)
16 (DEST B)
1 (DEST C)
NOTES:
1. Application has a need to copy data items from three separate locations in memory into one combined buffer.
2. Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three
µDMA copy “tasks.”
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the
alternate control structure, where it is executed by the µDMA controller.
4. The SRC and DST pointers in the task list must point to the last location in the corresponding buffer.
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Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence
Task List
in Memory
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
COPIED
DST
TASK A
TASK B
SRC
SRC C
ALT
COPIED
DST
TASK C
DEST A
DEST B
DEST C
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer A to
the destination buffer.
Using the channel’s primary control structure, the µDMA
controller copies task A configuration to the channel’s
alternate control structure.
Task List
in Memory
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC B
SRC
PRI
DST
TASK A
SRC
TASK B
TASK C
SRC C
COPIED
ALT
COPIED
DST
DEST A
DEST B
DEST C
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer B to
the destination buffer.
Using the channel’s primary control structure, the µDMA
controller copies task B configuration to the channel’s
alternate control structure.
Task List
in Memory
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
DST
TASK A
SRC
TASK B
TASK C
SRC C
ALT
DST
DEST A
COPIED
COPIED
DEST B
DEST C
Using the channel’s primary control structure, the µDMA
controller copies task C configuration to the channel’s
alternate control structure.
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer C to
the destination buffer.
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8.2.6.6
Peripheral Scatter-Gather
Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers
are controlled by a peripheral making a μDMA request. Upon detecting a request from the peripheral,
the μDMA controller uses the primary control structure to copy one entry from the list to the alternate
control structure and then performs the transfer. At the end of this transfer, the next transfer is started
only if the peripheral again asserts a μDMA request. The μDMA controller continues to perform
transfers from the list only when the peripheral is making a request, until the last transfer is complete.
A completion interrupt is generated only after the last transfer.
By using this method, the μDMA controller can transfer data to or from a peripheral from a set of
arbitrary locations whenever the peripheral is ready to transfer data.
Refer to Figure 8-5 on page 379 and Figure 8-6 on page 380, which show an example of operation
in Peripheral Scatter-Gather mode. This example shows a gather operation, where data from three
separate buffers in memory is copied to a single peripheral data register. Figure 8-5 on page 379
shows how the application sets up a µDMA task list in memory that is used by the controller to
perform three sets of copy operations from different locations in memory. The primary control
structure for the channel that is used for the operation is configured to copy from the task list to the
alternate control structure.
Figure 8-6 on page 380 shows the sequence as the µDMA controller performs the three sets of copy
operations. First, using the primary control structure, the µDMA controller loads the alternate control
structure with task A. It then performs the copy operation specified by task A, copying the data from
the source buffer A to the peripheral data register. Next, the µDMA controller again uses the primary
control structure to load task B into the alternate control structure, and then performs the B operation
with the alternate control structure. The process is repeated for task C.
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Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration
1
2
3
Source Buffer
in Memory
Task List in Memory
Channel Control
Table in Memory
4 WORDS (SRC A)
SRC
A
DST
ITEMS=4
16 WORDS (SRC B)
SRC
DST
SRC
ITEMS=12
DST
B
“TASK” A
Unused
ITEMS=16
Channel Primary
Control Structure
“TASK” B
Unused
SRC
DST
ITEMS=1
“TASK” C
Unused
SRC
DST
Channel Alternate
Control Structure
ITEMS=n
1 WORD (SRC C)
C
Peripheral Data
Register
DEST
NOTES:
1. Application has a need to copy data items from three separate locations in memory into a peripheral data
register.
2. Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three
µDMA copy “tasks.”
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the
alternate control structure, where it is executed by the µDMA controller.
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Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence
Task List
in Memory
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
COPIED
DST
TASK A
TASK B
SRC
SRC C
ALT
COPIED
DST
TASK C
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer A to
the peripheral data register.
Using the channel’s primary control structure, the µDMA
controller copies task A configuration to the channel’s
alternate control structure.
Task List
in Memory
Peripheral
Data
Register
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
DST
TASK A
SRC
TASK B
TASK C
SRC C
COPIED
ALT
COPIED
DST
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer B to
the peripheral data register.
Using the channel’s primary control structure, the µDMA
controller copies task B configuration to the channel’s
alternate control structure.
Task List
in Memory
Peripheral
Data
Register
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
DST
TASK A
SRC
TASK B
TASK C
SRC C
ALT
DST
COPIED
COPIED
Peripheral
Data
Register
Using the channel’s primary control structure, the µDMA
controller copies task C configuration to the channel’s
alternate control structure.
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer C to
the peripheral data register.
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8.2.7
Transfer Size and Increment
The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination
data size must be the same for any given transfer. The source and destination address can be
auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and
destination address increment values can be set independently, and it is not necessary for the
address increment to match the data size as long as the increment is the same or larger than the
data size. For example, it is possible to perform a transfer using 8-bit data size, but using an address
increment of full words (4 bytes). The data to be transferred must be aligned in memory according
to the data size (8, 16, or 32 bits).
Table 8-5 shows the configuration to read from a peripheral that supplies 8-bit data.
Table 8-5. μDMA Read Example: 8-Bit Peripheral
8.2.8
Field
Configuration
Source data size
8 bits
Destination data size
8 bits
Source address increment
No increment
Destination address increment
Byte
Source end pointer
Peripheral read FIFO register
Destination end pointer
End of the data buffer in memory
Peripheral Interface
Each peripheral that supports μDMA has a single request and/or burst request signal that is asserted
when the peripheral is ready to transfer data (see Table 8-2 on page 370). The request signal can
be disabled or enabled using the DMA Channel Request Mask Set (DMAREQMASKSET) and
DMA Channel Request Mask Clear (DMAREQMASKCLR) registers. The μDMA request signal
is disabled, or masked, when the channel request mask bit is set. When the request is not masked,
the μDMA channel is configured correctly and enabled, and the peripheral asserts the request signal,
the μDMA controller begins the transfer.
Note:
When using μDMA to transfer data to and from a peripheral, the peripheral must disable all
interrupts to the NVIC.
When a μDMA transfer is complete, the μDMA controller generates an interrupt, see “Interrupts and
Errors” on page 382 for more information.
For more information on how a specific peripheral interacts with the μDMA controller, refer to the
DMA Operation section in the chapter that discusses that peripheral.
8.2.9
Software Request
One μDMA channel is dedicated to software-initiated transfers. This channel also has a dedicated
interrupt to signal completion of a μDMA transfer. A transfer is initiated by software by first configuring
and enabling the transfer, and then issuing a software request using the DMA Channel Software
Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should be
used.
It is possible to initiate a transfer on any channel using the DMASWREQ register. If a request is
initiated by software using a peripheral μDMA channel, then the completion interrupt occurs on the
interrupt vector for the peripheral instead of the software interrupt vector. Any channel may be used
for software requests as long as the corresponding peripheral is not using μDMA for data transfer.
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8.2.10
Interrupts and Errors
When a μDMA transfer is complete, the μDMA controller generates a completion interrupt on the
interrupt vector of the peripheral. Therefore, if μDMA is used to transfer data for a peripheral and
interrupts are used, then the interrupt handler for that peripheral must be designed to handle the
μDMA transfer completion interrupt. If the transfer uses the software μDMA channel, then the
completion interrupt occurs on the dedicated software μDMA interrupt vector (see Table
8-6 on page 382).
When μDMA is enabled for a peripheral, the μDMA controller stops the normal transfer interrupts
for a peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's
interrupt registers). Thus, when a large amount of data is transferred using μDMA, instead of receiving
multiple interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt
when the transfer is complete. Unmasked peripheral error interrupts continue to be sent to the
interrupt controller.
When a μDMA channel generates a completion interrupt, the CHIS bit corresponding to the peripheral
channel is set in the DMA Channel Interrupt Status (DMACHIS) register (see page 417). This
register can be used by the peripheral interrupt handler code to determine if the interrupt was caused
by the μDMA channel or an error event reported by the peripheral's interrupt registers. The completion
interrupt request from the μDMA controller is automatically cleared when the interrupt handler is
activated.
If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data
transfer, it disables the μDMA channel that caused the error and generates an interrupt on the μDMA
error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register
to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be
cleared by writing a 1 to the ERRCLR bit.
Table 8-6 shows the dedicated interrupt assignments for the μDMA controller.
Table 8-6. μDMA Interrupt Assignments
Interrupt
Assignment
46
μDMA Software Channel Transfer
47
μDMA Error
8.3
Initialization and Configuration
8.3.1
Module Initialization
Before the μDMA controller can be used, it must be enabled in the System Control block and in the
peripheral. The location of the channel control structure must also be programmed.
The following steps should be performed one time during system initialization:
1. The μDMA peripheral must be enabled in the System Control block. To do this, set the UDMA
bit of the System Control RCGC2 register (see page 277).
2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG)
register.
3. Program the location of the channel control table by writing the base address of the table to the
DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be
aligned on a 1024-byte boundary.
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8.3.2
Configuring a Memory-to-Memory Transfer
μDMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used
for software-initiated, memory-to-memory transfer if the associated peripheral is not being used.
8.3.2.1
Configure the Channel Attributes
First, configure the channel attributes:
1. Program bit 30 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 30 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 30 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 30 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
8.3.2.2
Configure the Channel Control Structure
Now the channel control structure must be configured.
This example transfers 256 words from one memory buffer to another. Channel 30 is used for a
software transfer, and the control structure for channel 30 is at offset 0x1E0 of the channel control
table. The channel control structure for channel 30 is located at the offsets shown in Table 8-7.
Table 8-7. Channel Control Structure Offsets for Channel 30
Offset
Description
Control Table Base + 0x1E0
Channel 30 Source End Pointer
Control Table Base + 0x1E4
Channel 30 Destination End Pointer
Control Table Base + 0x1E8
Channel 30 Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
1. Program the source end pointer at offset 0x1E0 to the address of the source buffer + 0x3FC.
2. Program the destination end pointer at offset 0x1E4 to the address of the destination buffer +
0x3FC.
The control word at offset 0x1E8 must be programmed according to Table 8-8.
Table 8-8. Channel Control Word Configuration for Memory Transfer Example
Field in DMACHCTL
Bits
Value
DSTINC
31:30
2
32-bit destination address increment
DSTSIZE
29:28
2
32-bit destination data size
SRCINC
27:26
2
32-bit source address increment
SRCSIZE
25:24
2
32-bit source data size
reserved
23:18
0
Reserved
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Table 8-8. Channel Control Word Configuration for Memory Transfer Example (continued)
Field in DMACHCTL
Bits
Description
ARBSIZE
17:14
3
XFERSIZE
13:4
255
3
0
N/A for this transfer type
2:0
2
Use Auto-request transfer mode
NXTUSEBURST
XFERMODE
8.3.2.3
Value
Arbitrates after 8 transfers
Transfer 256 items
Start the Transfer
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 30 of the DMA Channel Enable Set (DMAENASET) register.
2. Issue a transfer request by setting bit 30 of the DMA Channel Software Request (DMASWREQ)
register.
The μDMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt
when the transfer is complete. If needed, the status can be checked by reading bit 30 of the
DMAENASET register. This bit is automatically cleared when the transfer is complete. The status
can also be checked by reading the XFERMODE field of the channel control word at offset 0x1E8.
This field is automatically cleared at the end of the transfer.
8.3.3
Configuring a Peripheral for Simple Transmit
This example configures the μDMA controller to transmit a buffer of data to a peripheral. The
peripheral has a transmit FIFO with a trigger level of 4. The example peripheral uses μDMA channel
7.
8.3.3.1
Configure the Channel Attributes
First, configure the channel attributes:
1. Configure bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
8.3.3.2
Configure the Channel Control Structure
This example transfers 64 bytes from a memory buffer to the peripheral's transmit FIFO register
using μDMA channel 7. The control structure for channel 7 is at offset 0x070 of the channel control
table. The channel control structure for channel 7 is located at the offsets shown in Table 8-9.
Table 8-9. Channel Control Structure Offsets for Channel 7
Offset
Description
Control Table Base + 0x070
Channel 7 Source End Pointer
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Table 8-9. Channel Control Structure Offsets for Channel 7 (continued)
Offset
Description
Control Table Base + 0x074
Channel 7 Destination End Pointer
Control Table Base + 0x078
Channel 7 Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Because the peripheral pointer does not change, it simply points to the peripheral's data register.
1. Program the source end pointer at offset 0x070 to the address of the source buffer + 0x3F.
2. Program the destination end pointer at offset 0x074 to the address of the peripheral's transmit
FIFO register.
The control word at offset 0x078 must be programmed according to Table 8-10.
Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example
Field in DMACHCTL
Bits
Value
DSTINC
31:30
3
Destination address does not increment
DSTSIZE
29:28
0
8-bit destination data size
SRCINC
27:26
0
8-bit source address increment
SRCSIZE
25:24
0
8-bit source data size
reserved
23:18
0
Reserved
ARBSIZE
17:14
2
Arbitrates after 4 transfers
XFERSIZE
13:4
63
Transfer 64 items
3
0
N/A for this transfer type
2:0
1
Use Basic transfer mode
NXTUSEBURST
XFERMODE
Note:
8.3.3.3
Description
In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 4, the arbitration size is set to
4. If the peripheral does make a burst request, then 4 bytes are transferred, which is what
the FIFO can accommodate. If the peripheral makes a single request (if there is any space
in the FIFO), then one byte is transferred at a time. If it is important to the application that
transfers only be made in bursts, then the Channel Useburst SET[7] bit should be set in
the DMA Channel Useburst Set (DMAUSEBURSTSET) register.
Start the Transfer
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 7 of the DMA Channel Enable Set (DMAENASET) register.
The μDMA controller is now configured for transfer on channel 7. The controller makes transfers to
the peripheral whenever the peripheral asserts a μDMA request. The transfers continue until the
entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller disables
the channel and sets the XFERMODE field of the channel control word to 0 (Stopped). The status of
the transfer can be checked by reading bit 7 of the DMA Channel Enable Set (DMAENASET)
register. This bit is automatically cleared when the transfer is complete. The status can also be
checked by reading the XFERMODE field of the channel control word at offset 0x078. This field is
automatically cleared at the end of the transfer.
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If peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when
the entire transfer is complete.
8.3.4
Configuring a Peripheral for Ping-Pong Receive
This example configures the μDMA controller to continuously receive 8-bit data from a peripheral
into a pair of 64-byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example
peripheral uses μDMA channel 8.
8.3.4.1
Configure the Channel Attributes
First, configure the channel attributes:
1. Configure bit 8 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 8 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 8 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 8 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
8.3.4.2
Configure the Channel Control Structure
This example transfers bytes from the peripheral's receive FIFO register into two memory buffers
of 64 bytes each. As data is received, when one buffer is full, the μDMA controller switches to use
the other.
To use Ping-Pong buffering, both primary and alternate channel control structures must be used.
The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the
alternate channel control structure is at offset 0x280. The channel control structures for channel 8
are located at the offsets shown in Table 8-11.
Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8
Offset
Description
Control Table Base + 0x080
Channel 8 Primary Source End Pointer
Control Table Base + 0x084
Channel 8 Primary Destination End Pointer
Control Table Base + 0x088
Channel 8 Primary Control Word
Control Table Base + 0x280
Channel 8 Alternate Source End Pointer
Control Table Base + 0x284
Channel 8 Alternate Destination End Pointer
Control Table Base + 0x288
Channel 8 Alternate Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Because the peripheral pointer does not change, it simply points to the peripheral's data register.
Both the primary and alternate sets of pointers must be configured.
1. Program the primary source end pointer at offset 0x080 to the address of the peripheral's receive
buffer.
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2. Program the primary destination end pointer at offset 0x084 to the address of ping-pong buffer
A + 0x3F.
3. Program the alternate source end pointer at offset 0x280 to the address of the peripheral's
receive buffer.
4. Program the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer
B + 0x3F.
The primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially
programmed the same way.
1. Program the primary channel control word at offset 0x088 according to Table 8-12.
2. Program the alternate channel control word at offset 0x288 according to Table 8-12.
Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example
Field in DMACHCTL
Bits
Value
DSTINC
31:30
0
8-bit destination address increment
DSTSIZE
29:28
0
8-bit destination data size
SRCINC
27:26
3
Source address does not increment
SRCSIZE
25:24
0
8-bit source data size
reserved
23:18
0
Reserved
ARBSIZE
17:14
3
Arbitrates after 8 transfers
XFERSIZE
13:4
63
Transfer 64 items
3
0
N/A for this transfer type
2:0
3
Use Ping-Pong transfer mode
NXTUSEBURST
XFERMODE
Note:
8.3.4.3
Description
In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 8, the arbitration size is set to
8. If the peripheral does make a burst request, then 8 bytes are transferred, which is what
the FIFO can accommodate. If the peripheral makes a single request (if there is any data
in the FIFO), then one byte is transferred at a time. If it is important to the application that
transfers only be made in bursts, then the Channel Useburst SET[8] bit should be set in
the DMA Channel Useburst Set (DMAUSEBURSTSET) register.
Configure the Peripheral Interrupt
An interrupt handler should be configured when using μDMA Ping-Pong mode, it is best to use an
interrupt handler. However, the Ping-Pong mode can be configured without interrupts by polling.
The interrupt handler is triggered after each buffer is complete.
1. Configure and enable an interrupt handler for the peripheral.
8.3.4.4
Enable the μDMA Channel
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 8 of the DMA Channel Enable Set (DMAENASET) register.
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8.3.4.5
Process Interrupts
The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral
asserts the μDMA request signal, the μDMA controller makes transfers into buffer A using the primary
channel control structure. When the primary transfer to buffer A is complete, it switches to the
alternate channel control structure and makes transfers into buffer B. At the same time, the primary
channel control word mode field is configured to indicate Stopped, and an interrupt is
When an interrupt is triggered, the interrupt handler must determine which buffer is complete and
process the data or set a flag that the data must be processed by non-interrupt buffer processing
code. Then the next buffer transfer must be set up.
In the interrupt handler:
1. Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the
field is 0, this means buffer A is complete. If buffer A is complete, then:
a. Process the newly received data in buffer A or signal the buffer processing code that buffer
A has data available.
b. Reprogram the primary channel control word at offset 0x88 according to Table
8-12 on page 387.
2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the
field is 0, this means buffer B is complete. If buffer B is complete, then:
a. Process the newly received data in buffer B or signal the buffer processing code that buffer
B has data available.
b. Reprogram the alternate channel control word at offset 0x288 according to Table
8-12 on page 387.
8.3.5
Configuring Channel Assignments
Channel assignments for each μDMA channel can be changed using the DMACHASGN register.
Each bit represents a μDMA channel. If the bit is set, then the secondary function is used for the
channel.
Refer to Table 8-1 on page 368 for channel assignments.
For example, to use SSI1 Receive on channel 8 instead of UART0, set bit 8 of the DMACHASGN
register.
8.4
Register Map
Table 8-13 on page 389 lists the μDMA channel control structures and registers. The channel control
structure shows the layout of one entry in the channel control table. The channel control table is
located in system memory, and the location is determined by the application, that is, the base
address is n/a (not applicable). In the table below, the offset for the channel control structures is the
offset from the entry in the channel control table. See “Channel Configuration” on page 371 and Table
8-3 on page 371 for a description of how the entries in the channel control table are located in memory.
The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base
address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers
can be programmed (see page 277). There must be a delay of 3 system clocks after the μDMA
module clock is enabled before any μDMA module registers are accessed.
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Table 8-13. μDMA Register Map
Offset
Name
Type
Reset
Description
See
page
μDMA Channel Control Structure (Offset from Channel Control Table Base)
0x000
DMASRCENDP
R/W
-
DMA Channel Source Address End Pointer
391
0x004
DMADSTENDP
R/W
-
DMA Channel Destination Address End Pointer
392
0x008
DMACHCTL
R/W
-
DMA Channel Control Word
393
DMA Status
398
DMA Configuration
400
μDMA Registers (Offset from μDMA Base Address)
0x000
DMASTAT
RO
0x001F.0000
0x004
DMACFG
WO
-
0x008
DMACTLBASE
R/W
0x0000.0000
DMA Channel Control Base Pointer
401
0x00C
DMAALTBASE
RO
0x0000.0200
DMA Alternate Channel Control Base Pointer
402
0x010
DMAWAITSTAT
RO
0xFFFF.FFC0
DMA Channel Wait-on-Request Status
403
0x014
DMASWREQ
WO
-
DMA Channel Software Request
404
0x018
DMAUSEBURSTSET
R/W
0x0000.0000
DMA Channel Useburst Set
405
0x01C
DMAUSEBURSTCLR
WO
-
DMA Channel Useburst Clear
406
0x020
DMAREQMASKSET
R/W
0x0000.0000
DMA Channel Request Mask Set
407
0x024
DMAREQMASKCLR
WO
-
DMA Channel Request Mask Clear
408
0x028
DMAENASET
R/W
0x0000.0000
DMA Channel Enable Set
409
0x02C
DMAENACLR
WO
-
DMA Channel Enable Clear
410
0x030
DMAALTSET
R/W
0x0000.0000
DMA Channel Primary Alternate Set
411
0x034
DMAALTCLR
WO
-
DMA Channel Primary Alternate Clear
412
0x038
DMAPRIOSET
R/W
0x0000.0000
DMA Channel Priority Set
413
0x03C
DMAPRIOCLR
WO
-
DMA Channel Priority Clear
414
0x04C
DMAERRCLR
R/W
0x0000.0000
DMA Bus Error Clear
415
0x500
DMACHASGN
R/W
0x0000.0000
DMA Channel Assignment
416
0x504
DMACHIS
R/W1C
0x0000.0000
DMA Channel Interrupt Status
417
0xFD0
DMAPeriphID4
RO
0x0000.0004
DMA Peripheral Identification 4
422
0xFE0
DMAPeriphID0
RO
0x0000.0030
DMA Peripheral Identification 0
418
0xFE4
DMAPeriphID1
RO
0x0000.00B2
DMA Peripheral Identification 1
419
0xFE8
DMAPeriphID2
RO
0x0000.000B
DMA Peripheral Identification 2
420
0xFEC
DMAPeriphID3
RO
0x0000.0000
DMA Peripheral Identification 3
421
0xFF0
DMAPCellID0
RO
0x0000.000D
DMA PrimeCell Identification 0
423
0xFF4
DMAPCellID1
RO
0x0000.00F0
DMA PrimeCell Identification 1
424
0xFF8
DMAPCellID2
RO
0x0000.0005
DMA PrimeCell Identification 2
425
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Table 8-13. μDMA Register Map (continued)
Offset
Name
0xFFC
DMAPCellID3
8.5
Type
Reset
RO
0x0000.00B1
Description
DMA PrimeCell Identification 3
See
page
426
μDMA Channel Control Structure
The μDMA Channel Control Structure holds the transfer settings for a μDMA channel. Each channel
has two control structures, which are located in a table in system memory. Refer to “Channel
Configuration” on page 371 for an explanation of the Channel Control Table and the Channel Control
Structure.
The channel control structure is one entry in the channel control table. Each channel has a primary
and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and
so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on.
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Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset
0x000
DMA Channel Source Address End Pointer (DMASRCENDP) is part of the Channel Control
Structure and is used to specify the source address for a μDMA transfer.
The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash
memory and ROM are located on a separate internal bus, it is not possible to transfer data from the
Flash memory or ROM with the μDMA controller.
Note:
The offset specified is from the base address of the control structure in system memory,
not the μDMA module base address.
DMA Channel Source Address End Pointer (DMASRCENDP)
Base n/a
Offset 0x000
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
31:0
ADDR
R/W
-
R/W
-
Description
Source Address End Pointer
This field points to the last address of the μDMA transfer source
(inclusive). If the source address is not incrementing (the SRCINC field
in the DMACHCTL register is 0x3), then this field points at the source
location itself (such as a peripheral data register).
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Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP),
offset 0x004
DMA Channel Destination Address End Pointer (DMADSTENDP) is part of the Channel Control
Structure and is used to specify the destination address for a μDMA transfer.
Note:
The offset specified is from the base address of the control structure in system memory,
not the μDMA module base address.
DMA Channel Destination Address End Pointer (DMADSTENDP)
Base n/a
Offset 0x004
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
ADDR
Type
Reset
ADDR
Type
Reset
Bit/Field
Name
Type
Reset
31:0
ADDR
R/W
-
Description
Destination Address End Pointer
This field points to the last address of the μDMA transfer destination
(inclusive). If the destination address is not incrementing (the DSTINC
field in the DMACHCTL register is 0x3), then this field points at the
destination location itself (such as a peripheral data register).
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Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008
DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used
to specify parameters of a μDMA transfer.
Note:
The offset specified is from the base address of the control structure in system memory,
not the μDMA module base address.
DMA Channel Control Word (DMACHCTL)
Base n/a
Offset 0x008
Type R/W, reset 31
30
DSTINC
28
27
DSTSIZE
26
24
23
22
21
SRCSIZE
20
19
18
17
reserved
16
ARBSIZE
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARBSIZE
Type
Reset
25
SRCINC
R/W
-
R/W
-
NXTUSEBURST
Type
Reset
29
XFERSIZE
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
31:30
DSTINC
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
XFERMODE
R/W
-
R/W
-
R/W
-
Description
Destination Address Increment
This field configures the destination address increment.
The address increment value must be equal or greater than the value
of the destination size (DSTSIZE).
Value Description
0x0
Byte
Increment by 8-bit locations
0x1
Half-word
Increment by 16-bit locations
0x2
Word
Increment by 32-bit locations
0x3
No increment
Address remains set to the value of the Destination Address
End Pointer (DMADSTENDP) for the channel
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Bit/Field
Name
Type
Reset
29:28
DSTSIZE
R/W
-
Description
Destination Data Size
This field configures the destination item data size.
Note:
DSTSIZE must be the same as SRCSIZE.
Value Description
0x0
Byte
8-bit data size
0x1
Half-word
16-bit data size
0x2
Word
32-bit data size
0x3
27:26
SRCINC
R/W
-
Reserved
Source Address Increment
This field configures the source address increment.
The address increment value must be equal or greater than the value
of the source size (SRCSIZE).
Value Description
0x0
Byte
Increment by 8-bit locations
0x1
Half-word
Increment by 16-bit locations
0x2
Word
Increment by 32-bit locations
0x3
No increment
Address remains set to the value of the Source Address End
Pointer (DMASRCENDP) for the channel
25:24
SRCSIZE
R/W
-
Source Data Size
This field configures the source item data size.
Note:
DSTSIZE must be the same as SRCSIZE.
Value Description
0x0
Byte
8-bit data size.
0x1
Half-word
16-bit data size.
0x2
Word
32-bit data size.
0x3
23:18
reserved
R/W
-
Reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
17:14
ARBSIZE
R/W
-
Description
Arbitration Size
This field configures the number of transfers that can occur before the
μDMA controller re-arbitrates. The possible arbitration rate configurations
represent powers of 2 and are shown below.
Value
Description
0x0
1 Transfer
Arbitrates after each μDMA transfer
0x1
2 Transfers
0x2
4 Transfers
0x3
8 Transfers
0x4
16 Transfers
0x5
32 Transfers
0x6
64 Transfers
0x7
128 Transfers
0x8
256 Transfers
0x9
512 Transfers
0xA-0xF 1024 Transfers
In this configuration, no arbitration occurs during the μDMA
transfer because the maximum transfer size is 1024.
13:4
XFERSIZE
R/W
-
Transfer Size (minus 1)
This field configures the total number of items to transfer. The value of
this field is 1 less than the number to transfer (value 0 means transfer
1 item). The maximum value for this 10-bit field is 1023 which represents
a transfer size of 1024 items.
The transfer size is the number of items, not the number of bytes. If the
data size is 32 bits, then this value is the number of 32-bit words to
transfer.
The μDMA controller updates this field immediately prior to entering the
arbitration process, so it contains the number of outstanding items that
is necessary to complete the μDMA cycle.
3
NXTUSEBURST
R/W
-
Next Useburst
This field controls whether the Useburst SET[n] bit is automatically set
for the last transfer of a peripheral scatter-gather operation. Normally,
for the last transfer, if the number of remaining items to transfer is less
than the arbitration size, the μDMA controller uses single transfers to
complete the transaction. If this bit is set, then the controller uses a burst
transfer to complete the last transfer.
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Bit/Field
Name
Type
Reset
2:0
XFERMODE
R/W
-
Description
μDMA Transfer Mode
This field configures the operating mode of the μDMA cycle. Refer to
“Transfer Modes” on page 372 for a detailed explanation of transfer
modes.
Because this register is in system RAM, it has no reset value. Therefore,
this field should be initialized to 0 before the channel is enabled.
Value Description
0x0
Stop
0x1
Basic
0x2
Auto-Request
0x3
Ping-Pong
0x4
Memory Scatter-Gather
0x5
Alternate Memory Scatter-Gather
0x6
Peripheral Scatter-Gather
0x7
Alternate Peripheral Scatter-Gather
XFERMODE Bit Field Values.
Stop
Channel is stopped or configuration data is invalid. No more transfers can occur.
Basic
For each trigger (whether from a peripheral or a software request), the μDMA controller performs
the number of transfers specified by the ARBSIZE field.
Auto-Request
The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer
of XFERSIZE items without any further requests.
Ping-Pong
This mode uses both the primary and alternate control structures for this channel. When the
number of transfers specified by the XFERSIZE field have completed for the current control
structure (primary or alternate), the µDMA controller switches to the other one. These switches
continue until one of the control structures is not set to ping-pong mode. At that point, the µDMA
controller stops. An interrupt is generated on completion of the transfers configured by each
control structure. See “Ping-Pong” on page 373.
Memory Scatter-Gather
When using this mode, the primary control structure for the channel is configured to allow a list
of operations (tasks) to be performed. The source address pointer specifies the start of a table
of tasks to be copied to the alternate control structure for this channel. The XFERMODE field for
the alternate control structure should be configured to 0x5 (Alternate memory scatter-gather)
to perform the task. When the task completes, the µDMA switches back to the primary channel
control structure, which then copies the next task to the alternate control structure. This process
continues until the table of tasks is empty. The last task must have an XFERMODE value other
than 0x5. Note that for continuous operation, the last task can update the primary channel control
structure back to the start of the list or to another list. See “Memory Scatter-Gather” on page 374.
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Alternate Memory Scatter-Gather
This value must be used in the alternate channel control data structure when the μDMA controller
operates in Memory Scatter-Gather mode.
Peripheral Scatter-Gather
This value must be used in the primary channel control data structure when the μDMA controller
operates in Peripheral Scatter-Gather mode. In this mode, the μDMA controller operates exactly
the same as in Memory Scatter-Gather mode, except that instead of performing the number of
transfers specified by the XFERSIZE field in the alternate control structure at one time, the
μDMA controller only performs the number of transfers specified by the ARBSIZE field per
trigger; see Basic mode for details. See “Peripheral Scatter-Gather” on page 378.
Alternate Peripheral Scatter-Gather
This value must be used in the alternate channel control data structure when the μDMA controller
operates in Peripheral Scatter-Gather mode.
8.6
μDMA Register Descriptions
The register addresses given are relative to the μDMA base address of 0x400F.F000.
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Register 4: DMA Status (DMASTAT), offset 0x000
The DMA Status (DMASTAT) register returns the status of the μDMA controller. You cannot read
this register when the μDMA controller is in the reset state.
DMA Status (DMASTAT)
Base 0x400F.F000
Offset 0x000
Type RO, reset 0x001F.0000
31
30
29
28
27
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
26
25
24
23
22
21
20
19
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
10
9
8
7
6
5
4
3
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
STATE
RO
0
17
16
RO
1
RO
1
RO
1
2
1
0
DMACHANS
reserved
Type
Reset
18
reserved
RO
0
MASTEN
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:21
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20:16
DMACHANS
RO
0x1F
Available μDMA Channels Minus 1
This field contains a value equal to the number of μDMA channels the
μDMA controller is configured to use, minus one. The value of 0x1F
corresponds to 32 μDMA channels.
15:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4
STATE
RO
0x0
Control State Machine Status
This field shows the current status of the control state machine. Status
can be one of the following.
Value
Description
0x0
Idle
0x1
Reading channel controller data.
0x2
Reading source end pointer.
0x3
Reading destination end pointer.
0x4
Reading source data.
0x5
Writing destination data.
0x6
Waiting for µDMA request to clear.
0x7
Writing channel controller data.
0x8
Stalled
0x9
Done
0xA-0xF Undefined
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
0
MASTEN
RO
0
Description
Master Enable Status
Value Description
0
The μDMA controller is disabled.
1
The μDMA controller is enabled.
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Register 5: DMA Configuration (DMACFG), offset 0x004
The DMACFG register controls the configuration of the μDMA controller.
DMA Configuration (DMACFG)
Base 0x400F.F000
Offset 0x004
Type WO, reset 31
30
29
28
27
26
25
24
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
reserved
Type
Reset
reserved
Type
Reset
WO
-
MASTEN
WO
-
Bit/Field
Name
Type
Reset
Description
31:1
reserved
WO
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MASTEN
WO
-
Controller Master Enable
Value Description
0
Disables the μDMA controller.
1
Enables μDMA controller.
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Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008
The DMACTLBASE register must be configured so that the base pointer points to a location in
system memory.
The amount of system memory that must be assigned to the μDMA controller depends on the
number of μDMA channels used and whether the alternate channel control data structure is used.
See “Channel Configuration” on page 371 for details about the Channel Control Table. The base
address must be aligned on a 1024-byte boundary. This register cannot be read when the μDMA
controller is in the reset state.
DMA Channel Control Base Pointer (DMACTLBASE)
Base 0x400F.F000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
Type
Reset
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
ADDR
Type
Reset
R/W
0
R/W
0
R/W
0
reserved
R/W
0
R/W
0
R/W
0
RO
0
Bit/Field
Name
Type
Reset
31:10
ADDR
R/W
0x0000.00
RO
0
RO
0
RO
0
RO
0
Description
Channel Control Base Address
This field contains the pointer to the base address of the channel control
table. The base address must be 1024-byte aligned.
9:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE),
offset 0x00C
The DMAALTBASE register returns the base address of the alternate channel control data. This
register removes the necessity for application software to calculate the base address of the alternate
channel control structures. This register cannot be read when the μDMA controller is in the reset
state.
DMA Alternate Channel Control Base Pointer (DMAALTBASE)
Base 0x400F.F000
Offset 0x00C
Type RO, reset 0x0000.0200
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
ADDR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
ADDR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
31:0
ADDR
RO
RO
1
Reset
RO
0
Description
0x0000.0200 Alternate Channel Address Pointer
This field provides the base address of the alternate channel control
structures.
402
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Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset
0x010
This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can
hold off the μDMA from performing a single request until the peripheral is ready for a burst request
to enhance the μDMA performance. The use of this feature is dependent on the design of the
peripheral and is not controllable by software in any way. This register cannot be read when the
μDMA controller is in the reset state.
DMA Channel Wait-on-Request Status (DMAWAITSTAT)
Base 0x400F.F000
Offset 0x010
Type RO, reset 0xFFFF.FFC0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WAITREQ[n]
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
8
7
6
5
4
3
2
1
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WAITREQ[n]
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
31:0
WAITREQ[n]
RO
RO
1
Reset
RO
1
RO
1
Description
0xFFFF.FFC0 Channel [n] Wait Status
These bits provide the channel wait-on-request status. Bit 0 corresponds
to channel 0.
Value Description
1
The corresponding channel is waiting on a request.
0
The corresponding channel is not waiting on a request.
July 03, 2014
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Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014
Each bit of the DMASWREQ register represents the corresponding μDMA channel. Setting a bit
generates a request for the specified μDMA channel.
DMA Channel Software Request (DMASWREQ)
Base 0x400F.F000
Offset 0x014
Type WO, reset 31
30
29
28
27
26
25
24
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
SWREQ[n]
Type
Reset
SWREQ[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
SWREQ[n]
WO
-
WO
-
Description
Channel [n] Software Request
These bits generate software requests. Bit 0 corresponds to channel 0.
Value Description
1
Generate a software request for the corresponding channel.
0
No request generated.
These bits are automatically cleared when the software request has
been completed.
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Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018
Each bit of the DMAUSEBURSTSET register represents the corresponding μDMA channel. Setting
a bit disables the channel's single request input from generating requests, configuring the channel
to only accept burst requests. Reading the register returns the status of USEBURST.
If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET[n]
bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than
the arbitration (burst) size, the μDMA controller automatically clears the corresponding SET[n] bit,
allowing the remaining items to transfer using single requests. In order to resume transfers using
burst requests, the corresponding bit must be set again. A bit should not be set if the corresponding
peripheral does not support the burst request model.
Refer to “Request Types” on page 370 for more details about request types.
DMA Channel Useburst Set (DMAUSEBURSTSET)
Base 0x400F.F000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
31:0
SET[n]
R/W
Reset
Description
0x0000.0000 Channel [n] Useburst Set
Value Description
0
μDMA channel [n] responds to single or burst requests.
1
μDMA channel [n] responds only to burst requests.
Bit 0 corresponds to channel 0. This bit is automatically cleared as
described above. A bit can also be manually cleared by setting the
corresponding CLR[n] bit in the DMAUSEBURSTCLR register.
July 03, 2014
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Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C
Each bit of the DMAUSEBURSTCLR register represents the corresponding μDMA channel. Setting
a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register.
DMA Channel Useburst Clear (DMAUSEBURSTCLR)
Base 0x400F.F000
Offset 0x01C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
CLR[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Channel [n] Useburst Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAUSEBURSTSET register meaning that µDMA channel [n]
responds to single and burst requests.
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Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset
0x020
Each bit of the DMAREQMASKSET register represents the corresponding μDMA channel. Setting
a bit disables μDMA requests for the channel. Reading the register returns the request mask status.
When a μDMA channel's request is masked, that means the peripheral can no longer request μDMA
transfers. The channel can then be used for software-initiated transfers.
DMA Channel Request Mask Set (DMAREQMASKSET)
Base 0x400F.F000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SET[n]
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
SET[n]
R/W
R/W
0
Reset
R/W
0
Description
0x0000.0000 Channel [n] Request Mask Set
Value Description
0
The peripheral associated with channel [n] is enabled to request
μDMA transfers.
1
The peripheral associated with channel [n] is not able to request
μDMA transfers. Channel [n] may be used for software-initiated
transfers.
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAREQMASKCLR register.
July 03, 2014
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Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset
0x024
Each bit of the DMAREQMASKCLR register represents the corresponding μDMA channel. Setting
a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register.
DMA Channel Request Mask Clear (DMAREQMASKCLR)
Base 0x400F.F000
Offset 0x024
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
WO
-
Description
Channel [n] Request Mask Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAREQMASKSET register meaning that the peripheral
associated with channel [n] is enabled to request μDMA
transfers.
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July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028
Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit
enables the corresponding µDMA channel. Reading the register returns the enable status of the
channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the
channel can be used for software-initiated transfers.
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
31:0
SET[n]
R/W
Reset
Description
0x0000.0000 Channel [n] Enable Set
Value Description
0
µDMA Channel [n] is disabled.
1
µDMA Channel [n] is enabled.
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAENACLR register.
July 03, 2014
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Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C
Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAENASET register.
DMA Channel Enable Clear (DMAENACLR)
Base 0x400F.F000
Offset 0x02C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
CLR[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Clear Channel [n] Enable Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAENASET register meaning that channel [n] is disabled for
μDMA transfers.
Note:
The controller disables a channel when it completes the μDMA
cycle.
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July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030
Each bit of the DMAALTSET register represents the corresponding µDMA channel. Setting a bit
configures the µDMA channel to use the alternate control data structure. Reading the register returns
the status of which control data structure is in use for the corresponding µDMA channel.
DMA Channel Primary Alternate Set (DMAALTSET)
Base 0x400F.F000
Offset 0x030
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
31:0
SET[n]
R/W
Reset
Description
0x0000.0000 Channel [n] Alternate Set
Value Description
0
µDMA channel [n] is using the primary control structure.
1
µDMA channel [n] is using the alternate control structure.
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAALTCLR register.
Note:
For Ping-Pong and Scatter-Gather cycle types, the µDMA
controller automatically sets these bits to select the alternate
channel control data structure.
July 03, 2014
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Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset
0x034
Each bit of the DMAALTCLR register represents the corresponding μDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAALTSET register.
DMA Channel Primary Alternate Clear (DMAALTCLR)
Base 0x400F.F000
Offset 0x034
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
WO
-
Description
Channel [n] Alternate Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAALTSET register meaning that channel [n] is using the
primary control structure.
Note:
For Ping-Pong and Scatter-Gather cycle types, the µDMA
controller automatically sets these bits to select the alternate
channel control data structure.
412
July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038
Each bit of the DMAPRIOSET register represents the corresponding µDMA channel. Setting a bit
configures the µDMA channel to have a high priority level. Reading the register returns the status
of the channel priority mask.
DMA Channel Priority Set (DMAPRIOSET)
Base 0x400F.F000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
31:0
SET[n]
R/W
Reset
Description
0x0000.0000 Channel [n] Priority Set
Value Description
0
µDMA channel [n] is using the default priority level.
1
µDMA channel [n] is using a high priority level.
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAPRIOCLR register.
July 03, 2014
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Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C
Each bit of the DMAPRIOCLR register represents the corresponding µDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAPRIOSET register.
DMA Channel Priority Clear (DMAPRIOCLR)
Base 0x400F.F000
Offset 0x03C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
CLR[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Channel [n] Priority Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAPRIOSET register meaning that channel [n] is using the
default priority level.
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July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C
The DMAERRCLR register is used to read and clear the µDMA bus error status. The error status
is set if the μDMA controller encountered a bus error while performing a transfer. If a bus error
occurs on a channel, that channel is automatically disabled by the μDMA controller. The other
channels are unaffected.
DMA Bus Error Clear (DMAERRCLR)
Base 0x400F.F000
Offset 0x04C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ERRCLR
R/W1C
0
RO
0
ERRCLR
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Bus Error Status
Value Description
0
No bus error is pending.
1
A bus error is pending.
This bit is cleared by writing a 1 to it.
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Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500
Each bit of the DMACHASGN register represents the corresponding µDMA channel. Setting a bit
selects the secondary channel assignment as specified in Table 8-1 on page 368.
DMA Channel Assignment (DMACHASGN)
Base 0x400F.F000
Offset 0x500
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
CHASGN[n]
Type
Reset
CHASGN[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CHASGN[n]
R/W
-
R/W
-
Description
Channel [n] Assignment Select
Value Description
0
Use the primary channel assignment.
1
Use the secondary channel assignment.
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Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504
Each bit of the DMACHIS register represents the corresponding µDMA channel. A bit is set when
that μDMA channel causes a completion interrupt. The bits are cleared by a writing a 1.
DMA Channel Interrupt Status (DMACHIS)
Base 0x400F.F000
Offset 0x504
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
CHIS[n]
Type
Reset
CHIS[n]
Type
Reset
Bit/Field
Name
Type
31:0
CHIS[n]
R/W1C
Reset
Description
0x0000.0000 Channel [n] Interrupt Status
Value Description
1
The corresponding μDMA channel caused an interrupt.
0
The corresponding μDMA channel has not caused an interrupt.
This bit is cleared by writing a 1 to it.
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Register 23: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0
The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA Peripheral Identification 0 (DMAPeriphID0)
Base 0x400F.F000
Offset 0xFE0
Type RO, reset 0x0000.0030
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x30
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
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Register 24: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4
The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA Peripheral Identification 1 (DMAPeriphID1)
Base 0x400F.F000
Offset 0xFE4
Type RO, reset 0x0000.00B2
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID1
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0xB2
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
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Register 25: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8
The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA Peripheral Identification 2 (DMAPeriphID2)
Base 0x400F.F000
Offset 0xFE8
Type RO, reset 0x0000.000B
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
reserved
Type
Reset
reserved
Type
Reset
PID2
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x0B
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
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Register 26: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC
The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA Peripheral Identification 3 (DMAPeriphID3)
Base 0x400F.F000
Offset 0xFEC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID3
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
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Register 27: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0
The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA Peripheral Identification 4 (DMAPeriphID4)
Base 0x400F.F000
Offset 0xFD0
Type RO, reset 0x0000.0004
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID4
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x04
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register
Can be used by software to identify the presence of this peripheral.
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Register 28: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0
The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 0 (DMAPCellID0)
Base 0x400F.F000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
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Register 29: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4
The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 1 (DMAPCellID1)
Base 0x400F.F000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
CID1
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
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Register 30: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8
The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 2 (DMAPCellID2)
Base 0x400F.F000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID2
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
μDMA PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
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Register 31: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC
The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 3 (DMAPCellID3)
Base 0x400F.F000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID3
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
μDMA PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
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9
General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of nine physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H, Port J). The GPIO module
supports up to 60 programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
■ Up to 60 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant in input configuration
■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back
access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility
with existing code
■ Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for
ports on APB
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA
for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
9.1
Signal Description
GPIO signals have alternate hardware functions. The following table lists the GPIO pins and their
analog and digital alternate functions. The AINx and VREFA analog signals are not 5-V tolerant and
go through an isolation circuit before reaching their circuitry. These signals are configured by clearing
the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the
corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. Other analog
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signals are 5-V tolerant and are connected directly to their circuitry (C0-, C0+, C1-, C1+, C2-, C2+,
USB0VBUS, USB0ID). These signals are configured by clearing the DEN bit in the GPIO Digital
Enable (GPIODEN) register. All GPIO signals are 5-V tolerant when configured as inputs except
for PB0 and PB1, which are limited to 3.6 V. The digital alternate hardware functions are enabled
by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN
registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the
numeric encoding shown in the table below. Note that each pin must be programmed individually;
no type of grouping is implied by the columns in the table. Table entries that are shaded gray are
the default values for the corresponding GPIO pin.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-1. GPIO Pins With Non-Zero Reset Values
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
0
0
0
GPIOPCTL
0
0x1
PA[5:2]
SSI0
0
0
0
0
0x1
PB[3:2]
I2C0
0
0
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
Table 9-2. GPIO Pins and Alternate Functions (100LQFP)
IO
Pin
Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PA0
26
-
U0Rx
-
-
-
-
-
-
I2C1SCL
U1Rx
-
-
PA1
27
-
U0Tx
-
-
-
-
-
-
I2C1SDA
U1Tx
-
-
PA2
28
-
SSI0Clk
-
-
-
-
-
-
-
I2S0RXSD
-
-
PA3
29
-
SSI0Fss
-
-
-
-
-
-
-
I2S0RXMCLK
-
-
PA4
30
-
SSI0Rx
-
-
-
CAN0Rx
-
-
-
I2S0TXSCK
-
-
PA5
31
-
SSI0Tx
-
-
-
CAN0Tx
-
-
-
I2S0TXWS
-
-
PA6
34
-
I2C1SCL
CCP1
-
-
-
CAN0Rx
-
USB0EPEN U1CTS
-
-
USB0PFLT U1DCD
PA7
35
-
I2C1SDA
CCP4
-
-
-
CAN0Tx
CCP3
-
-
PB0
66
USB0ID
CCP0
-
-
-
U1Rx
-
-
-
-
-
-
PB1
67
USB0VBUS
CCP2
-
-
CCP1
U1Tx
-
-
-
-
-
-
PB2
72
-
I2C0SCL
-
-
CCP3
CCP0
-
-
USB0EPEN
-
-
-
PB3
65
-
I2C0SDA
-
-
-
-
-
-
USB0PFLT
-
-
-
PB4
92
AIN10
C0-
-
-
-
U2Rx
CAN0Rx
-
U1Rx
EPI0S23
-
-
-
PB5
91
AIN11
C1-
C0o
CCP5
CCP6
CCP0
CAN0Tx
CCP2
U1Tx
EPI0S22
-
-
-
PB6
90
VREFA
C0+
CCP1
CCP7
C0o
-
-
CCP5
-
-
I2S0TXSCK
-
-
PB7
89
-
-
-
-
NMI
-
-
-
-
-
-
-
PC0
80
-
-
-
TCK
SWCLK
-
-
-
-
-
-
-
-
428
July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Table 9-2. GPIO Pins and Alternate Functions (100LQFP) (continued)
IO
Pin
Analog
Function
PC1
79
-
PC2
78
-
PC3
77
-
PC4
25
PC5
PC6
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
-
-
TMS
SWDIO
-
-
-
-
-
-
-
-
-
-
TDI
-
-
-
-
-
-
-
-
-
-
TDO
SWO
-
-
-
-
-
-
-
-
-
CCP5
-
-
-
CCP2
CCP4
-
EPI0S2
CCP1
-
-
24
C1+
CCP1
C1o
C0o
-
CCP3
USB0EPEN
-
EPI0S3
-
-
-
23
C2+
CCP3
-
C2o
-
U1Rx
CCP0
USB0PFLT EPI0S4
-
-
-
PC7
22
C2-
CCP4
-
-
CCP0
U1Tx
USB0PFLT
C1o
-
-
-
EPI0S5
PD0
10
AIN15
-
CAN0Rx
-
U2Rx
U1Rx
CCP6
-
I2S0RXSCK U1CTS
-
-
PD1
11
AIN14
-
CAN0Tx
-
U2Tx
U1Tx
CCP7
-
I2S0RXWS U1DCD
CCP2
-
PD2
12
AIN13
U1Rx
CCP6
-
CCP5
-
-
-
EPI0S20
-
-
-
PD3
13
AIN12
U1Tx
CCP7
-
CCP0
-
-
-
EPI0S21
-
-
-
PD4
97
AIN7
CCP0
CCP3
-
-
-
-
-
I2S0RXSD
U1RI
EPI0S19
-
PD5
98
AIN6
CCP2
CCP4
-
-
-
-
-
I2S0RXMCLK
U2Rx
EPI0S28
-
PD6
99
AIN5
-
-
-
-
-
-
-
I2S0TXSCK
U2Tx
EPI0S29
-
PD7
100
AIN4
-
C0o
CCP1
-
-
-
-
I2S0TXWS U1DTR
EPI0S30
-
-
-
-
-
PE0
74
-
-
SSI1Clk
CCP3
-
-
-
-
EPI0S8 USB0PFLT
PE1
75
-
-
SSI1Fss
-
CCP2
CCP6
-
-
EPI0S9
-
PE2
95
AIN9
CCP4
SSI1Rx
-
-
CCP2
-
-
EPI0S24
-
-
-
PE3
96
AIN8
CCP1
SSI1Tx
-
-
CCP7
-
-
EPI0S25
-
-
-
PE4
6
AIN3
CCP3
-
-
-
U2Tx
CCP2
-
-
I2S0TXWS
-
-
PE5
5
AIN2
CCP5
-
-
-
-
-
-
-
I2S0TXSD
-
-
PE6
2
AIN1
-
C1o
-
-
-
-
-
-
U1CTS
-
-
PE7
1
AIN0
-
C2o
-
-
-
-
-
-
U1DCD
-
-
PF0
47
-
CAN1Rx
-
-
-
-
-
-
I2S0TXSD U1DSR
-
-
PF1
61
-
CAN1Tx
-
-
-
-
-
-
I2S0TXMCLK U1RTS
CCP3
-
PF2
60
-
LED1
-
-
-
-
-
-
-
SSI1Clk
-
-
PF3
59
-
LED0
-
-
-
-
-
-
-
SSI1Fss
-
-
PF4
42
-
CCP0
C0o
-
-
-
-
-
EPI0S12 SSI1Rx
-
-
PF5
41
-
CCP2
C1o
-
-
-
-
-
EPI0S15 SSI1Tx
-
-
PG0
19
-
U2Rx
-
I2C1SCL
-
-
-
-
-
-
PG1
18
-
U2Tx
-
I2C1SDA
-
-
-
-
EPI0S14
-
-
-
PG7
36
-
-
-
-
-
-
-
-
CCP5
EPI0S31
-
-
-
-
-
USB0EPEN EPI0S13
PH0
86
-
CCP6
-
-
-
-
-
-
EPI0S6
PH1
85
-
CCP7
-
-
-
-
-
-
EPI0S7
-
-
-
PH2
84
-
-
C1o
-
-
-
-
-
EPI0S1
-
-
-
PH3
83
-
-
-
-
USB0EPEN
-
-
-
EPI0S0
-
-
-
PH4
76
-
-
-
-
USB0PFLT
-
-
-
EPI0S10
-
-
SSI1Clk
PH5
63
-
-
-
-
-
-
-
-
EPI0S11
-
-
SSI1Fss
PH6
62
-
-
-
-
-
-
-
-
EPI0S26
-
-
SSI1Rx
July 03, 2014
429
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Table 9-2. GPIO Pins and Alternate Functions (100LQFP) (continued)
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
IO
Pin
Analog
Function
1
2
3
4
5
6
7
8
9
10
11
PH7
15
-
-
-
-
-
-
-
-
EPI0S27
-
-
SSI1Tx
PJ0
14
-
-
-
-
-
-
-
-
EPI0S16
-
-
I2C1SCL
PJ1
87
-
-
-
-
-
-
-
-
EPI0S17 USB0PFLT
-
I2C1SDA
PJ2
39
-
-
-
-
-
-
-
-
EPI0S18
-
-
CCP0
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin.
Table 9-3. GPIO Pins and Alternate Functions (108BGA)
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
IO
Pin
Analog
Function
1
2
3
4
5
6
7
8
9
10
11
PA0
L3
-
U0Rx
-
-
-
-
-
-
I2C1SCL
U1Rx
-
-
PA1
M3
-
U0Tx
-
-
-
-
-
-
I2C1SDA
U1Tx
-
-
PA2
M4
-
SSI0Clk
-
-
-
-
-
-
-
I2S0RXSD
-
-
PA3
L4
-
SSI0Fss
-
-
-
-
-
-
-
I2S0RXMCLK
-
-
PA4
L5
-
SSI0Rx
-
-
-
CAN0Rx
-
-
-
I2S0TXSCK
-
-
PA5
M5
-
SSI0Tx
-
-
-
CAN0Tx
-
-
-
I2S0TXWS
-
-
PA6
L6
-
I2C1SCL
CCP1
-
-
-
CAN0Rx
-
USB0EPEN U1CTS
-
-
USB0PFLT U1DCD
PA7
M6
-
I2C1SDA
CCP4
-
-
-
CAN0Tx
CCP3
PB0
E12
USB0ID
CCP0
-
-
-
U1Rx
-
-
-
-
-
-
-
-
PB1
D12
USB0VBUS
CCP2
-
-
CCP1
U1Tx
-
-
-
-
-
-
PB2
A11
-
I2C0SCL
-
-
CCP3
CCP0
-
-
USB0EPEN
-
-
-
PB3
E11
-
I2C0SDA
-
-
-
-
-
-
USB0PFLT
-
-
-
PB4
A6
AIN10
C0-
-
-
-
U2Rx
CAN0Rx
-
U1Rx
EPI0S23
-
-
-
PB5
B7
AIN11
C1-
C0o
CCP5
CCP6
CCP0
CAN0Tx
CCP2
U1Tx
EPI0S22
-
-
-
PB6
A7
VREFA
C0+
CCP1
CCP7
C0o
-
-
CCP5
-
-
I2S0TXSCK
-
-
PB7
A8
-
-
-
-
NMI
-
-
-
-
-
-
-
PC0
A9
-
-
-
TCK
SWCLK
-
-
-
-
-
-
-
-
PC1
B9
-
-
-
TMS
SWDIO
-
-
-
-
-
-
-
-
PC2
B8
-
-
-
TDI
-
-
-
-
-
-
-
-
PC3
A10
-
-
-
TDO
SWO
-
-
-
-
-
-
-
-
PC4
L1
-
CCP5
-
-
-
CCP2
CCP4
-
EPI0S2
CCP1
-
-
PC5
M1
C1+
CCP1
C1o
C0o
-
CCP3
USB0EPEN
-
EPI0S3
-
-
-
PC6
M2
C2+
CCP3
-
C2o
-
U1Rx
CCP0
USB0PFLT EPI0S4
-
-
-
-
PC7
L2
C2-
CCP4
-
-
CCP0
U1Tx
USB0PFLT
C1o
PD0
G1
AIN15
-
CAN0Rx
-
U2Rx
U1Rx
CCP6
-
PD1
G2
AIN14
-
CAN0Tx
-
U2Tx
U1Tx
CCP7
PD2
H2
AIN13
U1Rx
CCP6
-
CCP5
-
-
430
-
-
I2S0RXSCK U1CTS
-
-
-
I2S0RXWS U1DCD
CCP2
-
-
EPI0S20
-
-
EPI0S5
-
July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Table 9-3. GPIO Pins and Alternate Functions (108BGA) (continued)
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
IO
Pin
Analog
Function
1
2
3
4
5
6
7
8
9
10
11
PD3
H1
AIN12
U1Tx
CCP7
-
CCP0
-
-
-
EPI0S21
-
-
-
PD4
B5
AIN7
CCP0
CCP3
-
-
-
-
-
I2S0RXSD
U1RI
EPI0S19
-
PD5
C6
AIN6
CCP2
CCP4
-
-
-
-
-
I2S0RXMCLK
U2Rx
EPI0S28
-
PD6
A3
AIN5
-
-
-
-
-
-
-
I2S0TXSCK
U2Tx
EPI0S29
-
PD7
A2
AIN4
-
C0o
CCP1
-
-
-
-
I2S0TXWS U1DTR
EPI0S30
-
PE0
B11
-
-
SSI1Clk
CCP3
-
-
-
-
EPI0S8 USB0PFLT
-
-
PE1
A12
-
-
SSI1Fss
-
CCP2
CCP6
-
-
EPI0S9
-
-
-
PE2
A4
AIN9
CCP4
SSI1Rx
-
-
CCP2
-
-
EPI0S24
-
-
-
PE3
B4
AIN8
CCP1
SSI1Tx
-
-
CCP7
-
-
EPI0S25
-
-
-
PE4
B2
AIN3
CCP3
-
-
-
U2Tx
CCP2
-
-
I2S0TXWS
-
-
PE5
B3
AIN2
CCP5
-
-
-
-
-
-
-
I2S0TXSD
-
-
PE6
A1
AIN1
-
C1o
-
-
-
-
-
-
U1CTS
-
-
PE7
B1
AIN0
-
C2o
-
-
-
-
-
-
U1DCD
-
-
PF0
M9
-
CAN1Rx
-
-
-
-
-
-
I2S0TXSD U1DSR
-
-
I2S0TXMCLK U1RTS
PF1
H12
-
CAN1Tx
-
-
-
-
-
-
CCP3
-
PF2
J11
-
LED1
-
-
-
-
-
-
-
SSI1Clk
-
-
PF3
J12
-
LED0
-
-
-
-
-
-
-
SSI1Fss
-
-
PF4
K4
-
CCP0
C0o
-
-
-
-
-
EPI0S12 SSI1Rx
-
-
PF5
K3
-
CCP2
C1o
-
-
-
-
-
EPI0S15 SSI1Tx
-
-
PG0
K1
-
U2Rx
-
I2C1SCL
-
-
-
PG1
K2
-
U2Tx
-
I2C1SDA
-
-
-
PG7
C10
-
-
-
-
-
-
-
-
-
-
-
EPI0S14
-
-
-
-
CCP5
EPI0S31
-
-
USB0EPEN EPI0S13
PH0
C9
-
CCP6
-
-
-
-
-
-
EPI0S6
-
-
-
PH1
C8
-
CCP7
-
-
-
-
-
-
EPI0S7
-
-
-
PH2
D11
-
-
C1o
-
-
-
-
-
EPI0S1
-
-
-
PH3
D10
-
-
-
-
USB0EPEN
-
-
-
EPI0S0
-
-
-
PH4
B10
-
-
-
-
USB0PFLT
-
-
-
EPI0S10
-
-
SSI1Clk
PH5
F10
-
-
-
-
-
-
-
-
EPI0S11
-
-
SSI1Fss
PH6
G3
-
-
-
-
-
-
-
-
EPI0S26
-
-
SSI1Rx
PH7
H3
-
-
-
-
-
-
-
-
EPI0S27
-
-
SSI1Tx
PJ0
F3
-
-
-
-
-
-
-
-
EPI0S16
-
-
I2C1SCL
PJ1
B6
-
-
-
-
-
-
-
-
EPI0S17 USB0PFLT
-
I2C1SDA
PJ2
K6
-
-
-
-
-
-
-
-
EPI0S18
-
-
CCP0
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin.
9.2
Functional Description
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
9-1 on page 432 and Figure 9-2 on page 433). The LM3S9U90 microcontroller contains nine ports
and thus nine of these physical GPIO blocks. Note that not all pins may be implemented on every
block. Some GPIO pins can function as I/O signals for the on-chip peripheral modules. For information
on which GPIO pins are used for alternate hardware functions, refer to Table 23-5 on page 1181.
July 03, 2014
431
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Figure 9-1. Digital I/O Pads
Commit
Control
GPIOLOCK
GPIOCR
Port
Control
GPIOPCTL
Mode
Control
GPIOAFSEL
Periph 1
DEMUX
Alternate Input
Alternate Output
Alternate Output Enable
MUX
Periph 0
Pad Input
Periph n
GPIO Output
GPIO Output Enable
Interrupt
Control
Pad
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
MUX
GPIODATA
GPIODIR
Interrupt
MUX
GPIO Input
Data
Control
Pad Output
Digital
I/O
Pad
Package I/O Pin
Pad Output
Enable
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
432
July 03, 2014
Texas Instruments-Production Data
®
Stellaris LM3S9U90 Microcontroller
Figure 9-2. Analog/Digital I/O Pads
Commit
Control
GPIOLOCK
GPIOCR
Port
Control
GPIOPCTL
Mode
Control
GPIOAFSEL
Periph 1
DEMUX
Alternate Input
Alternate Output
Alternate Output Enable
MUX
Periph 0
Pad Input
Periph n
MUX
MUX
Data
Control
Pad Output
Pad Output Enable
Analog/Digital
I/O Pad
Package I/O Pin
GPIO Input
GPIO Output
GPIODATA
GPIODIR
Interrupt
GPIO Output Enable
Interrupt
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Pad
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
GPIOAMSEL
Analog Circuitry
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
9.2.1
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
ADC
(for GPIO pins that
connect to the ADC
input MUX)
Isolation
Circuit
Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of
the part. This issue can be avoided with a software routine that restores JTAG functionality based on
an external or software trigger.
9.2.1.1
Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 441) is used to configure each individual pin as
an input or output. When the data direction bit is cleared, the GPIO is configured as an input, and
the corresponding data register bit captures and stores the value on the GPIO port. When the data
direction bit is set, the GPIO is configured as an output, and the corresponding data register bit is
driven out on the GPIO port.
July 03, 2014
433
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
9.2.1.2
Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 440) by using bits [9:2] of the address bus as a mask.
In this manner, software drivers can modify individual GPIO pins in a single instruction without
affecting the state of the other pins. This method is more efficient than the conventional method of
performing a read-modify-write operation to set or clear an individual GPIO pin. To implement this
feature, the GPIODATA register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set, the value of the GPIODATA
register is altered. If the address bit is cleared, the data bit is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 has the results shown in
Figure 9-3, where u indicates that data is unchanged by the write.
Figure 9-3. GPIODATA Write Example
ADDR[9:2]
0x098
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
0
0
0
0xEB
1
1
1
0
1
0
1
1
GPIODATA
u
u
1
u
u
0
1
u
7
6
5
4
3
2
1
0
During a read, if the address bit associated with the data bit is set, the value is read. If the address
bit associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual
value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-4.
Figure 9-4. GPIODATA Read Example
9.2.2
ADDR[9:2]
0x0C4
9
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
1
0
0
GPIODATA
1
0
1
1
1
1
1
0
Returned Value
0
0
1
1
0
0
0
0
7
6
5
4
3
2
1
0
Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. These registers
are used to select the source of the interrupt, its polarity, and the edge properties. When one or
more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for
the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any
further interrupts. For a level-sensitive interrupt, the external source must hold the level constant
for the interrupt to be recognized by the controller.
Three registers define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 442)
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■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 443)
■ GPIO Interrupt Event (GPIOIEV) register (see page 444)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 445).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 446 and page 447). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates
that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the
interrupt controller.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 449).
When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts
should be masked (GPIOIM cleared). Writing any value to an interrupt control register can generate
a spurious interrupt if the corresponding bits are enabled.
9.2.2.1
ADC Trigger Source
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set), an interrupt
for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event
Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion
is initiated. See page 662.
If no other Port B pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0)
register can disable the Port B interrupts, and the ADC interrupt can be used to read back the
converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts on PB4 and
wait for the ADC interrupt, or the ADC interrupt must be disabled in the EN0 register and the Port
B interrupt handler must poll the ADC registers until the conversion is completed. See page 126 for
more information.
9.2.3
Mode Control
The GPIO pins can be controlled by either software or hardware. Software control is the default for
most signals and corresponds to the GPIO mode, where the GPIODATA register is used to read
or write the corresponding pins. When hardware control is enabled via the GPIO Alternate Function
Select (GPIOAFSEL) register (see page 450), the pin state is controlled by its alternate function
(that is, the peripheral).
Further pin muxing options are provided through the GPIO Port Control (GPIOPCTL) register which
selects one of several peripheral functions for each GPIO. For information on the configuration
options, refer to Table 23-5 on page 1181.
Note:
9.2.4
If any pin is to be used as an ADC input, the appropriate bit in the GPIOAMSEL register
must be set to disable the analog isolation circuit.
Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD
pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 450), GPIO Pull Up Select (GPIOPUR) register (see page 456), GPIO Pull-Down
Select (GPIOPDR) register (see page 458), and GPIO Digital Enable (GPIODEN) register (see
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page 461) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 463)
has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 464)
have been set.
9.2.5
Pad Control
The pad control registers allow software to configure the GPIO pads based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable
for each GPIO.
9.2.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
9.3
Initialization and Configuration
The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the
Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other
aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides
better back-to-back access performance than the APB bus. These apertures are mutually exclusive.
The aperture enabled for a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL
register (see page 224).
To use the pins in a particular GPIO port, the clock for the port must be enabled by setting the
appropriate GPIO Port bit field (GPIOn) in the RCGC2 register (see page 277).
When the internal POR signal is asserted and until otherwise configured, all GPIO pins are configured
to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0, except for
the pins shown in Table 9-1 on page 428. Table 9-4 on page 436 shows all possible configurations
of the GPIO pads and the control register settings required to achieve them. Table 9-5 on page 437
shows how a rising edge interrupt is configured for pin 2 of a GPIO port.
Table 9-4. GPIO Pad Configuration Examples
a
Configuration
GPIO Register Bit Value
AFSEL
DIR
ODR
DEN
PUR
PDR
DR2R
DR4R
DR8R
SLR
Digital Input (GPIO)
0
0
0
1
?
?
X
X
X
X
Digital Output (GPIO)
0
1
0
1
?
?
?
?
?
?
Open Drain Output
(GPIO)
0
1
1
1
X
X
?
?
?
?
Open Drain
Input/Output (I2C)
1
X
1
1
X
X
?
?
?
?
Digital Input (Timer
CCP)
1
X
0
1
?
?
X
X
X
X
Digital Output (Timer
PWM)
1
X
0
1
?
?
?
?
?
?
Digital Input/Output
(SSI)
1
X
0
1
?
?
?
?
?
?
Digital Input/Output
(UART)
1
X
0
1
?
?
?
?
?
?
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Table 9-4. GPIO Pad Configuration Examples (continued)
a
Configuration
GPIO Register Bit Value
DR2R
DR4R
DR8R
Analog Input
(Comparator)
AFSEL
0
DIR
0
ODR
0
DEN
0
PUR
0
PDR
0
X
X
X
SLR
X
Digital Output
(Comparator)
1
X
0
1
?
?
?
?
?
?
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 9-5. GPIO Interrupt Configuration Example
Desired Interrupt
Event Trigger
Register
GPIOIS
0=edge
a
Pin 2 Bit Value
7
6
5
4
3
2
1
0
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
0
0
0
0
0
1
0
0
1=level
GPIOIBE
0=single edge
1=both edges
GPIOIEV
0=Low level, or falling
edge
1=High level, or rising
edge
GPIOIM
0=masked
1=not masked
a. X=Ignored (don’t care bit)
9.4
Register Map
Table 9-7 on page 438 lists the GPIO registers. Each GPIO port can be accessed through one of
two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible
with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers
the same register map but provides better back-to-back access performance than the APB bus.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to unconnected bits has no effect, and reading unconnected bits returns
no meaningful data.
The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s
base address:
■
■
■
■
■
■
■
■
■
■
GPIO Port A (APB): 0x4000.4000
GPIO Port A (AHB): 0x4005.8000
GPIO Port B (APB): 0x4000.5000
GPIO Port B (AHB): 0x4005.9000
GPIO Port C (APB): 0x4000.6000
GPIO Port C (AHB): 0x4005.A000
GPIO Port D (APB): 0x4000.7000
GPIO Port D (AHB): 0x4005.B000
GPIO Port E (APB): 0x4002.4000
GPIO Port E (AHB): 0x4005.C000
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■
■
■
■
■
■
■
■
GPIO Port F (APB): 0x4002.5000
GPIO Port F (AHB): 0x4005.D000
GPIO Port G (APB): 0x4002.6000
GPIO Port G (AHB): 0x4005.E000
GPIO Port H (APB): 0x4002.7000
GPIO Port H (AHB): 0x4005.F000
GPIO Port J (APB): 0x4003.D000
GPIO Port J (AHB): 0x4006.0000
Note that each GPIO module clock must be enabled before the registers can be programmed (see
page 277). There must be a delay of 3 system clocks after the GPIO module clock is enabled before
any GPIO module registers are accessed.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-6. GPIO Pins With Non-Zero Reset Values
GPIO Pins
Default State
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
GPIOPCTL
PA[1:0]
UART0
0
0
0
0
0x1
PA[5:2]
SSI0
0
0
0
0
0x1
PB[3:2]
I2C0
0
0
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the
NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are the only GPIOs that
are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO
Port C[3:0] is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception
of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is
not accidentally programmed as GPIO pins, the PC[3:0] pins default to non-committable. Similarly,
to ensure that the NMI pin is not accidentally programmed as a GPIO pin, the PB7 pin defaults to
non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F
while the default reset value of GPIOCR for Port C is 0x0000.00F0.
Table 9-7. GPIO Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
GPIODATA
R/W
0x0000.0000
GPIO Data
440
0x400
GPIODIR
R/W
0x0000.0000
GPIO Direction
441
0x404
GPIOIS
R/W
0x0000.0000
GPIO Interrupt Sense
442
0x408
GPIOIBE
R/W
0x0000.0000
GPIO Interrupt Both Edges
443
0x40C
GPIOIEV
R/W
0x0000.0000
GPIO Interrupt Event
444
0x410
GPIOIM
R/W
0x0000.0000
GPIO Interrupt Mask
445
0x414
GPIORIS
RO
0x0000.0000
GPIO Raw Interrupt Status
446
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Table 9-7. GPIO Register Map (continued)
Offset
Name
0x418
Reset
GPIOMIS
RO
0x0000.0000
GPIO Masked Interrupt Status
447
0x41C
GPIOICR
W1C
0x0000.0000
GPIO Interrupt Clear
449
0x420
GPIOAFSEL
R/W
-
GPIO Alternate Function Select
450
0x500
GPIODR2R
R/W
0x0000.00FF
GPIO 2-mA Drive Select
452
0x504
GPIODR4R
R/W
0x0000.0000
GPIO 4-mA Drive Select
453
0x508
GPIODR8R
R/W
0x0000.0000
GPIO 8-mA Drive Select
454
0x50C
GPIOODR
R/W
0x0000.0000
GPIO Open Drain Select
455
0x510
GPIOPUR
R/W
-
GPIO Pull-Up Select
456
0x514
GPIOPDR
R/W
0x0000.0000
GPIO Pull-Down Select
458
0x518
GPIOSLR
R/W
0x0000.0000
GPIO Slew Rate Control Select
460
0x51C
GPIODEN
R/W
-
GPIO Digital Enable
461
0x520
GPIOLOCK
R/W
0x0000.0001
GPIO Lock
463
0x524
GPIOCR
-
-
GPIO Commit
464
0x528
GPIOAMSEL
R/W
0x0000.0000
GPIO Analog Mode Select
466
0x52C
GPIOPCTL
R/W
-
GPIO Port Control
468
0xFD0
GPIOPeriphID4
RO
0x0000.0000
GPIO Peripheral Identification 4
470
0xFD4
GPIOPeriphID5
RO
0x0000.0000
GPIO Peripheral Identification 5
471
0xFD8
GPIOPeriphID6
RO
0x0000.0000
GPIO Peripheral Identification 6
472
0xFDC
GPIOPeriphID7
RO
0x0000.0000
GPIO Peripheral Identification 7
473
0xFE0
GPIOPeriphID0
RO
0x0000.0061
GPIO Peripheral Identification 0
474
0xFE4
GPIOPeriphID1
RO
0x0000.0000
GPIO Peripheral Identification 1
475
0xFE8
GPIOPeriphID2
RO
0x0000.0018
GPIO Peripheral Identification 2
476
0xFEC
GPIOPeriphID3
RO
0x0000.0001
GPIO Peripheral Identification 3
477
0xFF0
GPIOPCellID0
RO
0x0000.000D
GPIO PrimeCell Identification 0
478
0xFF4
GPIOPCellID1
RO
0x0000.00F0
GPIO PrimeCell Identification 1
479
0xFF8
GPIOPCellID2
RO
0x0000.0005
GPIO PrimeCell Identification 2
480
0xFFC
GPIOPCellID3
RO
0x0000.00B1
GPIO PrimeCell Identification 3
481
9.5
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 441).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be set. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are set in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are clear in the address mask cause
the corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
DATA
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DATA
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and written to the registers are
masked by the eight address lines [9:2]. Reads from this register return
its current state. Writes to this register only affect bits that are not masked
by ADDR[9:2] and are configured as outputs. See “Data Register
Operation” on page 434 for examples of reads and writes.
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Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures
the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be
an input. All bits are cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DIR
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DIR
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Data Direction
Value Description
0
Corresponding pin is an input.
1
Corresponding pins is an output.
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures
the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect
edges. All bits are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x404
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
IS
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Sense
Value Description
0
The edge on the corresponding pin is detected (edge-sensitive).
1
The level on the corresponding pin is detected (level-sensitive).
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the
GPIO Interrupt Sense (GPIOIS) register (see page 442) is set to detect edges, setting a bit in the
GPIOIBE register configures the corresponding pin to detect both rising and falling edges, regardless
of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 444). Clearing
a bit configures the pin to be controlled by the GPIOIEV register. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x408
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IBE
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
IBE
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Both Edges
Value Description
0
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 444).
1
Both edges on the corresponding pin trigger an interrupt.
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General-Purpose Input/Outputs (GPIOs)
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures
the corresponding pin to detect rising edges or high levels, depending on the corresponding bit
value in the GPIO Interrupt Sense (GPIOIS) register (see page 442). Clearing a bit configures the
pin to detect falling edges or low levels, depending on the corresponding bit value in the GPIOIS
register. All bits are cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x40C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IEV
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
IEV
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Event
Value Description
0
A falling edge or a Low level on the corresponding pin triggers
an interrupt.
1
A rising edge or a High level on the corresponding pin triggers
an interrupt.
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Stellaris LM3S9U90 Microcontroller
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows
interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the
combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being
sent to the interrupt controller. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x410
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IME
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
7:0
IME
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Mask Enable
Value Description
0
The interrupt from the corresponding pin is masked.
1
The interrupt from the corresponding pin is sent to the interrupt
controller.
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General-Purpose Input/Outputs (GPIOs)
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt
condition occurs on the corresponding GPIO pin. If the corresponding bit in the GPIO Interrupt
Mask (GPIOIM) register (see page 445) is set, the interrupt is sent to the interrupt controller. Bits
read as zero indicate that corresponding input pins have not initiated an interrupt. A bit in this register
can be cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR)
register.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x414
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RIS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
7:0
RIS
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Raw Status
Value Description
1
An interrupt condition has occurred on the corresponding pin.
0
An interrupt condition has not occurred on the corresponding
pin.
A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR
register.
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Stellaris LM3S9U90 Microcontroller
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the
corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either
no interrupt has been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set), an interrupt
for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event
Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion
is initiated. See page 662.
If no other Port B pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0)
register can disable the Port B interrupts, and the ADC interrupt can be used to read back the
converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts on PB4 and
wait for the ADC interrupt, or the ADC interrupt must be disabled in the EN0 register and the Port
B interrupt handler must poll the ADC registers until the conversion is completed. See page 126 for
more information.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x418
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
MIS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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General-Purpose Input/Outputs (GPIOs)
Bit/Field
Name
Type
Reset
Description
7:0
MIS
RO
0x00
GPIO Masked Interrupt Status
Value Description
1
An interrupt condition on the corresponding pin has triggered
an interrupt to the interrupt controller.
0
An interrupt condition on the corresponding pin is masked or
has not occurred.
A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR
register.
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®
Stellaris LM3S9U90 Microcontroller
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt bit in the GPIORIS and GPIOMIS registers. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x41C
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
W1C
0
W1C
0
W1C
0
W1C
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IC
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
7:0
IC
W1C
0x00
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Clear
Value Description
1
The corresponding interrupt is cleared.
0
The corresponding interrupt is unaffected.
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General-Purpose Input/Outputs (GPIOs)
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. If a bit is clear, the pin is used as a
GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the
corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral
functions are multiplexed on each GPIO. The GPIO Port Control (GPIOPCTL) register is used to
select one of the possible functions. Table 23-5 on page 1181 details which functions are muxed on
each GPIO pin. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed
in the table below.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-8. GPIO Pins With Non-Zero Reset Values
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
0
0
0
0
GPIOPCTL
0x1
PA[5:2]
SSI0
0
0
0
0
0x1
PB[3:2]
I2C0
0
0
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins
to their GPIO functionality, the debugger may not have enough time to connect and halt the controller
before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part.
This issue can be avoided with a software routine that restores JTAG functionality based on an external
or software trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD
pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 450), GPIO Pull Up Select (GPIOPUR) register (see page 456), GPIO Pull-Down
Select (GPIOPDR) register (see page 458), and GPIO Digital Enable (GPIODEN) register (see
page 461) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 463)
has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 464)
have been set.
When using the I2C module, in addition to setting the GPIOAFSEL register bits for the I2C clock
and data pins, the data pins should be set to open drain using the GPIO Open Drain Select
(GPIOODR) register (see examples in “Initialization and Configuration” on page 436).
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GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x420
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
AFSEL
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
AFSEL
R/W
-
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Alternate Function Select
Value Description
0
The associated pin functions as a GPIO and is controlled by
the GPIO registers.
1
The associated pin functions as a peripheral signal and is
controlled by the alternate hardware function.
The reset value for this register is 0x0000.0000 for GPIO ports
that are not listed in Table 9-1 on page 428.
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General-Purpose Input/Outputs (GPIOs)
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be
individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal,
the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are
automatically cleared by hardware. By default, all GPIO pins have 2-mA drive.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x500
Type R/W, reset 0x0000.00FF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DRV2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DRV2
R/W
0xFF
RO
0
R/W
1
R/W
1
R/W
1
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Output Pad 2-mA Drive Enable
Value Description
1
The corresponding GPIO pin has 2-mA drive.
0
The drive for the corresponding GPIO pin is controlled by the
GPIODR4R or GPIODR8R register.
Setting a bit in either the GPIODR4 register or the GPIODR8 register
clears the corresponding 2-mA enable bit. The change is effective on
the second clock cycle after the write if accessing GPIO via the APB
memory aperture. If using AHB access, the change is effective on the
next clock cycle.
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Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. Each GPIO signal in the port can be
individually configured without affecting the other pads. When setting the DRV4 bit for a GPIO signal,
the corresponding DRV2 bit in the GPIODR2R register and DRV8 bit in the GPIODR8R register are
automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x504
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DRV4
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DRV4
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Output Pad 4-mA Drive Enable
Value Description
1
The corresponding GPIO pin has 4-mA drive.
0
The drive for the corresponding GPIO pin is controlled by the
GPIODR2R or GPIODR8R register.
Setting a bit in either the GPIODR2 register or the GPIODR8 register
clears the corresponding 4-mA enable bit. The change is effective on
the second clock cycle after the write if accessing GPIO via the APB
memory aperture. If using AHB access, the change is effective on the
next clock cycle.
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General-Purpose Input/Outputs (GPIOs)
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. Each GPIO signal in the port can be
individually configured without affecting the other pads. When setting the DRV8 bit for a GPIO signal,
the corresponding DRV2 bit in the GPIODR2R register and DRV4 bit in the GPIODR4R register are
automatically cleared by hardware. The 8-mA setting is also used for high-current operation.
Note:
There is no configuration difference between 8-mA and high-current operation. The additional
current capacity results from a shift in the VOH/VOL levels. See “Recommended Operating
Conditions” on page 1222 for further information.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x508
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DRV8
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DRV8
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Output Pad 8-mA Drive Enable
Value Description
1
The corresponding GPIO pin has 8-mA drive.
0
The drive for the corresponding GPIO pin is controlled by the
GPIODR2R or GPIODR4R register.
Setting a bit in either the GPIODR2 register or the GPIODR4 register
clears the corresponding 8-mA enable bit. The change is effective on
the second clock cycle after the write if accessing GPIO via the APB
memory aperture. If using AHB access, the change is effective on the
next clock cycle.
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Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 461).
Corresponding bits in the drive strength and slew rate control registers (GPIODR2R, GPIODR4R,
GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts
as an input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while
the GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has
no effect until the GPIO is changed to an output.
When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate
Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set (see
examples in “Initialization and Configuration” on page 436).
GPIO Open Drain Select (GPIOODR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x50C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
ODE
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
ODE
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Output Pad Open Drain Enable
Value Description
1
The corresponding pin is configured as open drain.
0
The corresponding pin is not configured as open drain.
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General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on
the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 458). Write access
to this register is protected with the GPIOCR register. Bits in GPIOCR that are cleared prevent writes
to the equivalent bit in this register.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-9. GPIO Pins With Non-Zero Reset Values
Note:
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
0
0
0
GPIOPCTL
0
0x1
PA[5:2]
SSI0
0
0
0
0
0x1
PB[3:2]
I2C0
0
0
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7)
and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate
Function Select (GPIOAFSEL) register (see page 450), GPIO Pull Up Select (GPIOPUR)
register (see page 456), GPIO Pull-Down Select (GPIOPDR) register (see page 458), and
GPIO Digital Enable (GPIODEN) register (see page 461) are not committed to storage
unless the GPIO Lock (GPIOLOCK) register (see page 463) has been unlocked and the
appropriate bits of the GPIO Commit (GPIOCR) register (see page 464) have been set.
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x510
Type R/W, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
PUE
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Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PUE
R/W
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Pad Weak Pull-Up Enable
Value Description
0
The corresponding pin's weak pull-up resistor is disabled.
1
The corresponding pin's weak pull-up resistor is enabled.
Setting a bit in the GPIOPDR register clears the corresponding bit in
the GPIOPUR register. The change is effective on the second clock
cycle after the write if accessing GPIO via the APB memory aperture.
If using AHB access, the change is effective on the next clock cycle.
The reset value for this register is 0x0000.0000 for GPIO ports that are
not listed in Table 9-1 on page 428.
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General-Purpose Input/Outputs (GPIOs)
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set, a weak pull-down resistor
on the corresponding GPIO signal is enabled. Setting a bit in GPIOPDR automatically clears the
corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 456).
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-10. GPIO Pins With Non-Zero Reset Values
Note:
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
0
0
0
GPIOPCTL
0
0x1
PA[5:2]
SSI0
0
0
0
0
0x1
PB[3:2]
I2C0
0
0
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7)
and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate
Function Select (GPIOAFSEL) register (see page 450), GPIO Pull Up Select (GPIOPUR)
register (see page 456), GPIO Pull-Down Select (GPIOPDR) register (see page 458), and
GPIO Digital Enable (GPIODEN) register (see page 461) are not committed to storage
unless the GPIO Lock (GPIOLOCK) register (see page 463) has been unlocked and the
appropriate bits of the GPIO Commit (GPIOCR) register (see page 464) have been set.
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x514
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PDE
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Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PDE
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Pad Weak Pull-Down Enable
Value Description
0
The corresponding pin's weak pull-down resistor is disabled.
1
The corresponding pin's weak pull-down resistor is enabled.
Setting a bit in the GPIOPUR register clears the corresponding bit in
the GPIOPDR register. The change is effective on the second clock
cycle after the write if accessing GPIO via the APB memory aperture.
If using AHB access, the change is effective on the next clock cycle.
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Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 454).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x518
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
SRL
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
SRL
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Slew Rate Limit Enable (8-mA drive only)
Value Description
1
Slew rate control is enabled for the corresponding pin.
0
Slew rate control is disabled for the corresponding pin.
460
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®
Stellaris LM3S9U90 Microcontroller
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note:
Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed
below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do
not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To
use the pin as a digital input or output (either GPIO or alternate function), the corresponding GPIODEN
bit must be set.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-11. GPIO Pins With Non-Zero Reset Values
Note:
GPIO Pins
Default State
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
GPIOPCTL
PA[1:0]
UART0
0
0
0
0
0x1
PA[5:2]
SSI0
0
0
0
0
0x1
PB[3:2]
I2C0
0
0
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7)
and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate
Function Select (GPIOAFSEL) register (see page 450), GPIO Pull Up Select (GPIOPUR)
register (see page 456), GPIO Pull-Down Select (GPIOPDR) register (see page 458), and
GPIO Digital Enable (GPIODEN) register (see page 461) are not committed to storage
unless the GPIO Lock (GPIOLOCK) register (see page 463) has been unlocked and the
appropriate bits of the GPIO Commit (GPIOCR) register (see page 464) have been set.
July 03, 2014
461
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
GPIO Digital Enable (GPIODEN)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x51C
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14