ISSI IS93C46B-3GI 1,024-bit serial electrically erasable prom Datasheet

ISSI
IS93C46B
1,024-BIT SERIAL ELECTRICALLY
ERASABLE PROM
®
JULY 2003
FEATURES
DESCRIPTION
• Industry-standard Microwire Interface
— Non-volatile data storage
— Low voltage operation:
Vcc = 2.5V to 5.5V
— Full TTL compatible inputs and outputs
— Auto increment for efficient data dump
• x16 bit organization
• Hardware and software write protection
— Defaults to write-disabled state at power-up
— Software instructions for write-enable/disable
• Enhanced low voltage CMOS E2PROM
technology
• Versatile, easy-to-use Interface
— Self-timed programming cycle
— Automatic erase-before-write
— Programming status indicator
— Word and chip erasable
— Chip select enables power savings
• Durable and reliable
— 40-year data retention after 1M write cycles
— 1 million write cycles
— Unlimited read cycles
— Schmitt-trigger inputs
• Industrial and Automotive Temperature Grade
The IS93C46B is a low-cost 1kb non-volatile,
ISSI ® serial EEPROM. It is fabricated using an
enhanced CMOS design and process. The
IS93C46B contains power-efficient read/write
memory, and organization of 64 words of 16 bits.
The IS93C46B is fully backward compatible with
IS93C46.
An instruction set defines the operation of the
devices, including read, write, and mode-enable
functions. To protect against inadvertent data
modification, all erase and write instructions are
accepted only while the device is write-enabled. A
selected x16 word can be modified with a single
WRITE or ERASE instruction. Additionally, the
two instructions WRITE ALL or ERASE ALL can
program the entire array. Once a device begins
its self-timed program procedure, the data out pin
(Dout) can indicate the READY/BUSY status by
raising chip select (CS). The self-timed write cycle
includes an automatic erase-before-write
capability. The device can output any number of
consecutive words using a single READ
instruction.
FUNCTIONAL BLOCK DIAGRAM
DATA
REGISTER
INSTRUCTION
REGISTER
DIN
CS
SK
DUMMY
BIT
DOUT
R/W
AMPS
INSTRUCTION
DECODE,
CONTROL,
AND
CLOCK
GENERATION
ADDRESS
REGISTER
ADDRESS
DECODER
EEPROM
ARRAY
64x16
WRITE
ENABLE
HIGH VOLTAGE
GENERATOR
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
1
ISSI
IS93C46B
®
PIN CONFIGURATIONS
8-Pin JEDEC SOIC “GR”
8-Pin JEDEC SOIC “G”
8-Pin DIP, 8-Pin TSSOP
CS
1
8
VCC
NC
1
8
NC
CS
1
8
VCC
SK
2
7
NC
VCC
2
7
GND
SK
2
7
NC
DIN
3
6
NC
CS
3
6
DOUT
DIN
3
6
NC
DOUT
4
5
GND
SK
4
5
DIN
DOUT
4
5
GND
(Rotated)
PIN DESCRIPTIONS
CS
Chip Select
SK
Serial Data Clock
D IN
Serial Data Input
DOUT
Serial Data Output
NC
Not Connected
Vcc
Power
GND
Ground
instruction begins with a start bit of the logical “1” or
HIGH. Following this are the opcode (2 bits),
address field (6 bits), and data, if appropriate. The
clock signal may be held stable at any moment to
suspend the device at its last state, allowing clockspeed flexibility. Upon completion of bus
communication, CS would be pulled LOW. The device
then would enter Standby mode if no internal
programming is underway.
Read (READ)
Applications
The IS93C46B is very popular in many high-volume
applications which require low-power, low-density
storage. Applications using this device include
industrial controls, networking, and numerous other
consumer electronics.
Endurance and Data Retention
The IS93C46B is designed for applications requiring up to
1M programming cycles (WRITE, WRALL, ERASE and
ERAL). It provides 40 years of secure data retention without
power after the execution of 1M programming cycles.
Device Operations
The IS93C46B is controlled by a set of instructions
which are clocked-in serially on the Din pin. Before
each low-to-high transition of the clock (SK), the CS pin
must have already been raised to HIGH, and the Din
value must be stable at either LOW or HIGH. Each
2
The READ instruction is the only instruction that outputs
serial data on the DOUT pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory register into a serial shift register. (Please
note that one logical “0” bit precedes the actual 16-bit
output data string.) The output on DOUT changes during the
low-to-high transitions of SK (see Figure 3).
Low Voltage Read
The IS93C46B has been designed to ensure that data
read operations are reliable in low voltage environments.
They provide accurate operation with Vcc as low as 2.5V.
Auto Increment Read Operations
In the interest of memory transfer operation applications,
the IS93C46B has been designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location address. Once the 16 bits of the addressed register have
been clocked out, the data in consecutively higher address
locations is output. The address will wrap around continuously with CS HIGH until the chip select (CS) control pin is
brought LOW. This allows for single instruction data dumps
to be executed with a minimum of firmware overhead.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
ISSI
IS93C46B
Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done. When Vcc is applied,
this device powers up in the write disabled state. The
device then remains in a write disabled state until a WEN
instruction is executed. Thereafter, the device remains
enabled until a WDS instruction is executed or until Vcc
is removed. (See Figure 4.) (Note: Chip select must
remain LOW until Vcc reaches its operational value.)
Write (WRITE)
The WRITE instruction includes 16 bits of data to be
written into the specified register. After the last data bit
has been applied to DIN, and before the next rising edge
of SK, CS must be brought LOW. If the device is writeenabled, then the falling edge of CS initiates the selftimed programming cycle (see WEN).
If CS is brought HIGH, after a minimum wait of 250 ns (5V
operation) after the falling edge of CS (tCS) DOUT will
indicate the READY/BUSY status of the chip. Logical “0”
means programming is still in progress; logical “1” means
the selected register has been written, and the part is
ready for another instruction (see Figure 5). The READY/
BUSY status will not be available if: a) The CS input goes
HIGH after the end of the self-timed programming cycle,
tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and
SK goes HIGH, which clears the status flag.
®
Write All (WRALL)
The write all (WRALL) instruction programs all registers
with the data pattern specified in the instruction. As with the
WRITE instruction, the falling edge of CS must occur to
initiate the self-timed programming cycle. If CS is then
brought HIGH after a minimum wait of 250 ns (tCS), the
DOUT pin indicates the READY/BUSY status of the chip (see
Figure 6).
Write Disable (WDS)
The write disable (WDS) instruction disables all programming
capabilities. This protects the entire device against accidental modification of data until a WEN instruction is
executed. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation.
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought
LOW. The falling edge of CS initiates the self-timed internal
programming cycle. Bringing CS HIGH after a minimum of
tCS, will cause DOUT to indicate the READ/BUSY status of the
chip: a logical “0” indicates programming is still in progress;
a logical “1” indicates the erase cycle is complete and the
part is ready for another instruction (see Figure 8).
Erase All (ERAL)
Full chip erase is provided for ease of programming. Erasing
the entire chip involves setting all bits in the entire memory
array to a logical “1” (see Figure 9).
INSTRUCTION SET - IS93C46B
Instruction
16-bit Organization
Address (1)
Input Data
Start Bit
OP Code
READ
1
10
(A5-A0)
—
WEN (Write Enable)
1
00
11xxxx
—
WRITE
1
01
(A5-A0)
(D15-D0) (2)
WRALL (Write All Registers)
1
00
01xxxx
(D15-D0) (2)
WDS (Write Disable)
1
00
00xxxx
—
ERASE
1
11
(A5-A0)
—
ERAL (Erase All Registers)
1
00
10xxxx
—
Notes:
1. x = Don't care bit.
2. If input data is not 16 bits exactly, the last 16 bits will be taken as input data.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
3
ISSI
IS93C46B
®
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VGND
T BIAS
T BIAS
TSTG
Parameter
Voltage with Respect to GND
Temperature Under Bias (Industrial)
Temperature Under Bias (Automotive)
Storage Temperature
Value
–0.3 to +6.5
–40 to +85
–40 to +125
–65 to +150
Unit
V
°C
°C
°C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Ambient Temperature
0°C to +70°C
VCC
2.5V to 5.5V
Industrial
–40°C to +85°C
2.5V to 5.5V
Automotive
–40°C to +125°C
2.7V to 5.5V or 4.5V to 5.5V
CAPACITANCE
4
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
5
pF
VOUT = 0V
5
pF
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
ISSI
IS93C46B
®
DC ELECTRICAL CHARACTERISTICS
TA = 0°C to +70°C for Commercial, –40°C to +85°C for Industrial, and –40°C to +125°C for Automotive.
Symbol Parameter
Test Conditions
VOL
Output LOW Voltage
IOL = 100 µA
VOL1
Output LOW Voltage
VOH
Vcc
Min.
Max.
Unit
2.5V to 5.5V
—
0.2
V
IOL = 2.1 mA
4.5V to 5.5V
—
0.4
V
Output HIGH Voltage
IOH = –100 µA
2.5V to 5.5V
VCC – 0.2
—
V
VOH1
Output HIGH Voltage
IOH = –400 µA
4.5V to 5.5V
2.4
—
V
VIH
Input HIGH Voltage
2.5V to 5.5V
4.5V to 5.5V
0.7XVCC
0.7XVCC
VCC+1
VCC+1
V
VIL
Input LOW Voltage
2.5V to 5.5V
4.5V to 5.5V
–0.3
–0.3
0.2XVCC
0.8
V
ILI
Input Leakage
VIN = 0V to VCC (CS, SK,DIN,ORG)
0
2.5
µA
ILO
Output Leakage
VOUT = 0V to VCC, CS = 0V
0
2.5
µA
Notes:
Automotive grade devices in this table are tested with Vcc = 2.7V to 5.5V and 4.5V to 5.5V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
5
ISSI
IS93C46B
®
POWER SUPPLY CHARACTERISTICS
TA = 0°C to +70°C for Commercial
Symbol Parameter
Test Conditions
Vcc
Min.
Max.
Unit
ICC1
Vcc Read Supply Current
CS = VIH, SK = 1 MHz
CMOS input levels
2.7V
5.0V
—
—
100
500
µA
µA
ICC2
Vcc Write Supply Current
CS = VIH, SK = 1 MHz
CMOS input levels
2.7V
5.0V
—
—
1
3
mA
mA
ISB
Standby Current
CS = VIH, SK = 0V
2.7V
5.0V
—
—
10
30
µA
µA
POWER SUPPLY CHARACTERISTICS
TA = –40°C to +85°C for Industrial
Symbol Parameter
Test Conditions
Vcc
Min.
Max.
Unit
ICC1
Vcc Read Supply Current
CS = VIH, SK = 1 MHz
CMOS input levels
2.7V
5.0V
—
—
100
500
µA
µA
ICC2
Vcc Write Supply Current
CS = VIH, SK = 1 MHz
CMOS input levels
2.7V
5.0V
—
—
1
3
mA
mA
ISB
Standby Current
CS = VIH, SK = 0V
2.7V
5.0V
—
—
2
4
µA
µA
POWER SUPPLY CHARACTERISTICS
TA = –40°C to +125°C for Automotive
6
Symbol Parameter
Test Conditions
Vcc
Min.
Max.
Unit
ICC1
Vcc Read Supply Current
CS = VIH, SK = 1 MHz
CMOS input levels
2.7V
5.0V
—
—
100
500
µA
µA
ICC2
Vcc Write Supply Current
CS = VIH, SK = 1 MHz
CMOS input levels
2.7V
5.0V
—
—
1
3
mA
mA
ISB
Standby Current
CS = VIH, SK = 0V
2.7V
5.0V
—
—
3
8
µA
µA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
ISSI
IS93C46B
®
AC ELECTRICAL CHARACTERISTICS
TA = TA = 0°C to +70°C for Commercial, –40°C to +85°C for Industrial
Symbol Parameter
Test Conditions
Vcc
Min.
Max.
Unit
fSK
SK Clock Frequency
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
0
0
0
1
1
2
Mhz
Mhz
Mhz
tSKH
SK HIGH Time
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
500
350
250
—
—
—
ns
ns
ns
tSKL
SK LOW Time
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
500
350
250
—
—
—
ns
ns
ns
tCS
Minimum CS LOW Time
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
500
250
250
—
—
—
ns
ns
ns
tCSS
CS Setup Time
Relative to SK
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
100
50
50
—
—
—
ns
ns
ns
tDIS
Din Setup Time
Relative to SK
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
100
100
100
—
—
—
ns
ns
ns
tCSH
CS Hold Time
Relative to SK
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
0
0
0
—
—
—
ns
ns
ns
tDIH
Din Hold Time
Relative to SK
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
100
100
100
—
—
—
ns
ns
ns
tPD1
Output Delay to “1”
AC Test
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
—
—
—
400
350
250
ns
ns
ns
tPD0
Output Delay to “0”
AC Test
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
—
—
—
400
350
250
ns
ns
ns
tSV
CS to Status Valid
AC Test
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
—
—
—
400
250
250
ns
ns
ns
tDF
CS to Dout in 3-state
AC Test, CS=VIL
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
—
—
—
200
200
100
ns
ns
ns
tWP
Write Cycle Time
2.5V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
—
—
—
10
10
5
ms
ms
ms
Notes:
1. C L = 100pF
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
7
ISSI
IS93C46B
®
AC ELECTRICAL CHARACTERISTICS
TA = –40°C to +125°C for Automotive
Symbol Parameter
fSK
tSKH
tSKL
tCS
tCSS
tDIS
tCSH
tDIH
tPD1
tPD0
tSV
tDF
tWP
Test Conditions
SK Clock Frequency
SK HIGH Time
SK LOW Time
Minimum CS LOW Time
CS Setup Time
Din Setup Time
CS Hold Time
Din Hold Time
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
CS to Dout in 3-state
Write Cycle Time
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC Test
AC Test
AC Test
AC Test, CS=VIL
Vcc
Min.
Max.
Unit
2.7V to 5.5V
0
1
Mhz
4.5V to 5.5V
0
2
Mhz
2.7V to 5.5V
500
—
ns
4.5V to 5.5V
250
—
ns
2.7V to 5.5V
500
—
ns
4.5V to 5.5V
250
—
ns
2.7V to 5.5V
250
—
ns
4.5V to 5.5V
250
—
ns
2.7V to 5.5V
100
—
ns
4.5V to 5.5V
50
—
ns
2.7V to 5.5V
100
—
ns
4.5V to 5.5V
100
—
ns
2.7V to 5.5V
0
—
ns
4.5V to 5.5V
0
—
ns
2.7V to 5.5V
100
—
ns
4.5V to 5.5V
100
—
ns
2.7V to 5.5V
—
400
ns
4.5V to 5.5V
—
250
ns
2.7V to 5.5V
—
400
ns
4.5V to 5.5V
—
250
ns
2.7V to 5.5V
—
250
ns
4.5V to 5.5V
—
250
ns
2.7V to 5.5V
—
200
ns
4.5V to 5.5V
—
100
ns
2.7V to 5.5V
—
10
ms
4.5V to 5.5V
—
5
ms
Notes:
1. C L = 100pF
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
ISSI
IS93C46B
®
AC WAVEFORMS
FIGURE 2.
SYNCHRONOUS DATA TIMING
CS
T
tCSS
tSKH
tSKL
tCSH
SK
tDIS
tDIH
DIN
tPD0
tPD1
tDF
DOUT
(READ)
tSV
tDF
DOUT
(WRITE)
(WRALL)
(ERASE)
(ERAL)
FIGURE 3.
STATUS VALID
READ CYCLE TIMING
tCS
CS
DIN
DOUT
1
1
0
An
A0
0
Dm
D0
*
*Address Pointer Cycles to the Next Register
Notes:
To determine address bits An-A0 and data bits Dm-Do, see Instruction Set.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
9
ISSI
IS93C46B
®
AC WAVEFORMS
FIGURE 4.
WRITE ENABLE (WEN) TIMING
tCS
CS
DIN
1
0
0
1
1
DOUT = 3-state
FIGURE 5.
WRITE (WRITE) CYCLE TIMING
tCS
CS
DIN
1
0
1
An
A0
Dm
D0
tSV
DOUT
BUSY
tDF
READY
tWP
Notes:
1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status
(DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.
2. To determine address bits An-A0 and data bits Dm-D0, see Instruction Set.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
ISSI
IS93C46B
®
AC WAVEFORMS
FIGURE 6.
WRITE ALL (WRALL) TIMING
tCS
CS
1
DIN
0
0
0
1
Dm
D0
tSV
BUSY
DOUT
READY
tWP
Notes:
1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status
(DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.
2. To determine data bits Dm-D0, see Instruction Set.
FIGURE 7.
WRITE DISABLE (WDS) CYCLE TIMING
tCS
CS
DIN
1
0
0
0
0
DOUT = 3-STATE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
11
ISSI
IS93C46B
®
AC WAVEFORMS
FIGURE 8.
ERASE (REGISTER ERASE) CYCLE TIMING
tCS
CS
DIN
1
1
1
An
An-1
A0
tSV
DOUT
tDF
BUSY
READY
tWP
Notes:
To determine data bits An - A0, see Instruction Set.
FIGURE 9.
ERASE ALL (ERAL) CYCLE TIMING
tCS
CS
DIN
1
0
0
1
0
tSV
DOUT
BUSY
tDF
READY
tWP
Note for Figures 8 and 9:
After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT
indicates BUSY status) then attempting to perform another instruction could cause device malfunction.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
ISSI
IS93C46B
®
ORDERING INFORMATION
Commercial: 0ºC to +70ºC
Speed
1Mhz *
Voltage Range
2.5V to 5.5V
Order Part No.
IS93C46B-3P
IS93C46B-3G
IS93C46B-3GR
IS93C46B-3Z
Package
300-mil Plastic DIP
SOIC (rotated) JEDEC
SOIC JEDEC
169-mil TSSOP
Order Part No.
IS93C46B-3PI
IS93C46B-3GI
IS93C46B-3GRI
IS93C46B-3ZI
Package
300-mil Plastic DIP
SOIC (rotated) JEDEC
SOIC JEDEC
169-mil TSSOP
Order Part No.
IS93C46B-3PA
IS93C46B-3GRA
Package
300-mil Plastic DIP
SOIC JEDEC
ORDERING INFORMATION
Industrial Range: -40ºC to +85ºC
Speed
1Mhz *
Voltage Range
2.5V to 5.5V
ORDERING INFORMATION
Automotive Range: -40ºC to +125ºC
Speed
1Mhz *
Voltage Range
2.7V to 5.5V
* The specification allows for higher speed. Please see the AC Charateristics for more information.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
07/23/03
13