MWS5101, MWS5101A 256-Word x 4-Bit LSI Static RAM March 1997 Features Description • Industry Standard Pinout The MWS5101 and MWS5101A are 256 word by 4-bit static random access memories designed for use in memory systems where high speed, very low operating current, and simplicity in use are desirable. They have separate data inputs and outputs and utilize a single power supply of 4V to 6.5V. The MWS5101 and MWS5101A differ in input voltage characteristics (MWS5101A is TTL compatible). • Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA at VDD = 5V and Cycle Time = 1µs • Two Chip Select Inputs Simple Memory Expansion • Memory Retention for Standby. . . . . . . . . . . . . 2V (Min) Battery Voltage • Output Disable for Common I/O Systems • Three-State Data Output for Bus Oriented Systems • Separate Data Inputs and Outputs • TTL Compatible (MWS5101A) Pinout The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input. MWS5101, MWS5101A (PDIP, SBDIP) TOP VIEW 1 22 VDD A2 2 21 A4 A1 3 20 R/W A0 4 19 CSI A5 5 18 O.D. A6 6 17 CS2 A3 Two Chip Select inputs are provided to simplify system expansion. An Output Disable control provides Wire-OR capability and is also useful in common Input/Output systems by forcing the output into a high impedance state during a write operation independent of the Chip Select input condition. The output assumes a high impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2. A7 7 16 DO4 VSS 8 15 DI4 DI1 9 14 DO3 DO1 10 13 DI3 DI2 11 12 DO2 For applications requiring wider temperature and operating voltage ranges, the mechanically and functionally equivalent static RAM, CDP1822 may be used. The MWS5101 and MWS5101A types are supplied in 22 lead hermetic dual-in-line, sidebrazed ceramic packages (D suffix), in 22 lead dual-in-line plastic packages (E suffix), and in chip form (H suffix). Ordering Information MWS5101 PACKAGE TEMP. RANGE PDIP Burn-In 0oC to +70oC SBDIP Burn-In 0oC to +70oC 250ns MWS5101EL2 MWS5101A 350ns MWS5101ELS 250ns MWS5101AEL2 350ns PKG. NO. MWS5101AEL3 E22.4 MWS5101AEL3X E22.4 - MWS5101DL3X - MWS5101ADL3 D22.4A D22.4A CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 6-56 File Number 1106.2 MWS5101, MWS5101A OPERATIONAL MODES INPUTS CHIP SELECT 1 (CS1) CHIP SELECT 2 (CS2) OUTPUT DISABLE (OD) READ/WRITE (R/W) Read 0 1 0 1 Read Write 0 1 0 0 Data In Write 0 1 1 0 High Impedance Standby 1 X X X High Impedance Standby X 0 X X High Impedance Output Disable X X 1 X High Impedance MODE OUTPUT NOTE: Logic 1 = High, Logic 0 = Low, X = Don’t Care. Functional Block Diagram A0 A1 †4 †3 †2 A2 †1 A3 A4 † 21 (5) INPUT BUFFERS AND ALL ROWS DESELECT FUNCTION (32) ROW 22 DECODERS (8 x 32) STORAGE ARRAY †9 DI1 † 11 DI2 DI3 DI4 † 13 † 15 †5 A5 †6 A6 A7 R/W CSI CS2 OD †7 †17 (8 x 32) STORAGE ARRAY (8 x 32) STORAGE ARRAY (4) GATES (4) BITS (1-4) (3) INPUT BUFFERS AND ALL COLUMNS DESELECT FUNCTION †20 †19 (8 x 32) STORAGE ARRAY BIT (1) BIT (2) BIT (3) (8) (8) (8) (8) COLUMN DECODERS COLUMN DECODERS COLUMN DECODERS COLUMN DECODERS BUFFER DRIVERS 10 ††† VDD †† D01 12 †† D02 14 †† D03 16 †† D04 BIT (4) CONTROL B 8 CONTROL C CONTROL A †18 VDD VDD VSS † INPUT PROTECTION NETWORK VDD VSS † † OUTPUT VSS † † † OVER VOLTAGE PROTECTION CIRCUIT PROTECTION CIRCUIT 6-57 ††† VSS MWS5101, MWS5101A Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 80 21 Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (During Soldering) At distance 1/16 ±1/32 In. (1.59 ±0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS PARAMETER DC Operating Voltage Range Input Voltage Range Static Electrical Specifications MIN MAX UNITS 4 6.5 V VSS VDD V At TA = 0oC to +70oC, VDD = 5V ±5% CONDITIONS LIMITS MWS5101 PARAMETER Quiescent Device Current L2 Types MWS5101A SYMBOL VO (V) VIN (V) MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX UNITS IDD - 0, 5 - 25 50 - 25 50 µA - 0, 10 - 100 200 - 100 200 µA L3 Types Output Low (Sink) Current IOL 0.4 0, 5 2 4 - 2 4 - mA Output High (Source) Current IOH 4.6 0, 5 -1 -2 - -1 -2 - mA Output Voltage Low-Level VOL - 0, 5 - 0 0.1 - 0 0.1 V Output Voltage High-Level VOH - 0, 5 4.9 5 - 4.9 5 - V Input Low Voltage VIL - - - - 1.5 - - 0.65 V Input High Voltage VIH - - 3.5 - - 2.2 - - V Input Leakage Current IIN - 0, 5 - - ±5 - - ±5 µA Operating Current (Note 2) IDD1 - 0, 5 - 4 8 - 4 8 mA Three-State Output Leakage Current IOUT 0, 5 0, 5 - - ±5 - - ±5 µA 0, 5 0, 5 - - ±5 - - ±5 µA CIN - - - 5 7.5 - 5 7.5 pF COUT - - - 10 15 - 10 15 pF L2 Types L3 Types Input Capacitance Output Capacitance NOTES: 1. Typical values are for TA = +25oC and nominal VDD. 2. Outputs open circuited; Cycle time = 1µs. 6-58 MWS5101, MWS5101A Dynamic Electrical Specifications at TA = 0oC to +70oC, VDD = 5V ±5% LIMITS (NOTE 1) L2 TYPES L3 TYPES SYMBOL (NOTE 2) MIN (NOTE 3) TYP MAX (NOTE 2) MIN (NOTE 3) TYP MAX UNITS Read Cycle tRC 250 - - 350 - - ns Access from Address tAA - 150 250 - 200 350 ns Output Valid from Chip Select 1 tDOA1 - 150 250 - 200 350 ns Output Valid from Chip Select 2 tDOA2 - 150 250 - 200 350 ns Output Valid from Output Disable tDOA3 - - 110 - - 150 ns Output Hold from Chip Select 1 tDOH1 20 - - 20 - - ns Output Hold from Chip Select 2 tDOH2 20 - - 20 - - ns Output Hold from Output Disable tDOH3 20 - - 20 - - ns Write Cycle tWC 300 - - 400 - - ns Address Setup tAS 110 - - 150 - - ns Write Recovery tWR 40 - - 50 - - ns tWRW 150 - - 200 - - ns Input Data Setup Time tDS 150 - - 200 - - ns Data in Hold tDH 40 - - 50 - - ns Chip Select 1 Setup tCS1S 110 - - 150 - - ns Chip Select 2 Setup tCS2S 110 - - 150 - - ns Chip Select 1 Hold tCS1H 0 - - 0 - - ns Chip Select 2 Hold tCS2H 0 - - 0 - - ns Output Disable Setup tODS 110 - - 150 - - ns PARAMETER READ CYCLE TIMES (FIGURE 1) WRITE CYCLE TIMES (FIGURE 2) Write Width NOTES: 1. MWS5101: tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD; CL = 100pF and MWS5101A: tR, tF = 20ns, VIH = 2.2V, VIL = 0.65V; CL = 50pF and 1 TTL Load. 2. Time required by a limit device to allow for the indicated function. 3. Typical values are for TA = 25oC and nominal VDD. 6-59 MWS5101, MWS5101A tRC A0 - A7 tDOA1 CHIP SELECT 1 tDOH1 tDOH2 tDOA2 CHIP SELECT 2 tDOH3 tDOA3 OUTPUT DISABLE READ/WRITE tAA DATA OUT VALID DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE FIGURE 1. READ CYCLE TIMING WAVEFORMS tWC tWR A0-A7 tCS1S tCS1H CHIP SELECT 1 CHIP SELECT 2 tCS2H tCS2S OUTPUT DISABLE (NOTE) tODS tDS DI1-DI4 tDH DATA IN STABLE tWRW READ/WRITE tAS DON’T CARE NOTE: tODS is required for common I/O operation only; for separate I/O operations, output disable is “don’t care”. FIGURE 2. WRITE CYCLE TIME WAVEFORMS 6-60 MWS5101, MWS5101A Data Retention Specifications at TA = 0oC to +70oC; See Figure 3 TEST CONDITIONS LIMITS ALL TYPES PARAMETER SYMBOL VDR (V) VDD (V) MIN (NOTE 1) TYP MAX UNITS VDR - - - 1.5 2 V IDD 2 - - 2 10 µA 2 - - 5 50 µA tCDR - 5 600 - - ns tRC - 5 600 - - ns tR, tF 2 5 1 - - µs Minimum Data Retention Voltage Data Retention Quiescent Current L2 Types L3 Types Chip Deselect to Data Retention Time Recovery to Normal Operation Time VDD to VDR Rise and Fall Time NOTE: 1. Typical Values are for TA = 25oC and nominal VDD . READ ADDRESS DECODER DATA RETENTION MODE VDD 0.95 VDD DATA IN 0.95 VDD VDR tCDR CS2 VIH VIL tF tR VSS tRC WRITE ADDRESS DECODER VIH VIL VDD FIGURE 3. LOW VDD DATA RETENTION TIMING WAVEFORMS 6-61 FIGURE 4. MEMORY CELL CONFIGURATION DATA OUT VDD MWS5101, MWS5101A CONTROL A CS1 19 A CHIP-SELECT CONTROL CS2 17 CONTROL B B CHIP-SELECT AND R/W CONTROL R/W 20 CONTROL C C OUTPUT DISABLE CONTROL OUTPUT 18 DISABLE FIGURE 5. LOGIC DIAGRAM OF CONTROLS FOR MWS5101, MWS5101A All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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