INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4502B buffers Strobed hex inverter/buffer Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4502B buffers Strobed hex inverter/buffer DESCRIPTION The HEF4502B consists of six inverter/buffers with 3-state outputs. When the output enable input (EO) is HIGH all six outputs (O1 to O6) are in the high impedance OFF-state. When the enable input (E) is HIGH all six outputs are switched to LOW. The outputs have a 2-TTL load drive capability. Fig.2 Pinning diagram. HEF4502BP(N): 16-lead DIL; plastic (SOT38-1) HEF4502BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4502BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING D1 to D6 data inputs E enable input EO output enable input O1 to O6 3-state outputs Fig.1 Functional diagram. TRUTH TABLE INPUTS OUTPUT Dn E EO On L L L H H L L L X H L L X X H Z Fig.3 Logic diagram. Notes FAMILY DATA, IDD LIMITS category BUFFERS 1. H = HIGH state (the more pos. voltage) L = LOW state (the less pos. voltage) X = state is immaterial Z = high impedance off state January 1995 See Family Specifications 2 Philips Semiconductors Product specification HEF4502B buffers Strobed hex inverter/buffer DC CHARACTERISTICS VSS = 0 V Tamb (°C) VDD V VOH V VOL V −40 SYMBOL MIN. Output current HIGH 5 4,6 10 9,5 15 13,5 5 2,5 + 25 MAX. 1,2 −IOH MIN. MAX. + 85 MIN. MAX. 1,0 0,8 mA 3,8 3,2 2,5 mA 12,0 10,0 8,0 mA 3,8 3,2 2,5 mA 3,5 2,9 2,3 mA 12,0 10,0 8,0 mA 24,0 20,0 16,0 mA Output current HIGH Output current LOW −IOH 4,75 0,4 10 0,5 15 1,5 IOL AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns Dynamic power dissipation per package (P) VDD V TYPICAL FORMULA FOR P (µW) 5 5 000 fi + ∑ (foCL) × VDD2 10 25 000 fi + ∑ (foCL) × VDD2 fi = input freq. (MHz) 15 85 000 fi + ∑ (foCL) × fo = output freq. (MHz) VDD2 where CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 Philips Semiconductors Product specification HEF4502B buffers Strobed hex inverter/buffer AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays Dn, E → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 Output transition times HIGH to LOW 170 ns 77 ns + (0,17 ns/pF) CL 40 80 ns 37 ns + (0,06 ns/pF) CL 35 70 ns 33 ns + (0,04 ns/pF) CL 80 160 ns 66 ns + (0,28 ns/pF) CL 35 70 ns 28 ns + (0,13 ns/pF) CL 30 60 ns 25 ns + (0,10 ns/pF) CL 25 50 ns 10 ns + (0,30 ns/pF) CL 12 24 ns 7 ns + (0,11 ns/pF) CL 8 15 ns 5 ns + (0,07 ns/pF) CL 30 60 ns 5 ns + (0,50 ns/pF) CL 15 30 ns 3 ns + (0,24 ns/pF) CL 15 12 24 ns 3 ns + (0,18 ns/pF) CL 5 60 160 ns 55 140 ns 15 55 140 ns 5 50 100 ns 35 70 ns 15 30 60 ns 5 60 120 ns 5 10 tTHL 15 5 LOW to HIGH 85 10 tTLH 3-state propagation delays Output disable times EO → On HIGH LOW 10 10 tPHZ tPLZ Output enable times EO → On HIGH LOW 10 tPZH 35 70 ns 15 30 60 ns 5 55 110 ns 25 50 ns 20 40 ns 10 tPZL 15 January 1995 4