A/D Flash USB MCU HT66FB570 Revision: V1.10 Date: ����������������� December 15, 2016 HT66FB570 A/D Flash USB MCU Table of Contents Features............................................................................................................. 7 CPU Features.......................................................................................................................... 7 Peripheral Features.................................................................................................................. 8 General Description.......................................................................................... 9 Block Diagram................................................................................................... 9 Pin Assignment............................................................................................... 10 Pin Description............................................................................................... 12 Absolute Maximum Ratings........................................................................... 17 D.C. Characteristics........................................................................................ 18 A.C. Characteristics........................................................................................ 21 A/D Converter Electrical Characteristics...................................................... 22 LVR/LVD Electrical Characteristics............................................................... 23 Reference Voltage Characteristics................................................................ 24 Comparator Electrical Characteristics......................................................... 24 USB Electrical Characteristics...................................................................... 25 Power-on Reset Characteristics.................................................................... 25 System Architecture....................................................................................... 26 Clocking and Pipelining.......................................................................................................... 26 Program Counter.................................................................................................................... 27 Stack...................................................................................................................................... 28 Arithmetic and Logic Unit – ALU............................................................................................ 28 Flash Program Memory.................................................................................. 29 Structure................................................................................................................................. 29 Special Vectors...................................................................................................................... 29 Look-up Table......................................................................................................................... 30 Table Program Example......................................................................................................... 30 In Circuit Programming – ICP................................................................................................ 31 On-Chip Debug Support – OCDS.......................................................................................... 32 In Application Programming – IAP......................................................................................... 33 In System Programming – ISP............................................................................................... 47 Data Memory................................................................................................... 48 Structure................................................................................................................................. 48 Data Memory Addressing....................................................................................................... 49 General Purpose Data Memory............................................................................................. 49 Special Purpose Data Memory.............................................................................................. 49 Special Function Register Description......................................................... 51 Indirect Addressing Registers – IAR0, IAR1, IAR2................................................................ 51 Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H.......................................................... 51 Program Memory Bank Pointer – PBP................................................................................... 53 Rev. 1.10 2 December 15, 2016 HT66FB570 A/D Flash USB MCU Accumulator – ACC................................................................................................................ 53 Program Counter Low Register – PCL................................................................................... 53 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 53 Status Register – STATUS..................................................................................................... 54 EEPROM Data Memory................................................................................... 56 EEPROM Data Memory Structure......................................................................................... 56 EEPROM Registers............................................................................................................... 56 Reading Data from the EEPROM.......................................................................................... 58 Writing Data to the EEPROM................................................................................................. 58 Write Protection...................................................................................................................... 58 EEPROM Interrupt................................................................................................................. 58 Programming Considerations................................................................................................. 59 Oscillators....................................................................................................... 60 Oscillator Overview................................................................................................................ 60 System Clock Configurations................................................................................................. 60 Internal PLL Frequency Generator......................................................................................... 61 External Crystal/Ceramic Oscillator – HXT............................................................................ 62 Internal High Speed RC Oscillator – HIRC............................................................................ 63 External 32.768kHz Crystal Oscillator – LXT......................................................................... 63 Internal 32kHz Oscillator – LIRC............................................................................................ 64 Operating Modes and System Clocks.......................................................... 65 System Clocks....................................................................................................................... 65 System Operation Modes....................................................................................................... 66 Control Registers................................................................................................................... 67 Operating Mode Switching..................................................................................................... 71 Standby Current Considerations............................................................................................ 75 Wake-up................................................................................................................................. 75 Watchdog Timer.............................................................................................. 76 Watchdog Timer Clock Source............................................................................................... 76 Watchdog Timer Control Register.......................................................................................... 76 Watchdog Timer Operation.................................................................................................... 77 Reset and Initialisation................................................................................... 78 Reset Functions..................................................................................................................... 78 Reset Initial Conditions.......................................................................................................... 82 Input/Output Ports.......................................................................................... 87 Pull-high Resistors................................................................................................................. 89 I/O Port Wake-up................................................................................................................... 89 Port A Wake-up Polarity Control Register.............................................................................. 89 I/O Port Control Registers...................................................................................................... 90 Port A Power Source Control Register................................................................................... 90 I/O Port Output Slew Rate Control Registers......................................................................... 91 I/O Port Output Current Control Registers............................................................................. 93 Pin-shared Functions............................................................................................................. 95 I/O Pin Structures................................................................................................................. 101 Programming Considerations............................................................................................... 102 Rev. 1.10 3 December 15, 2016 HT66FB570 A/D Flash USB MCU Timer Modules – TM..................................................................................... 103 Introduction.......................................................................................................................... 103 TM Operation....................................................................................................................... 103 TM Clock Source.................................................................................................................. 103 TM Interrupts........................................................................................................................ 104 TM External Pins.................................................................................................................. 104 TM Input/Output Pin Selection............................................................................................. 105 Programming Considerations............................................................................................... 106 Standard Type TM – STM............................................................................. 107 Standard TM Operation........................................................................................................ 107 Standard Type TM Register Description.............................................................................. 108 Standard Type TM Operation Modes....................................................................................112 Periodic Type TM – PTM............................................................................... 122 Periodic TM Operation ........................................................................................................ 122 Periodic Type TM Register Description ............................................................................... 122 Periodic Type TM Operating Modes .................................................................................... 127 Analog to Digital Converter ........................................................................ 136 A/D Converter Overview...................................................................................................... 136 A/D Converter Register Description..................................................................................... 137 A/D Converter Data Registers – SADOL, SADOH............................................................... 137 A/D Converter Control Registers – SADC0, SADC1, SADC2.............................................. 137 A/D Converter Operation ..................................................................................................... 140 A/D Converter Reference Voltage........................................................................................ 141 A/D Converter Input Signals................................................................................................. 141 Conversion Rate and Timing Diagram................................................................................. 142 Summary of A/D Conversion Steps...................................................................................... 143 Programming Considerations............................................................................................... 144 A/D Conversion Function..................................................................................................... 144 A/D Conversion Programming Examples............................................................................. 145 Comparators................................................................................................. 147 Comparator Operation......................................................................................................... 147 Comparator Registers.......................................................................................................... 147 Comparator Interrupt............................................................................................................ 148 Programming Considerations............................................................................................... 148 Serial Interface Module – SIM...................................................................... 149 SPI Interface........................................................................................................................ 149 I2C Interface......................................................................................................................... 158 Serial Peripheral Interface – SPIA............................................................... 168 SPIA Interface Operation..................................................................................................... 168 SPIA Registers..................................................................................................................... 169 SPIA Communication........................................................................................................... 172 SPIA Bus Enable/Disable..................................................................................................... 174 SPIA Operation.................................................................................................................... 174 Error Detection..................................................................................................................... 175 Rev. 1.10 4 December 15, 2016 HT66FB570 A/D Flash USB MCU UART Interface.............................................................................................. 176 UART External Pins............................................................................................................. 177 UART Data Transfer Scheme.............................................................................................. 177 UART Status and Control Registers.................................................................................... 177 Baud Rate Generator........................................................................................................... 183 UART Setup and Control..................................................................................................... 184 UART Transmitter................................................................................................................ 185 UART Receiver.................................................................................................................... 186 Managing Receiver Errors................................................................................................... 188 UART Interrupt Structure..................................................................................................... 189 UART Power Down and Wake-up........................................................................................ 190 Low Voltage Detector – LVD........................................................................ 191 LVD Register........................................................................................................................ 191 LVD Operation...................................................................................................................... 192 USB Interface................................................................................................ 193 Power Plane......................................................................................................................... 193 USB Interface Operation...................................................................................................... 193 USB Interface Registers....................................................................................................... 194 USB Suspend Mode and Wake-Up...................................................................................... 205 USB Interrupts...................................................................................................................... 206 Interrupts....................................................................................................... 207 Interrupt Registers................................................................................................................ 207 Interrupt Operation............................................................................................................... 214 External Interrupts................................................................................................................ 216 USB Interrupt....................................................................................................................... 216 Comparator Interrupts.......................................................................................................... 216 SIM Interrupt........................................................................................................................ 217 SPIA Interrupt....................................................................................................................... 217 Time Base Interrupts............................................................................................................ 217 Multi-function Interrupts........................................................................................................ 219 A/D Converter Interrupt........................................................................................................ 219 UART Interrupt..................................................................................................................... 219 EEPROM Interrupt............................................................................................................... 220 LVD Interrupt........................................................................................................................ 220 TM Interrupts........................................................................................................................ 220 Interrupt Wake-up Function.................................................................................................. 221 Programming Considerations............................................................................................... 221 Configuration Options.................................................................................. 222 Application Circuits...................................................................................... 222 Rev. 1.10 5 December 15, 2016 HT66FB570 A/D Flash USB MCU Instruction Set............................................................................................... 223 Introduction.......................................................................................................................... 223 Instruction Timing................................................................................................................. 223 Moving and Transferring Data.............................................................................................. 223 Arithmetic Operations........................................................................................................... 223 Logical and Rotate Operation.............................................................................................. 224 Branches and Control Transfer............................................................................................ 224 Bit Operations...................................................................................................................... 224 Table Read Operations........................................................................................................ 224 Other Operations.................................................................................................................. 224 Instruction Set Summary............................................................................. 225 Table Conventions................................................................................................................ 225 Extended Instruction Set...................................................................................................... 227 Instruction Definition.................................................................................... 229 Extended Instruction Definition............................................................................................ 238 Package Information.................................................................................... 245 48-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 246 64-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 247 Rev. 1.10 6 December 15, 2016 HT66FB570 A/D Flash USB MCU Features CPU Features • Operating voltage ♦♦ VDD (MCU) ––fSYS=6MHz: 2.2V~5.5V ––fSYS=12MHz: 2.7V~5.5V ––fSYS=16MHz: 4.5V~5.5V ♦♦ VDD (USB mode) ––fSYS=6/12MHz: 3.3V~5.5V ––fSYS=16MHz: 4.5V~5.5V • Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillator types ♦♦ External High Speed Crystal – HXT ♦♦ External Low Speed 32.768kHz Crystal – LXT ♦♦ Internal High Speed RC – HIRC ♦♦ Internal Low Speed 32kHz RC – LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 12MHz oscillator requires no external components • All instructions executed in 1~3 instruction cycles • Table read instructions • 115 powerful instructions • 12-level subroutine nesting • Bit manipulation instruction Rev. 1.10 7 December 15, 2016 HT66FB570 A/D Flash USB MCU Peripheral Features • Flash Program Memory: 32K×16 • RAM Data Memory: 1024×8 • True EEPROM Memory: 256×8 • Watchdog Timer function • 55 bidirectional I/O lines • Dual pin-shared external interrupts • Multiple Timer Modules for time measurement, input capture, compare match output or PWM output or single pulse output function ♦♦ 1 Standard type 16-bit Timer Module – STM ♦♦ 5 Periodic type 10-bit Timer Modules – PTM0~PTM4 • USB interface ♦♦ USB 2.0 Full Speed compatible ♦♦ 8 endpoints supported including endpoint 0 ♦♦ All endpoints except endpoint 0 can support interrupt and bulk transfer ♦♦ All endpoints except endpoint 0 can be configured as 8, 16, 32, 64 bytes FIFO size ♦♦ Endpoint 0 support control transfer ♦♦ Endpoint 0 has 8 byte FIFO ♦♦ Support 3.3V LDO and internal UDP 1.5kΩ pull-up resistor ♦♦ Internal 12MHz RC oscillator with 0.25% accuracy for all USB modes • Serial Interface Module with Dual SPI and I2C interfaces • Single Serial Peripheral Interface – SPIA • Fully-duplex Universal Asynchronous Receiver and Transmitter Interface – UART • Dual comparator functions • Dual Time-Base functions for generation of fixed time interrupt signals • 24-channel 12-bit resolution A/D converter • Low voltage reset function • Low voltage detect function • In Application Programming function – IAP • In System Programing function – ISP • Flash program memory can be re-programmed up to 100,000 times • Flash program memory data retention > 10 years • True EEPROM data memory can be re-programmed up to 1,000,000 times • True EEPROM data memory data retention > 10 years • Package type: 48/64-pin LQFP Rev. 1.10 8 December 15, 2016 HT66FB570 A/D Flash USB MCU General Description The device is a Flash Memory A/D with USB type 8-bit high performance RISC architecture microcontroller, designed for applications that interface directly to analog signals and require an USB interface. Offering users the convenience of Flash Memory multi-programming features, the device also includes a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter and two comparators. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by including fully integrated SPI, I2C, UART and USB interface functions, four popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. The external interrupt can be triggered with falling edges or both falling and rising edges. A full choice of external, internal high and low oscillators is provided including two fully integrated system oscillators which require no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimize microcontroller operation and minimize power consumption. The inclusion of flexible I/O programming features along with many other features ensure that the device will find specific excellent use in a wide range of application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. The device is fully supported by the Holtek range of fully functional development and programming tools, providing a means for fast and efficient product development cycles. Block Diagram Reset Ci��uit Wat�hdog Ti�e� Flash/EEPROM P�og�a��ing Ci��uit�y EEPROM Data Me�o�y Flash P�og�a� Me�o�y USB �.0 XCVR USB �.0 Full Speed Engine 3.3V LDO LVD/ LVR RAM Data Me�o�y Inte��upt Cont�olle� 8-�it RISC MCU Co�e Inte�nal HIRC/LIRC Os�illato�s Ti�e Bases Exte�nal HXT/LXT Os�illato�s 1�-�it A/D Conve�te� UART Rev. 1.10 SIM (SPI/I�C) SPIA Ti�e� Modules I/O 9 Co�pa�ato�s December 15, 2016 HT66FB570 A/D Flash USB MCU Pin Assignment PC4/TX/AN12 PC5/RX/AN13 PC6/AN14 PC7/AN15 PE0/VDDIO/VREF PA7/INT0/AN7 PA6/STCK/C1PA5/PTP0/PTP0I/C1+ PA4/SCSA/STP/STPI/C1X PA3/SCKA/C0PA2/SDIA/C0+ PA1/SDOA/C0X PA0/PTCK0/OCDSDA PG3/AN23 UDN/OD0/ICPDA UDP/OD1 V33O UBUS AVDD/VDD VSS/AVSS PE3/XT1 PE4/XT2 RES/ICPCK/OCDSCK PE2/AN17 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 5 32 HT66FB570/HT66VB570 31 6 7 30 48 LQFP-A 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PC3/AN11 PC2/AN10 PC1/PTCK4/AN9 PC0/PTP4/PTP4I/AN8 PB7/PTP4/PTP4I/AN18 PB6/INT1/AN6 PB5/AN5 PB4/STP/STPI/AN4 PB3/SCS/AN3 PB2/SCK/AN2 VDD PB1/SDI/SCL/AN1 PB0/SDO/SDA/AN0 VSS PF0/PTP3/PTP3I PD7/PTP1/PTP1I PD6/PTP2/PTP2I PD5/PTP0/PTP0I PD4/PTCK2 PD3/PTCK3 PD2/PTCK1 PD1/PTP1/PTP1I/OSC2 PD0/PTP2/PTP2I/OSC1 PE5/AN16 Rev. 1.10 10 December 15, 2016 HT66FB570 A/D Flash USB MCU PG7/AN19 PC4/TX/AN12 PC5/RX/AN13 PC6/AN14 PC7/AN15 PE0/VDDIO/VREF PA7/INT0/AN7 PA6/STCK/C1PA5/PTP0/PTP0I/C1+ PA4/SCSA/STP/STPI/C1X PA3/SCKA/C0PA2/SDIA/C0+ PA1/SDOA/C0X PA0/PTCK0/OCDSDA PG6/AN20 PG5/AN21 PG4/AN22 PG3/AN23 UDN/OD0/ICPDA UDP/OD1 V33O UBUS AVDD/VDD VSS/AVSS PE3/XT1 PE4/XT2 PE6 RES/ICPCK/OCDSCK PG2 PG1 PG0 PE2/AN17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 HT66FB570/HT66VB570 41 64 LQFP-A 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PC3/AN11 PC2/AN10 PC1/PTCK4/AN9 PC0/PTP4/PTP4I/AN8 PB7/PTP4/PTP4I/AN18 PB6/INT1/AN6 PB5/AN5 PB4/STP/STPI/AN4 PB3/SCS/AN3 PB2/SCK/AN2 VDD PB1/SDI/SCL/AN1 PB0/SDO/SDA/AN0 VSS PE7 PF7 PF6 PF5 PF4 PF3 PF2 PF1/PTP3/PTP3I PF0/PTP3/PTP3I PD7/PTP1/PTP1I PD6/PTP2/PTP2I PD5/PTP0/PTP0I PD4/PTCK2 PD3/PTCK3 PD2/PTCK1 PD1/PTP1/PTP1I/OSC2 PD0/PTP2/PTP2I/OSC1 PE5/AN16 Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, the desired pin-shared function is determined by the corresponding software control bits. 2. The OCDSDA and OCDSCK pins are supplied for the OCDS dedicated pins and as such only available for the HT66VB570 device which is the OCDS EV chip for the HT66FB570 device. Rev. 1.10 11 December 15, 2016 HT66FB570 A/D Flash USB MCU Pin Description The pins on the device can be referenced by its Port name, e.g. PA0, PA1 etc., which refer to the digital I/O function of the pins. However these Port pins are also shared with other functions such as the Analog to Digital Converter, Serial Port pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. As the Pin Description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. Pin Name PA0/PTCK0/ OCDSDA PA1/SDOA/C0X PA2/SDIA/C0+ PA3/SCKA/C0- PA4/SCSA/STP/ STPI/C1X PA5/PTP0/ PTP0I/C1+ PA6/STCK/C1- Rev. 1.10 Function OPT I/T O/T Description PA0 PAPU PAWUEG0 PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up PTCK0 PAS0 ST — OCDSDA — ST CMOS OCDS data/address pin, for EV chip only. PA1 PAPU PAWUEG0 PAS0 ST CMOS SDOA PAS0 — CMOS SPIA serial data output C0X PAS0 — CMOS Comparator 0 output PA2 PAPU PAWUEG0 PAS0 ST CMOS SDIA PAS0 ST — SPIA serial data input C0+ PAS0 AN — Comparator 0 positive input PA3 PAPU PAWUEG0 PAS0 ST CMOS SCKA PAS0 ST CMOS SPIA serial clock C0- PAS0 AN — PA4 PAPU PAWUEG1 PAS1 ST CMOS SCSA PAS1 ST CMOS SPIA slave select STP PAS1 — CMOS STM ouput STPI PAS1 IFS ST C1X PAS1 — CMOS Comparator 1 output PA5 PAPU PAWUEG1 PAS1 ST CMOS PTP0 PAS1 — CMOS PTM0 ouput PTP0I PAS1 IFS ST — PTM0 capture input C1+ PAS1 AN — Comparator 1 positive input PA6 PAPU PAWUEG1 PAS1 ST CMOS STCK PAS1 ST — STM clock input C1- PAS1 AN — Comparator 1 negative input — 12 PTM0 clock input General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up Comparator 0 negative input General purpose I/O. Register enabled pull-up and wake-up STM capture input General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up December 15, 2016 HT66FB570 A/D Flash USB MCU Pin Name PA7/INT0/AN7 PB0/SDO/SDA/ AN0 PB1/SDI/SCL/AN1 PB2/SCK/AN2 PB3/SCS/AN3 PB4/STP/STPI/ AN4 PB5/AN5 PB6/INT1/AN6 Rev. 1.10 Function OPT I/T O/T Description PA7 PAPU PAWUEG1 PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT0 PAS1 INTEG INTC0 ST — External interrupt 0 input AN7 PAS1 AN — A/D Converter external input 7 PB0 PBPU PBWU PBS0 ST CMOS SDO PBS0 — CMOS SPI serial data output SDA PBS0 ST NMOS I2C data line AN0 PBS0 AN — PB1 PBPU PBWU PBS0 ST CMOS SDI PBS0 ST — SCL PBS0 ST AN1 PBS0 AN — PB2 PBPU PBWU PBS0 ST CMOS SCK PBS0 ST CMOS SPI serial clock AN2 PBS0 AN — PB3 PBPU PBWU PBS0 ST CMOS CMOS SPI slave select General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 0 General purpose I/O. Register enabled pull-up and wake-up SPI serial data input NMOS I2C clock line A/D Converter external input 1 General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 2 General purpose I/O. Register enabled pull-up and wake-up SCS PBS0 ST AN3 PBS0 AN — PB4 PBPU PBWU PBS1 ST CMOS STP PBS1 — CMOS STM ouput STPI PBS1 IFS ST — STM capture input AN4 PBS1 AN — A/D Converter external input 4 PB5 PBPU PBWU PBS1 ST CMOS AN5 PBS1 AN — PB6 PBPU PBWU PBS1 ST CMOS INT1 PBS1 INTEG INTC0 ST — External interrupt 1 input AN6 PBS1 AN — A/D Converter external input 6 13 A/D Converter external input 3 General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 5 General purpose I/O. Register enabled pull-up and wake-up December 15, 2016 HT66FB570 A/D Flash USB MCU Pin Name PB7/PTP4/PTP4I/ AN18 PC0/PTP4/PTP4I/ AN8 PC1/PTCK4/AN9 PC2/AN10 PC3/AN11 PC4/TX/AN12 PC5/RX/AN13 PC6/AN14 PC7/AN15 Rev. 1.10 Function OPT I/T O/T Description PB7 PBPU PBWU PBS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up PTP4 PBS1 — CMOS PTM4 ouput PTP4I PBS1 IFS ST — PTM4 capture input AN18 PBS1 AN — A/D Converter external input 18 PC0 PCPU PCWU PCS0 ST CMOS PTP4 PCS0 — CMOS PTM4 ouput PTP4I PCS0 IFS ST — PTM4 capture input AN8 PCS0 AN — A/D Converter external input 8 PC1 PCPU PCWU PCS0 ST CMOS PTCK4 PCS0 ST — PTM4 clock input AN9 PCS0 AN — A/D Converter external input 9 PC2 PCPU PCWU PCS0 ST CMOS AN10 PCS0 AN — PC3 PCPU PCWU PCS0 ST CMOS AN11 PCS0 AN — PC4 PCPU PCWU PCS1 ST CMOS TX PCS1 — CMOS UART TX serial data output AN12 PCS1 AN — PC5 PCPU PCWU PCS1 ST CMOS RX PCS1 ST — UART RX serial data input AN13 PCS1 AN — A/D Converter external input 13 PC6 PCPU PCWU PCS1 ST CMOS AN14 PCS1 AN — PC7 PCPU PCWU PCS1 ST CMOS AN15 PCS1 AN — 14 General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 10 General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 11 General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 12 General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 14 General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 15 December 15, 2016 HT66FB570 A/D Flash USB MCU Pin Name PD0/PTP2/ PTP2I/OSC1 PD1/PTP1/ PTP1I/OSC2 PD2/PTCK1 PD3/PTCK3 PD4/PTCK2 PD5/PTP0/PTP0I PD6/PTP2/PTP2I PD7/PTP1/PTP1I PE0/VDDIO/VREF Rev. 1.10 Function OPT I/T O/T Description PD0 PDPU PDWU PDS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up PTP2 PDS0 — CMOS PTM2 ouput PTP2I PDS0 IFS ST — PTM2 capture input OSC1 PDS0 HXT — HXT oscillator pin PD1 PDPU PDWU PDS0 ST CMOS PTP1 PDS0 — CMOS PTM1 ouput PTP1I PDS0 IFS ST — OSC2 PDS0 — HXT PD2 PDPU PDWU PDS0 ST CMOS PTCK1 PDS0 ST — PD3 PDPU PDWU PDS0 ST CMOS PTCK3 PDS0 ST — PD4 PDPU PDWU PDS1 ST CMOS PTCK2 PDS1 ST — PD5 PDPU PDWU PDS1 ST CMOS PTP0 PDS1 — CMOS PTM0 ouput PTP0I PDS1 IFS ST — PD6 PDPU PDWU PDS1 ST CMOS PTP2 PDS1 — CMOS PTM2 ouput PTP2I PDS1 IFS ST — PD7 PDPU PDWU PDS1 ST CMOS PTP1 PDS1 — CMOS PTM1 ouput PTP1I PDS1 IFS ST — PE0 PEPU PEWU PES0 ST CMOS VDDIO PES0 PWR — PA external power input VREF PES0 AN — A/D Converter external reference voltage input 15 General purpose I/O. Register enabled pull-up and wake-up PTM1 capture input HXT oscillator pin General purpose I/O. Register enabled pull-up and wake-up PTM1 clock input General purpose I/O. Register enabled pull-up and wake-up PTM3 clock input General purpose I/O. Register enabled pull-up and wake-up PTM2 clock input General purpose I/O. Register enabled pull-up and wake-up PTM0 capture input General purpose I/O. Register enabled pull-up and wake-up PTM2 capture input General purpose I/O. Register enabled pull-up and wake-up PTM1 capture input General purpose I/O. Register enabled pull-up and wake-up December 15, 2016 HT66FB570 A/D Flash USB MCU Pin Name Function OPT I/T O/T Description PE2 PEPU PEWU PES0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up AN17 PES0 AN — PE3 PEPU PEWU PES0 ST CMOS XT1 PES0 LXT — PE4 PEPU PEWU PES1 ST CMOS XT2 PES1 — LXT PE5 PEPU PEWU PES1 ST CMOS AN16 PES1 AN — PEn PEPU PEWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PF0 PFPU PFWU PFS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up PTP3 PFS0 — CMOS PTM3 ouput PTP3I PFS0 IFS ST — PF1 PFPU PFWU PFS0 ST CMOS PTP3 PFS0 — CMOS PTM3 ouput PTP3I PFS0 IFS ST — PF2~PF7 PFn PFPU PFWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PG0~PG2 PGn PGPU PGWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PG3 PGPU PGWU PGS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up AN23 PGS0 AN — PG4 PGPU PGWU PGS1 ST CMOS AN22 PGS1 AN — PG5 PGPU PGWU PGS1 ST CMOS AN21 PGS1 AN — PG6 PGPU PGWU PGS1 ST CMOS AN20 PGS1 AN — PE2/AN17 PE3/XT1 PE4/XT2 PE5/AN16 PE6~PE7 PF0/PTP3/PTP3I PF1/PTP3/PTP3I PG3/AN23 PG4/AN22 PG5/AN21 PG6/AN20 Rev. 1.10 16 A/D Converter external input 17 General purpose I/O. Register enabled pull-up and wake-up LXT oscillator pin General purpose I/O. Register enabled pull-up and wake-up LXT oscillator pin General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 16 PTM3 capture input General purpose I/O. Register enabled pull-up and wake-up PTM3 capture input A/D Converter external input 23 General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 22 General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 21 General purpose I/O. Register enabled pull-up and wake-up A/D Converter external input 20 December 15, 2016 HT66FB570 A/D Flash USB MCU Pin Name PG7/AN19 Function OPT I/T O/T Description PG7 PGPU PGWU PGS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up AN19 PGS1 AN — A/D Converter external input 19 USB SIE power supply UBUS* UBUS — PWR — V33O V33O — — PWR UDN — ST CMOS USB UDN line OD0 — ST NMOS NMOS Open Drain I/O pin ICPDA — ST CMOS ICP address/data UDN/OD0/ICPDA UDP/OD1 RES/ICPCK/ OCDSCK AVDD/VDD VSS/AVSS USB 3.3V regulator output UDP — ST CMOS USB UDP line OD1 — ST NMOS NMOS Open Drain I/O pin RES — ST — External reset input ICPCK — ST — ICP clock OCDSCK — ST — OCDS clock pin, for EV chip only AVDD — PWR — Analog positive power supply It should be double bonded to VDD. VDD — PWR — Positive power supply VSS — PWR — Negative power supply, ground. AVSS — PWR — Analog negative power supply, ground. It should be double bonded to VSS. Legend: I/T: Input type; O/T: Output type OPT: Optional by register option; PWR: Power ST: Schmitt Trigger input; CMOS: CMOS output NMOS: NMOS output; AN: Analog signal HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: UBUS pin needs to be connected to VDD/AVDD for ICP mode Absolute Maximum Ratings Supply Voltage..................................................................................................VSS-0.3V to VSS+6.0V Input Voltage....................................................................................................VSS-0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOL Total...................................................................................................................................... 80mA IOH Total.....................................................................................................................................-80mA Total Power Dissipation.......................................................................................................... 500mW Note:These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of the device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.10 17 December 15, 2016 HT66FB570 A/D Flash USB MCU D.C. Characteristics Ta=25°C Symbol Parameter Operating Voltage (HXT) VDD Test Conditions VDD — Typ. Max. Unit fSYS=fHXT=6MHz 2.2 — 5.5 V fSYS=fHXT=12MHz 2.7 — 5.5 V fSYS=fHXT=16MHz 4.5 — 5.5 V — fSYS=fHIRC=12MHz 2.7 — 5.5 V Operating Voltage (LXT) — fSYS=fLXT=32.768kHz 2.2 — 5.5 V Operating Voltage (LIRC) — fSYS=fLIRC=32kHz 2.2 — 5.5 V — fSYS=fPLL=6MHz, PLLEN=1 2.2 — 5.5 V — fSYS=fPLL=12MHz, PLLEN=1 2.7 — 5.5 V — fSYS=fPLL=16MHz, PLLEN=1 4.5 — 5.5 V 3V fSYS=fHXT=6MHz No load, all peripherals off — 0.7 1.5 mA — 1.6 3.0 mA fSYS=fHXT=12MHz No load, all peripherals off — 1.3 3.0 mA — 2.7 6.0 mA — 3.6 8.0 fSYS=fHIRC=12MHz No load, all peripherals off — 1.6 3.0 mA — 2.8 6.0 mA fSYS=fLXT=32768Hz No load, all peripherals off — 17 30 μA — 30 50 μA fSYS=fLIRC=32kHz No load, all peripherals off — 16 30 μA — 28 50 μA fSYS=fPLL=6MHz, PLLEN=1, No load, all peripherals off — 1.5 2.0 mA — 3 4.0 mA fSYS=fPLL=12MHz, PLLEN=1, No load, all peripherals off — 2.1 3.5 mA — 3.8 7.0 mA — 4.5 9.0 mA 5V Operating Current (HXT) 3V 5V 5V Operating Current (HIRC) Operating Current (LXT) Operating Current (LIRC) 3V 5V 3V 5V 3V 5V 3V 5V Operating Current (PLL) 3V 5V 5V Rev. 1.10 Min. Operating Voltage (HIRC) Operating Voltage (PLL) IDD Conditions fSYS=fHXT=16MHz No load, all peripherals off fSYS=fPLL=16MHz, PLLEN=1, No load, all peripherals off 18 December 15, 2016 HT66FB570 A/D Flash USB MCU Symbol Parameter Test Conditions 3V 5V Standby Current (SLEEP Mode) 3V 5V 3V 5V 3V Standby Current (IDLE0 Mode) 5V 3V 5V 3V ISTB 5V 3V 5V Standby Current (IDLE1 Mode, fSYS=fH=fPLL) 3V 5V 3V 5V 5V VIL RPH ILEAK fSYS off, fSUB off, No load, all peripherals off, WDT disable — 0.2 0.8 μA — 0.5 1 μA fSYS off, fSUB=fLXT on, No load, all peripherals off, WDT enable — 0.7 1.5 μA — 1.5 3 μA fSYS off, fSUB=fLIRC on, No load, all peripherals off, WDT enable — — 3 μA — — 5 μA fSYS off, fSUB=fLXT on No load, all peripherals off — 1.8 3 μA — 2.8 5 μA fSYS off, fSUB=fLIRC on No load, all peripherals off — 1.5 3 μA — 2.8 5 μA fSYS=fHIRC=12MHz on, fSUB on No load, all peripherals off — 0.65 1.4 mA — 1.3 3 mA fSYS=fHXT=12MHz on, fSUB on No load, all peripherals off — 0.9 1.5 mA — 1.4 3 mA fSYS=fPLL=6MHz, fSUB on, PLLEN=1, No load, all peripherals off — 1.0 2.5 mA — 2.0 3.5 mA fSYS=fPLL=12MHz, fSUB on, PLLEN=1, No load, all peripherals off — 1.5 3 mA — 2.5 4 mA — 3 5 mA fSYS=fPLL=16MHz, fSUB on, PLLEN=1, No load, all peripherals off Unit — 0 — 1.5 V — 0 — 0.2VDD V — — 0 — 0.4VDD V 5V — 3.5 — 5 V — — 0.8VDD — VDD V Input High Voltage for RES Pin — — 0.9VDD — VDD V Pull-high Resistance for I/O Ports 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ 3V VIN=VDD or VIN=VSS — — ±1 μA 5V VIN=VDD or VIN=VSS — — ±1 μA 3V SLEWCn[m+1, m]=00B (n=0,1..., m=0 or 2 or 4 or 6), 0.1VDD to 0.9VDD or 0.9VDD to 0.1VDD, CLOAD=20pF 150 — — 380 — — SLEWCn[m+1, m]=01B (n=0,1..., m=0 or 2 or 4 or 6), 0.1VDD to 0.9VDD or 0.9VDD to 0.1VDD, CLOAD=20pF — 87 — — 240 — SLEWCn[m+1, m]=10B (n=0,1..., m=0 or 2 or 4 or 6), 0.1VDD to 0.9VDD or 0.9VDD to 0.1VDD, CLOAD=20pF — 45 — — 120 — SLEWCn[m+1, m]=11B (n=0,1..., m=0 or 2 or 4 or 6), 0.1VDD to 0.9VDD or 0.9VDD to 0.1VDD, CLOAD=20pF — 20 — — 60 — Input High Voltage for I/O Ports Input Leakage Current 3V Output Rising Edge Slew Rate for I/O Ports 5V 3V 5V 3V 5V Rev. 1.10 Max. — 5V SRRISE Typ. Conditions 5V Input Low Voltage for I/O Ports Input Low Voltage for RES Pin VIH Min. VDD 19 V/μs V/μs V/μs V/μs December 15, 2016 HT66FB570 A/D Flash USB MCU Symbol Parameter Test Conditions 3V 5V 3V SRFALL Output Falling Ddge Slew Rate for I/O Ports 5V 3V 5V 3V 5V IOL IOH VOL VOH Rev. 1.10 Max. SLEWCn[m+1, m]=00B (n=0,1..., m=0 or 2 or 4 or 6), 0.1VDD to 0.9VDD or 0.9VDD to 0.1VDD, CLOAD=20pF 200 — — 500 — — SLEWCn[m+1, m]=01B (n=0,1..., m=0 or 2 or 4 or 6), 0.1VDD to 0.9VDD or 0.9VDD to 0.1VDD, CLOAD=20pF — 61 — — 180 — SLEWCn[m+1, m]=10B (n=0,1..., m=0 or 2 or 4 or 6), 0.1VDD to 0.9VDD or 0.9VDD to 0.1VDD, CLOAD=20pF — 29 — — 90 — SLEWCn[m+1, m]=11B (n=0,1..., m=0 or 2 or 4 or 6), 0.1VDD to 0.9VDD or 0.9VDD to 0.1VDD, CLOAD=20pF — 15 — — 45 — Unit V/μs V/μs V/μs V/μs VOL=0.1VDD, DRVCCn[m]=0 (n=0,1..., m=0,1,...,7) 1 2 — mA 5V VOL=0.1VDD, DRVCCn[m]=0 (n=0,1..., m=0,1,...,7) 2 4 — mA 3V VOL=0.1VDD, DRVCCn[m]=1 (n=0,1..., m=0,1,...,7) 5 10 — mA 5V VOL=0.1VDD, DRVCCn[m]=1 (n=0,1..., m=0,1,...,7) 10 20 — mA 3V VOH=0.9VDD, DRVCCn[m]=0 (n=0,1..., m=0,1,...,7) -1 -2 — mA 5V VOH=0.9VDD, DRVCCn[m]=0 (n=0,1..., m=0,1,...,7) -2 -4 — mA 3V VOH=0.9VDD, DRVCCn[m]=1 (n=0,1..., m=0,1,...,7) -1 -5 — mA 5V VOH=0.9VDD, DRVCCn[m]=1 (n=0,1..., m=0,1,...,7) -5 -10 — mA 3V IOL=1mA, DRVCCn[m]=0 (n=0,1..., m=0,1,...,7) — — 0.3 V 5V IOL=2mA, DRVCCn[m]=0 (n=0,1..., m=0,1,...,7) — — 0.5 V 3V IOL=5mA, DRVCCn[m]=1 (n=0,1..., m=0,1,...,7) — — 0.3 V 5V IOL=10mA, DRVCCn[m]=1 (n=0,1..., m=0,1,...,7) — — 0.5 V 3V IOH=-1mA, DRVCCn[m]=0 (n=0,1..., m=0,1,...,7) 2.7 — — V 5V IOH=-2mA, DRVCCn[m]=0 (n=0,1..., m=0,1,...,7) 4.5 — — V 3V IOH=-1mA, DRVCCn[m]=1 (n=0,1..., m=0,1,...,7) 2.7 — — V 5V IOH=-5mA, DRVCCn[m]=1 (n=0,1..., m=0,1,...,7) 4.5 — — V Source Current for I/O Ports Output High Voltage for I/O Ports Typ. Conditions 3V Sink Current for I/O Ports Output Low Voltage for I/O Ports Min. VDD 20 December 15, 2016 HT66FB570 A/D Flash USB MCU A.C. Characteristics Ta=25°C Symbol Parameter Conditions Min. Unit — 6 — MHz — 12 — MHz System Clock (HIRC) 2.7V~5.5V fSYS=fHIRC=12MHz — 12 — MHz System Clock (LXT) 2.2V~5.5V fSYS=fLXT=32.768kHz — 32.768 — kHz System Clock (LIRC) 2.2V~5.5V fSYS=fLIRC=32kHz — 32 — kHz High Speed Internal RC Oscillator (HIRC) Low Speed Internal RC Oscillator (LIRC) 12 +0.25% MHz Ta=25°C -2% 12 +2% MHz Ta=0°C~70°C -3% 12 +3% MHz Ta= -40°C~85°C -5% 12 +5% MHz Ta=0°C~70°C -7% 12 +7% MHz Ta= -40°C~85°C -10% 12 +10% MHz Ta=25°C -10% 32 +10% kHz Ta= -40°C~85°C -40% 32 +40% kHz 2.2V~5.5V Ta= -40°C~85°C -50% 32 +60% kHz 5V 2.7V~5.5V fLIRC Max. 2.7V~5.5V fSYS=fHXT=12MHz USB mode and CLKADJ=1, 4.4V~5.25V UDP/UDN plug in the -0.25% HOST, Ta=-40°C~85°C fHIRC Typ. 2.2V~5.5V fSYS=fHXT=6MHz System Clock (HXT) fSYS Test Conditions VDD 3V 3V±0.3V tTCK STCK, PTCKn Input Pin Minimum Pulse Width — — 0.3 — — μs tTPI STPI, PTPnI Input Pin Minimum Pulse Width — — 0.3 — — μs tINT External Interrupt Minimum Pulse Width — — 10 — — μs tRES External Reset Minimum Low Pulse Width — — 10 — — μs — fSYS=fLXT 922 1024 1126 tLXT — fSYS=fHXT ~ fHXT/64 115 128 141 tHXT — fSYS=fHIRC ~ fHIRC/64 14 16 18 tHIRC — fPLL off → on (PLLF=1) 2304 2560 2816 — fSYS=fLIRC — 2 3 — fHXT off → on (HXTF=1) 922 1024 1126 tHXT — fHIRC off → on (HIRCF=1) 14 16 18 tHIRC — fPLL off → on (PLLF=1) 2304 2560 2816 — fLXT off → on (LXTF=1) 922 1024 1126 tLXT — fSYS=fH ~ fH/64, fH=fHXT or fHIRC or fPLL — 2 3 tH — fSYS=fLXT or fLIRC — 2 3 tSUB System Reset Delay Time (Power-on Reset, LVR Hardware Reset, LVR Software Reset, WDT Software Reset) — — 25 50 100 ms System Reset Delay Time (RES Pin Reset, WDT Time-out Hardware Cold Reset) — — 8.3 16.7 33.3 ms System Start-up Timer Period (Wake-up from Power Down Mode and fSYS Off, RES Pin Reset) tSST System Start-up Timer Period (Slow Mode ↔ Normal Mode, or fH=fHIRC ↔ fHXT, or fSUB=fLIRC ↔ fLXT) System Start-up Timer Period (Wake-up from Power Down Mode and fSYS On) tRSTD Rev. 1.10 21 tPLL (48MHz) tLIRC tPLL (48MHz) December 15, 2016 HT66FB570 A/D Flash USB MCU A/D Converter Electrical Characteristics Ta= -40°C~85°C, unless otherwise specify Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit VDD Operating Voltage — — 2.7 — 5.5 V VADI Input Voltage — — 0 — VREF V VREF Reference Voltage — — 2 — VDD V — — ±3 LSB — — ±4 LSB — 1 2 mA mA DNL INL Differential Nonlinearity Integral Nonlinearity 3V VREF=VDD, tADCK=0.5μs 5V VREF=VDD, tADCK=0.5μs 3V VREF=VDD, tADCK=10μs 5V VREF=VDD, tADCK=10μs 3V VREF=VDD, tADCK=0.5μs 5V VREF=VDD, tADCK=0.5μs 3V VREF=VDD, tADCK=10μs 5V VREF=VDD, tADCK=10μs No load, tADCK=0.5μs 5V No load, tADCK=0.5μs IADC Additional Current Consumption for A/D Converter Enable 3V — 1.5 3 tADCK Clock Period — — 0.5 — 10 μs tON2ST A/D Converter On-to-Start Time — — 4 — — μs tADC Conversion Time (Including A/D Sample and Hold Time) — — — 16 — tADCK Rev. 1.10 22 December 15, 2016 HT66FB570 A/D Flash USB MCU LVR/LVD Electrical Characteristics Ta=25°C Symbol VLVR VLVD ILVRLVDBG tLVDS Parameter Low Voltage Reset Voltage Low Voltage Detection Voltage Test Conditions VDD Conditions Min. Typ. Max. — LVR enable, voltage select 2.1V -5% 2.1 +5% — LVR enable, voltage select 2.55V -5% 2.55 +5% — LVR enable, voltage select 3.15V -5% 3.15 +5% Unit V — LVR enable, voltage select 3.8V -5% 3.8 +5% — LVD enable, voltage select 2.0V -5% 2.0 +5% — LVD enable, voltage select 2.2V -5% 2.2 +5% — LVD enable, voltage select 2.4V -5% 2.4 +5% — LVD enable, voltage select 2.7V -5% 2.7 +5% — LVD enable, voltage select 3.0V -5% 3.0 +5% — LVD enable, voltage select 3.3V -5% 3.3 +5% — LVD enable, voltage select 3.6V -5% 3.6 +5% — LVD enable, voltage select 4.0V -5% 4.0 +5% 3V LVD enable, LVR enable, VBGEN=0 — — 20 μA 5V LVD enable, LVR enable, VBGEN=0 — 20 25 μA 3V LVD enable, LVR enable, VBGEN=1 — — 150 μA 5V LVD enable, LVR enable, VBGEN=1 — 180 200 μA — For LVR enable, VBGEN=0, LVD off → on — — 15 μs — For LVR disable, VBGEN=0, LVD off → on — — 150 μs Operating Current LVDO Stable Time V tLVR Minimum Low Voltage Width to Reset — — 120 240 480 μs tLVD Minimum Low Voltage Width to Interrupt — — 60 120 240 μs ILVR Additional Current for LVR Enable — LVD disable, VBGEN=0 — — 24 μA ILVD Additional Current for LVD Enable — LVR disable, VBGEN=0 — — 24 μA Rev. 1.10 23 December 15, 2016 HT66FB570 A/D Flash USB MCU Reference Voltage Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions — Min. Typ. Max. Unit -5% 1.04 +5% V VBG Bandgap Reference Voltage — tBGS VBG Turn On Stable Time — No load — — 150 μs IBG Additional Current for Bandgap Reference Enable — LVR disable, LVD disable — — 200 μA Note: The VBG voltage is used as the A/D converter internal signal input. Comparator Electrical Characteristics Ta=25°C All measurement is under Cn+ input voltage=(VDD-1.4)/2 and remain constant Symbol VDD ICMP VOS Parameter Comparator Operating Voltage Comparator Operating Current Comparator Input Offset Voltage Test Condition — — 2.2 — 5.5 V — — — 200 μA 5V — — — 200 μA 3V — -10 — +10 mV — 5V 5V Input Common Mode Voltage Range AOL Comparator Open Loop Gain tPD Comparator Response Time Unit 3V Hysteresis Width VCM Max. Conditions 3V VHYS Min. Typ. VDD -10 — +10 mV Hysteresis enable CMPnHYEN=1 12 24 36 mV Hysteresis disable CMPnHYEN=0 0 0 5 mV Hysteresis enable CMPnHYEN=1 20 40 60 mV Hysteresis disable CMPnHYEN=0 0 0 5 mV 3V — VSS — VDD-1.4 V 5V — VSS — VDD-1.4 V 3V — 60 80 — dB 5V — 60 80 — dB — — 2 μs — 200 400 ns 2.2V~5.5V With 10mV overdrive 3V With 100mV overdrive (Note) 5V Note: Measured with comparator one input pin at VCM=(VDD-1.4)/2 while the other pin input transition from VSS to (VCM+100mV) or from VDD to (VCM-100mV). Rev. 1.10 24 December 15, 2016 HT66FB570 A/D Flash USB MCU USB Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions Max. Unit 4.5 9 mA 9.5 15 mA — 5 10 mA — 10.5 16 mA 5V fSYS=fPLL=16MHz, No load, USB and PLL on, other peripherals off — 11 18 mA 5V fH off, fSUB=fLIRC or fLXT, No load, MCU powered down, USB and PLL on, other peripherals off, SUSP2=0 — 360 450 μA ISUS 5V fH off, fSUB=fLIRC or fLXT, No load, MCU powered down, USB and PLL on, other peripherals off, SUSP2=1 — 240 330 μA VV33O 3.3V Regulator Output Voltage 5V IV33O=70mA 3.0 3.3 3.6 V Pull-high Resistance of UDP to V33O RUDP 3.3V -5% 1.5 +5% kΩ Pull-high Resistance of UDP to UBUS 5V RCTRL=1 5.9 9.2 12.5 kΩ Operating Current (USB) Typ. fSYS=fPLL=6MHz, No load, USB and PLL on, other peripherals off — — fSYS=fPLL=12MHz, No load, USB and PLL on, other peripherals off Conditions 3V 5V IDD Min. VDD 3V 5V Suspend Current (USB) (IDLE0 Mode) — RUDPN Pull-high Resistance of UDP/UDN 5V to UBUS PU=1 300 650 1000 kΩ RPL Pull-low Resistance of UBUS 5V SUSP2=1, RUBUS=0 0.5 1.0 1.5 MΩ ROD Pull-high Resistance of OD0/OD1 to VDD 5V UMS[2:0]=001B 2.0 4.7 8.0 kΩ IOL_OD Sink Current of OD0/OD1 5V UMS[2:0]=001B, VOL=0.1VDD 8 12 — mA 2.0 — 5.0 V 0.0 — 0.8 V VIH Input High Voltage of OD0/OD1 5V UMS[2:0]=001B, OD1O/OD0O=11B VIL Input Low Voltage of OD0/OD1 5V UMS[2:0]=001B, OD1O/OD0O=11B Power-on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms VDD tPOR RRPOR VPOR Rev. 1.10 25 Ti�e December 15, 2016 HT66FB570 A/D Flash USB MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of the device take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one or two cycles for most of the standard or extended instructions respectively. The exceptions to this are branch or call instructions which need one more cycle. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Os�illato� Clo�k (Syste� Clo�k) Phase Clo�k T1 Phase Clo�k T� Phase Clo�k T3 Phase Clo�k T4 P�og�a� Counte� Pipelining PC PC+1 PC+� Fet�h Inst. (PC) Exe�ute Inst. (PC-1) Fet�h Inst. (PC+1) Exe�ute Inst. (PC) Fet�h Inst. (PC+�) Exe�ute Inst. (PC+1) System Clocking and Pipelining Rev. 1.10 26 December 15, 2016 HT66FB570 A/D Flash USB MCU 1 � 3 4 � � DELAY: MOV A� [1�H] CALL DELAY CPL [1�H] : : NOP Fet�h Inst. 1 Exe�ute Inst. 1 Fet�h Inst. � Exe�ute Inst. � Fet�h Inst. 3 Flush Pipeline Fet�h Inst. � Exe�ute Inst. � Fet�h Inst. 7 Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. As the device memory capacity is greater than 8K words, the Program Memory address may be located in a certain program memory bank which is selected by the program memory bank pointer bits, PBP1~PBP0. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Program Counter High Byte PCL Register PBP1~PBP0, PC12~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.10 27 December 15, 2016 HT66FB570 A/D Flash USB MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 12 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P�og�a� Counte� Top of Sta�k Sta�k Level 1 Sta�k Level � Sta�k Pointe� Sta�k Level 3 Botto� of Sta�k Sta�k Level 1� : : : P�og�a� Me�o�y Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA, LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA, LAND, LANDM, LOR, LORM, LXOR, LXORM, LCPL, LCPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC, LRR, LRRA, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC • Increment and Decrement: INCA, INC, DECA, DEC, LINCA, LINC, LDECA, LDEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI, LSNZ, LSZ, LSZA, LSIZ, LSIZA, LSDZ, LSDZA Rev. 1.10 28 December 15, 2016 HT66FB570 A/D Flash USB MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For the device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 32K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. 0000H Reset 0004H Inte��upt Ve�to�s 003CH Bank 0 1FFFH �000H 3FFFH 4000H �FFFH �000H 7FFFH 1� �its Bank 1 Bank � Bank 3 Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 0000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Rev. 1.10 29 December 15, 2016 HT66FB570 A/D Flash USB MCU Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the corresponding table read instruction such as "TABRD [m]" when the memory [m] is located in sector 0. If the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as "LTABRD [m]". When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. The accompanying diagram illustrates the addressing data flow of the look-up table. P�og�a� Me�o�y Add�ess Last Page o� TBHP Registe� TBLP Registe� Data 1� �its Registe� TBLH Use� Sele�ted Registe� High Byte Low Byte Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "7000H" which refers to the start address of the specified page within the 32K Program Memory of the device. The table pointer low byte register is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "7006H" or 6 locations after the start of the specified page. Note that the value for the table pointer is referenced to the first address of the present page pointed by the TBHP register if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m] instruction is executed. Because the TBLH register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.10 30 December 15, 2016 HT66FB570 A/D Flash USB MCU Table Read Program Example rombank 3 code3 ds .section ‘data’ tempreg1 db? ; temporary register#1 tempreg2 db? ; temporary register#2 code0 .section ‘code’ mov a,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,70h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; data at program memory address "7006H" transferred to ; tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; data at program memory address "7005H" transferred to ; tempreg2 and TBLH ; in this example the data "1AH" is transferred to ; tempreg1 and data "0FH" to tempreg2 ; the value "00H" will be transferred to the high byte register TBLH : : code3 .section ‘code’ org 1000h ; sets initial address of specified page dc 00Ah,00Bh,00Ch,00Dh,00Eh,00Fh,01Ah,01Bh In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPDA UDN Programming Serial Data/Address ICPCK RES Programming Clock VDD VDD/AVDD & UBUS VSS VSS Power Supply Ground The Program Memory and EEPROM Data Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the device is beyond the scope of this document and will be supplied in supplementary literature. During the programming process, taking control of the UDN and RES pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. Rev. 1.10 31 December 15, 2016 HT66FB570 A/D Flash USB MCU W�ite� Conne�to� Signals MCU P�og�a��ing Pins W�ite�_VDD VDD/HVDD UBUS ICPDA UDN ICPCK RES W�ite�_VSS VSS * To othe� Ci��uit Note: * may be resistor or capacitor. The resistance of * must be greater than 300Ω or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip named HT66VB570 which is used to emulate the HT66FB570 device. The EV chip device also provides an "On-Chip Debug" function to debug the real MCU device during the development process. The EV chip and the real MCU device are almost functionally compatible except for "On-Chip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Rev. 1.10 Holtek e-Link Pins EV Chip Pins OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output Pin Description OCDSCK OCDSCK On-Chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground 32 December 15, 2016 HT66FB570 A/D Flash USB MCU In Application Programming – IAP Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. The provision of not only an IAP function but also an additional ISP function offers users the convenience of Flash Memory multi-programming features. The convenience of the IAP function is that it can execute the updated program procedure using its internal firmware, without requiring an external Program Writer or PC. In addition, the IAP interface can also be any type of communication protocol, such as UART or USB, using I/O pins. Regarding the internal firmware, the user can select versions provided by HOLTEK or create their own. The following section illustrates the procedures regarding how to implement the IAP firmware. Flash Memory Read/Write Size The flash memory Erase and Write operations are carried out in a page format while the Read operation is carried out in a word format. The page size and write buffer size are both assigned with a capacity of 64 words. Note that the Erase operation should be executed before the Write operation is executed. When the Flash Memory Erase/Write Function is successfully enabled, the CFWEN bit will be set high. When the CFWEN bit is set high, the data can be written into the write buffer. The FWT bit is used to initiate the write process and then indicate the write operation status. This bit is set high by application programs to initiate a write process and will be cleared by hardware if the write process is finished. The Read operation can be carried out by executing a specific read procedure. The FRDEN bit is used to enable the read function and the FRD bit is used to initiate the read process by application programs and then indicate the read operation status. When the read process is finished, this bit will be cleared by hardware. Operations Format Erase 64 words/page Write 64 words/time Read 1 word/time Note: Page size =Write buffer size = 64 words. IAP Read/Write Format Erase Page FARH FARL [7:6] FARL [5:0] 0 0000 0000 00 xx xxxx 1 0000 0000 01 xx xxxx 2 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx : : : : : : : : 510 0111 1111 10 xx xxxx 511 0111 1111 11 xx xxxx “x”: don’t care Erase Page Number and Selection Rev. 1.10 33 December 15, 2016 HT66FB570 A/D Flash USB MCU Write Page Data to FD0L/FD0H (64 Words/Page) Read Data Word to FD0H/FD0L Flash Memory FARH/FARL =A14~A0 FARH/FARL =A14~A0 Word m FD0H Flash Memory Page addr. =A14~A6 Page n Write buffer addr. =A5~A0 FD0L CLWB Note: “m” is specified by A14~A0 000000b Write Buffer 111111b FD0H FD0L Note: “n” is specified by A14~A6 Flash Memory IAP Read/Write Structure • Write Buffer The write buffer is used to store the written data temporarily when executing the write operation. The Write Buffer can be filled with written data after the Flash Memory Erase/Write Function has been successfully enabled by executing the Flash Memory Erase/Write Function Enable procedure. The write buffer can be cleared by configuring the CLWB bit in the FRCR register. The CLWB bit can be set high to enable the Clear Write Buffer procedure. When the procedure is finished this bit will be cleared to low by the hardware. It is recommended that the write buffer should be cleared by setting the CLWB bit high before the write buffer is used for the first time or when the data in the write buffer is updated. The write buffer size is 64 words corresponding to a page. The write buffer address is mapped to a specific flash memory page specified by the memory address bits, A14~A6. The data written into the FD0L and FD0H registers will be loaded into the write buffer. When data is written into the high byte data register, FD0H, it will result in the data stored in the high and low byte data registers both being written into the write buffer. It will also cause the flash memory address to be incremented by one, after which the new address will be loaded into the FARH and FARL address registers. When the flash memory address reaches the page boundary, 111111b of a page with 64 words, the address will now not be incremented but will stop at the last address of the page. At this point a new page address should be specified for any other erase/write operations. After a write process is finished, the write buffer will automatically be cleared by the hardware. Note that the write buffer should be cleared manually by the application program when the data written into the flash memory is incorrect in the data verification step. The data should again be written into the write buffer after the write buffer has been cleared when the data is found to be incorrect during the data verification step. IAP Flash Program Memory Registers There are two address registers, four 16-bit data registers and two control registers. The address and data high byte registers together with the control registers are located in Sector 1 while other registers are located in Sector 0. Read and Write operations to the Flash memory are carried out using 16-bit data operations using the address and data registers and the control register. Several registers control the overall operation of the internal Flash Program Memory. The address registers are named FARL and FARH, the data registers are named FDnL and FDnH and the control registers are named FCR and FRCR. As the FARL and FDnL registers are located in Sector 0, they can be directly accessed in the same way as any other Special Function Register. The FARH, FDnH, FCR and FRCR registers, being located in Sector 1, can be addressed directly only using the Rev. 1.10 34 December 15, 2016 HT66FB570 A/D Flash USB MCU corresponding extended instructions or can be read from or written to indirectly using the MP1H/ MP1L or MP2H/MP2L Memory Pointer pairs and Indirect Addressing Register, IAR1 or IAR2. Register Name Bit 7 6 5 4 3 2 1 0 FCR CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD FRCR D7 D6 — D4 — — — CLWB FARL A7 A6 A5 A4 A3 A2 A1 A0 FARH — A14 A13 A12 A11 A10 A9 A8 FD0L D7 D6 D5 D4 D3 D2 D1 D0 FD0H D15 D14 D13 D12 D11 D10 D9 D8 FD1L D7 D6 D5 D4 D3 D2 D1 D0 FD1H D15 D14 D13 D12 D11 D10 D9 D8 FD2L D7 D6 D5 D4 D3 D2 D1 D0 FD2H D15 D14 D13 D12 D11 D10 D9 D8 FD3L D7 D6 D5 D4 D3 D2 D1 D0 FD3H D15 D14 D13 D12 D11 D10 D9 D8 IAP Registers List • FARL Register Bit 7 6 5 4 3 2 1 0 Name A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Flash Memory Address bit 7 ~ bit 0 • FARH Register Bit 7 6 5 4 3 2 1 0 Name — A14 A13 A12 A11 A10 A9 A8 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as 0. Bit 6~0 Flash Memory Address bit 14 ~ bit 8 • FD0L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 The first Flash Memory data word bit 7 ~ bit 0 Note that data written into the low byte data register FD0L will only be stored in the FD0L register and not loaded into the lower 8-bit write buffer. 35 December 15, 2016 HT66FB570 A/D Flash USB MCU • FD0H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The first Flash Memory data word bit 15 ~ bit 8 Note that when 8-bit data is written into the high byte data register FD0H, the whole 16-bits of data stored in the FD0H and FD0L registers will simultaneously be loaded into the 16-bit write buffer after which the contents of the Flash memory address register pair, FARH and FARL, will be incremented by one. • FD1L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data word bit 7 ~ bit 0 • FD1H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data word bit 15 ~ bit 8 • FD2L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data word bit 7 ~ bit 0 • FD2H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data word bit 15 ~ bit 8 • FD3L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 The fourth Flash Memory data word bit 7 ~ bit 0 36 December 15, 2016 HT66FB570 A/D Flash USB MCU • FD3H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The fourth Flash Memory data word bit 15 ~ bit 8 • FCR Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CFWEN: Flash Memory Erase/Write function enable control 0: Flash memory erase/write function is disabled 1: Flash memory erase/write function has been successfully enabled When this bit is cleared to “0” by application program, the Flash memory erase/write function is disabled. Note that this bit cannot be set high by application programs. Writing a “1” into this bit results in no action. This bit is used to indicate the Flash memory erase/write function status. When this bit is set to “1” by the hardware, it means that the Flash memory erase/write function is enabled successfully. Otherwise, the Flash memory erase/write function is disabled if the bit is zero. Bit 6~4 FMOD2~FMOD0: Flash memory Mode selection 000: Write Mode 001: Page erase Mode 010: Reserved 011: Read Mode 100: Reserved 101: Reserved 110: Flash memory Erase/Write function Enable Mode 111: Reserved These bits are used to select the Flash Memory operation modes. Note that the “Flash memory Erase/Write function Enable Mode” should first be successfully enabled before the Erase or Write Flash memory operation is executed. Bit 3 BWT: Flash memory Erase/Write function enable procedure Trigger 0: Erase/Write function enable procedure is not triggered or procedure timer times out 1: Erase/Write function enable procedure is triggered and procedure timer starts to count This bit is used to activate the flash memory Erase/Write function enable procedure and an internal timer. It is set by the application programs and then cleared by the hardware when the internal timer times out. The correct patterns must be written into the FD1L/FD1H, FD2L/FD2H and FD3L/FD3H register pairs respectively as soon as possible after the BWT bit is set high. Bit 2 FWT: Flash memory write initiate control 0: Do not initiate Flash memory write or indicating that a Flash memory write process has completed 1: Initiate Flash memory write process This bit is set by software and cleared by the hardware when the Flash memory write process has completed. Note that all CPU operations will temporarily cease when this bit is set to “1”. 37 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 1 FRDEN: Flash memory read enable control 0: Flash memory read disable 1: Flash memory read enable This is the Flash memory Read Enable Bit which must be set high before any Flash memory read operations are carried out. Clearing this bit to zero will inhibit Flash memory read operations. Bit 0 FRD: Flash memory read initiate control 0: Do not initiate Flash memory read or indicating that a Flash memory read process has completed 1: Initiate Flash memory read process This bit is set by software and cleared by the hardware when the Flash memory read process has completed. Note that all CPU operations will temporarily cease when this bit is set to “1”. Note: The FWT, FRDEN and FRD bits cannot be set to “1” at the same time with a single instruction. • FRCR Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 — D4 — — — CLWB R/W R/W R — R/W — — — R/W POR 0 0 — 0 — — — 0 Bit 7 D7: Reserved bit, cannot be used and must be fixed at “0” Bit 6 D6: Reserved bit Bit 5 Unimplemented, read as “0”. Bit 4 D4: Reserved bit, cannot be used and must be fixed at “0” Bit 3~1 Unimplemented, read as “0”. Bit 0 CLWB: Flash memory Write Buffer Clear control 0: Do not initiate a Write Buffer Clear process or indicating that a Write Buffer Clear process has completed 1: Initiate Write Buffer Clear process This bit is set by software and cleared by hardware when the Write Buffer Clear process has completed. Flash Memory Erase/Write Flow It is important to understand the Flash memory Erase/Write flow before the Flash memory contents are updated. Users can refer to the corresponding operation procedures when developing their IAP program to ensure that the flash memory contents are correctly updated. Flash Memory Erase/Write Flow Descriptions: 1. Activate the “Flash Memory Erase/Write function enable procedure” first. When the Flash Memory Erase/Write function is successfully enabled, the CFWEN bit in the FCR register will automatically be set high by hardware. After this, Erase or Write operations can be executed on the Flash memory. Refer to the “Flash Memory Erase/Write Function Enable Procedure” for details. 2. Configure the flash memory address to select the desired erase page and then erase this page. 3. Execute a Blank Check operation to ensure whether the page erase operation is successful or not. The “TABRD” instruction should be executed to read the flash memory contents and to check if the contents is 0000h or not. If the flash memory page erase operation fails, users should go back to Step 2 and execute the page erase operation again. Rev. 1.10 38 December 15, 2016 HT66FB570 A/D Flash USB MCU 4. Write data into the specific page. Refer to the “Flash Memory Write Procedure” for details. 5. Execute the “TABRD” instruction to read the flash memory contents and check if the written data is correct or not. If the data read from the flash memory is different from the written data, it means that the page write operation has failed. The CLWB bit should be set high to clear the write buffer and then write the data into the specific page again if the write operation has failed. 6. Clear the CFWEN bit to disable the Flash Memory Erase/Write function enable mode if the current page Erase and Write operations are complete if no more pages need to be erased or written. Flash Memory Erase/Write Flow Flash Memory Erase/Write Function Enable Procedure(*) (CFWEN=1) Page Erase Flash Memory No Blank Check Page Data =0000h? Yes Flash Memory (Page) Write Procedure(*) Set CLWB bit No Verify Page Data Correct? Yes Clear CFWEN bit Disable Flash Memory Erase/Write Function END Flash Memory Erase/Write Flow Note : The Flash Memory Erase/Write Function Enable procedure and Flash Memory Write procedure will be described in the following sections. Rev. 1.10 39 December 15, 2016 HT66FB570 A/D Flash USB MCU Flash Memory Erase/Write Function Enable Procedure The Flash Memory Erase/Write Function Enable Mode is specially designed to prevent the flash memory contents from being wrongly modified. In order to allow users to change the Flash memory data using the IAP control registers, users must first enable the Flash memory Erase/Write function. Flash Memory Erase/Write Function Enable Procedure Description 1. Write data “110” to the FMOD [2:0] bits in the FCR register to select the Flash Memory Erase/ Write Function Enable Mode. 2. Set the BWT bit in the FCR register to “1” to activate the Flash Memory Erase/Write Function. This will also activate an internal timer. 3. Write the correct data pattern into the Flash data registers, FD1L~FD3L and FD1H~FD3H, as soon as possible after the BWT bit is set high. The enable Flash memory erase/write function data pattern is 00H, 0DH, C3H, 04H, 09H and 40H corresponding to the FD1L~FD3L and FD1H~FD3H registers respectively. 4. Once the timer has timed out, the BWT bit will automatically be cleared to “0” by hardware regardless of the input data pattern. 5. If the written data pattern is incorrect, the Flash memory erase/write function will not be enabled successfully and the above steps should be repeated. If the written data pattern is correct, the Flash memory erase/write function will be enabled successfully. 6. Once the Flash memory erase/write function is enabled, the Flash memory contents can be updated by executing the page erase and write operations using the IAP control registers. To disable the Flash memory erase/write function, the CFWEN bit in the FCR register can be cleared. There is no need to execute the above procedure. Rev. 1.10 40 December 15, 2016 HT66FB570 A/D Flash USB MCU Flash Memory Erase/Write Function Enable Procedure FMOD[2:0]=110 set BWT=1 Hardware start a timer Wrtie the following pattern to Flash Data register FD1L=00h, FD1H=04h FD2L=0Dh, FD2H=09h FD3L=C3h, FD3H=40h No Is timer Time-out BWT=0? Yes No Is pattern correct? Yes CFWEN=1 Flash Memory Erase/Write Function Enabled CFWEN=0 Flash Memory Erase/Write Function Disabled END Flash Memory Erase/Write Function Enable Procedure Rev. 1.10 41 December 15, 2016 HT66FB570 A/D Flash USB MCU Flash Memory Write Procedure After the Flash memory erase/write function has been successfully enabled as the CFWEN bit is set high, the data to be written into the flash memory can be loaded into the write buffer. The selected flash memory page data should be erased by properly configuring the IAP control registers before the data write procedure is executed. The write buffer size is 64 words, known as a page, whose address is mapped to a specific flash memory page specified by the memory address bits, A14~A6. It is important to ensure that the page where the write buffer data is located is the same one which the memory address bits, A14~A6, specify. • Flash Memory Consecutive Write Description The maximum amount of write data is 64 words for each write operation. The write buffer address will be automatically incremented by one when consecutive write operations are executed. The start address of a specific page should first be written into the FARL and FARH registers. Then the data word should first be written into the FD0L register and then the FD0H register. At the same time the write buffer address will be incremented by one and then the next data word can be written into the FD0L and FD0H registers for the next address without modifying the address register pair, FARH and FARL. When the write buffer address reaches the page boundary the address will not be further incremented but will stop at the last address of the page. 1. Activate the “Flash Memory Erase/Write function enable procedure”. Check the CFWEN bit value and then execute the erase/write operations if the CFWEN bit is set high. Refer to the “Flash Memory Erase/Write function enable procedure” for more details. 2. Set the FMOD field to “001” to select the erase operation. Set the FWT bit high to erase the desired page which is specified by the FARH and FARL registers. Wait until the FWT bit goes low. 3. Execute a Blank Check operation using the table read instruction to ensure that the erase operation has successfully completed. Go to step 2 if the erase operation is not successful. Go to step 4 if the erase operation is successful. 4. Set the FMOD field to “000” to select the write operation. 5. Setup the desired start address in the FARH and FARL registers. Write the desired data words consecutively into the FD0L and FD0H registers within a page as specified by their consecutive addresses. The maximum written data number is 64 words. 6. Set the FWT bit high to write the data words from the write buffer to the flash memory. Wait until the FWT bit goes low. 7. Verify the data using the table read instruction to ensure that the write operation has successfully completed. If the write operation has not successfully completed, set the CLWB bit high to clear the write buffer and then go to step 5. Go to step 8 if the write operation is successful. 8. Clear the CFWEN bit low to disable the Flash memory erase/write function. Rev. 1.10 42 December 15, 2016 HT66FB570 A/D Flash USB MCU Write Flash Memory Flash Memory Erase/Write Function Enable Procedure Page Erase FARH = xxH, FARL = xxH FMOD[2:0] = 001 FWT = 1 No FWT = 0 ? Yes Blank Check with Table Read instruction No Blank Check Page Data=0000h? Yes Write FMOD[2:0]= 000 Specify Flash Memory Address FARH = xxH, FARL = xxH Write data to Write Buffer FD0L = xxH, FD0H = xxH No Write next data Write to Buffer Finish? Yes FWT = 1 No Set CLWB bit FWT = 0 ? Verify data with Table Read instruction DATA correct ? No Yes No Write another Page Write Finish ? Yes Clear CFWEN bit END Flash Memory Consecutive Write Procedure Note: When the FWT bit is set to 1 all CPU operations will temporarily cease. Rev. 1.10 43 December 15, 2016 HT66FB570 A/D Flash USB MCU • Flash Memory Non-Consecutive Write Description The main difference between Flash Memory Consecutive and Non-Consecutive Write operations is whether the data words to be written are located in consecutive addresses or not. If the data to be written is not located in consecutive addresses the desired address should be re-assigned after a data word is successfully written into the Flash Memory. A two data word non-consecutive write operation is taken as an example here and described as follows: 1. Activate the “Flash Memory Erase/Write function enable procedure”. Check the CFWEN bit value and then execute the erase/write operation if the CFWEN bit is set high. Refer to the “Flash Memory Erase/Write function enable procedure” for more details. 2. Set the FMOD field to “001” to select the erase operation. Set the FWT bit high to erase the desired page which is specified by the FARH and FARL registers. Wait until the FWT bit goes low. 3. Execute a Blank Check operation using the table read instruction to ensure that the erase operation has successfully completed. Go to step 2 if the erase operation is not successful. Go to step 4 if the erase operation is successful. 4. Set the FMOD field to “000” to select the write operation. 5. Setup the desired address ADDR1 in the FARH and FRARL registers. Write the desired data word DATA1 first into the FD0L register and then into the FD0H register. 6. Set the FWT bit high to transfer the data word from the write buffer to the flash memory. Wait until the FWT bit goes low. 7. Verify the data using the table read instruction to ensure that the write operation has successfully completed. If the write operation has not successfully completed, set the CLWB bit high to clear the write buffer and then go to step 5. Go to step 8 if the write operation is successful. 8. Setup the desired address ADDR2 in the FARH and FRARL registers. Write the desired data word DATA2 first into the FD0L register and then into the FD0H register. 9. Set the FWT bit high to transfer the data word from the write buffer to the flash memory. Wait until the FWT bit goes low. 10. Verify the data using the table read instruction to ensure that the write operation has successfully completed. If the write operation has not successfully completed, set the CLWB bit high to clear the write buffer and then go to step 8. Go to step 11 if the write operation is successful. 11. Clear the CFWEN bit low to disable the Flash memory erase/write function. Rev. 1.10 44 December 15, 2016 HT66FB570 A/D Flash USB MCU Write Flash Memory Flash Memory Erase/Write Function Enable Procedure Page Erase FARH = xxH, FARL = xxH FMOD[2:0] = 001 FWT = 1 No FWT = 0 ? Yes Blank Check with Table Read instruction Blank Check Page Data=0000h? No Yes Write FMOD[2:0]= 000 Specify Flash Memory Address FARH = xxH, FARL = xxH Write data to Write Buffer FD0L = xxH, FD0H = xxH FWT = 1 No Set CLWB bit FWT = 0 ? Verify data with Table Read instruction DATA correct ? No Yes Yes Write another word Write Another Data Word ? No Clear CFWEN bit END Flash Memory Non-Consecutive Write Procedure Note: When the FWT bit is set to 1 all CPU operations will temporarily cease. Rev. 1.10 45 December 15, 2016 HT66FB570 A/D Flash USB MCU • Important Points to Note for Flash Memory Write Operations 1. The “Flash Memory Erase/Write Function Enable Procedure” must be successfully activated before the Flash Memory erase/write operation is executed. 2. The Flash Memory erase operation is executed to erase a whole page. 3. The whole write buffer data will be written into the flash memory in a page format. The corresponding address cannot exceed the page boundary. 4. Bit 7 ~ bit 1 in the FRCR register must remain at “0” to avoid unpredictable errors during the IAP supported operations. 5. After the data is written into the flash memory the flash memory contents must be read out using the table read instruction, TABRD, and checked if it is correct or not. If the data written into the flash memory is incorrect, the write buffer should be cleared by setting the CLWB bit high and then writing the data again into the write buffer. Then activate a write operation on the same flash memory page without erasing it. The data check, buffer clear and data re-write steps should be repeatedly executed until the data written into the flash memory is correct. 6. The system frequency should be setup to the maximum application frequency when data write and data check operations are executed using the IAP function. Flash Memory Read Procedure To activate the Flash Memory Read procedure, the FMOD field should be set to “011” to select the flash memory read mode and the FRDEN bit should be set high to enable the read function. The desired flash memory address should be written into the FARH and FARL registers and then the FRD bit should be set high. After this the flash memory read operation will be activated. The data stored in the specified address can be read from the data registers, FD0H and FD0L, when the FRD bit goes low. There is no need to first activate the Flash Memory Erase/Write Function Enable Procedure before the flash memory read operation is executed. Read Flash Memory FMOD[2:0]=011 FRDEN=1 Flash address register: FARH=xxh, FARL=xxh FRD=1 No FRD=0 ? Yes Read value: FD0L=xxh, FD0H=xxh No Read Finish ? Yes FRDEN=0 END Flash Memory Read Procedure Note: When the FRD bit is set to 1 all CPU operations will temporarily cease. Rev. 1.10 46 December 15, 2016 HT66FB570 A/D Flash USB MCU In System Programming – ISP As an additional convenience, Holtek has provided a means of programming the microcontroller in-system using a two-line USB interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the microcontroller device. The Program Memory can be programmed serially in-system using the USB interface, namely using the UDN and UDP pins. The power is supplied by the UBUS pin. The technical details regarding the in-system programming are beyond the scope of this document and will be supplied in supplementary literature. The Flash Program Memory Read/Write function is implemented using a series of registers. ISP Bootloader An ISP Bootloader function is provided to upgrade the software in the Flash Memory. The user can utilise either the ISP Bootloader application software provided by the Holtek IDE tools or to create their own Bootloader software. When the Holtek Bootloader software is selected note that it will occupy an area of 0.5K capacity area in the Flash Memory. The accompanying diagram illustrates the Flash Memory structure including the Holtek Bootloader software. Bootloader 0000H Bank 0 1FFFH Bank 1 3FFFH Bank 2 5FFFH Bank 3 7D00H 7DFFH Last Page Flash Memory Structure including Bootloader Rev. 1.10 47 December 15, 2016 HT66FB570 A/D Flash USB MCU Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Categorized into two types, the first of these is an area of RAM, known as the Special Function Data Memory. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. Switching between the different Data Memory sectors is achieved by properly setting the Memory Pointers to correct value. Structure The Data Memory is subdivided into several sectors, all of which are implemented in 8-bit wide RAM. Each of the Data Memory Sector is categorized into two types, the special Purpose Data Memory and the General Purpose Data Memory. The address range of the Special Purpose Data Memory for the device is from 00H to 7FH while the General Purpose Data Memory address range is from 80H to FFH. Special Purpose Data Memory General Purpose Data Memory Located Sectors Capacity Sector: Address 1024×8 0: 80H~FFH 1: 80H~FFH : : 6: 80H~FFH 7: 80H~FFH 0, 1 Data Memory Summary 00H Spe�ial Pu�pose Data Me�o�y (Se�to� 0 ~ Se�to� 1) 7FH 80H Gene�al Pu�pose Data Me�o�y (Se�to� 0 ~ Se�to� 7) FFH Se�to� 0 Se�to� 1 Se�to� 7 Data Memory Structure Rev. 1.10 48 December 15, 2016 HT66FB570 A/D Flash USB MCU Data Memory Addressing For the device that supports the extended instructions, there is no Bank Pointer for Data Memory. The Bank Pointer, PBP, is only available for Program Memory. For Data Memory the desired Sector is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected sector is specified by the MP1L or MP2L register when using indirect addressing access. Direct Addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. For the accessed data memory which is located in any data memory sectors except sector 0, the extended instructions can be used to access the data memory instead of using the indirect addressing access. The main difference between standard instructions and extended instructions is that the data memory address "m" in the extended instructions can be 11 bits for this device, the high byte indicates a sector and the low byte indicates a specific address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value "00H". Rev. 1.10 49 December 15, 2016 HT66FB570 A/D Flash USB MCU 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Sector 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS PBP IAR2 MP2L MP2H RSTFC INTC0 INTC1 INTC2 INTC3 PA PAC PAPU PAWUEG0 PAWUEG1 PB PBC PBPU PBWU PC PCC PCPU PCWU PE PEC PEPU PEWU SPIAC0 SPIAC1 SPIAD LVRC LVDC USR UCR1 UCR2 TXR_RXR BRG STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP PTM0C0 PTM0C1 PTM0DL PTM0DH PTM0AL PTM0AH PTM0RPL PTM0RPH EEA EED Sector 1 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH SLEWC0 SLEWC1 SLEWC2 SLEWC3 MFI0 MFI1 MFI2 MFI3 MFI4 MFI5 PMPS DRVCC0 DRVCC1 IFS INTEG PD PDC PDPU PDWU PF PFC PFPU PFWU PG PGC PGPU PGWU PAS0 PAS1 PBS0 PBS1 PCS0 PCS1 PDS0 PDS1 PES0 PES1 PFS0 PFS1 PGS0 PGS1 PTM1C0 PTM1C1 PTM1DL PTM1DH PTM1AL PTM1AH PTM1RPL PTM1RPH EEC Sector 0 FARL FD0L FD1L FD2L FD3L PTM2C0 PTM2C1 PTM2DL PTM2DH PTM2AL PTM2AH PTM2RPL PTM2RPH WDTC SADOL SADOH SADC0 SADC1 SADC2 SCC HIRCC HXTC LXTC PLLC TB0C TB1C SYSC USB_STAT UINT USC UESR UCC AWR STLI STLO SIES MISC UFIEN UFOEN UFC0 UFC1 UFC2 FIFO0 FIFO1 FIFO2 FIFO3 FIFO4 FIFO5 FIFO6 FIFO7 SIMC0 SIMC1 SIMD SIMA/SIMC2 SIMTOC Sector 1 FRCR FCR FARH FD0H FD1H FD2H FD3H PTM3C0 PTM3C1 PTM3DL PTM3DH PTM3AL PTM3AH PTM3RPL PTM3RPH PTM4C0 PTM4C1 PTM4DL PTM4DH PTM4AL PTM4AH PTM4RPL PTM4RPH CMP0C CMP1C PSCR : Unused, read as 00H Special Purpose Data Memory Rev. 1.10 50 December 15, 2016 HT66FB570 A/D Flash USB MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section; however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with the MP1L/MP1H register pair and IAR2 register together with the MP2L/MP2H register pair can access data from any Data Memory Sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers will return a result of "00H" and writing to the registers will result in no operation. Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L, MP2H, are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all sectors according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example 1 data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a, 04h; setup size of block mov block, a mov a, offset adres1 ; Accumulator loaded with first RAM address mov mp0, a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: Rev. 1.10 51 December 15, 2016 HT66FB570 A/D Flash USB MCU Indirect Addressing Program Example 2 data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a, 04h; setup size of block mov block, a mov a, 01h; setup the memory sector mov mp1h, a mov a, offset adres1 ; Accumulator loaded with first RAM address mov mp1l, a ; setup memory pointer with first RAM address loop: clr IAR1 ; clear the data at address defined by MP1L inc mp1l ; increment memory pointer MP1L sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Direct Addressing Program Example using extended instructions data .section ´data´ temp db ? code .section at 0 ´code´ org 00h start: lmov a, [m]; move [m] data to acc lsub a, [m+1] ; compare [m] and [m+1] data snz c; [m]>[m+1]? jmp continue; no lmov a, [m] ; yes, exchange [m] and [m+1] data mov temp, a lmov a, [m+1] lmov [m], a mov a, temp lmov [m+1], a continue: Note: Here "m" is a data memory address located in any data memory sectors. For example, m=1F0H, it indicates address 0F0H in Sector 1. Rev. 1.10 52 December 15, 2016 HT66FB570 A/D Flash USB MCU Program Memory Bank Pointer – PBP For this device the Program Memory is divided into several banks. Selecting the required Program Memory area is achieved using the Program Memory Bank Pointer, PBP. The PBP register should be properly configured before the device executes the "Branch" operation using the "JMP" or "CALL" instruction. After that a jump to a non-consecutive Program Memory address which is located in a certain bank selected by the program memory bank pointer bits will occur. PBP Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — PBP1 PBP0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~3 Unimplemented, read as "0" Bit 1~0 PBP1~PBP0: Program Memory Bank Pointer bit 1~ bit 0 00: Bank 0 01: Bank 1 10: Bank 2 11: Bank 3 Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.10 53 December 15, 2016 HT66FB570 A/D Flash USB MCU Status Register – STATUS This 8-bit register contains the SC flag, CZ flag, zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. • CZ is the operational result of different flags for different instructions. Refer to register definitions for more details. • SC is the result of the "XOR" operation which is performed by the OV flag and the MSB of the current instruction operation result. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.10 54 December 15, 2016 HT66FB570 A/D Flash USB MCU STATUS Register Bit 7 6 5 4 3 2 1 0 Name SC CZ TO PDF OV Z AC C R/W R R R R R/W R/W R/W R/W POR x x 0 0 x x x x "x" unknown Rev. 1.10 Bit 7 SC: The result of the "XOR" operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6 CZ: The operational result of different flags for different instructions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/SBCM/LSBC/LSBCM instructions, the CZ flag is the "AND" operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag will not be affected. Bit 5 TO: Watchdog Time-out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation The "C" flag is also affected by a rotate through carry instruction. 55 December 15, 2016 HT66FB570 A/D Flash USB MCU EEPROM Data Memory This device contains an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 256×8 bits for the device. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and a data register in Sector 0 and a single control register in Sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Sector 0, they can be directly accessed in the same way as any other Special Function Register. The EEC register however, being located in Sector 1, can be read from or written to indirectly using the MP1L/MP1H or MP2L/MP2H Memory Pointer and Indirect Addressing Register, IAR1/IAR2. Because the EEC control register is located at address 3EH in Sector 1, the MP1L or MP2L Memory Pointer must first be set to the value 3EH and the MP1H or MP2H Memory Pointer high byte set to the value, 01H, before any operations on the EEC register are executed. Bit Register Name 7 6 5 4 3 2 1 0 EEA EEA7 EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 EED EED7 EED6 EED5 EED4 EED3 EED2 EED1 EED0 EEC — — — — WREN WR RDEN RD EEPROM Registers List EEA Register Bit 7 6 5 4 3 2 1 0 Name EEA7 EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 EEA7~EEA0: Data EEPROM address bit 7 ~ bit 0 EED Register Bit 7 6 5 4 3 2 1 0 Name EED7 EED6 EED5 EED4 EED3 EED2 EED1 EED0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 EED7~EED0: Data EEPROM data bit 7 ~ bit 0 56 December 15, 2016 HT66FB570 A/D Flash USB MCU EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0 RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD cannot be set high at the same time in one instruction. The WR and RD cannot be set high at the same time. Rev. 1.10 57 December 15, 2016 HT66FB570 A/D Flash USB MCU Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset to zero, which means that Data Memory Sector 0 will be selected. As the EEPROM control register is located in Sector 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Rev. 1.10 58 December 15, 2016 HT66FB570 A/D Flash USB MCU Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte register, MP1H or MP2H, could be normally cleared to zero as this would inhibit access to Sector 1 where the EEPROM control register exists. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples • Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 03EH MOV MP1L, A MOV A, 01H MOV MP1H, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR MP1H MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer MP1L ; MP1 points to EEC register ; setup memory pointer MP1H ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register • Writing Data to the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 03EH MOV MP1L, A MOV A, 01H MOV MP1H, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR MP1H Rev. 1.10 ; user defined address ; user defined data ; setup memory pointer MP1L ; MP1 points to EEC register ; setup memory pointer MP1H ; set WREN bit, enable write operations ; start Write Cycle - set WR bit — executed immediately ; after set WREN bit ; check for write cycle end ; disable EEPROM read/write 59 December 15, 2016 HT66FB570 A/D Flash USB MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through the relevant control registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through the relevant control registers. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. For USB applications, the HXT pins must be connected to a 6MHz or 12MHz crystal if the HXT oscillator is selected to be used. Type Name Frequency Pins External High Speed Crystal HXT 6MHz or 12MHz OSC1/OSC2 Internal High Speed RC HIRC 12MHz — External Low Speed Crystal LXT 32.768kHz XT1/XT2 Internal Low Speed RC LIRC 32kHz — Oscillator Types System Clock Configurations There are several oscillator sources, two high speed oscillators and two low speed oscillators. The high speed system clocks are sourced from the external crystal/ceramic oscillator, HXT, and the internal 12MHz RC oscillator, HIRC. The low speed oscillators are the external 32.768kHz crystal oscillator, LXT, and the internal 32kHz RC oscillator, LIRC. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the CKS2~CKS0 bits in the SCC register and as the system clock can be dynamically selected. The actual source clock used for the low speed oscillators is chosen via the FSS bit in the SCC register while for the high speed oscillator the source clock is selected by the FHS bit in the SCC register. The frequency of the slow speed or high speed system clock is also determined using the CKS2~CKS0 bits in the SCC register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. In addition, the internal PLL frequency generator, whose clock source is supplied by an external crystal oscillator, can be enabled by a software control bit to generate various frequencies for the USB interface and system clock. Rev. 1.10 60 December 15, 2016 HT66FB570 A/D Flash USB MCU PLLEN PLLIS Config.Option Selects 6/12MHz HXT HXTEN fH 48MHz HXT fH/2 6MHz fHOSC HIRCEN fPLL_48MHz PLL fH/4 12MHz HIRC 16MHz High Speed Oscillators fHOSC fH/8 IDLE0 SLEEP Prescaler fH/32 FHS fH/64 fSUB PLLOS[2:0] LXTEN fSYS fH/16 LXT CKS[2:0] IDLE2 SLEEP LIRC Low Speed Oscillators fSUB fWDT FSS System Clock Configurations Internal PLL Frequency Generator The internal PLL frequency generator is used to generate the frequency for the USB interface and the system clock. This PLL generator can be enabled or disabled by the PLL control bit PLLEN in the PLLC register. After a power on reset, the PLL control bit will be set to 1 to turn on the PLL generator. The PLL generator will provide the fixed 48MHz frequency for the USB operating frequency and another frequency for the system clock source which can be 6MHz, 12MHz or 16MHz. The selection of this system frequency is implemented using the PLLEN and PLLOS2~PLLOS0 bits in the PLLC register. The following table illustrates the high frequency system clock fH selected by the related control bits. PLLEN PLLOS2 PLLOS1 PLLOS0 fH 0 x x x fHOSC – HXT or HIRC, depending on the FHS bit in the SCC register. 1 0 x x fHOSC – HXT or HIRC, depending on the FHS bit in the SCC register. 1 1 0 0 fPLL=6MHz 1 1 0 1 fPLL=12MHz 1 1 1 0 fPLL=16MHz 1 1 1 1 Reserved "x": don’t care Rev. 1.10 61 December 15, 2016 HT66FB570 A/D Flash USB MCU PLLC Register Bit 7 6 5 4 3 2 1 0 Name D7 — PLLIS PLLOS2 PLLOS1 PLLOS0 PLLF PLLEN R/W R/W — R/W R/W R/W R/W R R/W POR 0 — 0 0 0 0 0 1 Bit 7 D7: Reserved bit, cannot be used and must be fixed at 0 Bit 6 Unimplemented, read as "0" Bit 5 PLLIS: PLL input clock source selection 0: 12MHz clock 1: 6MHz clock If FHS=1, when a 12MHz crystal or resonator is used, the HXT frequency is divided by 2 and then multiplied by 8 using the internal PLL circuit, when a 6MHz crystal or resonator is used, the HXT frequency is directly multiplied by 8 using the internal PLL circuit. If FHS=0, the 12MHz HIRC is selected, this bit will be automatically cleared to zero by the hardware. Bit 4~2 PLLOS2~PLLOS0: fHOSC or fPLL for fH clock source selection 0xx: fHOSC 100: fPLL=6MHz 101: fPLL=12MHz 110: fPLL=16MHz 111: fPLL=Reserved Bit 1 PLLF: PLL clock stable flag 0: Unstable 1: Stable This bit is used to indicate whether the PLL clock is stable or not. When the PLLEN bit is set to 1 to enable the PLL clock, the PLLF bit will first be cleared to 0 and then set to 1 after the PLL clock is stable. Bit 0 PLLEN: PLL enable control 0: Disable 1: Enable External Crystal/Ceramic Oscillator – HXT The External Crystal System Oscillator is one of the high frequency oscillators. The External Crystal/Ceramic System Oscillator is one of the high frequency oscillators. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. For USB applications, the HXT pins must be connected to a 6MHz or 12MHz crystal if the HXT oscillator is selected to be used. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. Rev. 1.10 62 December 15, 2016 HT66FB570 A/D Flash USB MCU C1 Internal Oscillator Circuit OSC1 RP RF OSC� C� To inte�nal �i��uits Note: 1. RP is no��ally not �equi�ed. C1 and C� a�e �equi�ed. �. Although not shown OSC1/OSC� pins have a pa�asiti� �apa�itan�e of a�ound 7pF. Crystal/Resonator Oscillator – HXT Crystal Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz 0pF 0pF 8MHz 0pF 0pF 6MHz 0pF 0pF 4MHz 0pF 0pF 1MHz 100pF 100pF Note: C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values Internal High Speed RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PD0 and PD1 are free for use as normal I/O pins. The HIRC has its own power supply pin, AVDD. The AVDD pin must be connected to VDD and a 0.1μF capacitor to ground. External 32.768kHz Crystal Oscillator – LXT The External 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. After the LXT oscillator is enabled by setting the LXTEN bit to 1, there is a time delay associated with the LXT oscillator waiting for it to start-up. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. The external parallel feedback resistor, RP, is required. The pin-shared software control bits determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O or other pin-shared functional pins. Rev. 1.10 63 December 15, 2016 HT66FB570 A/D Flash USB MCU • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O or other pin-shared functional pins. • If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. C1 Internal Oscillator Circuit XT1 3�.7�8 kHz Inte�nal RC Os�illato� RP To inte�nal �i��uits XT� C� Note: 1. RP� C1 and C� a�e �equi�ed. �. Although not shown XT1/XT� pins have a pa�asiti� �apa�itan�e of a�ound 7pF. External LXT Oscillator LXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 32.768kHz 10pF 10pF Note: 1. C1 and C2 values are for guidance only. 2. RP=5M~10MΩ is recommended. 32.768kHz Crystal Recommended Capacitor Values LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Speed Up Mode and the Low Power Mode. The mode selection is executed using the LXTSP bit in the LXTC register. LXTSP Bit LXT Mode 0 Low Power 1 Speed Up When the LXTSP bit is set to high, the LXT Speed Up Mode will be enabled. In the Speed Up Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up, it can be placed into the Low Power Mode by clearing the LXTSP bit to zero and the oscillator will continue to run bit with reduced current consumption. It is important to note that the LXT operating mode switching must be properly controlled before the LXT oscillator clock is selected as the system clock source. Once the LXT oscillator clock is selected as the system clock source using the CKS bit field and FSS bit in the SCC register, the LXT oscillator operating mode cannot be changed. It should be note, that no matter what condition the LXTSP is set to, the LXT oscillator will always function normally. The only difference is that it will take more time to start up if in the Low Power Mode. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Rev. 1.10 64 December 15, 2016 HT66FB570 A/D Flash USB MCU Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. As Holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from a high frequency, fH, or low frequency, fSUB, source, and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock can be sourced from an HXT or HIRC oscillator or the USB PLL output clock, selected via configuring the FHS bit in the SCC register together with the PLLEN and PLLOS2~PLLOS0 bits in the PLLC register. The low speed system clock source can be sourced from the internal clock fSUB. If fSUB is selected then it can be sourced by either the LXT or LIRC oscillators, selected via configuring the FSS bit in the SCC register. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. PLLEN PLLIS Config.Option Selects 6/12MHz HXT HXTEN 48MHz HXT fHOSC HIRCEN To USB Circuits fH USBCKEN fH/2 6MHz PLL fH/4 12MHz HIRC 16MHz High Speed Oscillators fHOSC fH/8 Prescaler IDLE0 SLEEP fH/32 FHS fH/64 fSUB PLLOS[2:0] LXTEN LXT CKS[2:0] IDLE2 SLEEP LIRC Low Speed Oscillators fSYS fH/16 FSS fWDT fSUB TB0[2:0] TB0ON fSUB WDT fSYS/4 fPSC fSYS Prescaler TB1ON CLKSEL0[1:0] Time Base 0 Time Base 1 TB1[2:0] Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillator will stop to conserve the power or continue to oscillate to provide the clock source, fH ~ fH/64, for peripheral circuit to use, which is determined by configuring the corresponding high speed oscillator enable control bit. Rev. 1.10 65 December 15, 2016 HT66FB570 A/D Flash USB MCU System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0, IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode CPU NORMAL On Register Setting FHIDEN FSIDEN CKS2~CKS0 x x SLOW On x x IDLE0 Off 0 1 IDLE1 Off 1 1 IDLE2 Off 1 0 SLEEP Off 0 0 000~110 fSYS fH fH~fH/64 On 111 fSUB 000~110 Off 111 On xxx On 000~110 On 111 Off xxx Off fSUB fWDT fPLL On On On On On Off On On Off On On On On On Off On/Off (2) On Off Off On/Off (2) Off On/Off (1) On/Off (3) "x": Don’t care Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable bit in the SLOW mode. 2. The fWDT clock can be switched on or off which is controlled by the WDT function being enabled or disabled. 3. The fPLL clock can be switched on or off which is controlled by the PLLEN bit in the PLLC register in the SLOW mode. 4. The USB function is inactive in IDLE0 and SLEEP mode. NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 bits in the SCC register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. In the USB mode, the PLL circuit of which the clock source can be derived from the HXT or HIRC oscillator can generate a clock with a frequency of 6MHz, 12MHz or 16MHz as the device system clock. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. The fSUB clock is derived from either the LIRC or LXT oscillator determined by the FSS bit in the SCC register. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. The fSUB clock provided to the peripheral function will also be stopped, too. However the fWDT clock can continues to operate if the WDT function is enabled. Rev. 1.10 66 December 15, 2016 HT66FB570 A/D Flash USB MCU IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. IDLE2 Mode The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Control Registers The registers, SCC, HIRCC, HXTC, LXTC and PLLC, are used to control the system clock and the corresponding oscillator configurations. Register Name SCC HIRCC Bit 7 6 CKS2 CKS1 CLKADJ CLKADJF 5 4 3 2 1 0 CKS0 — FHS FSS FHIDEN FSIDEN CLKFIX — — — HIRCF HIRCEN HXTC — — — — — HXTM HXTF HXTEN LXTC — — — — — LXTSP LXTF LXTEN PLLC D7 — PLLIS PLLOS2 PLLOS1 PLLOS0 PLLF PLLEN System Operating Mode Control Registers List SCC Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — FHS FSS FHIDEN FSIDEN R/W R/W R/W R/W — R/W R/W R/W R/W POR 0 1 0 — 0 0 0 0 Bit 7~5 CKS2~CKS0: System clock selection 000: fH 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fSUB These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or fSUB, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as 0. 67 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 3 FHS: High Frequency clock, fHOSC, selection 0: HIRC 1: HXT Bit 2 FSS: Low Frequency clock selection 0: LIRC 1: LXT Bit 1 FHIDEN: High Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. Bit 0 FSIDEN: Low Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. The low frequency oscillator is controlled by this bit together with the WDT function enable control. If this bit is cleared to 0 but the WDT function is enabled, the fWDT clock will also be enabled. HIRCC Register Bit Name Rev. 1.10 7 6 CLKADJ CLKADJF 5 4 3 2 1 0 CLKFIX — — — HIRCF HIRCEN R/W R/W R/W R/W — — — R R/W POR 0 0 0 — — — 0 1 Bit 7 CLKADJ: HIRC clock automatic adjustment function control in the USB mode 0: Disable 1: Enable Note that if the user selects the HIRC as the system clock, the CLKADJ bit must be set to 1 to adjust the PLL frequency automatically. Bit 6 CLKADJF: HIRC clock automatic adjustment stable flag 0: Unstable 1: Stable The CLKADJF bit indicates whether the HIRC frequency adjusting operation is completed or not when the CLKADJ bit is set to 1. Users can continuously monitor the CLKADJF bit by application programs to make sure that the HIRC frequency accuracy is stably adjusted in the range of ±0.25%. The CLKADJF bit can be cleared by the application program. Bit 5 CLKFIX: HIRC clock fix automatic adjustment function control 0: Disable 1: Enable Note that when CLKADJF=1, the CLKFIX bit can be set high to fix the HIRC frequency accuracy in the range of ±0.25%. Bit 4~2 Unimplemented, read as 0. Bit 1 HIRCF: HIRC oscillator stable flag 0: HIRC unstable 1: HIRC stable This bit is used to indicate whether the HIRC oscillator is stable or not. When the HIRCEN bit is set to 1 to enable the HIRC oscillator, the HIRCF bit will first be cleared to 0 and then set to 1 after the HIRC oscillator is stable. Bit 0 HIRCEN: HIRC oscillator enable control 0: Disable 1: Enable 68 December 15, 2016 HT66FB570 A/D Flash USB MCU HXTC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — HXTM HXTF HXTEN R/W — — — — — R/W R R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as 0. Bit 2 HXTM: HXT mode selection 0: HXT frequency ≤ 10MHz 1: HXT frequency > 10MHz This bit is used to select the HXT oscillator operating mode. Note that this bit must be properly configured before the HXT is enabled. When the HXTEN bit is set to 1 to enable the HXT oscillator, it is invalid to change the value of this bit. Bit 1 HXTF: HXT oscillator stable flag 0: HXT unstable 1: HXT stable This bit is used to indicate whether the HXT oscillator is stable or not. When the HXTEN bit is set to 1 to enable the HXT oscillator, the HXTF bit will first be cleared to 0 and then set to 1 after the HXT oscillator is stable. Bit 0 HXTEN: HXT oscillator enable control 0: Disable 1: Enable LXTC Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — — — — LXTSP LXTF LXTEN R/W — — — — — R/W R R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as 0. Bit 2 LXTSP: LXT speed-up control 0: Disable 1: Enable This bit is used to control whether the LXT oscillator is operating in the low power or quick start mode. When the LXTSP bit is set to 1, the LXT oscillator will oscillate quickly but consume more power. If the LXTSP bit is cleared to 0, the LXT oscillator will consume less power but take longer time to stablise. It is important to note that this bit can not be changed after the LXT oscillator is selected as the system clock source using the CKS2~CKS0 and FSS bits in the SCC register. Bit 1 LXTF: LXT oscillator stable flag 0: LXT unstable 1: LXT stable This bit is used to indicate whether the LXT oscillator is stable or not. When the LXTEN bit is set to 1 to enable the LXT oscillator, the LXTF bit will first be cleared to 0 and then set to 1 after the LXT oscillator is stable. Bit 0 LXTEN: LXT oscillator enable control 0: Disable 1: Enable 69 December 15, 2016 HT66FB570 A/D Flash USB MCU PLLC Register Bit 7 6 5 4 3 2 1 0 Name D7 — PLLIS PLLOS2 PLLOS1 PLLOS0 PLLF PLLEN R/W R/W — R/W R/W R/W R/W R R/W POR 0 — 0 0 0 0 0 1 Bit 7 Rev. 1.10 D7: Reserved bit, cannot be used and must be fixed at 0 Bit 6 Unimplemented, read as "0" Bit 5 PLLIS: PLL input clock source selection 0: 12MHz clock 1: 6MHz clock If FHS=1, when a 12MHz crystal or resonator is used, the HXT frequency is divided by 2 and then multiplied by 8 using the internal PLL circuit, when a 6MHz crystal or resonator is used, the HXT frequency is directly multiplied by 8 using the internal PLL circuit. If FHS=0, the 12MHz HIRC is selected, this bit will be automatically cleared to zero by the hardware. Bit 4~2 PLLOS2~PLLOS0: fHOSC or fPLL for fH clock source selection 0xx: fHOSC 100: fPLL=6MHz 101: fPLL=12MHz 110: fPLL=16MHz 111: fPLL=Reserved Bit 1 PLLF: PLL clock stable flag 0: Unstable 1: Stable This bit is used to indicate whether the PLL clock is stable or not. When the PLLEN bit is set to 1 to enable the PLL clock, the PLLF bit will first be cleared to 0 and then set to 1 after the PLL clock is stable. Bit 0 PLLEN: PLL enable control 0: Disable 1: Enable 70 December 15, 2016 HT66FB570 A/D Flash USB MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register. NORMAL fSYS=fH~fH/�4 fH on CPU �un fSYS on fSUB on SLOW fSYS=fSUB fSUB on CPU �un fSYS on fH on/off SLEEP HALT inst�u�tion exe�uted CPU stop FHIDEN=0 FSIDEN=0 fH off fSUB off IDLE0 HALT inst�u�tion exe�uted CPU stop FHIDEN=0 FSIDEN=1 fH off fSUB on IDLE2 HALT inst�u�tion exe�uted CPU stop FHIDEN=1 FSIDEN=0 fH on fSUB off Rev. 1.10 71 IDLE1 HALT inst�u�tion exe�uted CPU stop FHIDEN=1 FSIDEN=1 fH on fSUB on December 15, 2016 HT66FB570 A/D Flash USB MCU NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to "111" in the SCC register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC register and therefore requires this oscillator to be stable before full mode switching occurs. NORMAL Mode CKS�~CKS0 = 111 SLOW Mode FHIDEN=0� FSIDEN=0 HALT inst�u�tion is exe�uted SLEEP Mode FHIDEN=0� FSIDEN=1 HALT inst�u�tion is exe�uted IDLE0 Mode FHIDEN=1� FSIDEN=1 HALT inst�u�tion is exe�uted IDLE1 Mode FHIDEN=1� FSIDEN=0 HALT inst�u�tion is exe�uted IDLE2 Mode Rev. 1.10 72 December 15, 2016 HT66FB570 A/D Flash USB MCU SLOW Mode to NORMAL Mode Switching In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the NORMAL mode from fSUB, the CKS2~CKS0 bits should be set to "000"~"110" and then the system clock will respectively be switched to fH~fH/64. However, if fH is not used in SLOW mode and thus switched off, it will take some time to reoscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is monitored using the HXTF bit in the HXTC register or the HIRCF bit in the HIRCC register or the PLLF bit in the PLLC register. The time duration required for the high speed system oscillator stabilization is specified in the A.C. characteristics. SLOW Mode CKS�~CKS0 = 000~110 NORMAL Mode FHIDEN=0� FSIDEN=0 HALT inst�u�tion is exe�uted SLEEP Mode FHIDEN=0� FSIDEN=1 HALT inst�u�tion is exe�uted IDLE0 Mode FHIDEN=1� FSIDEN=1 HALT inst�u�tion is exe�uted IDLE1 Mode FHIDEN=1� FSIDEN=0 HALT inst�u�tion is exe�uted IDLE2 Mode Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "0". In this mode all the clocks and functions will be switched off except the WDT function. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. • The WDT will be cleared and resume counting������������������������������������������������� if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and then stopped. • The USB will enter the suspend mode if the USB function is enabled. Rev. 1.10 73 December 15, 2016 HT66FB570 A/D Flash USB MCU Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "0" and the FSIDEN bit in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be stopped and the application program will stop at the "HALT" instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. • The WDT will be cleared and resume counting������������������������������������������������� if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and then stopped. • The USB will enter the suspend mode if the USB function is enabled. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The fH and fSUB clocks will be on but the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. • The WDT will be cleared and resume counting ������������������������������������������������ if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and then stopped. Entering the IDLE2 Mode There is only one way for the device to enter the IDLE2 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "1" and the FSIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be on but the fSUB clock will be off and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. • The WDT will be cleared and resume counting ������������������������������������������������ if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and then stopped. Rev. 1.10 74 December 15, 2016 HT66FB570 A/D Flash USB MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to the device which has different package types, as there may be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LXT or LIRC oscillator has enabled. In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external pin reset • An USB reset signal reset • An external trigger edge on I/O Port • A system interrupt • A WDT overflow If the system is woken up by an external pin or USB reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on I/O Port can be setup using the PAWUEG0, PAWUEG1 or PBWU~PGPU register to permit an active trigger edge transition on the pin to wake-up the system. When a pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.10 75 December 15, 2016 HT66FB570 A/D Flash USB MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fWDT, which can be sourced from either the LXT or LIRC oscillator determined by the FSS bit in the SCC register. The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable and reset MCU operation. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4~WE0: WDT function software control 10101: Disable 01010: Enable Other values: Reset MCU When these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after 2~3 fLIRC clock cycles and the WRF bit in the RSTFC register will be set high. Bit 2~0 WS2~WS0: WDT time-out period selection 000: 28/fWDT 001: 210/fWDT 010: 212/fWDT 011: 214/fWDT 100: 215/fWDT 101: 216/fWDT 110: 217/fWDT 111: 218/fWDT These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period. RSTFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — LVRF LRF WRF R/W — — — — — R/W R/W R/W POR — — — — — x 0 Bit 7~3 Bit 2 Bit 1 Rev. 1.10 Unimplemented, read as "0" LVRF: LVR function reset flag Described elsewhere. LRF: LVR control register software reset flag Described elsewhere. 76 0 "x": unknown December 15, 2016 HT66FB570 A/D Flash USB MCU WRF: WDT control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Bit 0 Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTC register to offer the enable/disable control and reset control of the Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B while the WDT function will be enabled if the WE4~WE0 bits are equal to 01010B. If the WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device after 2~3 fLIRC clock cycles. After power on these bits will have a value of 01010B. WE4~WE0 Bits WDT Function 10101B Disable 01010B Enable Any other values Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Four methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bits, the second is using the Watchdog Timer software clear instruction, the third is via a HALT instruction and the fourth is an external hardware reset, which means a low level on the external RES pin. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT. The maximum time-out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. WDTC Registe� WE4~WE0 �its Reset MCU “CLR WDT” Inst�u�tion CLR “HALT” Inst�u�tion RES pin �eset fWDT 8-stage Divide� fWDT/�8 WS�~WS0 WDT P�es�ale� WDT Ti�e-out (�8/fWDT ~ �18/fWDT) 8-to-1 MUX Watchdog Timer Rev. 1.10 77 December 15, 2016 HT66FB570 A/D Flash USB MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the device is running. One example of this is where after power has been applied and the device is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the registers remain unchanged allowing the device to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD 0.9VDD RES tRSTD+tSST Inte�nal Reset Note: tRSTD is power-on delay, typical time=50ms Power-on Reset Timing Chart Rev. 1.10 78 December 15, 2016 HT66FB570 A/D Flash USB MCU RES Pin Reset Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. VDD VDD 1N4148* 10kΩ~ 100kΩ 0.01µF** 300Ω* RES 0.1µF~1µF VSS Note: * It is recommended that this component is added for added ESD protection. ** It is recommended that this component is added in environments where power line noise is significant. External RES Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point. 0.4VDD RES 0.9VDD tRSTD+tSST Inte�nal Reset Note: tRSTD is power-on delay, typical time=16.7ms RES Reset Timing Chart Rev. 1.10 79 December 15, 2016 HT66FB570 A/D Flash USB MCU Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provides an MCU reset should the value fall below a certain predefined level. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery in battery powered applications, the LVR will automatically reset the device internally and the LVRF bit in the RSTFC register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the LVR/LVD characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some different values by environmental noise, the LVR will reset the device after 2~3 fLIRC clock cycles. When this happens, the LRF bit in the RSTFC register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. LVR tRSTD + tSST Inte�nal Reset Note: tRSTD is power-on delay, typical time=50ms Low Voltage Reset Timing Chart • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0 Rev. 1.10 LVS7~LVS0: LVR Voltage Select control 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Any other value: Generates MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after 2~3 fLIRC clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 fLIRC clock cycles. However in this situation the register contents will be reset to the POR value. 80 December 15, 2016 HT66FB570 A/D Flash USB MCU • RSTFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — LVRF LRF WRF R/W — — — — — R/W R/W R/W POR — — — — — x 0 0 "x": unknown Bit 7~3 Unimplemented, read as "0" Bit 2 LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program. Bit 1 LRF: LVR control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the LVRC register contains any non-defined LVR voltage register values. This in effect acts like a software-reset function. This bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT control register software reset flag Describe elsewhere. Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to "1". WDT Ti�e-out tRSTD + tSST Inte�nal Reset Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details. WDT Ti�e-out tSST Inte�nal Reset WDT Time-out Reset during SLEEP or IDLE Timing Chart Rev. 1.10 81 December 15, 2016 HT66FB570 A/D Flash USB MCU Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset RESET Conditions u u RES, LVR or USB reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Register Power On Reset RES Reset (Normal) WDT Time-out (Normal) RES Reset (IDLE/SLEEP) WDT Time-out (IDLE/SLEEP) USB-reset (Normal) USB-reset (IDLE/SLEEP) IAR0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MP0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 IAR1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MP1L 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MP1H 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBHP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu STATUS x x 0 0 x x x x u u u u u u u u u u 0 1 u u u u x x 1 u u u u u u u 11 u u u u x x u u u u u u x x u u u u u u PBP - - - - IAR2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MP2L 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MP2H 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 RSTFC - - - - - - 0 0 - - - - - x 0 0 - - - - - - u u - - - - - u u u - - - - - - u u - - - - - u u u - - - - - - u u - - - - - u u u - - - - - - u u - - - - - u u u - - - - - - u u - - - - - u u u - - - - - - u u - u u u INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 INTC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 Rev. 1.10 82 December 15, 2016 HT66FB570 A/D Flash USB MCU Register Power On Reset RES Reset (Normal) WDT Time-out (Normal) RES Reset (IDLE/SLEEP) WDT Time-out (IDLE/SLEEP) USB-reset (Normal) USB-reset (IDLE/SLEEP) INTC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 INTC3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PAPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAWUEG0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAWUEG1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PBPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PBWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PCPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PCWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PE 1111 11-1 1111 11-1 1111 11-1 1111 11-1 uuuu uu-u 1111 11-1 1111 11-1 PEC 1111 11-1 1111 11-1 1111 11-1 1111 11-1 uuuu uu-u 1111 11-1 1111 11-1 PEPU 0000 00-0 0000 00-0 0000 00-0 0000 00-0 uuuu uu-u 0000 00-0 0000 00-0 PEWU 0000 00-0 0000 00-0 0000 00-0 0000 00-0 uuuu uu-u 0000 00-0 0000 00-0 SPIAC0 111- --00 111- --00 111- --00 111- --00 uuu- --uu 111- --00 111- --00 SPIAC1 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 SPIAD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx LVRC 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu 0101 0101 0101 0101 LVDC --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 USR 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 u u u u u u u u 0 0 0 0 1 0 11 0 0 0 0 1 0 11 UCR1 0000 00x0 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu 0000 00x0 0000 00x0 UCR2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TXR_RXR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx BRG xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx STMC0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- STMC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STMDL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STMDH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STMAL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STMAH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STMRP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM0C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- PTM0C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM0DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM0DH - - - - PTM0AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 Rev. 1.10 - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - 83 - - 0 0 - - - - - - u u - - - - - - 0 0 - - - - - - 0 0 December 15, 2016 HT66FB570 A/D Flash USB MCU Register Power On Reset RES Reset (Normal) - - 0 0 - - - - WDT Time-out (Normal) RES Reset (IDLE/SLEEP) - - - - 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u - - - - USB-reset (IDLE/SLEEP) PTM0AH - - 0 0 - - - - - - 0 0 - - - - USB-reset (Normal) PTM0RPL - - 0 0 - - - - - - 0 0 - - - - WDT Time-out (IDLE/SLEEP) - - u u - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 PTM0RPH - - - - EEA 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 - - 0 0 EED 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FARL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FD0L 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FD1L 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FD2L 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FD3L 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM2C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- PTM2C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM2DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM2DH - - - - PTM2AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM2AH - - - - PTM2RPL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM2RPH - - - - WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u u 0 1 0 1 0 0 11 0 1 0 1 0 0 11 SADOL x x x x (ADRFS=0) - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - - - x x x x - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - - - x x x x - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - - - x x x x - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - - - uuuu - - u u - - - - - - u u - - - - - - u u - - - - ---- x x x x - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - - - x x x x - - 0 0 - - 0 0 - - 0 0 - - - - SADOL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx (ADRFS=1) SADOH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx (ADRFS=0) SADOH - - - (ADRFS=1) x x x x - - - ---- 0000 x x x x - - - ---- 0000 x x x x - - - ---- 0000 x x x x ------- uuuu uuuu - - - ---- 0000 x x x x - - - ---- 0000 x x x x SADC0 0000 ---- SADC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SADC2 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu ---0 0000 ---0 0000 SCC 010- 0000 010- 0000 010- 0000 010- 0000 uuu- uuuu 010- 0000 010- 0000 HIRCC 000- --01 uuu- --01 uuu- --01 uuu- --01 uuu- --uu uuu- --01 uuu- --01 HXTC - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u u - - - - - 0 0 0 - - - - - 0 0 0 LXTC - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u u - - - - - 0 0 0 - - - - - 0 0 0 PLLC 0-00 0001 0-uu uu0u 0-uu uu0u 0-uu uu0u u-uu uuuu 0-uu uu0u 0-uu uu0u TB0C 0--- -000 0--- -000 0--- -000 0--- -000 u--- -uuu 0--- -000 0--- -000 TB1C 0--- -000 0--- -000 0--- -000 0--- -000 u--- -uuu 0--- -000 0--- -000 SYSC -000 --0x -000 --0x -000 --0x -000 --0x -uuu --ux -000 --0x -000 --0x USB_STAT 11 x x 0 0 0 - uuxx uuu- uuxx uuu- uuxx uuu- uuxx uuu- uuxx uuu- uuxx uuu- UINT 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USC 1000 xxxx uuuu xuux uuuu xuux uuuu xuux uuuu xuux uuuu 0100 uuuu 0100 UESR xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu UCC 0-0x 0xxx u-uu uuuu u-uu uuuu u-uu uuuu u-uu uuuu u-u0 u000 u-u0 u000 AWR xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 Rev. 1.10 84 December 15, 2016 HT66FB570 A/D Flash USB MCU Register Power On Reset RES Reset (Normal) WDT Time-out (Normal) RES Reset (IDLE/SLEEP) WDT Time-out (IDLE/SLEEP) USB-reset (Normal) USB-reset (IDLE/SLEEP) STLI xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 STLO xxxx xxx- uuuu uuu- uuuu uuu- uuuu uuu- uuuu uuu- 0000 000- 0000 000- SIES xxxx xxxx uxxx xuuu uxxx xuuu uxxx xuuu uxxx xuuu 0000 0000 0000 0000 MISC xxx0 -xxx xxuu -uxx xxuu -uxx xxuu -uxx xxuu -uxx 000u -000 000u -000 UFIEN 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu UFOEN 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu UFC0 0000 00-- uuuu uu-- uuuu uu-- uuuu uu-- uuuu uu-- uuuu uu-- uuuu uu-- UFC1 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu UFC2 ---- 0000 ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu FIFO0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu FIFO1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu FIFO2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu FIFO3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu FIFO4 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu FIFO5 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu FIFO6 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu FIFO7 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu SIMC0 111 - 0 0 0 0 111 - 0 0 0 0 111 - 0 0 0 0 111 - 0 0 0 0 uuu- uuuu 111 - 0 0 0 0 111 - 0 0 0 0 SIMC1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu 1000 0001 1000 0001 SIMD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx SIMA 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SIMC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SIMTOC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SLEWC0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SLEWC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SLEWC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SLEWC3 ---- MFI0 --00 0000 -----00 --00 --00 --00 --00 --00 --00 --uu --uu --00 --00 --00 --00 MFI1 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu --00 --00 --00 --00 MFI2 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu --00 --00 --00 --00 MFI3 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu --00 --00 --00 --00 MFI4 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MFI5 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu ---- uuuu ---- 0000 ---- 0000 ---- 0000 PMPS ---- DRVCC0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 DRVCC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 IFS --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 INTEG ---- PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PDPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 Rev. 1.10 85 December 15, 2016 HT66FB570 A/D Flash USB MCU Register Power On Reset RES Reset (Normal) WDT Time-out (Normal) RES Reset (IDLE/SLEEP) WDT Time-out (IDLE/SLEEP) USB-reset (Normal) USB-reset (IDLE/SLEEP) PDWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PF 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PFC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PFPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PFWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PG 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PGC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PGPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PGWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PBS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PBS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PCS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PCS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PDS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PDS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PES0 0000 --00 0000 --00 0000 --00 0000 --00 uuuu --uu 0000 --00 0000 --00 PES1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PFS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PFS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PGS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PGS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM1C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- PTM1C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM1DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM1DH - - - - PTM1AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - - - PTM1RPH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u - - - - - - 0 0 - - - - - - 0 0 EEC ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 FRCR 00-0 ---u 00-u - - 0 0 - - - - - - 0 0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 uu-u - - u u - - - - - - 0 0 - - - - PTM1AH ---0 00-u - - 0 0 - - - - - - u u - - - - PTM1RPL - - - 0 000-u ---0 0 0 - u - - 0 0 - - - - - - 0 0 - - - - ---0 00-u - - 0 0 ---0 FCR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FARH -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 FD0H 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FD1H 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FD2H 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FD3H 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM3C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- PTM3C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 Rev. 1.10 86 December 15, 2016 HT66FB570 A/D Flash USB MCU Register Power On Reset RES Reset (Normal) WDT Time-out (Normal) RES Reset (IDLE/SLEEP) WDT Time-out (IDLE/SLEEP) USB-reset (Normal) USB-reset (IDLE/SLEEP) PTM3DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM3DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u - - - - - - 0 0 - - - - - - 0 0 PTM3AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM3AH - - - - PTM3RPL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u - - - - - - u u - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 PTM3RPH - - - - PTM4C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- - - 0 0 PTM4C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM4DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PTM4DH - - - - PTM4AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 - - 0 0 - - - - CMP1C -000 PSCR - - - - - - 0 0 - - - ---1 -000 ---1 -000 - - 0 0 - - - - - - 0 0 - - - ---1 -000 ---1 -000 - - 0 0 - - - - - - 0 0 - - - ---1 -000 ---1 -000 - - 0 0 - - - - - - 0 0 - - - ---1 -uuu ---1 -uuu - - 0 0 - - - - - - u u - - - - - - 0 0 - - - - - - u u - - - ---u -000 ---u -000 - - u u - - - - - - 0 0 - - - - - - 0 0 - - - - - - - - - - 0 0 - - - - - - u u - - - - 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 -000 - - 0 0 - - - - - - 0 0 - - - - PTM4AH PTM4RPH - - 0 0 - - - - - - 0 0 - - - - PTM4RPL CMP0C - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - ---1 -000 ---1 -000 - - 0 0 - - - - - - 0 0 - - 0 0 ---1 ---1 - - 0 0 Note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PG. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Rev. 1.10 87 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit Register Name 7 6 5 4 3 2 1 0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWUEG0 PAWUEG07 PAWUEG06 PAWUEG05 PAWUEG04 PAWUEG03 PAWUEG02 PAWUEG01 PAWUEG00 PAWUEG1 PAWUEG17 PAWUEG16 PAWUEG15 PAWUEG14 PAWUEG13 PAWUEG12 PAWUEG11 PAWUEG10 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PBWU PBWU7 PBWU6 PBWU5 PBWU4 PBWU3 PBWU2 PBWU1 PBWU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PCWU PCWU7 PCWU6 PCWU5 PCWU4 PCWU3 PCWU2 PCWU1 PCWU0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PDWU PDWU7 PDWU6 PDWU5 PDWU4 PDWU3 PDWU2 PDWU1 PDWU0 PE PE7 PE6 PE5 PE4 PE3 PE2 — PE0 PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 — PEC0 PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 — PEPU0 PEWU PEWU7 PEWU6 PEWU5 PEWU4 PEWU3 PEWU2 — PEWU0 PF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PFC PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 PFPU PFPU7 PFPU6 PFPU5 PFPU4 PFPU3 PFPU2 PFPU1 PFPU0 PFWU PFWU7 PFWU6 PFWU5 PFWU4 PFWU3 PFWU2 PFWU1 PFWU0 PG PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PGC PGC7 PGC6 PGC5 PGC4 PGC3 PGC2 PGC1 PGC0 PGPU PGPU7 PGPU6 PGPU5 PGPU4 PGPU3 PGPU2 PGPU1 PGPU0 PGWU PGWU7 PGWU6 PGWU5 PGWU4 PGWU3 PGWU2 PGWU1 PGWU0 I/O Basic Function Registers List "—": Unimplemented, read as "0". PAn/PBn/PCn/PDn/PEn/PFn/PGn: I/O Port Data bit 0: Data 0 1: Data 1 PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn: I/O Port Input/Output control 0: Output 1: Input PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn: I/O Port Pull-high function control 0: Disable 1: Enable PAWUEG0n/PAWUEG1n: PA Port Wake-up edge control Described elsewhere. PBWUn/PCWUn/PDWUn/PEWUn/PFWUn/PGWUn: PB~PG Port Wake-up function control 0: Disable 1: Enable Rev. 1.10 88 December 15, 2016 HT66FB570 A/D Flash USB MCU Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers, namely PAPU~PGPU, and are implemented using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as an input or NMOS output. Otherwise, the pull-high resistors cannot be enabled. I/O Port Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port B ~ Port G pins from high to low, while from high to low or from low to high or both on one of the Port A pins. This function is especially suitable for applications that can be woken up via external switches. Each pin on PA~PG can be selected individually to have this wake-up feature using the PAWUEG0, PAWUEG1, PBWU~PGWU registers. Note that the wake-up function can be controlled by the wake-up control registers only when the pin-shared functional pin is selected as general purpose input/output and the MCU enters the Power down mode. Port A Wake-up Polarity Control Register The Port A can be setup to have a choice of wake-up polarity using specific registers. Each pin on Port A can be selected individually to have this Wake-up polarity feature using the PAWUEG0 or PAWUEG1 register. PAWUEG0 Register Bit 7 6 5 4 3 2 1 0 Name PAWUEG07 PAWUEG06 PAWUEG05 PAWUEG04 PAWUEG03 PAWUEG02 PAWUEG01 PAWUEG00 Rev. 1.10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PAWUEG07~PAWUEG06: PA3 wake-up edge control 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Rising and falling edges trigger Bit 5~4 PAWUEG05~PAWUEG04: PA2 wake-up edge control 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Rising and falling edges trigger Bit 3~2 PAWUEG03~PAWUEG02: PA1 wake-up edge control 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Rising and falling edges trigger Bit 1~0 PAWUEG01~PAWUEG00: PA0 wake-up edge control 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Rising and falling edges trigger 89 December 15, 2016 HT66FB570 A/D Flash USB MCU PAWUEG1 Register Bit Name 7 6 5 4 3 2 1 0 PAWUEG17 PAWUEG16 PAWUEG15 PAWUEG14 PAWUEG13 PAWUEG12 PAWUEG11 PAWUEG10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PAWUEG17~PAWUEG16: PA7 wake-up edge control 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Rising and falling edges trigger Bit 5~4 PAWUEG15~PAWUEG14: PA6 wake-up edge control 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Rising and falling edges trigger Bit 3~2 PAWUEG13~PAWUEG12: PA5 wake-up edge control 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Rising and falling edges trigger Bit 1~0 PAWUEG11~PAWUEG10: PA4 wake-up edge control 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Rising and falling edges trigger I/O Port Control Registers Each I/O port has its own control register known as PAC~PGC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Port A Power Source Control Register The Port A can be setup to have a choice of various power source using specific register. The Port A must be selected by nibble pins to have various power sources using the PMPS register. PMPS Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — — — PMPS3 PMPS2 PMPS1 PMPS0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~2 PMPS3~PMPS2: PA7~PA4 power supply selection 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output 90 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 1~0 PMPS1~PMPS0: PA3~PA0 power supply selection 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output I/O Port Output Slew Rate Control Registers The I/O ports, PA~PG, can be setup to have a choice of various slew rate using specific registers. The PA~PG must be selected by nibble pins to have various slew rate using the SLEWC0~SLEWC3 registers. Refer to the D.C. Characteristics section to obtain the exact value. Bit Register Name 7 6 5 4 3 2 1 0 SLEWC0 SLEWC07 SLEWC06 SLEWC05 SLEWC04 SLEWC03 SLEWC02 SLEWC01 SLEWC00 SLEWC1 SLEWC17 SLEWC16 SLEWC15 SLEWC14 SLEWC13 SLEWC12 SLEWC11 SLEWC10 SLEWC2 SLEWC27 SLEWC26 SLEWC25 SLEWC24 SLEWC23 SLEWC22 SLEWC21 SLEWC20 SLEWC3 — — — — SLEWC33 SLEWC32 SLEWC31 SLEWC30 1 0 Output Slew Rate Control Registers List SLEWC0 Register Bit 7 6 5 4 3 2 Name SLEWC07 SLEWC06 SLEWC05 SLEWC04 SLEWC03 SLEWC02 SLEWC01 SLEWC00 Rev. 1.10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 SLEWC07~SLEWC06: PB7~PB4 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 Bit 5~4 SLEWC05~SLEWC04: PB3~PB0 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 Bit 3~2 SLEWC03~SLEWC02: PA7~PA4 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 Bit 1~0 SLEWC01~SLEWC00: PA3~PA0 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 Note: Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. 91 December 15, 2016 HT66FB570 A/D Flash USB MCU SLEWC1 Register Bit 7 6 5 4 3 2 1 0 Name SLEWC17 SLEWC16 SLEWC15 SLEWC14 SLEWC13 SLEWC12 SLEWC11 SLEWC10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 SLEWC17~SLEWC16: PD7~PD4 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 SLEWC15~SLEWC14: PD3~PD0 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 SLEWC13~SLEWC12: PC7~PC4 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 SLEWC11~SLEWC10: PC3~PC0 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 Note: Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. SLEWC2 Register Bit 7 6 5 4 3 2 1 0 Name SLEWC27 SLEWC26 SLEWC25 SLEWC24 SLEWC23 SLEWC22 SLEWC21 SLEWC20 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 Rev. 1.10 SLEWC27~SLEWC26: PF7~PF4 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 SLEWC25~SLEWC24: PF3~PF0 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 SLEWC23~SLEWC22: PE7~PE4 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 SLEWC21~SLEWC20: PE3, PE2, PE0 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 Note: Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. 92 December 15, 2016 HT66FB570 A/D Flash USB MCU SLEWC3 Register Bit 7 6 5 4 Name — — — — 3 2 1 0 SLEWC33 SLEWC32 SLEWC31 SLEWC30 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~2 SLEWC33~SLEWC32: PG7~PG4 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 Bit 1~0 SLEWC31~SLEWC30: PG3~PG0 output slew rate selection 00: Slew rate=Level 0 01: Slew rate=Level 1 10: Slew rate=Level 2 11: Slew rate=Level 3 Note: Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. I/O Port Output Current Control Registers The I/O ports, PA~PG, can be setup to have a choice of high or low drive currents using specific registers. The PA~PG must be selected by nibble pins to have various output current using the DRVCC0 and DRVCC1 registers. Refer to the D.C. Characteristics section to obtain the exact value. Bit Register Name 7 6 5 4 3 2 1 0 DRVCC0 DRVCC07 DRVCC06 DRVCC05 DRVCC04 DRVCC03 DRVCC02 DRVCC01 DRVCC00 DRVCC1 D7 D6 DRVCC15 DRVCC14 DRVCC13 DRVCC12 DRVCC11 DRVCC10 Output Current Control Registers List DRVCC0 Register Bit 7 6 5 4 3 2 1 0 Name DRVCC07 DRVCC06 DRVCC05 DRVCC04 DRVCC03 DRVCC02 DRVCC01 DRVCC00 Rev. 1.10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 DRVCC07: PD7~PD4 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 6 DRVCC06: PD3~PD0 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 5 DRVCC05: PC7~PC4 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 4 DRVCC04: PC3~PC0 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 3 DRVCC03: PB7~PB4 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) 93 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 2 DRVCC02: PB3~PB0 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 1 DRVCC01: PA7~PA4 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 0 DRVCC00: PA3~PA0 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Note: Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. DRVCC1 Register Rev. 1.10 Bit 7 6 Name D7 D6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 DRVCC15 DRVCC14 DRVCC13 DRVCC12 DRVCC11 DRVCC10 Bit 7~6 D7~D6: Reserved bits, can be read and written Bit 5 DRVCC15: PG7~PG4 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 4 DRVCC14: PG3~PG0 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 3 DRVCC13: PF7~PF4 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 2 DRVCC12: PF3~PF0 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 1 DRVCC11: PE7~PE4 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Bit 0 DRVCC10: PE3, PE2, PE0 source & sink current selection 0: Source & Sink current=Level 0 (Min.) 1: Source & Sink current=Level 1 (Max.) Note: Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. 94 December 15, 2016 HT66FB570 A/D Flash USB MCU Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the desired function of the multi-function I/O pins is selected by a series of registers via the application program control. Pin-shared Function Selection Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. The device includes Port "x" Output Function Selection register "n", labeled as PxSn, and Input Function Selection register, labeled as IFS, which can select the desired functions of the multi-function pin-shared pins. The most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. To select the desired pin-shared function, the pin-shared function should first be correctly selected using the corresponding pin-shared control register. After that the corresponding peripheral functional setting should be configured and then the peripheral function can be enabled. To correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modified to select other pin-shared functions. Register Name Bit 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 PBS0 PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PBS1 PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PCS1 PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 PDS0 PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 PDS1 PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PES0 PES07 PES06 PES05 PES04 — — PES01 PES00 PES1 PES17 PES16 PES15 PES14 PES13 PES12 PES11 PES10 PFS0 PFS07 PFS06 PFS05 PFS04 PFS03 PFS02 PFS01 PFS00 PFS1 PFS17 PFS16 PFS15 PFS14 PFS13 PFS12 PFS11 PFS10 PGS0 PGS07 PGS06 PGS05 PGS04 PGS03 PGS02 PGS01 PGS00 PGS1 PGS17 PGS16 PGS15 PGS14 PGS13 PGS12 PGS11 IFS — — PTP4IPS PTP3IPS PTP2IPS PTP1IPS PTP0IPS PGS10 STPIPS Pin-shared Function Selection Registers List Rev. 1.10 95 December 15, 2016 HT66FB570 A/D Flash USB MCU • PAS0 Register Bit 7 6 5 4 3 2 1 0 Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PAS07~PAS06: PA3 Pin-Shared function selection 00/01: PA3 10: SCKA 11: C0- Bit 5~4 PAS05~PAS04: PA2 Pin-Shared function selection 00/01: PA2 10: SDIA 11: C0+ Bit 3~2 PAS03~PAS02: PA1 Pin-Shared function selection 00/01: PA1 10: SDOA 11: C0X Bit 1~0 PAS01~PAS00: PA0 Pin-Shared function selection 00/01/10/11: PA0/PTCK0 • PAS1 Register Bit 7 6 5 4 3 2 1 0 Name PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PAS17~PAS16: PA7 Pin-Shared function selection 00/01/10: PA7/INT0 11: AN7 Bit 5~4 PAS15~PAS14: PA6 Pin-Shared function selection 00/01/10: PA6/STCK 11: C1- Bit 3~2 PAS13~PAS12: PA5 Pin-Shared function selection 00/01: PA5/PTP0I 10: PTP0 11: C1+ Bit 1~0 PAS11~PAS10: PA4 Pin-Shared function selection 00: PA4/STPI 01: SCSA 10: STP 11: C1X • PBS0 Register Bit 7 6 5 4 3 2 1 0 Name PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Rev. 1.10 PBS07~PBS06: PB3 Pin-Shared function selection 00/01: PB3 10: SCS 11: AN3 96 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 5~4 PBS05~PBS04: PB2 Pin-Shared function selection 00/01: PB2 10: SCK 11: AN2 Bit 3~2 PBS03~PBS02: PB1 Pin-Shared function selection 00/01: PB1 10: SDI/SCL 11: AN1 Bit 1~0 PBS01~PBS00: PB0 Pin-Shared function selection 00/01: PB0 10: SDO/SDA 11: AN0 • PBS1 Register Bit 7 6 5 4 3 2 1 0 Name PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PBS17~PBS16: PB7 Pin-Shared function selection 00/01: PB7/PTP4I 10: PTP4 11: AN18 Bit 5~4 PBS15~PBS14: PB6 Pin-Shared function selection 00/01/10: PB6/INT1 11: AN6 Bit 3~2 PBS13~PBS12: PB5 Pin-Shared function selection 00/01/10: PB5 11: AN5 Bit 1~0 PBS11~PBS10: PB4 Pin-Shared function selection 00/01: PB4/STPI 10: STP 11: AN4 • PCS0 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PCS07~PCS06: PC3 Pin-Shared function selection 00/01/10: PC3 11:AN11 Bit 5~4 PCS05~PCS04: PC2 Pin-Shared function selection 00/01/10: PC2 11: AN10 Bit 3~2 PCS03~PCS02: PC1 Pin-Shared function selection 00/01/10: PC1/PTCK4 11: AN9 Bit 1~0 PCS01~PCS00: PC0 Pin-Shared function selection 00/01: PC0/PTP4I 10: PTP4 11: AN8 97 December 15, 2016 HT66FB570 A/D Flash USB MCU • PCS1 Register Bit 7 6 5 4 3 2 1 0 Name PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PCS17~PCS16: PC7 Pin-Shared function selection 00/01/10: PC7 11: AN15 Bit 5~4 PCS15~PCS14: PC6 Pin-Shared function selection 00/01/10: PC6 11: AN14 Bit 3~2 PCS13~PCS12: PC5 Pin-Shared function selection 00/01: PC5 10: RX 11: AN13 Bit 1~0 PCS11~PCS10: PC4 Pin-Shared function selection 00/01: PC4 10: TX 11: AN12 • PDS0 Register Bit 7 6 5 4 3 2 1 0 Name PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 PDS07~PDS06: PD3 Pin-Shared function selection 00/01/10/11: PD3/PTCK3 PDS05~PDS04: PD2 Pin-Shared function selection 00/01/10/11: PD2/PTCK1 PDS03~PDS02: PD1 Pin-Shared function selection 00/01: PD1/PTP1I 10: PTP1 11: OSC2 PDS01~PDS00: PD0 Pin-Shared function selection 00/01: PD0/PTP2I 10: PTP2 11: OSC1 • PDS1 Register Bit 7 6 5 4 3 2 1 0 Name PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 Rev. 1.10 PDS17~PDS16: PD7 Pin-Shared function selection 00/01/10: PD7/PTP1I 11: PTP1 PDS15~PDS14: PD6 Pin-Shared function selection 00/01/10: PD6/PTP2I 11: PTP2 PDS13~PDS12: PD5 Pin-Shared function selection 00/01/10: PD5/PTP0I 11: PTP0 PDS11~PDS10: PD4 Pin-Shared function selection 00/01/10/11: PD4/ PTCK2 98 December 15, 2016 HT66FB570 A/D Flash USB MCU • PES0 Register Bit 7 6 5 4 3 2 1 0 Name PES07 PES06 PES05 PES04 — — PES01 PES00 R/W R/W R/W R/W R/W — — R/W R/W POR 0 0 0 0 — — 0 0 Bit 7~6 PES07~PES06: PE3 Pin-Shared function selection 00/01/10: PE3 11: XT1 Bit 5~4 PES05~PES04: PE2 Pin-Shared function selection 00/01/10: PE2 11: AN17 Bit 3~2 Unimplemented, read as "0" Bit 1~0 PES01~PES00: PE0 Pin-Shared function selection 00/01: PE0 10: VDDIO 11: VREF • PES1 Register Bit 7 6 5 4 3 2 1 0 Name PES17 PES16 PES15 PES14 PES13 PES12 PES11 PES10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PES17~PES16: PE7 Pin-Shared function selection 00/01/10/11: PE7 Bit 5~4 PES15~PES14: PE6 Pin-Shared function selection 00/01/10/11: PE6 Bit 3~2 PES13~PES12: PE5 Pin-Shared function selection 00/01/10: PE5 11: AN16 Bit 1~0 PES11~PES10: PE4 Pin-Shared function selection 00/01/10: PE4 11: XT2 • PFS0 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name PFS07 PFS06 PFS05 PFS04 PFS03 PFS02 PFS01 PFS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PFS07~PFS06: PF3 Pin-Shared function selection 00/01/10/11: PF3 Bit 5~4 PFS05~PFS04: PF2 Pin-Shared function selection 00/01/10/11: PF2 Bit 3~2 PFS03~PFS02: PF1 Pin-Shared function selection 00/01/10: PF1/PTP3I 11: PTP3 Bit 1~0 PFS01~PFS00: PF0 Pin-Shared function selection 00/01/10: PF0/PTP3I 11: PTP3 99 December 15, 2016 HT66FB570 A/D Flash USB MCU • PFS1 Register Bit 7 6 5 4 3 2 1 0 Name PFS17 PFS16 PFS15 PFS14 PFS13 PFS12 PFS11 PFS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PFS17~PFS16: PF7 Pin-Shared function selection 00/01/10/11: PF7 Bit 5~4 PFS15~PFS14: PF6 Pin-Shared function selection 00/01/10/11: PF6 Bit 3~2 PFS13~PFS12: PF5 Pin-Shared function selection 00/01/10/11: PF5 Bit 1~0 PFS11~PFS10: PF4 Pin-Shared function selection 00/01/10/11: PF4 • PGS0 Register Bit 7 6 5 4 3 2 1 0 Name PGS07 PGS06 PGS05 PGS04 PGS03 PGS02 PGS01 PGS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PGS07~PGS06: PG3 Pin-Shared function selection 00/01/10: PG3 11: AN23 Bit 5~4 PGS05~PGS04: PG2 Pin-Shared function selection 00/01/10/11: PG2 Bit 3~2 PGS03~PGS02: PG1 Pin-Shared function selection 00/01/10/11: PG1 Bit 1~0 PGS01~PGS00: PG0 Pin-Shared function selection 00/01/10/11: PG0 • PGS1 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name PGS17 PGS16 PGS15 PGS14 PGS13 PGS12 PGS11 PGS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PGS17~PGS16: PG7 Pin-Shared function selection 00/01/10: PG7 11: AN19 Bit 5~4 PGS15~PGS14: PG6 Pin-Shared function selection 00/01/10: PG6 11: AN20 Bit 3~2 PGS13~PGS12: PG5 Pin-Shared function selection 00/01/10: PG5 11: AN21 Bit 1~0 PGS11~PGS10: PG4 Pin-Shared function selection 00/01/10: PG4 11: AN22 100 December 15, 2016 HT66FB570 A/D Flash USB MCU • IFS Register Bit 7 6 Name — — 5 4 3 2 1 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 PTP4IPS PTP3IPS PTP2IPS PTP1IPS PTP0IPS Bit 7~6 Unimplemented, read as "0" Bit 5 PTP4IPS: PTP4I input source pin selection 0: PB7 1: PC0 Bit 4 PTP3IPS: PTP3I input source pin selection 0: PF0 1: PF1 Bit 3 PTP2IPS: PTP2I input source pin selection 0: PD6 1: PD0 Bit 2 PTP1IPS: PTP1I input source pin selection 0: PD7 1: PD1 Bit 1 PTP0IPS: PTP0I input source pin selection 0: PA5 1: PD5 Bit 0 STPIPS: STPI input source pin selection 0: PA4 1: PB4 0 STPIPS I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. VDD Cont�ol Bit Data Bus W�ite Cont�ol Registe� Chip Reset Read Cont�ol Registe� D Weak Pull-up CK Q S I/O pin Data Bit D W�ite Data Registe� Q Pull-high Registe� Sele�t Q CK Q S Read Data Registe� Syste� Wake-up M U X wake-up Sele�t Generic Input/Output Structure Rev. 1.10 101 December 15, 2016 HT66FB570 A/D Flash USB MCU VDD Cont�ol Bit Data Bus D W�ite Cont�ol Registe� Weak Pull-up CK Q S Chip Reset Read Cont�ol Registe� Q Pull-high Registe� Sele�t A/D Input Po�t Data Bit D W�ite Data Registe� Q CK Q S Read Data Registe� M U X Analog Input Sele�to� To A/D Conve�te� SACS4~SACS0 A/D Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pullhigh selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. All Ports have the additional capability of providing wake-up function. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is any edge transitions on the PA pins or a high to low transition on the PB~PG pins. Single or multiple pins on Ports can be setup to have this function. Rev. 1.10 102 December 15, 2016 HT66FB570 A/D Flash USB MCU Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Standard and Periodic TM sections. Introduction The device contains six TMs and each individual TM can be categorised as a certain type, namely Standard Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Standard and Periodic TMs will be described in this section. The detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the two types of TMs are summarised in the accompanying table. STM PTM Timer/Counter Function √ √ Input Capture √ √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output 1 1 Edge Edge Duty or Period Duty or Period PWM Alignment PWM Adjustment Period & Duty TM Function Summary TM Operation The different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTM control registers, where "x" stands for S or P type TM and "n" stands for the specific TM serial number. For STM there is no serial number "n" in the relevant pin or control bits since there is only one STM in the device. The clock source can be a ratio of the system clock fSYS or the internal high clock fH, the fSUB clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. Rev. 1.10 103 December 15, 2016 HT66FB570 A/D Flash USB MCU TM Interrupts The Standard and Periodic type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has two TM input pins, with the label xTCKn and xTPnI respectively. The xTMn input pin, xTCKn, is essentially a clock source for the xTMn and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. The xTCKn input pin can be chosen to have either a rising or falling active edge. The xTCKn pin is also used as the external trigger input pin in single pulse output mode. The other xTMn input pin, xTPnI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the xTnIO1~xTnIO0 bits in the xTMnC1 register. There is another capture input, PTCKn, for PTMn capture input mode, which can be used as the external trigger input source except the PTPnI pin. The TMs each have one output pin with the label xTPn. The TM output pins can be selected using the corresponding pin-shared function selection bits described in the Pin-shared Function section. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other functions, the TM output function must first be setup using relevant pin-shared function selection register. Note that for STM there is no serial number "n" in the relevant pin or control bits. STM Input STCK, STPI PTM Output Input Output STP PTCK0, PTP0I; PTCK1, PTP1I; PTCK2, PTP2I; PTCK3, PTP3I; PTCK4, PTP4I PTP0; PTP1; PTP2; PTP3; PTP4 TM External Pins Rev. 1.10 104 December 15, 2016 HT66FB570 A/D Flash USB MCU TM Input/Output Pin Selection Selecting to have a TM input/output or whether to retain its other shared function is implemented using the relevant pin-shared function selection registers, with the corresponding selection bits in each pin-shared function register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. STCK CCR �aptu�e input STPI STM CCR output STP STM Function Pin Control Block Diagram PTCKn CCR �aptu�e input PTPnI PTMn CCR output PTPn PTM Function Pin Control Block Diagram (n=0~4) Rev. 1.10 105 December 15, 2016 HT66FB570 A/D Flash USB MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PTMnRPL, using the following access procedures. Accessing the CCRA or CCRP low byte registers without following these access procedures will result in unpredictable values. xTMn Counte� Registe� (Read only) xTMnDL xTMnDH 8-�it Buffe� xTMnAL xTMnAH xTMn CCRA Registe� (Read/W�ite) PTMnRPL PTMnRPH PTMn CCRP Registe� (Read/W�ite) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA ♦♦ Step 1. Write data to Low Byte xTMnAL or PTMnRPL ––Note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte xTMnAH or PTMnRPH ––Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and or CCRA Rev. 1.10 ♦♦ Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMnRPH ––Here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMnRPL ––This step reads data from the 8-bit buffer. 106 December 15, 2016 HT66FB570 A/D Flash USB MCU Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with two external input pins and can drive an external output pin. CCRP 8-�it Co�pa�ato� P fSYS/4 000 fSYS 001 fH/1� 010 fH/�4 011 fSUB 100 fSUB 101 110 STCK Co�pa�ato� P Mat�h STMPF Inte��upt STOC �8~�1� 1�-�it Count-up Counte� STON STPAU 1�-�it Co�pa�ato� A 0 1 STCCLR �0~�1� 111 STCK�~STCK0 Counte� Clea� Co�pa�ato� A Mat�h CCRA Output Cont�ol Pola�ity Cont�ol Pin Cont�ol STM1� STM0 STIO1� STIO0 STPOL PxSn STP STMAF Inte��upt STIO1� STIO0 PxSn IFS Edge Dete�to� Pin Cont�ol STPI Standard Type TM Block Diagram Standard TM Operation The size of Standard TM is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared the with highest 8 bits in the counter while the CCRA is the sixteen bits and therefore compares all counter bits. The only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the STON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a STM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.10 107 December 15, 2016 HT66FB570 A/D Flash USB MCU Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The STMRP register is used to store the 8-bit CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 1 0 STMC0 STPAU STCK2 STCK1 STCK0 STON — — — STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR STMDL D7 D6 D5 D4 D3 D2 D1 D0 STMDH D15 D14 D13 D12 D11 D10 D9 D8 STMAL D7 D6 D5 D4 D3 D2 D1 D0 STMAH D15 D14 D13 D12 D11 D10 D9 D8 STMRP D7 D6 D5 D4 D3 D2 D1 D0 16-bit Standard TM Registers List STMC0 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name STPAU STCK2 STCK1 STCK0 STON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 STPAU: STM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the STM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 STCK2~STCK0: Select STM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: STCK rising edge clock 111: STCK falling edge clock These three bits are used to select the clock source for the STM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. 108 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 3 STON: STM Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the STM. Setting the bit high enables the counter to run while clearing the bit disables the STM. Clearing this bit to zero will stop the counter from counting and turn off the STM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the STM is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode then the STM output pin will be reset to its initial condition, as specified by the STOC bit, when the STON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" STMC1 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 STM1~STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the STM. To ensure reliable operation the STM should be switched off before any changes are made to the STM1 and STM0 bits. In the Timer/Counter Mode, the STM output pin control will be disabled. Bit 5~4 STIO1~STIO0: Select STM external pin (STP or STPI) function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of STPI 01: Input capture at falling edge of STPI 10: Input capture at rising/falling edge of STPI 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the STM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the STM is running. 109 December 15, 2016 HT66FB570 A/D Flash USB MCU In the Compare Match Output Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the STM output pin should be setup using the STOC bit in the STMC1 register. Note that the output level requested by the STIO1 and STIO0 bits must be different from the initial value setup using the STOC bit otherwise no change will occur on the STM output pin when a compare match occurs. After the STM output pin changes state, it can be reset to its initial level by changing the level of the STON bit from low to high. In the PWM Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the STIO1 and STIO0 bits only after the STM has been switched off. Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed when the STM is running. Rev. 1.10 Bit 3 STOC: STM STP Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STM output pin. Its operation depends upon whether STM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the STM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the STM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. In the Single Pulse Output Mode it determines the logic level of the STM output pin when the STON bit changes from low to high. Bit 2 STPOL: STM STP Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the STP output pin. When the bit is set high the STM output pin will be inverted and not inverted when the bit is zero. It has no effect if the STM is in the Timer/Counter Mode. Bit 1 STDPX: STM PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 STCCLR: STM Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the STCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. 110 December 15, 2016 HT66FB570 A/D Flash USB MCU STMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: STM Counter Low Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 7 ~ bit 0 STMDH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 D15~D8: STM Counter High Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 15 ~ bit 8 STMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: STM CCRA Low Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 7 ~ bit 0 STMAH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D15~D8: STM CCRA High Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 15 ~ bit 8 STMRP Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 STRP7~STRP0: STM CCRP 8-bit register, compared with the STM counter bit 15~bit 8 Comparator P Match Period = 0: 65536 STM clocks 1~255: (1~255) x 256 STM clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the STCCLR bit is set to zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. 111 December 15, 2016 HT66FB570 A/D Flash USB MCU Standard Type TM Operation Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register. Compare Match Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the STM output pin, will change state. The STM output pin condition however only changes state when a STMAF interrupt request flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the STM output pin. The way in which the STM output pin changes state are determined by the condition of the STIO1 and STIO0 bits in the STMC1 register. The STM output pin can be selected using the STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the STM output pin, which is setup after the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and STIO0 bits are zero then no pin change will take place. Rev. 1.10 112 December 15, 2016 HT66FB570 A/D Flash USB MCU Counte� ove�flow Counter Value 0xFFFF STCCLR = 0; STM [1:0] = 00 CCRP > 0 Counte� �lea�ed �y CCRP value CCRP=0 CCRP > 0 Counte� Resta�t Resu�e CCRP Pause CCRA Stop Time STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin Output pin set to initial Level Low if STOC=0 Output not affe�ted �y STMAF flag. Re�ains High until �eset �y STON �it Output Toggle with STMAF flag He�e STIO [1:0] = 11 Toggle Output sele�t Note STIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when STPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – STCCLR=0 Note: 1. With STCCLR=0 a Comparator P match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to itsinitial state by a STON bit rising edge Rev. 1.10 113 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value STCCLR = 1; STM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0xFFFF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Time STON STPAU STPOL No STMAF flag gene�ated on CCRA ove�flow CCRA Int. flag STMAF CCRP Int. flag STMPF STMPF not gene�ated Output does not �hange STM O/P Pin Output pin set to initial Level Low if STOC=0 Output Toggle with STMAF flag He�e STIO [1:0] = 11 Toggle Output sele�t Output not affe�ted �y STMAF flag. Re�ains High until �eset �y STON �it Note STIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when STPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – STCCLR=1 Note: 1. With STCCLR=1 a Comparator A match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to its initial state by a STON bit rising edge 4. A STMPF flag is not generated when STCCLR=1 Rev. 1.10 114 December 15, 2016 HT66FB570 A/D Flash USB MCU Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the STM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within the STM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the STCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The STOC bit in the STMC1 register is used to select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to enable the PWM output or to force the STM output pin to a fixed high or low level. The STPOL bit is used to reverse the polarity of the PWM output waveform. • 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=0 CCRP 1~255 0 Period CCRP×256 65536 Duty CCRA If fSYS=16MHz, STM clock source is fSYS/4, CCRP=2 and CCRA=128, The STM PWM output frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz, duty=128/(2×256)= 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=1 CCRP 1~255 Period 0 CCRA CCRP×256 Duty 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is equal to 0. Rev. 1.10 115 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value STDPX = 0; STM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when STON �etu�ns high CCRP Pause Resu�e Counte� Stop if STON �it low CCRA Time STON STPAU STPOL CCRA Int. flag STMAF CCRP Int. flag STMPF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cy�le set �y CCRA PWM Pe�iod set �y CCRP PWM �esu�es ope�ation Output �ont�olled �y othe� pinOutput Inve�ts sha�ed fun�tion when STPOL = 1 PWM Output Mode – STDPX=0 Note: 1. Here STDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when STIO [1:0]=00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.10 116 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value STDPX = 1; STM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when STON �etu�ns high CCRA Pause Resu�e Counte� Stop if STON �it low CCRP Time STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cy�le set �y CCRP PWM Pe�iod set �y CCRA PWM �esu�es ope�ation Output �ont�olled �y othe� Output Inve�ts pin-sha�ed fun�tion when STPOL = 1 PWM Output Mode – STDPX=1 Note: 1. Here STDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when STIO [1:0]=00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.10 117 December 15, 2016 HT66FB570 A/D Flash USB MCU Single Pulse Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can be implemented using the application program. However in the Single Pulse Mode, the STON bit can also be made to automatically change from low to high using the external STCK pin, which will in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter can only be reset back to zero when the STON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. S/W Co��and SET“STON” o� STCK Pin T�ansition CCRA Leading Edge CCRA T�ailing Edge STON �it 0 1 STON �it 1 0 S/W Co��and CLR“STON” o� CCRA Co�pa�e Mat�h STP Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.10 118 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value STM [1:0] = 10 ; STIO [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when STON �etu�ns high CCRA Pause Counte� Stops �y softwa�e Resu�e CCRP Time STON Softwa�e T�igge� Auto. set �y STCK pin Clea�ed �y CCRA �at�h Softwa�e T�igge� STCK pin Softwa�e T�igge� Softwa�e Clea� Softwa�e T�igge� STCK pin T�igge� STPAU STPOL No CCRP Inte��upts gene�ated CCRP Int. Flag STMPF CCRA Int. Flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) Output Inve�ts when STPOL = 1 Pulse Width set �y CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the STCK pin or by setting the STON bit high 4. A STCK pin active edge will automatically set the STON bit high. 5. In the Single Pulse Mode, STIO [1:0] must be set to "11" and can not be changed. Rev. 1.10 119 December 15, 2016 HT66FB570 A/D Flash USB MCU Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STPI pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register. The counter is started when the STON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STPI pin the present value in the counter will be latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on the STPI pin the counter will continue to free run until the STON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STPI pin to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STPI pin, however it must be noted that the counter will continue to run. The STCCLR and STDPX bits are not used in this Mode. Rev. 1.10 120 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value STM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Stop Counte� Reset CCRP Resu�e YY Pause XX Time STON STPAU A�tive edge A�tive edge A�tive edge STM Captu�e Pin STPI CCRA Int. Flag STMAF CCRP Int. Flag STMPF XX CCRA Value STIO [1:0] Value 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disa�le Captu�e Capture Input Mode Note: 1. STM [1:0]=01 and active edge set by the STIO [1:0] bits 2. A STM Capture input pin active edge transfers the counter value to CCRA 3. STCCLR bit not used 4. No output function -- STOC and STPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.10 121 December 15, 2016 HT66FB570 A/D Flash USB MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can be controlled with two external input pins and can drive an external output pins. CCRP 10-�it Co�pa�ato� P fSYS/4 000 fSYS fH/1� fH/�4 fSUB 001 fSUB 101 PTMnPF Inte��upt PTnOC �0~�9 010 011 10-�it Count-up Counte� 100 110 PTCKn Co�pa�ato� P Mat�h PTnON PTnPAU Counte� Clea� PTnCCLR �0~�9 111 PTnCK�~PTnCK0 10-�it Co�pa�ato� A Output Cont�ol Pola�ity Cont�ol Pin Cont�ol PTnM1� PTnM0 PTnIO1� PTnIO0 PTnPOL PxSn 0 1 Co�pa�ato� A Mat�h PTMnAF Inte��upt PxSn IFS PTnIO1� PTnIO0 PTnCAPTS Edge Dete�to� 0 CCRA PTPn Pin Cont�ol 1 PTPnI Periodic Type TM Block Diagram (n=0~4) Periodic TM Operation The Periodic Type TM core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 10-bit wide. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the PTnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a PTMn interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control more than one output pin. All operating setup conditions are selected using relevant internal registers. Periodic Type TM Register Description Overall operation of the Periodic Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA value and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name Bit 7 6 5 4 3 2 1 0 PTMnC0 PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — PTMnC1 PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTMnDL D7 D6 D5 D4 D3 D2 D1 D0 PTMnDH — — — — — — D9 D8 PTMnAL D7 D6 D5 D4 D3 D2 D1 D0 PTnPOL PTnCAPTS PTnCCLR PTMnAH — — — — — — D9 D8 PTMnRPL D7 D6 D5 D4 D3 D2 D1 D0 PTMnRPH — — — — — — D9 D8 10-bit Periodic TM Registers List (n=0~4) Rev. 1.10 122 December 15, 2016 HT66FB570 A/D Flash USB MCU PTMnC0 Register Bit 7 6 5 4 3 2 1 0 Name PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 PTnPAU: PTMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 PTnCK2~PTnCK0: Select PTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCKn rising edge clock 111: PTCKn falling edge clock These three bits are used to select the clock source for the PTMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3 PTnON: PTMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the PTMn. Setting the bit high enables the counter to run, clearing the bit disables the PTMn. Clearing this bit to zero will stop the counter from counting and turn off the PTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTMn is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode then the PTMn output pin will be reset to its initial condition, as specified by the PTnOC bit, when the PTnON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" PTMnC1 Register Bit 7 6 5 4 3 Name PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Rev. 1.10 2 1 0 PTnPOL PTnCAPTS PTnCCLR PTnM1~PTnM0: Select PTMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTMn. To ensure reliable operation the PTMn should be switched off before any changes are made to the PTnM1 and PTnM0 bits. In the Timer/Counter Mode, the PTMn output pin control must be disabled. 123 December 15, 2016 HT66FB570 A/D Flash USB MCU Rev. 1.10 Bit 5~4 PTnIO1~PTnIO0: Select PTMn external pin (PTPn, PTPnI or PTCKn) function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of PTPnI or PTCKn 01: Input capture at falling edge of PTPnI or PTCKn 10: Input capture at falling/rising edge of PTPnI or PTCKn 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTMn is running. In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a compare match occurs from the Comparator A. The PTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTMn output pin should be setup using the PTnOC bit in the PTMnC1 register. Note that the output level requested by the PTnIO1 and PTnIO0 bits must be different from the initial value setup using the PTnOC bit otherwise no change will occur on the PTMn output pin when a compare match occurs. After the PTMn output pin changes state, it can be reset to its initial level by changing the level of the PTnON bit from low to high. In the PWM Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the PTnIO1 and PTnIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the PTnIO1 and PTnIO0 bits are changed when the PTMn is running. Bit 3 PTnOC: PTMn PTPn Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTMn output pin. Its operation depends upon whether PTMn is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the PTMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. In the Single Pulse Output Mode it determines the logic level of the PTMn output pin when the PTnON bit changes from low to high. 124 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 2 PTnPOL: PTMn PTPn Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the PTPn output pin. When the bit is set high the PTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTMn is in the Timer/Counter Mode. Bit 1 PTnCAPTS: PTMn Capture Trigger Source Selection 0: From PTPnI pin 1: From PTCKn pin Bit 0 PTnCCLR: Select PTMn Counter clear condition 0: PTMn Comparator P match 1: PTMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTnCCLR bit is not used in the PWM Mode, Single Pulse or Capture Input Mode. PTMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: PTMn Counter Low Byte Register bit 7 ~ bit 0 PTMn 10-bit Counter bit 7 ~ bit 0 PTMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 D9~D8: PTMn Counter High Byte Register bit 1 ~ bit 0 PTMn 10-bit Counter bit 9 ~ bit 8 PTMnAL Register Bit 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 7 D7~D0: PTMn CCRA Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRA bit 7 ~ bit 0 125 December 15, 2016 HT66FB570 A/D Flash USB MCU PTMnAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 D9~D8: PTMn CCRA High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRA bit 9 ~ bit 8 PTMnRPL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: PTMn CCRP Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRP bit 7 ~ bit 0 PTMnRPH Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 D9~D8: PTMn CCRP High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRP bit 9 ~ bit 8 126 December 15, 2016 HT66FB570 A/D Flash USB MCU Periodic Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register. Compare Match Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMnAF and PTMnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTnCCLR is high no PTMnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be cleared to zero. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the PTMn output pin, will change state. The PTMn output pin condition however only changes state when a PTMnAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTMn output pin. The way in which the PTMn output pin changes state are determined by the condition of the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The PTMn output pin can be selected using the PTnIO1 and PTnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTMn output pin, which is setup after the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the PTnIO1 and PTnIO0 bits are zero then no pin change will take place. Rev. 1.10 127 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value Counte� ove�flow CCRP > 0 Counte� �lea�ed �y CCRP value CCRP=0 0x3FF CCRP > 0 PTnCCLR = 0; PTnM[1:0] = 00 Counte� Resta�t Resu�e CCRP Pause CCRA Stop Time PTnON PTnPAU PTnPOL CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTMn O/P Pin Output pin set to initial Level Low if PTnOC=0 Output not affe�ted �y PTMnAF flag. Re�ains High until �eset �y PTnON �it Output Toggle with PTMnAF flag He�e PTnIO [1:0] = 11 Toggle Output sele�t Note PTnIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when PTnPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – PTnCCLR=0 (n=0~4) Note: 1. With PTnCCLR=0 a Comparator P match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge Rev. 1.10 128 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value PTnCCLR = 1; PTnM[1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0x3FF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Time PTnON PTnPAU PTnPOL No PTMnAF flag gene�ated on CCRA ove�flow CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF PTMn O/P Pin PTMnPF not gene�ated Output pin set to initial Level Low if PTnOC=0 Output does not �hange Output Toggle with PTMnAF flag He�e PTnIO [1:0] = 11 Toggle Output sele�t Output not affe�ted �y PTMnAF flag. Re�ains High until �eset �y PTnON �it Note PTnIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when PTnPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – PTnCCLR=1 (n=0~4) Note: 1. With PTnCCLR=1 a Comparator A match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge 4. A PTMnPF flag is not generated when PTnCCLR=1 Rev. 1.10 129 December 15, 2016 HT66FB570 A/D Flash USB MCU Timer/Counter Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively. The PWM function within the PTMn is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the PTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the PTnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTnOC bit in the PTMnC1 register is used to select the required polarity of the PWM waveform while the two PTnIO1 and PTnIO0 bits are used to enable the PWM output or to force the PTMn output pin to a fixed high or low level. The PTnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PTMn, PWM Mode, Edge-aligned Mode CCRP 1~1023 0 Period 1~1023 1024 Duty CCRA If fSYS=12MHz, PTMn clock source select fSYS/4, CCRP=512 and CCRA=128, The PTMn PWM output frequency=(fSYS/4)/512=fSYS/2048=5.8594kHz, duty=128/(2×256)=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.10 130 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value PTnM[1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when PTnON �etu�ns high CCRP Pause Resu�e Counte� Stop if PTnON �it low CCRA Time PTnON PTnPAU PTnPOL CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF PTMn O/P Pin (PTnOC=1) PTMn O/P Pin (PTnOC=0) PWM Duty Cy�le set �y CCRA PWM Pe�iod set �y CCRP Output �ont�olled �y othe� pin-sha�ed fun�tion PWM �esu�es ope�ation Output Inve�ts When PTnPOL = 1 PWM Output Mode (n=0~4) Note: 1. Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTnIO[1:0]=00 or 01 4. The PTnCCLR bit has no influence on PWM operation Rev. 1.10 131 December 15, 2016 HT66FB570 A/D Flash USB MCU Single Pulse Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTMn output pin. The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTnON bit can also be made to automatically change from low to high using the external PTCKn pin, which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTMn interrupt. The counter can only be reset back to zero when the PTnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR bit is not used in this Mode. CCRA Leading Edge CCRA T�ailing Edge PTnON �it 0 1 PTnON �it 1 0 S/W Co��and SET "PTnON" o� PTCKn Pin T�ansition S/W Co��and CLR "PTnON" o� CCRA Co�pa�e Mat�h PTPn Output Pin Pulse Width = CCRA Value Single Pulse Generation (n=0~4) Rev. 1.10 132 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value PTnM[1:0] = 10 ; PTnIO[1:0] = 11 Counte� stopped �y CCRA Counte� Reset when PTnON �etu�ns high CCRA Pause Counte� Stops �y softwa�e Resu�e CCRP Time PTnON Softwa�e T�igge� Auto. set �y PTCKn pin Softwa�e T�igge� Clea�ed �y CCRA �at�h PTCKn pin Softwa�e T�igge� Softwa�e Softwa�e T�igge� Clea� PTCKn pin T�igge� PTnPAU PTnPOL CCRP Int. Flag PTMnPF No CCRP Inte��upts gene�ated CCRA Int. Flag PTMnAF PTMn O/P Pin (PTnOC=1) PTMn O/P Pin (PTnOC=0) Output Inve�ts when PTnPOL = 1 Pulse Width set �y CCRA Single Pulse Mode (n=0~4) Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the PTCKn pin or by setting the PTnON bit high 4. A PTCKn pin active edge will automatically set the PTnON bit high 5. In the Single Pulse Mode, PTnIO[1:0] must be set to "11" and cannot be changed. Rev. 1.10 133 December 15, 2016 HT66FB570 A/D Flash USB MCU Capture Input Mode To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPnI or PTCKn pin which is selected using the PTnCAPTS bit in the PTMnC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The counter is started when the PTnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPnI or PTCKn pin the present value in the counter will be latched into the CCRA registers and a PTMn interrupt generated. Irrespective of what events occur on the PTPnI or PTCKn pin, the counter will continue to free run until the PTnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTMn interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPnI or PTCKn pin to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPnI or PTCKn pin, however it must be noted that the counter will continue to run. As the PTPnI or PTCKn pin is pin shared with other functions, care must be taken if the PTMn is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits are not used in this Mode. Rev. 1.10 134 December 15, 2016 HT66FB570 A/D Flash USB MCU Counter Value PTnM[1:0] = 01 Counte� �lea�ed �y CCRP Counte� Stop Counte� Reset CCRP YY Resu�e Pause XX Time PTnON PTnPAU A�tive edge A�tive edge A�tive edge PTMn Captu�e Pin PTPnI o� PTCKn CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF XX CCRA Value PTnIO [1:0] Value 00 - Rising edge YY XX 01 - Falling edge 10 - Both edges YY 11 - Disa�le Captu�e Capture Input Mode (n=0~4) Note: 1. PTnM[1:0]=01 and active edge set by the PTnIO[1:0] bits 2. A PTMn Capture input pin active edge transfers the counter value to CCRA 3. PTnCCLR bit not used 4. No output function – PTnOC and PTnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.10 135 December 15, 2016 HT66FB570 A/D Flash USB MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Converter Overview This device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. It also can convert the internal signal, the Bandgap reference voltage VBG, into a 12-bit digital value. The external or internal analog signal to be converted is determined by the SAINS2~SAINS0 bits together with the SACS4~SACS0 bits. When the external analog signal is to be converted, the corresponding pin-shared control bits should first be properly configured and then desired external channel input should be selected using the SAINS2~SAINS0 and SACS4~SACS0 bits. Note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly configured except the SAINS and SACS bit fields. More detailed information about the A/D input signal is described in the "A/D Converter Control Registers" and "A/D Converter Input Signals" sections respectively. External Input Channels Internal Signal A/D Channel Select Bits 24: AN0~AN23 1: VBG SAINS2~SAINS0, SACS4~SACS0 The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. AVDD fSYS Pin-sha�ed Sele�tion SACS4~SACS0 SACKS�~ SACKS0 ÷ �N SAVRS1~SAVRS0 (N=0~7) A/D Clo�k AN0 AN1 VREF ADCEN A/D Refe�en�e Voltage A/D Conve�te� SADOL SADOH A/D Data Registe�s AN�3 START VBG ADBZ ADCEN AVSS ADRFS SAINS�~SAINS0 A/D Converter Structure Rev. 1.10 136 December 15, 2016 HT66FB570 A/D Flash USB MCU A/D Converter Register Description Overall operation of the A/D converter is controlled using five registers. A read only register pair exists to store the A/D converter data 12-bit value. The remaining three registers are control registers which setup the operating and control function of the A/D converter. Bit Register Name SADOL(ADRFS=0) 7 6 5 4 3 2 1 0 D3 D2 D1 D0 — — — — SADOL(ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 SADOH(ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 SADOH(ADRFS=1) — — — — D11 D10 D9 D8 SADC0 START ADBZ ADCEN ADRFS — — — — SADC1 SAINS2 SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS2 SACKS1 SACKS0 SADC2 — — — SACS4 SACS3 SACS2 SACS1 SACS0 A/D Converter Registers List A/D Converter Data Registers – SADOL, SADOH As this device contains an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as SADOH, and a low byte register, known as SADOL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the SADC0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. Note that A/D data registers contents will be unchanged if the A/D converter is disabled. ADRFS SADOH SADOL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D Converter Data Registers A/D Converter Control Registers – SADC0, SADC1, SADC2 To control the function and operation of the A/D converter, three control registers known as SADC0~SADC2 are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter busy status. As the device contains only one actual analog to digital converter hardware circuit, each of the external or internal analog signal inputs must be routed to the converter. The SACS4~SACS0 bits in the SADC2 register are used to determine which external channel input is selected to be converted. The SAINS2~SAINS0 bits in the SADC1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pinshared function will be removed. In addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an A/D converter input. Rev. 1.10 137 December 15, 2016 HT66FB570 A/D Flash USB MCU SADC0 Register Bit 7 6 5 4 3 2 1 0 Name START ADBZ ADCEN ADRFS — — — — R/W R/W R R/W R/W — — — — POR 0 0 0 0 — — — — Bit 7 START: Start the A/D conversion 0→1→0: Start This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 ADBZ: A/D converter busy flag 0: No A/D conversion is in progress 1: A/D conversion is in progress This read only flag is used to indicate whether the A/D conversion is in progress or not. When the START bit is set from low to high and then to low again, the ADBZ flag will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be cleared to 0 after the A/D conversion is complete. Bit 5 ADCEN: A/D converter function enable control 0: Disable 1: Enable This bit controls the A/D internal function. This bit should be set to one to enable the A/D converter. If the bit is set low, then the A/D converter will be switched off reducing the device power consumption. When the A/D converter function is disabled, the contents of the A/D data register pair known as SADOH and SADOL will be unchanged. Bit 4 ADRFS: A/D converter data format select 0: A/D converter data format → SADOH=D[11:4]; SADOL=D[3:0] 1: A/D converter data format → SADOH=D[11:8]; SADOL=D[7:0] This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Bit 3~0 Unimplemented, read as "0" SADC1 Register Bit 7 6 5 4 3 2 1 0 Name SAINS2 SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS2 SACKS1 SACKS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~5 Rev. 1.10 SAINS2~SAINS0: A/D converter input signal select 000: External input – External analog channel input 001: Internal input – Internal Bandgap reference voltage, VBG 010~100: Reserved, connected to ground 101~111: External input – External analog channel input Care must be taken if the SAINS2~SAINS0 bits are set "001" to select the internal analog signal to be converted. When the internal analog signal is selected to be converted, the external input pin must never be selected as the A/D input signal by properly setting the SACS4~SACS0 bits with a value from 11000 to 11111. Otherwise, the external channel input will be connected together with the internal analog signal. This will result in unpredictable situations such as an irreversible damage. 138 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 4~3 SAVRS1~SAVRS0: A/D converter reference voltage select 00: VREF pin 01: Internal A/D converter power, AVDD 1x: VREF pin These bits are used to select the A/D converter reference voltage. Care must be taken if the SAVRS1~SAVRS0 bits are set to "01" to select the internal A/D converter power as the reference voltage source. When the internal A/D converter power is selected as the reference voltage, the VREF pin cannot be configured as the reference voltage input by properly configuring the corresponding pin-shared function control bits. Otherwise, the external input voltage on VREF pin will be connected to the internal A/D converter power. Bit 2~0 SACKS2~SACKS0: A/D conversion clock source select 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 These three bits are used to select the clock source for the A/D converter. SADC2 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — — SACS4 SACS3 SACS2 SACS1 SACS0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as "0" Bit 4~0 SACS4~SACS0: A/D converter external analog channel input select 00000: AN0 00001: AN1 : : 10111: AN23 11000~11111: Non-existed channel, the input will be floating if selected 139 December 15, 2016 HT66FB570 A/D Flash USB MCU A/D Converter Operation The START bit in the SADC0 register is used to start the AD conversion. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can poll the ADBZ bit in the SADC0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by the system clock fSYS and by bits SACKS2~SACKS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example, as the system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set to 000, 001 or 111. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Clock Period (tADCK) fSYS SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0] = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 (fSYS) (fSYS/2) (fSYS/4) (fSYS/8) (fSYS/16) (fSYS/32) (fSYS/64) (fSYS/128) 1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs * 2MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 4MHz 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 8MHz 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * 12MHz 83ns * 167ns * 333ns * 667ns 1.33μs 2.67μs 5.33μs 10.67μs * 16MHz 62.5ns * 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADCEN bit in the SADC0 register. This bit must be set high to power on the A/D converter. When the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be consumed. In power conscious applications it is therefore recommended that the ADCEN is set low to reduce power consumption when the A/D converter function is not being used. Rev. 1.10 140 December 15, 2016 HT66FB570 A/D Flash USB MCU A/D Converter Reference Voltage The reference voltage supply to the A/D converter can be supplied from the positive power supply pin, AVDD, or from an external reference source supplied on pin VREF. The desired selection is made using the SAVRS1 and SAVRS0 bits. When the SAVRS bit field is set to "01", the A/D converter reference voltage will come from the AVDD pin. Otherwise, if the SAVRS bit field is set to any other value except "01", the A/D converter reference voltage will come from the VREF pin. As the VREF pin is pin-shared with other functions, when the VREF pin is selected as the reference voltage supply pin, the VREF pin-shared function control bits should be properly configured to disable other pin functions. However, if the internal A/D converter power is selected as the reference voltage, the VREF pin must not be configured as the reference voltage input function to avoid the internal connection between the VREF pin to A/D converter power AVDD. The analog input values must not be allowed to exceed the value of the selected reference voltage, VREF. A/D Converter Input Signals All the external A/D analog channel input pins are pin-shared with the I/O pins as well as other functions. The corresponding control bits for each A/D external input pin in the PxS0 and PxS1 register determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the pin is setup to be as an A/D analog channel input, the original pin functions will be disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the pin-shared function control bits enable an A/D input, the status of the port control register will be overridden. There is an internal analog signal derived from the Bandgap reference voltage, which can be connected to the A/D converter as the analog input signal by configuring the SAINS2~SAINS0 bits. If the external channel input is selected to be converted, the SAINS2~SAINS0 bits should be set to "000" and the SACS4~SACS0 bits can determine which external channel is selected. If the internal analog signal is selected to be converted, the SACS4~SACS0 bits must be configured with a value from 11000 to 11111 to switch off the external analog channel input. Otherwise, the internal analog signal will be connected together with the external channel input. This will result in unpredictable situations. SAINS[2:0] 000, 101~111 SACS[4:0] Input Signals 00000~10111 AN0~AN23 Description External pin analog input 11000~11111 — Non-existed channel, input is floating. 001 11000~11111 VBG Internal Bandgap reference voltage 010~100 11000~11111 — Reserved, connected to ground. A/D Converter Input Signal Selection Rev. 1.10 141 December 15, 2016 HT66FB570 A/D Flash USB MCU Conversion Rate and Timing Diagram A complete A/D conversion contains two parts, data sampling and data conversion. The data sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D clock cycles. Therefore a total of 16 A/D clock cycles for an external input A/D conversion which is defined as tADC are necessary. Maximum single A/D conversion rate=A/D clock period / 16 The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period. tON�ST ADCEN off on off A/D sa�pling ti�e tADS A/D sa�pling ti�e tADS Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion on START ADBZ SACS[4:0] (SAINS[�:0]=000) End of A/D �onve�sion 00011B A/D �hannel swit�h Sta�t of A/D �onve�sion End of A/D �onve�sion 00010B 00000B 00001B tADC A/D �onve�sion ti�e tADC A/D �onve�sion ti�e tADC A/D �onve�sion ti�e A/D Conversion Timing – External Channel Input Rev. 1.10 142 December 15, 2016 HT66FB570 A/D Flash USB MCU Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits SACKS2~SACKS0 in the SADC1 register. • Step 2 Enable the A/D by setting the ADCEN bit in the SADC0 register to one. • Step 3 Select which signal is to be connected to the internal A/D converter by correctly configuring the SAINS2~SAINS0 bits Select the external channel input to be converted, go to Step 4. Select the internal analog signal to be converted, go to Step 5. • Step 4 If the A/D input signal comes from the external channel input selected by configuring the SAINS bit field, the corresponding pins should be configured as A/D input function by configuring the relevant pin-shared function control bits. The desired analog channel then should be selected by configuring the SACS bit field. After this step, go to Step 6. • Step 5 Before the A/D input signal is selected to come from the internal analog signal by configuring the SAINS bit field, the corresponding external input pin must be switched to a non-existed channel input by setting the SACS4~SACS0 bits with a value from 11000 to 11111. The desired internal analog signal then can be selected by configuring the SAINS bit field. After this step, go to Step 6. • Step 6 Select the reference voltage source by configuring the SAVRS1~SAVRS0 bits in the SADC1 register. • Step 7 Select A/D converter output data format by setting the ADRFS bit in the SADC0 register. • Step 8 If A/D conversion interrupt is used, the interrupt control registers must be correctly configured to ensure the A/D interrupt function is active. The master interrupt control bit, EMI, and the A/D conversion interrupt control bit, ADE, must both be set high in advance. • Step 9 The A/D conversion procedure can now be initialized by setting the START bit from low to high and then low again. • Step 10 If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion process is complete, the ADBZ flag will go low and then the output data can be read from SADOH and SADOL registers. Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit in the SADC0 register is used, the interrupt enable step above can be omitted. Rev. 1.10 143 December 15, 2016 HT66FB570 A/D Flash USB MCU Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by clearing bit ADCEN to 0 in the SADC0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Conversion Function As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to 0FFFH. Since the full-scale analog input value is equal to the VREF voltage, this gives a single bit analog input value of VREF divided by 4096. 1 LSB=VREF ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage=A/D output digital value × VREF ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VREF level. 1.� LSB FFFH FFEH FFDH A/D Conversion Result 03H 0.� LSB 0�H 01H 0 1 � 3 4093 4094 409� 409� VREF 409� Analog Input Voltage Ideal A/D Transfer Function Rev. 1.10 144 December 15, 2016 HT66FB570 A/D Flash USB MCU A/D Conversion Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an ADBZ polling method to detect the end of conversion clr ADE; disable ADC interrupt mov a,03H mov SADC1,a ; select fSYS/8 as A/D clock set ADCEN mov a,03h ; setup PBS0 to configure pin AN0 mov PBS0,a mov a,20h mov SADC0,a mov a,00h mov SADC2,a ; enable and connect AN0 channel to A/D converter : : start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D polling_EOC: sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,SADOL ; read low byte conversion result value mov SADOL_buffer,a ; save result to user defined register mov a,SADOH ; read high byte conversion result value mov SADOH_buffer,a ; save result to user defined register : : jmp start_conversion ; start next A/D conversion Rev. 1.10 145 December 15, 2016 HT66FB570 A/D Flash USB MCU Example: using the interrupt method to detect the end of conversion clr ADE; disable ADC interrupt mov a,03H mov SADC1,a ; select fSYS/8 as A/D clock set ADCEN mov a,03h ; setup PBS0 to configure pin AN0 mov PBS0,a mov a,20h mov SADC0,a mov a,00h mov SADC2,a ; enable and connect AN0 channel to A/D converter : : start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE ; enable ADC interrupt set EMI ; enable global interrupt : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory : : mov a,SADOL ; read low byte conversion result value mov SADOL_buffer,a ; save result to user defined register mov a,SADOH ; read high byte conversion result value mov SADOH_buffer,a ; save result to user defined register : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.10 146 December 15, 2016 HT66FB570 A/D Flash USB MCU Comparators Two independent analog comparators are contained within the device. These functions offer flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused. CMPnHYEN Cn+ One Shot + CMP n Interrupt CMPnO Cn- − CnX Pin CMPnPOL CMPnEN Pin-shared select Pin-shared select Comparators (n=0~1) Comparator Operation The device contains two comparator functions which are used to compare two analog voltages and provide an output based on their difference. Any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. As the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. This can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. Ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level. However, unavoidable input offsets introduce some uncertainties here. The hysteresis function, if enabled, also increases the switching offset value. Comparator Registers Full control over each internal comparator is provided via the control register, CMPnC. The comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a shared I/O pin. Additional comparator functions include output polarity, hysteresis functions and power down control. CMPnC Register Rev. 1.10 Bit 7 Name — 6 R/W — R/W POR — 0 5 4 3 2 1 0 CMPnO — — — CMPnHYEN R/W R — — — R/W 0 0 — — — 1 CMPnEN CMPnPOL Bit 7 Unimplemented, read as "0" Bit 6 CMPnEN: Comparator n enable control 0: Disable 1: Enable This is the Comparator n on/off control bit. If the bit is zero the comparator n will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator n is not used or before the device enters the SLEEP or IDLE mode. Note that the comparator n output will be set low when this bit is cleared to zero. 147 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 5 CMPnPOL: Comparator n output polarity control 0: Output is not inverted 1: Output is inverted This is the comparator n polarity control bit. If the bit is zero then the comparator n output bit, CMPnO, will reflect the non-inverted output condition of the comparator n. If the bit is high the comparator n output bit will be inverted. Bit 4 CMPnO: Comparator n output bit If CMPnPOL=0, 0: Cn+ < Cn1: Cn+ > CnIf CMPnPOL=1, 0: Cn+ > Cn1: Cn+ < CnThis bit stores the comparator n output bit. The polarity of the bit is determined by the voltages on the comparator n inputs and by the condition of the CMPnPOL bit. Bit 3~1 Unimplemented, read as "0" Bit 0 CMPnHYEN: Comparator n hysteresis enable control 0: Disable 1: Enable This is the comparator n hysteresis enable control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. Comparator Interrupt Each comparator also possesses its own interrupt function. When any one of the output bits changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. Note that it is the changing state of the CMPnO bit and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE Mode and the Comparator is enabled, then if the external input lines cause the Comparator output to change state, the resulting generated interrupt flag will also generate a wakeup. If it is required to disable a wake-up from occurring, then the interrupt flag should be first set high before entering the SLEEP or IDLE Mode. Programming Considerations If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal I/O pins the I/O registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. Rev. 1.10 148 December 15, 2016 HT66FB570 A/D Flash USB MCU Serial Interface Module – SIM The device contains a Serial Interface Module, which includes both the four line SPI interface and the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O are selected using pull-high control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface This SPI interface function, which is part of the Serial Interface Module, should not be confused with the other independent SPI function, which is described in another section of this datasheet. The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but the device provides only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, the SCK pin is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first be selected by configuring the pin-shared function selection bits and setting the correct bits in the SIMC0 and SIMC2 registers. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state. SPI Maste� SPI Slave SCK SCK SDO SDI SDI SDO SCS SCS SPI Master/Slave Connection Rev. 1.10 149 December 15, 2016 HT66FB570 A/D Flash USB MCU The SPI function in the device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. Data Bus SIMD SDI Pin TX/RX Shift Registe� SDO Pin Clo�k Edge/Pola�ity Cont�ol CKEG CKPOLB Busy Status SCK Pin Clo�k Sou��e Sele�t fSYS fSUB STM CCRP �at�h f�equen�y/� SCS Pin WCOL TRF SIMICF CSEN SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two control registers, SIMC0 and SIMC2. Bit Register Name 7 6 5 4 SIMC0 SIM2 SIM1 SIM0 — SIMC2 D7 D6 CKPOLB CKEG MLS SIMD D7 D6 D5 D4 D3 3 2 1 0 SIMEN SIMICF CSEN WCOL TRF D2 D1 D0 SIMDEB1 SIMDEB0 SPI Registers List Rev. 1.10 150 December 15, 2016 HT66FB570 A/D Flash USB MCU SPI Data Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. • SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0 D7~D0: SIM data register bit 7 ~ bit 0 SPI Control Registers There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC0 register is used to control the enable/disable function and to set the data transmission clock frequency. The SIMC2 register is used for other control functions such as LSB/MSB selection, write collision flag etc. • SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — R/W R/W R/W R/W — R/W R/W POR 1 1 1 — 0 0 Bit 7~5 Rev. 1.10 3 2 SIMDEB1 SIMDEB0 1 0 SIMEN SIMICF R/W R/W 0 0 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is STM CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from STM and fSUB. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2 SIMDEB1~SIMDEB0: I2C Debounce Time Selection The SIMDEB1~SIMDEB0 bits are not used in SPI mode of SIM, please ignore these selection bits when operating in SPI mode. 151 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 1 SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SIMICF: SIM SPI Incomplete Flag 0: SIM SPI incomplete condition is not occurred 1: SIM SPI incomplete condition is occurred This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program. • SIMC2 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 D7~D6: Undefined bits These bits can be read or written by the application program. Bit 5 CKPOLB: SPI clock line base condition selection 0: The SCK line will be high when the clock is inactive 1: The SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. 152 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 3 MLS: SPI data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 CSEN: SPI SCS pin control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into I/O pin or the other functions. If the bit is high the SCS pin will be enabled and used as a select pin. Bit 1 WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Bit 0 TRF: SPI Transmit/Receive complete flag 0: SPI data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set "1" automatically when an SPI data transmission is completed, but must set to "0" by the application program. It can be used to generate an interrupt. SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function in special IDLE Modes if the clock source used by the SPI interface is still active. Rev. 1.10 153 December 15, 2016 HT66FB570 A/D Flash USB MCU SIMEN=1� CSEN=0 (Exte�nal Pull-high) SCS SIMEN� CSEN=1 SCK (CKPOLB=1� CKEG=0) SCK (CKPOLB=0� CKEG=0) SCK (CKPOLB=1� CKEG=1) SCK (CKPOLB=0� CKEG=1) SDO (CKEG=0) D7/D0 D�/D1 D�/D� D4/D3 D3/D4 D�/D� D1/D� D0/D7 SDO (CKEG=1) D7/D0 D�/D1 D�/D� D4/D3 D3/D4 D�/D� D1/D� D0/D7 SDI Data Captu�e W�ite to SIMD SPI Master Mode Timing SCS SCK (CKPOLB=1) SCK (CKPOLB=0) SDO D7/D0 D�/D1 D�/D� D4/D3 D3/D4 D�/D� D1/D� D0/D7 SDI Data Captu�e W�ite to SIMD (SDO does not �hange until fi�st SCK edge) SPI Slave Mode Timing – CKEG=0 SCS SCK (CKPOLB=1) SCK (CKPOLB=0) SDO D7/D0 D�/D1 D�/D� D4/D3 D3/D4 D�/D� D1/D� D0/D7 SDI Data Captu�e W�ite to SIMD (SDO �hanges as soon as w�iting o��u�s; SDO is floating if SCS=1) Note: Fo� SPI slave �ode� if SIMEN=1 and CSEN=0� SPI is always ena�led and igno�es the SCS level. SPI Slave Mode Timing – CKEG=1 Rev. 1.10 154 December 15, 2016 HT66FB570 A/D Flash USB MCU SPI T�ansfe� Maste� Maste� o� Slave ? A W�ite Data into SIMD Clea� WCOL Slave Y SIM[�:0]=000� 001� 010� 011 o� 100 WCOL=1? SIM[�:0]=101 N N Configu�e CKPOLB� CKEG� CSEN and MLS T�ans�ission �o�pleted? (TRF=1?) Y SIMEN=1 Read Data f�o� SIMD A Clea� TRF T�ansfe� finished? N Y END SPI Transfer Control Flowchart Rev. 1.10 155 December 15, 2016 HT66FB570 A/D Flash USB MCU SPI Bus Enable/Disable To enable the SPI bus, set CSEN=1 and SCS=0, then wait for data to be written into the SIMD (TXRX buffer) register. For the Master Mode, after data has been written to the SIMD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred, the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCK, data in the TXRX buffer will be shifted out or data on SDI will be shifted in. To disable the SPI bus, the SCK, SDI, SDO and SCS will become I/O pins or the other functions. SPI Operation All communication is carried out using the 4-line interface for either Master or Slave Mode. The CSEN bit in the SIMC2 register controls the overall function of the SPI interface. Setting this bit high will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI interface. If the CSEN bit is low, the SPI interface will be disabled and the SCS line will be an I/O pin or the other functions and can therefore not be used for control of the SPI interface. If the CSEN bit and the SIMEN bit in the SIMC0 are set high, this will place the SDI line in a floating condition and the SDO line high. If in Master Mode the SCK line will be either high or low depending upon the clock polarity selection bit CKPOLB in the SIMC2 register. If in Slave Mode the SCK line will be in a floating condition. If the SIMEN bit is low, then the bus will be disabled and SCS, SDI, SDO and SCK will all become I/O pins or the other functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SIMD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode. Master Mode: • Step 1 Select the SPI Master mode and clock source using the SIM2~SIM0 bits in the SIMC0 control register. • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Slave devices. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then use the SCK and SCS lines to output the data. After this, go to step5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Rev. 1.10 156 December 15, 2016 HT66FB570 A/D Flash USB MCU Slave Mode: • Step 1 Select the SPI Slave mode using the SIM2~SIM0 bits in the SIMC0 control register • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master devices. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCK and SCS signal. After this, go to step5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Error Detection The WCOL bit in the SIMC2 register is provided to indicate errors during data transfer. The bit is set by the SPI serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SIMD register takes place during a data transfer operation and will prevent the write operation from continuing. Rev. 1.10 157 December 15, 2016 HT66FB570 A/D Flash USB MCU I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. VDD SDA SCL Devi�e Slave Devi�e Maste� Devi�e Slave I2C Master Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For the device, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. Data Bus I�C Data Registe� (SIMD) fSYS SCL Pin SDA Pin HTX De�oun�e Ci��uit�y SIMDEB[1:0] Add�ess Add�ess Mat�h–HAAS Co�pa�ato� Di�e�tion Cont�ol Data in MSB M U X Shift Registe� Read/W�ite Slave I�C Inte��upt SRW Data out MSB TXAK 8-�it Data T�ansfe� Co�plete–HCF T�ans�it/ Re�eive Cont�ol Unit fSUB SIMTOEN I�C Add�ess Registe� (SIMA) Dete�t Sta�t o� Stop HBB SIMTOF Ti�e-out Cont�ol Add�ess Mat�h I2C Block Diagram Rev. 1.10 158 December 15, 2016 HT66FB570 A/D Flash USB MCU START signal f�o� Maste� Send slave add�ess and R/W �it f�o� Maste� A�knowledge f�o� slave Send data �yte f�o� Maste� A�knowledge f�o� slave STOP signal f�o� Maste� The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) No Debounce fSYS > 2 MHz fSYS > 5 MHz 2 system clock debounce fSYS > 4 MHz fSYS > 10 MHz fSYS > 8 MHz fSYS > 20 MHz 4 system clock debounce I2C Fast Mode (400kHz) I C Minimum fSYS Frequency 2 I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMTOC, one address register SIMA and one data register, SIMD. Bit Register Name 7 6 5 4 3 2 0 SIMC0 SIM2 SIM1 SIM0 — SIMEN SIMICF SIMC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMA A6 A5 A4 A3 A2 A1 A0 D0 SIMTOC SIMTOEN SIMDEB1 SIMDEB0 1 SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 I2C Registers List Rev. 1.10 159 December 15, 2016 HT66FB570 A/D Flash USB MCU I2C Data Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. • SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0 D7~D0: SIM data register bit 7 ~ bit 0 I2C Address Register The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. • SIMA Register Bit 7 6 5 4 3 2 1 0 Name A6 A5 A4 A3 A2 A1 A0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~1 A6~A0: I2C slave address A6~A0 is the I2C slave address bit 6~bit 0. Bit 0 D0: Reserved bit, can be read or written I2C Control Registers There are three control registers for the I2C interface, SIMC0, SIMC1 and SIMTOC. The SIMC0 register is used to control the enable/disable function and to set the data transmission clock frequency. The SIMC1 register contains the relevant flags which are used to indicate the I2C communication status. Another register, SIMTOC, is used to control the I2C time-out function and described in the corresponding section. Rev. 1.10 160 December 15, 2016 HT66FB570 A/D Flash USB MCU • SIMC0 Register Rev. 1.10 Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — 3 R/W R/W R/W R/W — R/W POR 1 1 1 — 0 2 1 0 SIMEN SIMICF R/W R/W R/W 0 0 0 SIMDEB1 SIMDEB0 Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is STM CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from STM and fSUB. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2 SIMDEB1~SIMDEB0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce Bit 1 SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SIMICF: SIM SPI Incomplete Flag The SIMICF bit is not used in I2C mode of SIM, please ignore this flag when operating in I2C mode. 161 December 15, 2016 HT66FB570 A/D Flash USB MCU • SIMC1 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4 HTX: I2C slave device is transmitter or receiver selection 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8 bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. Bit 2 SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C Address Match Wake-up control 0: Disable 1: Enable This bit should be set to 1 to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. 162 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 0 RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and SIMTOF bits to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer completion or I2C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to "110" and "1" respectively to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME interrupt enable bit of the interrupt control register to enable the SIM interrupt. Sta�t SET SIM[�:0]=110 SET SIMEN W�ite Slave Add�ess to SIMA No I�C Bus Inte��upt=? Yes CLR SIME Poll SIMF to de�ide when to go to I�C Bus ISR SET SIME Wait fo� Inte��upt Go to Main P�og�a� Go to Main P�og�a� I2C Bus Initialisation Flow Chart Rev. 1.10 163 December 15, 2016 HT66FB570 A/D Flash USB MCU I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. I2C Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from three sources, when the program enters the interrupt subroutine, the HAAS and SIMTOF bits should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer or the I2C bus time-out occurrence. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0". Rev. 1.10 164 December 15, 2016 HT66FB570 A/D Flash USB MCU I2C Bus Data and Acknowledge Signal The transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8 bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. SCL Slave Add�ess Sta�t 1 0 1 SDA 1 0 1 SRW ACK 1 0 0 Data SCL 1 0 0 1 0 ACK 1 0 Stop 0 SDA S=Sta�t (1 �it) SA=Slave Add�ess (7 �its) SR=SRW �it (1 �it) M=Slave devi�e send a�knowledge �it (1 �it) D=Data (8 �its) A=ACK (RXAK �it fo� t�ans�itte�� TXAK �it fo� �e�eive�� 1 �it) P=Stop (1 �it) S SA SR M D A D A …… S SA SR M D A D A …… P I2C Communication Timing Diagram Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. Rev. 1.10 165 December 15, 2016 HT66FB570 A/D Flash USB MCU Sta�t No No No HTX=1? Yes HAAS=1? Yes Yes SIMTOF=1? Yes SET SIMTOEN CLR SIMTOF SRW=1? No RETI Read f�o� SIMD to �elease SCL Line RETI Yes SET HTX CLR HTX CLR TXAK W�ite data to SIMD to �elease SCL Line Du��y �ead f�o� SIMD to �elease SCL Line RETI RETI RXAK=1? No CLR HTX CLR TXAK W�ite data to SIMD to �elease SCL Line Du��y �ead f�o� SIMD to �elease SCL Line RETI RETI I2C Bus ISR Flow Chart I2C Time-out Control In order to reduce the problem of I2C lockup due to reception of erroneous clock sources, a time-out function is provided. If the clock source to the I2C is not received for a while, then the I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts counting on an I2C bus "START" & "address match" condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out setup by the SIMTOC register, then a time-out condition will occur. The time-out function will stop when an I2C "STOP" condition occurs. When an I2C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I2C interrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Registers After I2C Time-out SIMD, SIMA, SIMC0 No change SIMC1 Reset to POR condition I2C Registers after Time-out Rev. 1.10 166 December 15, 2016 HT66FB570 A/D Flash USB MCU SCL Sta�t Slave Add�ess 1 SDA 0 1 1 0 1 SRW ACK 1 0 0 I�C ti�e-out �ounte� sta�t Stop SCL 1 0 0 1 0 1 0 0 SDA I�C ti�e-out �ounte� �eset on SCL negative t�ansition I2C Time-out The SIMTOF flag can be cleared by the application program. There are 64 time-out periods which can be selected using SIMTOS bit field in the SIMTOC register. The time-out time is given by the formula: ((1~64) × 32) / fSUB. This gives a time-out period which ranges from about 1ms to 64ms. • SIMTOC Register Rev. 1.10 Bit 7 Name SIMTOEN 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 Bit 7 SIMTOEN: SIM I2C Time-out control 0: Disable 1: Enable Bit 6 SIMTOF: SIM I2C Time-out flag 0: No time-out occurred 1: Time-out occurred Bit 5~0 SIMTOS5~SIMTOS0: SIM I2C Time-out period selection I2C time-out clock source is fSUB/32. I2C time-out time is equal to (SIMTOS[5:0]+1) × (32/fSUB). 167 December 15, 2016 HT66FB570 A/D Flash USB MCU Serial Peripheral Interface – SPIA The device contains an independent SPI function. It is important not to confuse this independent SPI function with the additional one contained within the combined SIM function, which is described in another section of this datasheet. This independent SPI function will carry the name SPIA to distinguish it from the other one in the SIM. The SPIA interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPIA interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPIA interface specification can control multiple slave devices from a single master, however the device is provided with only one SCSA pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pins to select the slave devices. SPIA Interface Operation The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial Data Output lines, the SCKA pin is the Serial Clock line and SCSA is the Slave Select line. As the SPIA interface pins are pin-shared with normal I/O pins, the SPIA interface must first be enabled by configuring the corresponding selection bits in the pin-shared function selection registers. The SPIA can be disabled or enabled using the SPIAEN bit in the SPIAC0 register. Communication between devices connected to the SPIA interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCSA pin only one slave device can be utilized. The SCSA pin is controlled by the application program, set the SACSEN bit to "1" to enable the SCSA pin function and clear the SACSEN bit to "0" to place the SCSA pin into a floating state. SPIA Maste� SPIA Slave SCKA SCKA SDOA SDIA SDIA SDOA SCSA SCSA SPIA Master/Slave Connection The SPIA function in the device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPIA interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as SACSEN and SPIAEN. Rev. 1.10 168 December 15, 2016 HT66FB570 A/D Flash USB MCU Data Bus SPIAD SDIA Pin TX/RX Shift Registe� Clo�k Edge/Pola�ity Cont�ol SACKEG SACKPOLB Busy Status SCKA Pin SAWCOL SATRF SPIAICF Clo�k Sou��e Sele�t fSYS fSUB PTM0 CCRP �at�h f�equen�y/� SCSA Pin SDOA Pin SACSEN SPIA Block Diagram SPIA Registers There are three internal registers which control the overall operation of the SPIA interface. These are the SPIAD data register and two registers, SPIAC0 and SPIAC1. Bit Register Name 7 6 5 4 3 2 SPIAC0 SASPI2 SASPI1 SASPI0 — — — SPIAC1 — — SPIAD D7 D6 SACKPOLB SACKEG SAMLS D5 D4 D3 1 0 SPIAEN SPIAICF SACSEN SAWCOL D2 D1 SATRF D0 SPIA Registers List SPIA Data Register The SPIAD register is used to store the data being transmitted and received. Before the device writes data to the SPIA bus, the actual data to be transmitted must be placed in the SPIAD register. After the data is received from the SPIA bus, the device can read it from the SPIAD register. Any transmission or reception of data from the SPIA bus must be made via the SPIAD register. • SPIAD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0 Rev. 1.10 D7~D0: SPIA data register bit 7 ~ bit 0 169 December 15, 2016 HT66FB570 A/D Flash USB MCU SPIA Control Registers There are also two control registers for the SPIA interface, SPIAC0 and SPIAC1. The SPIAC0 register is used to control the enable/disable function and to set the data transmission clock frequency. The SPIAC1 register is used for other control functions such as LSB/MSB selection, write collision flag etc. • SPIAC0 Register Bit 7 6 5 4 3 2 1 0 Name SASPI2 SASPI1 SASPI0 — — SPIAICF R/W R/W R/W — — R/W R/W POR 1 1 1 — — — — — SPIAEN R/W 0 0 Bit 7~5 Rev. 1.10 SASPI2~SASPI0: SPIA Operating Mode Control 000: SPIA master mode; SPIA clock is fSYS/4 001: SPIA master mode; SPIA clock is fSYS/16 010: SPIA master mode; SPIA clock is fSYS/64 011: SPIA master mode; SPIA clock is fSUB 100: SPIA master mode; SPIA clock is PTM0 CCRP match frequency/2 101: SPIA slave mode 110: Unimplemented 111: Unimplemented These bits are used to control the SPIA Master/Slave selection and the SPIA Master clock frequency. The SPIA clock is a function of the system clock but can also be chosen to be sourced from PTM0 and fSUB. If the SPIA Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4~2 Unimplemented, read as "0" Bit 1 SPIAEN: SPIA Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SPIA interface. When the SPIAEN bit is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA lines will lose their SPIA function and the SPIA operating current will be reduced to a minimum value. When the bit is high the SPIA interface is enabled. Bit 0 SPIAICF: SPIA Incomplete Flag 0: SPIA incomplete condition is not occurred 1: SPIA incomplete condition is occured This bit is only available when the SPIA is configured to operate in an SPIA slave mode. If the SPIA operates in the slave mode with the SPIAEN and SACSEN bits both being set to 1 but the SCSA line is pulled high by the external master device before the SPIA data transfer is completely finished, the SPIAICF bit will be set to 1 together with the SATRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the SATRF bit will not be set to 1 if the SPIAICF bit is set to 1 by software application program. 170 December 15, 2016 HT66FB570 A/D Flash USB MCU • SPIAC1 Register Rev. 1.10 Bit 7 6 5 4 3 Name — — SACKPOLB SACKEG SAMLS 2 1 0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 SACSEN SAWCOL SATRF Bit 7~6 Unimplemented, read as "0". Bit 5 SACKPOLB: SPIA clock line base condition selection 0: The SCKA line will be high when the clock is inactive 1: The SCKA line will be low when the clock is inactive The SACKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOLB bit is low, then the SCKA line will be high when the clock is inactive. Bit 4 SACKEG: SPIA SCKA clock active edge type selection SACKPOLB=0 0: SCKA has high base level with data capture on SCKA rising edge 1: SCKA has high base level with data capture on SCKA falling edge SACKPOLB=1 0: SCKA has low base level with data capture on SCKA falling edge 1: SCKA has low base level with data capture on SCKA rising edge The SACKEG and SACKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPIA bus. These two bits must be configured before a data transfer is executed otherwise an erroneous clock edge may be generated. The SACKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOLB bit is low, then the SCKA line will be high when the clock is inactive. The SACKEG bit determines active clock edge type which depends upon the condition of the SACKPOLB bit. Bit 3 SAMLS: SPIA data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 SACSEN: SPIA SCSA pin control 0: Disable 1: Enable The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then the SCSA pin will be disabled and placed into other functions. If the bit is high the SCSA pin will be enabled and used as a select pin. Bit 1 SAWCOL: SPIA write collision flag 0: No collision 1: Collision The SAWCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SPIAD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Bit 0 SATRF: SPIA Transmit/Receive complete flag 0: SPIA data is being transferred 1: SPIA data transmission is completed The SATRF bit is the Transmit/Receive Complete flag and is set "1" automatically when an SPIA data transmission is completed, but must set to zero by the application program. It can be used to generate an interrupt. 171 December 15, 2016 HT66FB570 A/D Flash USB MCU SPIA Communication After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when data is written to the SPIAD register, transmission/reception will begin simultaneously. When the data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into the SPIAD register. The master should output an SCSA signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCSA signal depending upon the configurations of the SACKPOLB bit and SACKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCSA signal for various configurations of the SACKPOLB and SACKEG bits. The SPIA will continue to function in special IDLE Modes if the clock source used by the SPIA interface is still active. SPIAEN=1� SACSEN=0 (Exte�nal Pull-high) SCSA SPIAEN� SACSEN=1 SCKA (SACKPOLB=1� SACKEG=0) SCKA (SACKPOLB=0� SACKEG=0) SCKA (SACKPOLB=1� SACKEG=1) SCKA (SACKPOLB=0� SACKEG=1) SDOA (SACKEG=0) D7/D0 D�/D1 D�/D� D4/D3 D3/D4 D�/D� D1/D� D0/D7 SDOA (SACKEG=1) D7/D0 D�/D1 D�/D� D4/D3 D3/D4 D�/D� D1/D� D0/D7 SDIA Data Captu�e W�ite to SPIAD SPIA Master Mode Timing SCSA SCKA (SACKPOLB=1) SCKA (SACKPOLB=0) SDOA D7/D0 D�/D1 D�/D� D4/D3 D3/D4 D�/D� D1/D� D0/D7 SDIA Data Captu�e W�ite to SPIAD (SDOA does not �hange until fi�st SCKA edge) SPIA Slave Mode Timing – SACKEG=0 Rev. 1.10 172 December 15, 2016 HT66FB570 A/D Flash USB MCU SCSA SCKA (SACKPOLB=1) SCKA (SACKPOLB=0) SDOA D7/D0 D�/D1 D�/D� D4/D3 D3/D4 D�/D� D1/D� D0/D7 SDIA Data Captu�e W�ite to SPIAD (SDOA �hanges as soon as w�iting o��u�s; SDOA is floating if SCSA=1) Note: Fo� SPIA slave �ode� if SPIAEN=1 and SACSEN=0� SPIA is always ena�led and igno�es the SCSA level. SPIA Slave Mode Timing – SACKEG=1 SPIA T�ansfe� Maste� Maste� o� Slave ? A W�ite Data into SPIAD Clea� SAWCOL Slave Y SASPI[�:0]=000� 001� 010� 011 o� 100 SAWCOL=1? SASPI[�:0]=101 N N Configu�e SACKPOLB� SACKEG� SACSEN and SAMLS T�ans�ission �o�pleted? (SATRF=1?) Y SPIAEN=1 Read Data f�o� SPIAD A Clea� SATRF T�ansfe� finished? N Y END SPIA Transfer Control Flowchart Rev. 1.10 173 December 15, 2016 HT66FB570 A/D Flash USB MCU SPIA Bus Enable/Disable To enable the SPIA bus, set SACSEN=1 and SCSA=0, then wait for data to be written into the SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in. To Disable the SPIA bus SCKA, SDIA, SDOA, SCSA will become I/O pins or the other functions. SPIA Operation All communication is carried out using the 4-line interface for either Master or Slave Mode. The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting this bit high will enable the SPIA interface by allowing the SCSA line to be active, which can then be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled and the SCSA line will be an I/O pin or the other functions and can therefore not be used for control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are set high, this will place the SDIA line in a floating condition and the SDOA line high. If in Master Mode the SCKA line will be either high or low depending upon the clock polarity selection bit SACKPOLB in the SPIAC1 register. If in Slave Mode the SCKA line will be in a floating condition. If SPIAEN is low then the bus will be disabled and SCSA, SDIA, SDOA and SCKA will all become I/O pins or the other functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SPIAD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode. Master Mode: • Step 1 Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control register. • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB first, this must be same as the Slave device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface. • Step 4 For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then use the SCKA and SCSA lines to output the data. After this go to step 5. For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register. • Step 5 Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the SATRF bit or wait for a SPIA serial bus interrupt. • Step 7 Read data from the SPIAD register. • Step 8 Clear SATRF. • Step 9 Go to step 4. Rev. 1.10 174 December 15, 2016 HT66FB570 A/D Flash USB MCU Slave Mode: • Step 1 Select the SPIA Slave mode using the SASPI2~SASPI0 bits in the SPIAC0 control register. • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface. • Step 4 For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCKA and SCSA signal. After this, go to step 5. For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register. • Step 5 Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the SATRF bit or wait for a SPIA serial bus interrupt. • Step 7 Read data from the SPIAD register. • Step 8 Clear SATRF. • Step 9 Go to step 4. Error Detection The SAWCOL bit in the SPIAC1 register is provided to indicate errors during data transfer. The bit is set by the SPIA serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SPIAD register takes place during a data transfer operation and will prevent the write operation from continuing. Rev. 1.10 175 December 15, 2016 HT66FB570 A/D Flash USB MCU UART Interface The device contains an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, asynchronous communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler • Parity, framing, noise and overrun error detection • Support for interrupt on address detect (last character bit=1) • Separately enabled transmitter and receiver • 2-byte Deep FIFO Receive Data Buffer • RX pin wake-up function • Transmit and receive interrupts • Interrupts can be initialized by the following conditions: ♦♦ Transmitter Empty ♦♦ Transmitter Idle ♦♦ Receiver Full ♦♦ Receiver Overrun ♦♦ Address Mode Detect T�ans�itte� Shift Registe� (TSR) MSB ………………………… Re�eive� Shift Registe� (RSR) LSB TX Pin TXR_RXR Registe� RX Pin MSB Data to �e t�ans�itted LSB TXR_RXR Registe� Baud Rate Gene�ato� fH ………………………… Buffe� Data �e�eived MCU Data Bus UART Data Transfer Block Diagram Rev. 1.10 176 December 15, 2016 HT66FB570 A/D Flash USB MCU UART External Pins To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. The TX and RX pin function should first be selected by the corresponding pin-shared function selection register before the UART function is used. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will setup these pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX and RX pins. When the TX or RX pin function is disabled by clearing the UARTEN, TXEN or RXEN bit, the TX or RX pin will be set to a floating state. At this time whether the internal pull-high resistor is connected to the TX or RX pin or not is determined by the corresponding I/O pull-high function control bit. UART Data Transfer Scheme The above block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR_RXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR_RXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal TXR_RXR register, where it is buffered and can be manipulated by the application program. Only the TXR_ RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, only exists as a single shared register in the Data Memory. This shared register known as the TXR_RXR register is used for both data transmission and data reception. UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR_ RXR data register. Bit Register Name 7 6 5 4 3 2 1 0 USR PERR NF FERR OERR RIDLE RXIF TIDLE TXIF UCR1 UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 UCR2 TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE TXR_RXR D7 D6 D5 D4 D3 D2 D1 D0 BRG D7 D6 D5 D4 D3 D2 D1 D0 UART Registers List Rev. 1.10 177 December 15, 2016 HT66FB570 A/D Flash USB MCU USR Register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7 PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is "0", it indicates a parity error has not been detected. When the flag is "1", it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the TXR_RXR data register. Bit 6 NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is "1", it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the TXR_RXR data register. Bit 5 FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is "0", it indicates that there is no framing error. When the flag is "1", it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the TXR_RXR data register. Bit 4 OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is "0", it indicates that there is no overrun error. When the flag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the TXR_RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the TXR_RXR data register. Bit 3 RIDLE: Receiver status 0: Data reception is in progress (Data being received) 1: No data reception is in progress (Receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1" indicating that the UART receiver is idle and the RX pin stays in logic high condition. 178 December 15, 2016 HT66FB570 A/D Flash USB MCU Rev. 1.10 Bit 2 RXIF: Receive TXR_RXR data register status 0: TXR_RXR data register is empty 1: TXR_RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is "0", it indicates that the TXR_RXR read data register is empty. When the flag is "1", it indicates that the TXR_RXR read data register contains new data. When the contents of the shift register are transferred to the TXR_RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the TXR_RXR register, and if the TXR_RXR register has no data available. Bit 1 TIDLE: Transmission idle 0: Data transmission is in progress (Data being transmitted) 1: No data transmission is in progress (Transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is "0", it indicates that a transmission is in progress. This flag will be set high when the TXIF flag is "1" and when there is no transmit data or break character being transmitted. When TIDLE is equal to "1", the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR_RXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0 TXIF: Transmit TXR_RXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR_RXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicates that the character is not transferred to the transmitter shift register. When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR_RXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR_RXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. 179 December 15, 2016 HT66FB570 A/D Flash USB MCU UCR1 Register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x 0 "x" unknown Rev. 1.10 Bit 7 UARTEN: UART function enable control 0: Disable UART. TX and RX pins are in a floating state 1: Enable UART. TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to "0", the UART will be disabled and the RX pin as well as the TX pin will be set in a floating state. When the bit is equal to "1", the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6 BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Bit 5 PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This is the parity enable bit. When this bit is equal to "1", the parity function will be enabled. If the bit is equal to "0", then the parity function will be disabled. Replace the most significant bit position with a parity bit. Bit 4 PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to "1", odd parity type will be selected. If the bit is equal to "0", then even parity type will be selected. Bit 3 STOPS: Number of Stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to "1", two stop bits are used. If this bit is equal to "0", then only one stop bit is used. 180 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 2 TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is "0", there are no break characters and the TX pin operates normally. When the bit is "1", there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to "1", after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1 RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Bit 0 TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. UCR2 Register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below: Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN: UART Transmitter enabled control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be set in a floating state. If the TXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be set in a floating state. Bit 6 RXEN: UART Receiver enabled control 0: UART receiver is disabled 1: UART receiver is enabled The bit named RXEN is the Receiver Enable Bit. When this bit is equal to "0", the receiver will be disabled with any pending data receptions being aborted. In addition the receive buffers will be reset. In this situation the RX pin will be set in a floating state. If the RXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be set in a floating state. Bit 5 BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UART. If this bit is equal to "1", the high speed mode is selected. If the bit is equal to "0", the low speed mode is selected. 181 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 4 ADDEN: Address detect function enable control 0: Address detect function is disabled 1: Address detect function is enabled The bit named ADDEN is the address detect function enable control bit. When this bit is equal to "1", the address detect function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if BNO=1, has a value of "1", then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of BNO. If the address bit known as the 8th or 9th bit of the received word is "0" with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3 WAKE: RX pin wake-up UART function enable control 0: RX pin wake-up UART function is disabled 1: RX pin wake-up UART function is enabled This bit is used to control the wake-up UART function when a falling edge on the RX pin occurs. Note that this bit is only available when the UART clock (fH) is switched off. There will be no RX pin wake-up UART function if the UART clock (fH) exists. If the WAKE bit is set to 1 as the UART clock (fH) is switched off, a UART wakeup request will be initiated when a falling edge on the RX pin occurs. When this request happens and the corresponding interrupt is enabled, an RX pin wake-up UART interrupt will be generated to inform the MCU to wake up the UART function by switching on the UART clock (fH) via the application program. Otherwise, the UART function can not resume even if there is a falling edge on the RX pin when the WAKE bit is cleared to 0. Bit 2 RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to "1" and when the receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1 TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. If this bit is equal to "1" and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0 TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled This bit enables or disables the transmitter empty interrupt. If this bit is equal to "1" and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the TXIF flag. TXR_RXR register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0 Rev. 1.10 D7~D0: UART Transmit/Receive Data bit 7 ~ bit 0 182 December 15, 2016 HT66FB570 A/D Flash USB MCU BRG Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0 D7~D0: Baud Rate values By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup. Note: Baud rate= fH / [64 × (N+1)] if BRGH=0. Baud rate= fH / [16 × (N+1)] if BRGH=1. Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value N in the BRG register which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) fH / [64 (N+1)] fH / [16 (N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the Baud Rate and Error Values For a clock frequency of 4MHz, and with BRGH cleared to zero determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR=fH / [64 (N+1)] Re-arranging this equation gives N=[fH / (BR×64)] - 1 Giving a value for N=[4000000 / (4800×64)] - 1=12.0208 To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of BR=4000000 / [64 × (12+1)]=4808 Therefore the error is equal to (4808 - 4800) / 4800=0.16% Rev. 1.10 183 December 15, 2016 HT66FB570 A/D Flash USB MCU UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UART transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/Disabling the UART Interface The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O or other pin-shared functional pins. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Data, Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit, which is the MSB of the data byte, identifies the frame as an address character or data if the address detect function is enabled. The number of stop bits, which can be either one or two, are independent of the data length and only to be used for the transmitter. There is only one stop bit for the receiver. Start Bit Data Bits Address Bit Parity Bit Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats Rev. 1.10 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 184 December 15, 2016 HT66FB570 A/D Flash USB MCU Transmitter Receiver Data FormatThe following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. Sta�t Bit Pa�ity Bit Bit 0 Bit 1 Bit � Bit 3 Bit 4 Bit � Bit � Bit 7 8-bit Data Format Sta�t Bit Bit 0 Bit 1 Bit � Bit 3 Bit 4 Bit � Stop Bit Next Sta�t Bit Pa�ity Bit Bit � Bit 7 Bit 8 Stop Bit Next Sta�t Bit 9-bit Data Format UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR_RXR register. The data to be transmitted is loaded into this TXR_RXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR_RXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR_RXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR_RXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR_RXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin can then be configured as the I/O or other pin-shared function. Transmitting Data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR_RXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin. • Access the USR register and write the data that is to be transmitted into the TXR_RXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR_RXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR_RXR register write execution Rev. 1.10 185 December 15, 2016 HT66FB570 A/D Flash USB MCU The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR_RXR register is empty and that other data can now be written into the TXR_RXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR_RXR register will place the data into the TXR_RXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR_RXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR_RXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmit Break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13×N ‘0’ bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program, and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Rev. 1.10 186 December 15, 2016 HT66FB570 A/D Flash USB MCU Receiving Data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the TXR_RXR register forms a buffer between the internal bus and the receiver shift register. The TXR_RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from TXR_RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of BNO, PRT and PREN bits to define the word length and parity type. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received the following sequence of events will occur: • The RXIF bit in the USR register will be set when the TXR_RXR register has data available. There will be at most one more character available before an overrun error occurs. • When the contents of the shift register have been transferred to the TXR_RXR register, then if the RIE bit is set, an interrupt will be generated. • If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. A TXR_RXR register read execution Receive Break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO plusing one stop bit. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO plusing one stop bit. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. A break is regarded as a character that contains only zeros with the FERR flag set. If a long break signal has been detected, the receiver will regard it as a data frame including a start bit, data bits and the invalid stop bit and the FERR flag will be set. The receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, TXR_RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Rev. 1.10 187 December 15, 2016 HT66FB570 A/D Flash USB MCU Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, TXR_RXR. An overrun error can also generate an interrupt if RIE=1. Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR The TXR_RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the TXR_RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The TXR_RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the TXR_ RXR register. Noise Error – NF Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the Shift register to the TXR_RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by a TXR_RXR register read operation. Framing Error – FERR The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high; otherwise the FERR flag will be set. The FERR flag and the received data will be recorded in the USR and TXR_RXR registers respectively, and the flag is cleared in any reset. Rev. 1.10 188 December 15, 2016 HT66FB570 A/D Flash USB MCU Parity Error – PERR The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN=1, and if the parity type, odd or even is selected. The read only PERR flag and the received data will be recorded in the USR and TXR_RXR registers respectively. It is cleared on any reset, it should be noted that the flags, FERR and PERR, in the USR register should first be read by the application program before reading the data word. UART Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if the global interrupt enable bit, multi-function interrupt enable bit and its corresponding interrupt control bit are enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the UART clock (fH) source is switched off and the WAKE and RIE bits in the UCR2 register are set when a falling edge on the RX pin occurs. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. USR Registe� UCR� Registe� T�ans�itte� E�pty Flag TXIF TEIE T�ans�itte� Idle Flag TIDLE TIIE Re�eive� Ove��un Flag OERR RIE 1 WAKE 0 1 UART Inte��upt Request Flag URF URE MFnE EMI Inte��upt signal to MCU 0 1 ADDEN Re�eive� Data Availa�le RXIF RX Pin Wake-up 0 0 1 0 1 0 1 RX7 if BNO=0 RX8 if BNO=1 UCR� Registe� UART Interrupt Structure Rev. 1.10 189 December 15, 2016 HT66FB570 A/D Flash USB MCU Address Detect Mode Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the MFnE, URE and EMI interrupt enable bits must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit PREN to zero. ADDEN Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated 0 √ 0 1 1 √ 0 × 1 √ ADDEN Bit Function UART Power Down and Wake-up When the UART clock (fH) is off, the UART will cease to function, all clock sources to the module are shutdown. If the UART clock (fH) is off while a transmission is still in progress, then the transmission will be paused until the UART clock source derived from the microcontroller is activated. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be paused. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. It is recommended to make sure first that the UART data transmission or reception has been finished before the microcontroller enters the Power Down mode. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set when the UART clock (fH) is off, then a falling edge on the RX pin will trigger an RX pin wake-up UART interrupt. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, the Multi-function Interrupt enable bit, MFnE, and the UART interrupt enable bit, URE, must be set. If the EMI, MFnE and URE bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Rev. 1.10 190 December 15, 2016 HT66FB570 A/D Flash USB MCU Low Voltage Detector – LVD The device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN VBGEN VLVD2 VLVD1 VLVD0 R/W — — R R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 LVDO: LVD Output flag 0: No Low Voltage Detected 1: Low Voltage Detected Bit 4 LVDEN: Low Voltage Detector Enable control 0: Disable 1: Enable Bit 3 VBGEN: Bandgap Voltage Output Enable control 0: Disable 1: Enable Note that the Bandgap circuit is enabled when the LVD or LVR function is enabled or when the VBGEN bit is set to 1. Bit 2~0 VLVD2~VLVD0: LVD Voltage selection 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V 191 December 15, 2016 HT66FB570 A/D Flash USB MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is in the SLEEP mode, the low voltage detector will be disabled even if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. VDD VLVD LVDEN LVDO tLVDS LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.10 192 December 15, 2016 HT66FB570 A/D Flash USB MCU USB Interface The USB interface is a 4-wire serial bus that allows communication between a host device and up to 127 max peripheral devices on the same bus. A token based protocol method is used by the host device for communication control. Other advantages of the USB bus include live plugging and unplugging and dynamic device configuration. As the complexity of USB data protocol does not permit comprehensive USB operation information to be provided in this datasheet, the reader should therefore consult other external information for a detailed USB understanding. The device includes a USB interface function allowing for the convenient design of USB peripheral products. Power Plane There are three power planes for the device and they are USB SIE VDD, VDDIO and the MCU VDD. For the USB SIE VDD it will supply power for all circuits related to USB SIE and is sourced from pin "UBUS". Once the USB is removed from the USB interface and there is no power in the USB BUS, the USB SIE circuit is no longer operational. For the PA port, the power can be supplied by the VDD, V33O or VDDIO pin selected using the PMPS register. The VDDIO is pin-shared with PE0 and VREF pins .The VDDIO function can be selected by the corresponding pin-shared function selection bits. For the MCU VDD, it supplies power for all the device circuits except the USB SIE which is supplied by UBUS. USB Interface Operation To communicate with an external USB host, the internal USB module has the external pins known as UDP and UDN along with the 3.3V regulator output V33O. A Serial Interface Engine (SIE) decodes the incoming USB data stream and transfers it to the correct endpoint buffer memory known as the FIFO. The USB module has 8 endpoints, EP0 ~ EP7, and the FIFO size for each endpoint except endpoint 0 can respectively be configured using the UFC0~UFC2 registers by application programs. All endpoints except endpoint 0 can be configured to have 8, 16, 32 or 64 bytes together with the FIFOn registers as the FIFO size. The endpoint 0 has 8-byte FIFO size. The endpoint 0 supports the Control transfer while the endpoint 1 ~ endpoint 7 support the Interrupt or Bulk transfer. As the USB FIFO is assigned from the last sector of the General Purpose Data Memory and has a start address to the upper address, dependent on the FIFO size, if the corresponding data RAM sector is used for both general purpose RAM and the USB FIFO, special care should be taken that the RAM EQU definition should not overlap with the USB FIFO RAM address. The USB FIFO size and definition for IN/OUT control depends upon the UFC0~UFC2, UFIEN and UFOEN registers. Rev. 1.10 193 December 15, 2016 HT66FB570 A/D Flash USB MCU n80H Gene�al Pu�pose Data Me�o�y : : nC0H OUT 3 (8 �ytes) nC7H nC8H IN 3 (8 �ytes) nCFH nD0H OUT � (1� �ytes) nDFH nE0H IN � (1� �ytes) nEFH nF0H OUT 1 (8 �ytes) nF7H nF8H IN 1 (8 �ytes) nFFH n should Sta�t f�o� 7~0. USB FIFO size Configuration USB Interface Registers The USB function control is implemented using a series of registers. A series of status registers provide the user with the USB data transfer situation as well as any error conditions. The USB contains its own independent interrupt which can be used to indicate when the USB FIFOs are accessed by the host device or a change of the USB operating conditions including the USB suspend mode, resume event or USB reset occurs. Rev. 1.10 Bit Register Name 7 6 5 4 3 2 1 0 SYSC — USBDIS RUBUS UBUSF — — D1 ESDF USB_ STAT OD1O OD0O OD1I OD0I SE1 SE0 PU — UINT EP7EN EP6EN EP5EN EP4EN EP3EN EP2EN EP1EN EP0EN USC URD UMS2 UMS1 UMS0 RESUME URST RMWK SUSP UESR EP7F EP6F EP5F EP4F EP3F EP2F EP1F EP0F UCC RCTRL — JSUSP SUSP2 USBCKEN EPS2 EPS1 EPS0 AWR AD6 AD5 AD4 AD3 AD2 AD1 AD0 WKEN STLI STLI7 STLI6 STLI5 STLI4 STLI3 STLI2 STLI1 STLI0 STLO STLO7 STLO6 STLO5 STLO4 STLO3 STLO2 STLO1 — SIES NMI UERR2 UERR1 UERR0 IN OUT UFERR ASET MISC LEN0 V33OS — CLEAR TX REQUEST UFIEN SETI7 READY SETCMD SETI6 SETI5 SETI4 SETI3 SETI2 SETI1 FIFO_DEF UFOEN SETO7 SETO6 SETO5 SETO4 SETO3 SETO2 SETO1 DATATG UFC0 E3FS1 E3FS0 E2FS1 E2FS0 E1FS1 E1FS0 — — UFC1 E7FS1 E7FS0 E6FS1 E6FS0 E5FS1 E5FS0 E4FS1 E4FS0 UFC2 — — — — E3ODB E3IDB E2ODB E2IDB FIFO0 D7 D6 D5 D4 D3 D2 D1 D0 FIFO1 D7 D6 D5 D4 D3 D2 D1 D0 FIFO2 D7 D6 D5 D4 D3 D2 D1 D0 194 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit Register Name 7 6 5 4 3 2 1 0 FIFO3 D7 D6 D5 D4 D3 D2 D1 D0 FIFO4 D7 D6 D5 D4 D3 D2 D1 D0 FIFO5 D7 D6 D5 D4 D3 D2 D1 D0 FIFO6 D7 D6 D5 D4 D3 D2 D1 D0 FIFO7 D7 D6 D5 D4 D3 D2 D1 D0 USB Interface Registers List SYSC Register Bit 7 6 5 4 3 2 1 0 Name — USBDIS RUBUS UBUSF — — D1 ESDF R/W — R/W R/W R/W — — R/W R/W POR — 0 0 0 — — 0 x "x": unknown Bit 7 Unimplemented, read as "0" Bit 6 USBDIS: USB SIE function control 0: Enable 1: Disable This bit is used to control the USB SIE function. When this bit is set to 1, the USB SIE function will be disabled. Bit 5 RUBUS: UBUS pin pull low function control 0: Enable 1: Disable Bit 4 UBUSF: UBUS pin input status 0: Low level 1: High level Bit 3~2 Unimplemented, read as "0" Bit 1 D1: Reserved bit, cannot be used and must be fixed at 0 Bit 0 ESDF: ESD issue flag This bit will be set to 1 when there is an ESD issue. It is set by SIE and cleared by software. USB_STAT Register Bit 7 6 5 4 3 2 1 0 Name OD1O OD0O OD1I OD0I SE1 SE0 PU — R/W R/W R/W R R R/W R/W R/W — POR 1 1 x x 0 0 0 — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.10 "x": unknown OD1O: Output data on OD1 pin, open drain NMOS output OD0O: Output data on OD0 pin, open drain NMOS output OD1I: OD1 pin input status OD0I: OD0 pin input status SE1: USB bus SE1 noise indication This bit is used to indicate that the SIE has detected a SE1 noise on the USB bus. This bit is set by SIE and cleared by software. SE0: USB bus SE0 noise indication This bit is used to indicate that the SIE has detected a SE0 noise on the USB bus. This bit is set by SIE and cleared by software. PU: UDP/UDN pins pull-high function control 0: Disable – no internal pull-high resistor 1: Enable – internal 600kΩ pull-high resistor on UDP/UDN pins Unimplemented, read as "0" 195 December 15, 2016 HT66FB570 A/D Flash USB MCU UINT Register Bit 7 6 5 4 3 2 1 0 Name EP7EN EP6EN EP5EN EP4EN EP3EN EP2EN EP1EN EP0EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 EP7EN: USB endpoint 7 interrupt enable control 0: Disable 1: Enable Bit 6 EP6EN: USB endpoint 6 interrupt enable control 0: Disable 1: Enable Bit 5 EP5EN: USB endpoint 5 interrupt enable control 0: Disable 1: Enable Bit 4 EP4EN: USB endpoint 4 interrupt enable control 0: Disable 1: Enable Bit 3 EP3EN: USB endpoint 3 interrupt enable control 0: Disable 1: Enable Bit 2 EP2EN: USB endpoint 2 interrupt enable control 0: Disable 1: Enable Bit 1 EP1EN: USB endpoint 1 interrupt enable control 0: Disable 1: Enable Bit 0 EP0EN: USB endpoint 0 interrupt enable control 0: Disable 1: Enable USC Register Bit 7 6 5 4 3 2 1 0 Name URD UMS2 UMS1 UMS0 RESUME URST RMWK SUSP R/W R/W R/W R/W R/W R R/W R/W R POR 1 0 0 0 x x x x "x": unknown Rev. 1.10 Bit 7 URD: USB reset signal reset function control 0: USB reset signal cannot reset MCU 1: USB reset signal will reset MCU Bit 6~4 UMS2~UMS0: USB and OD mode select 000: No mode available – The V33O output will be floating. The relevant external pins will be in an input floating state. 001: Open drain output mode – The V33O output will be pulled high to VDD. The relevant external pins will become OD0/OD1 pins with a pull-high resistor respectively connected to VDD. 01x: USB mode – The V33O function will be enabled. The relevant external pins will be used as the UDP and UDN pins. 100~111: Undefined, the OD0/OD1 will be in a floating state. 196 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 3 RESUME: USB resume indication 0: Resume signal is not asserted or USB device has left the suspend mode 1: Resume signal is asserted and USB device is going to leave the suspend mode When the resume event occurs, this bit will be set high by SIE and then an interrupt will also be generated to wake up the MCU. In order to detect the suspend state, the MCU should set the USBCKEN bit to 1 and clear the SUSP2 bit to 0. When the USB device leaves the suspend mode, the SUSP bit will be cleared to 0 and then the RESUME bit will also be cleared to 0. The resume signal which causes the MCU to wake up should be noted and taken into consideration when the MCU is detecting the suspend mode. Bit 2 URST: USB reset indication 0: No USB reset event occurs 1: USB reset event occurs This bit is set and cleared by the SIE. When the URST bit is set high, it indicates that a USB reset event has occurred and a USB interrupt will be generated. Bit 1 RMWK: USB remote wake-up command 0: No USB remote wake-up command initiated 1: Initiate USB remote wake-up command The RMWK bit is set to 1 by the MCU to force the USB host leaving the suspend mode. Setting the RMWK bit to 1 will initiate a remote wake-up command. This bit is set to produce a high pulse to indicate that the USB host has left the suspend mode. Bit 0 SUSP: USB suspend indication 0: USB leaves the suspend mode 1: USB enters the suspend mode This bit is read only and set to 1 by the SIE to indicate that the USB has entered the suspend mode. The corresponding interrupt will also be generated when the SUSP bit changes from low to high. UESR Register The UESR register is the USB endpoint interrupt status register and is used to indicate which endpoint is accessed and to select the USB bus. The endpoint request flags, EPnF, are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to "1" and the USB interrupt will occur if the USB interrupt is enabled and the stack is not full. When the active endpoint request flag is serviced, the endpoint request flag has to be cleared to "0" by software. Bit 7 6 5 4 3 2 1 0 Name EP7F EP6F EP5F EP4F EP3F EP2F EP1F EP0F R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Rev. 1.10 Bit 7 EP7F: Endpoint 7 access interrupt request flag 0: Not accessed 1: Accessed Bit 6 EP6F: Endpoint 6 access interrupt request flag 0: Not accessed 1: Accessed Bit 5 EP5F: Endpoint 5 access interrupt request flag 0: Not accessed 1: Accessed Bit 4 EP4F: Endpoint 4 access interrupt request flag 0: Not accessed 1: Accessed 197 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 3 EP3F: Endpoint 3 access interrupt request flag 0: Not accessed 1: Accessed Bit 2 EP2F: Endpoint 2 access interrupt request flag 0: Not accessed 1: Accessed Bit 1 EP1F: Endpoint 1 access interrupt request flag 0: Not accessed 1: Accessed Bit 0 EP0F: Endpoint 0 access interrupt request flag 0: Not accessed 1: Accessed UCC Register Bit 7 6 5 4 3 2 1 0 Name RCTRL — JSUSP SUSP2 USBCKEN EPS2 EPS1 EPS0 R/W R/W — R R/W R/W R/W R/W R/W POR 0 — 0 x 0 x x x "x": unknown Rev. 1.10 Bit 7 RCTRL: 7.5kΩ resistor between UDP and UBUS connection control 0: Disable – No 7.5kΩ resistor is connected between UDP and UBUS lines 1: Enable – 7.5kΩ resistor is connected between UDP and UBUS lines Bit 6 Unimplemented, read as "0" Bit 5 JSUSP: USB J-STATE Suspend mode Indication 0: USB interface is not in the J-STATE suspend mode 1: USB interface is in the J-STATE suspend mode This bit indicates whether the USB interface is in the J-STATE suspend mode or not. Bit 4 SUSP2: USB suspend mode current reduction control 0: Current reduction is disabled in suspend mode 1: Current reduction is enabled in suspend mode The current can be reduced to meet the USB standard specification if this bit is set to 1 when entering the suspend mode. Bit 3 USBCKEN: USB clock enable control 0: Disable 1: Enable Bit 2~0 EPS2~EPS0: Endpoint FIFO access selection 000: Endpoint 0 FIFO is selected 001: Endpoint 1 FIFO is selected 010: Endpoint 2 FIFO is selected 011: Endpoint 3 FIFO is selected 100: Endpoint 4 FIFO is selected 101: Endpoint 5 FIFO is selected 110: Endpoint 6 FIFO is selected 111: Endpoint 7 FIFO is selected 198 December 15, 2016 HT66FB570 A/D Flash USB MCU AWR Register The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is "00H". The address value extracted from the USB host command is immediately loaded into this register or not is determined by the ASET bit in the SIES register. Bit 7 6 5 4 3 2 1 0 Name AD6 AD5 AD4 AD3 AD2 AD1 AD0 WKEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~1 AD6~AD0: USB device address bit 6 ~ bit 0 Bit 0 WKEN: USB remote wake-up enable control 0: Disable 1: Enable STLI/STLO Registers The STLI/STLO registers show whether the corresponding endpoint has worked properly or not. As soon as an endpoint improper IN/OUT operation occurs, the related bit in the STLI/STLO registers has to be set high by application program. The STLI/STLO registers content will be cleared by a USB reset signal and a setup token event. • STLI Register Bit 7 6 5 4 3 2 1 0 Name STLI7 STLI6 STLI5 STLI4 STLI3 STLI2 STLI1 STLI0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0 STLI7~STLI0: USB endpoint n FIFO IN operation stall indication 0: Endpoint n FIFO IN operation is not stalled 1: Endpoint n FIFO IN operation is stalled The STLIn bit is set by user when the USB endpoint n is stalled. The STLIn bit is cleared by a USB reset signal. For endpoint 0 the STLI0 bit can also be cleared by a SETUP token. • STLO Register Bit 7 6 5 4 3 2 1 0 Name STLO7 STLO6 STLO5 STLO4 STLO3 STLO2 STLO1 — R/W R/W R/W R/W R/W R/W R/W R/W — POR x x x x x x x — "x": unknown Rev. 1.10 Bit 7~1 STLO7~STLO1: USB endpoint n FIFO OUT operation stall indication 0: Endpoint n FIFO OUT operation is not stalled 1: Endpoint n FIFO OUT operation is stalled The STLOn bit is set by user when the USB endpoint n is stalled. The STLOn bit is cleared by a USB reset signal. Bit 0 Unimplemented, read as "0" 199 December 15, 2016 HT66FB570 A/D Flash USB MCU SIES Register The SIES register is used to indicate the present signal state which the SIE receives and also controls whether the SIE changes the device address automatically or not. Bit 7 6 5 4 3 2 1 0 Name NMI UERR2 UERR1 UERR0 IN OUT UFERR ASET R/W R/W R/W R/W R/W R R/W R/W R/W POR x x x x x x x x "x": unknown Rev. 1.10 Bit 7 NMI: NAK token interrupt mask control 0: NAK token interrupt is not masked 1: NAK token interrupt is masked If this bit is set to 1, the interrupt will not be generated when the device sends a NAK token to the USB host. Otherwise, the endpoint n NAK token interrupt will be generated if the corresponding endpoint interrupt control is enabled when this bit is set to 0 and the device sends a NAK token to the USB host. Bit 6~4 UERR2~UERR0: USB SIE error status 0xx: No error 100: USB PID error 101: Bit stuffing error 110: CRC error 111: Host no response to SIE These bits indicate which kind of error is detected by the USB SIE. These bits are set by the USB SIE and cleared by the application program. Bit 3 IN: IN token indication 0: The received token packet is not IN token 1: The received token packet is IN token The IN bit is used to indicate whether the current token packet received from the USB host is IN token or not. Bit 2 OUT: OUT token indication 0: The received token packet is not OUT token 1: The received token packet is OUT token The OUT bit is used to indicate whether the token received from the USB host is OUT token or not except the OUT zero length token. This bit should be cleared to 0 by application program after an OUT data has been read. Note that this bit will also be cleared when the next valid SETUP token is received. Bit 1 UFERR: FIFO access error indication 0: No error occurs 1: Error occurs This bit is used to indicate whether the USB bus errors, such as CRC error, PID error or bit stuffing error, etc., has occurred or not when the FIFO is accessed. This bit is set by SIE and cleared by application program. Bit 0 ASET: Device address update method control 0: Device address is immediately updated when an address is written into the AWR register 1: Device address is updated after the device IN token data has completely been read by the USB host This bit is used to configure the SIE to automatically change the device address by the value stored in the AWR register. When this bit is set to "1" by firmware, the SIE will update the device address by the value stored in the AWR register after the USB host has successfully read the data from the device by an IN operation. Otherwise, when this bit is cleared to "0", the SIE will update the device address immediately after an address is written to the AWR register. Therefore, in order to operate properly, the firmware has to clear this bit after a next valid SETUP token is received. 200 December 15, 2016 HT66FB570 A/D Flash USB MCU MISC Register Bit 7 6 5 4 3 2 1 0 Name LEN0 READY SETCMD V33OS — CLEAR TX REQUEST R/W R R R/W R/W — R/W R/W R/W POR x x x 0 — x x x "x": unknown Rev. 1.10 Bit 7 LEN0: 0-sized packet indication flag 0: Not 0-sized packet 1: 0-sized packet This bit is used to show that the host sent a 0-sized packet to the MCU. It is set by Hardware and cleared by Firmware. It will also be cleared by hardware after the MCU receives a valid USB SETUP token. Bit 6 READY: Endpoint FIFO ready indication 0: The desired endpoint FIFO is not ready 1: The desired endpoint FIFO is ready Bit 5 SETCMD: SETUP command indication 0: The data in the FIFO is not SETUP token 1: The data in the FIFO is SETUP token This bit is set by hardware and cleared by application program. Bit 4 V33OS: Voltage select 0: Internal V33O voltage 1: External 3.3V LDO Bit 3 Unimplemented, read as "0" Bit 2 CLEAR: FIFO clear function enable control 0: No operation 1: Clear the requested endpoint FIFO This bit is used to clear the requested FIFO even if the corresponding FIFO is not ready. The CLEAR bit should be set to 1 to generate a positive pulse with a pulse width to clear the requested FIFO and then clear this bit to zero. After clearing the FIFO, the USB interface Out pipe endpoint can receive new data from Host and In pipe endpoint can transfer new data to Host. Bit 1 TX: Data transfer direction indication 0: MCU read data from the USB FIFO 1: MCU wirte data to the USB FIFO This bit defines the data transfer direction between the MCU and USB endpoint FIFO. When the TX bit is set to 1, it means that the MCU wants to write data to the USB endpoint FIFO. After the MCU write operation has completed, this bit has to be cleared to 0 before terminating the FIFO request to indicate the end of the data transfer. For a MCU read operation this bit has to be cleared to 0 to indicate that the MCU wants to read data from the USB endpoint FIFO. Then this bit has to be set to 1 before terminating the FIFO request to indicate the end of the data transfer after an MCU read operation completion. Bit 0 REQUEST: FIFO request control 0: No reqeust or request completion 1: Request desired FIFO This bit is used to request an operation of the desired endpoint FIFO. After selecting the desired endpoint FIFO, the FIFO can be requested by setting this bit high. Then this bit should be cleared to zero after the operation completion. 201 December 15, 2016 HT66FB570 A/D Flash USB MCU UFIEN Register Bit 7 6 5 4 3 2 1 0 Name SETI7 SETI6 SETI5 SETI4 SETI3 SETI2 SETI1 FIFO_DEF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 SETI7: Endpoint 7 input FIFO enable control 0: Disable 1: Enable Bit 6 SETI6: Endpoint 6 input FIFO enable control 0: Disable 1: Enable Bit 5 SETI5: Endpoint 5 input FIFO enable control 0: Disable 1: Enable Bit 4 SETI4: Endpoint 4 input FIFO enable control 0: Disable 1: Enable Bit 3 SETI3: Endpoint 3 input FIFO enable control 0: Disable 1: Enable Bit 2 SETI2: Endpoint 2 input FIFO enable control 0: Disable 1: Enable Bit 1 SETI1: Endpoint 1 input FIFO enable control 0: Disable 1: Enable Bit 0 FIFO_DEF: FIFO configuration redefine enable control 0: Disable 1: Enable If this bit is set to 1, the SIE will redefine the FIFO configuration. Then this bit will be automatically cleared to 0 by the SIE. UFOEN Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name SETO7 SETO6 SETO5 SETO4 SETO3 SETO2 SETO1 DATATG R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 SETO7: Endpoint 7 output FIFO enable control 0: Disable 1: Enable Bit 6 SETO6: Endpoint 6 output FIFO enable control 0: Disable 1: Enable Bit 5 SETO5: Endpoint 5 output FIFO enable control 0: Disable 1: Enable Bit 4 SETO4: Endpoint 4 output FIFO enable control 0: Disable 1: Enable Bit 3 SETO3: Endpoint 3 output FIFO enable control 0: Disable 1: Enable 202 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 2 SETO2: Endpoint 2 output FIFO enable control 0: Disable 1: Enable Bit 1 SETO1: Endpoint 1 output FIFO enable control 0: Disable 1: Enable Bit 0 DATATG: Data token toggle control 0: DATA0 will be sent first 1: DATA1 will be sent first This bit is used to select the Data token toggle bit. When this bit is cleared to 0, a DATA0 will first be sent in the following IN or OUT Data pipe for the requested endpoint FIFO. Otherwise, a DATA1 will be sent first followed by the successive IN or OUT data transfer. UFC0 Register Bit 7 6 5 4 3 2 1 0 Name E3FS1 E3FS0 E2FS1 E2FS0 E1FS1 E1FS0 — — R/W R/W R/W R/W R/W R/W R/W — — POR 0 0 0 0 0 0 — — Bit 7~6 E3FS1~E3SF0: Endpoint 3 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes Bit 5~4 E2FS1~E2SF0: Endpoint 2 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes Bit 3~2 E1FS1~E1SF0: Endpoint 1 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes Bit 1~0 Unimplemented, read as "0" UFC1 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name E7FS1 E7FS0 E6FS1 E6FS0 E5FS1 E5FS0 E4FS1 E4FS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 E7FS1~E7SF0: Endpoint 7 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes Bit 5~4 E6FS1~E6SF0: Endpoint 6 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes 203 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 3~2 E5FS1~E5SF0: Endpoint 5 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes Bit 1~0 E4FS1~E4SF0: Endpoint 4 FIFO size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes UFC2 Register Bit 7 6 5 4 3 2 1 0 Name — — — — E3ODB E3IDB E2ODB E2IDB R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 E3ODB: Endpoint 3 output FIFO size for single or double buffer selection 0: Single buffer 1: Double buffer Bit 2 E3IDB: Endpoint 3 input FIFO size for single or double buffer selection 0: Single buffer 1: Double buffer Bit 1 E2ODB: Endpoint 2 output FIFO size for single or double buffer selection 0: Single buffer 1: Double buffer Bit 0 E2IDB: Endpoint 2 input FIFO size for single or double buffer selection 0: Single buffer 1: Double buffer Note: This register will be reset only by power-on reset. FIFOn Registers The FIFOn Register is used for data transactions storages between the USB device and the USB host. The MCU reads data from or writes data to the FIFOn via the specific combination of the corresponding control and selection bits. Name Type POR Descriptions FIFO0 R/W xxxx xxxx Endpoint 0 Data Pipe FIFO1 R/W xxxx xxxx Endpoint 1 Data Pipe FIFO2 R/W xxxx xxxx Endpoint 2 Data Pipe FIFO3 R/W xxxx xxxx Endpoint 3 Data Pipe FIFO4 R/W xxxx xxxx Endpoint 4 Data Pipe FIFO5 R/W xxxx xxxx Endpoint 5 Data Pipe FIFO6 R/W xxxx xxxx Endpoint 6 Data Pipe FIFO7 R/W xxxx xxxx Endpoint 7 Data Pipe "x": unknown Rev. 1.10 204 December 15, 2016 HT66FB570 A/D Flash USB MCU USB Suspend Mode and Wake-Up USB Suspend Mode If there is no signal on the USB bus for over 3ms, the USB device will enter the suspend mode. The Suspend flag, SUSP, in the USC register will then be set high and an USB interrupt will be generated to indicate that the device should jump to the suspend state to meet the requirements of the USB suspend current specification. In order to meet the requirements of the suspend current; the firmware should disable the USB clock by clearing the USBCKEN bit to "0". The suspend mode current can be further decreased by setting the SUSP2 bit in the UCC register. USB Host Wake-up When the resume signal is asserted by the USB host, the device will be woken up by the USB interrupt and the RESUME bit in the USC register will be set. To ensure correct device operation, the application program should set the USBCKEN bit high and the USB host will start to communicate with the USB device. Then the SUSP2 bit will be cleared low together with the RESUME bit when the USB device actually leaves the suspend mode. Therefore, when the device detects the suspend bit, SUSP2, the resume bit, RESUME, should be monitored and taken into consideration. SUSP RESUME USB_INT Suspend and Host Wake-up USB Remote Wake-up As the USB device has a remote wake-up function, the USB device can wake up the USB host by sending a remote wake-up pulse which is generated by setting the RMWK bit high. Once the USB host receives a remote wake-up signal from the USB device, the host will send a resume signal to device. SUSP 1 USB Clo�k (Min.) RMWK RESUME �.��s (Min.) USB_INT Suspend and Remote Wake-up Rev. 1.10 205 December 15, 2016 HT66FB570 A/D Flash USB MCU USB Interrupts Several USB conditions can generate an USB interrupt. When one of these conditions exists, an interrupt pulse will be generated to get the attention of the microcontroller. These conditions are the USB suspended, USB resumed, USB reset and USB endpoint FIFO access events. When the USB interrupt caused by any of these conditions occurs, if the corresponding interrupt control is enabled and the stack is not full, the program will jump to the corresponding interrupt vector where it can be serviced before returning to the main program. For the USB Endpoint FIFO access event, there are the corresponding indication flags to indicate which endpoint FIFO is accessed. As the Endpoint FIFO access flag is set, it will generate a USB interrupt if the associated Endpoint FIFO pipe and interrupt control are both enabled. The Endpoint FIFO access flags should be cleared by the application program. As the USB suspended or USB resume condition occurs, the corresponding indication flag, known as SUSP and RESUME bits, will be set and a USB interrupt will directly generate without enabling the associated interrupt control bit. The SUSP and RESUME bits are read only and set or cleared by the USB SIE. For a USB interrupt occurred to be serviced, in addition to the bits for the corresponding interrupt enable control in USB module being set, the global interrupt enable control and the related interrupt enable control bits in the host MCU must also be set. If these bits are not set, then no interrupt will be serviced. Rev. 1.10 206 December 15, 2016 HT66FB570 A/D Flash USB MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0~INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs, Comparators, LVD and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers falls into three categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the MFI0~MFI5 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag EMI — — INTn Pin INTnE INTnF n=0 or 1 USB USBE USBF — Comparator CPnE CPnF n=0 or 1 — Global Notes SIM SIME SIMF SPIA SPIAE SPIAF — Time Base TBnE TBnF n=0 or 1 Multi-function MFnE MFnF n=0~5 A/D Converter ADE ADF — UART URE URF — EEPROM DEE DEF — LVD STM PTM LVE LVF — STMPE STMPF — STMAE STMAF — PTMnPE PTMnPF PTMnAE PTMnAF n=0~4 Interrupt Register Bit Naming Conventions Rev. 1.10 207 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit Register Name 7 INTEG — — INTC0 — USBF 6 5 4 3 2 1 0 — — INT1S1 INT1S0 INT0S1 INT0S0 INT1F INT0F USBE INT1E INT0E EMI INTC1 MF1F MF0F CP1F CP0F MF1E MF0E CP1E CP0E INTC2 SIMF MF4F MF3F MF2F SIME MF4E MF3E MF2E INTC3 MF5F TB1F TB0F SPIAF MF5E TB1E TB0E SPIAE MFI0 — — STMAF STMPF — — STMAE STMPE MFI1 — — PTM0AF PTM0PF — — PTM0AE PTM0PE MFI2 — — PTM1AF PTM1PF — — PTM1AE PTM1PE MFI3 — — PTM2AF PTM2PF — — PTM2AE PTM2PE MFI4 PTM4AF PTM4PF PTM3AF PTM3PF PTM4AE PTM4PE PTM3AE PTM3PE MFI5 DEF ADF URF LVF DEE ADE URE LVE Interrupt Registers List INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~2 INT1S1~INT1S0: Interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 1~0 INT0S1~INT0S0: Interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges INTC0 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — USBF INT1F INT0F USBE INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 USBF: USB interrupt request flag 0: No request 1: Interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4 INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request 208 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 3 USBE: USB interrupt control 0: Disable 1: Enable Bit 2 INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 1 INT0E: INT0 interrupt control 0: Disable 1: Enable Bit 0 EMI: Global interrupt control 0: Disable 1: Enable INTC1 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name MF1F MF0F CP1F CP0F MF1E MF0E CP1E CP0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 MF1F: Multi-function interrupt 1 request flag 0: No request 1: Interrupt request Bit 6 MF0F: Multi-function interrupt 0 request flag 0: No request 1: Interrupt request Bit 5 CP1F: Comparator 1 interrupt request flag 0: No request 1: Interrupt request Bit 4 CP0F: Comparator 0 interrupt request flag 0: No request 1: Interrupt request Bit 3 MF1E: Multi-function interrupt 1 interrupt control 0: Disable 1: Enable Bit 2 MF0E: Multi-function interrupt 0 interrupt control 0: Disable 1: Enable Bit 1 CP1E: Comparator 1 interrupt control 0: Disable 1: Enable Bit 0 CP0E: Comparator 0 interrupt control 0: Disable 1: Enable 209 December 15, 2016 HT66FB570 A/D Flash USB MCU INTC2 Register Bit 7 6 5 4 3 2 1 0 Name SIMF MF4F MF3F MF2F SIME MF4E MF3E MF2E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 SIMF: SIM interrupt request flag 0: No request 1: Interrupt request Bit 6 MF4F: Multi-function interrupt 4 request flag 0: No request 1: Interrupt request Bit 5 MF3F: Multi-function interrupt 3 request flag 0: No request 1: Interrupt request Bit 4 MF2F: Multi-function interrupt 2 request flag 0: No request 1: Interrupt request Bit 3 SIME: SIM interrupt control 0: Disable 1: Enable Bit 2 MF4E: Multi-function interrupt 4 control 0: Disable 1: Enable Bit 1 MF3E: Multi-function interrupt 3 control 0: Disable 1: Enable Bit 0 MF2E: Multi-function interrupt 2 control 0: Disable 1: Enable INTC3 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name MF5F TB1F TB0F SPIAF MF5E TB1E TB0E SPIAE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 MF5F: Multi-function interrupt 5 request flag 0: No request 1: Interrupt request Bit 6 TB1F: Time Base1 interrupt request flag 0: No request 1: Interrupt request Bit 5 TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 4 SPIAF: SPIA interrupt request flag 0: No request 1: Interrupt request Bit 3 MF5E: Multi-function interrupt 5 control 0: No request 1: Interrupt request 210 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 2 TB1E: Time Base1 interrupt control 0: Disable 1: Enable Bit 1 TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 0 SPIAE: SPIA interrupt control 0: Disable 1: Enable MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — STMAF STMPF — — STMAE STMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 STMAF: STM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 STMPF: STM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 STMAE: STM Comparator A match interrupt control 0: Disable 1: Enable Bit 0 STMPE: STM Comparator P match interrupt control 0: Disable 1: Enable MFI1 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — PTM0AF PTM0PF — — PTM0AE PTM0PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 PTM0AF: PTM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 PTM0PF: PTM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 PTM0AE: PTM0 Comparator A match interrupt control 0: Disable 1: Enable Bit 0 PTM0PE: PTM0 Comparator P match interrupt control 0: Disable 1: Enable 211 December 15, 2016 HT66FB570 A/D Flash USB MCU MFI2 Register Bit 7 6 5 4 3 2 1 0 Name — — PTM1AF PTM1PF — — PTM1AE PTM1PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 PTM1AF: PTM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 PTM1PF: PTM1 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 PTM1AE: PTM1 Comparator A match interrupt control 0: Disable 1: Enable Bit 0 PTM1PE: PTM1 Comparator P match interrupt control 0: Disable 1: Enable MFI3 Register Bit 7 6 5 4 3 2 1 0 Name — — PTM2AF PTM2PF — — PTM2AE PTM2PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 PTM2AF: PTM2 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 PTM2PF: PTM2 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 PTM2AE: PTM2 Comparator A match interrupt control 0: Disable 1: Enable Bit 0 PTM2PE: PTM2 Comparator P match interrupt control 0: Disable 1: Enable MFI4 Register Bit 7 6 5 4 3 2 1 0 Name PTM4AF PTM4PF PTM3AF PTM3PF PTM4AE PTM4PE PTM3AE PTM3PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 Rev. 1.10 PTM4AF: PTM4 Comparator A match interrupt request flag 0: No request 1: Interrupt request 212 December 15, 2016 HT66FB570 A/D Flash USB MCU Bit 6 PTM4PF: PTM4 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 5 PTM3AF: PTM3 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 PTM3PF: PTM3 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3 PTM4AE: PTM4 Comparator A match interrupt control 0: Disable 1: Enable Bit 2 PTM4PE: PTM4 Comparator P match interrupt control 0: Disable 1: Enable Bit 1 PTM3AE: PTM3 Comparator A match interrupt control 0: Disable 1: Enable Bit 0 PTM3PE: PTM3 Comparator P match interrupt control 0: Disable 1: Enable MFI5 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name DEF ADF URF LVF DEE ADE URE LVE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 6 ADF: A/D Converter interrupt request flag 0: No request 1: Interrupt request Bit 5 URF: UART interrupt request flag 0: No request 1: Interrupt request Bit 4 LVF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 3 DEE: Data EEPROM interrupt control 0: Disable 1: Enable Bit 2 ADE: A/D Converter interrupt control 0: Disable 1: Enable Bit 1 URE: UART interrupt control 0: Disable 1: Enable Bit 0 LVE: LVD interrupt control 0: Disable 1: Enable 213 December 15, 2016 HT66FB570 A/D Flash USB MCU Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A match or A/D conversion completion etc., the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.10 214 December 15, 2016 HT66FB570 A/D Flash USB MCU xxF xxF xxE Legend Request Flag� no auto �eset in ISR Request Flag� auto �eset in ISR Inte��upt Na�e Request Flags Ena�le Bits Maste� Ena�le Vector Ena�le Bits INT0 Pin INT0F INT0E EMI 04H INT1 Pin INT1F INT1E EMI 08H USB USBF USBE EMI 0CH Co�p.0 CP0F CP0E EMI 10H Co�p.1 CP1F CP1E EMI 14H M. Fun�t. 0 MF0F MF0E EMI 18H M. Fun�t. 1 MF1F MF1E EMI 1CH M. Fun�t. � MF�F MF�E EMI �0H M. Fun�t. 3 MF3F MF3E EMI �4H M. Fun�t. 4 MF4F MF4E EMI �8H SIM SIMF SIME EMI �CH Inte��upt Na�e Request Flags Ena�le Bits Inte��upts �ontained within Multi-Fun�tion Inte��upts EMI auto disa�led in ISR P�io�ity High STM P STMPF STMPE STM A STMAF STMAE PTM0 P PTM0PF PTM0PE PTM0 A PTM0AF PTM0AE PTM1 P PTM1PF PTM1PE PTM1 A PTM1AF PTM1AE PTM� P PTM�PF PTM�PE PTM� A PTM�AF PTM�AE PTM3 P PTM3PF PTM3PE PTM3 A PTM3AF PTM3AE PTM4 P PTM4PF PTM4PE PTM4 A PTM4AF PTM4AE SPIA SPIAF SPIAE EMI 30H LVD LVF LVE Ti�e Base 0 TB0F TB0E EMI 34H EEPROM DEF DEE Ti�e Base 1 TB1F TB1E EMI 38H UART URF URE A/D ADF ADE M. Fun�t. � MF�F MF�E EMI 3CH Low Interrupt Structure Rev. 1.10 215 December 15, 2016 HT66FB570 A/D Flash USB MCU External Interrupts The external interrupts are controlled by signal transitions on the pins INT0 and INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. USB Interrupt Several USB conditions can generate a USB interrupt. When one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller. These conditions are the USB suspended, USB resumed, USB reset and USB endpoint FIFO access events. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and USB interrupt enable bit, USBE, must first be set. When the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the USB interrupt vector, will take place. When the interrupt is serviced, the USB interrupt request flag, USBF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Comparator Interrupts The comparator interrupts are controlled by the two internal comparators. A comparator interrupt request will take place when the comparator interrupt request flag, CPnF, is set, a situation that will occur when the comparator output bit changes state. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bit, CPnE, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced, the comparator interrupt request flag, CPnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Rev. 1.10 216 December 15, 2016 HT66FB570 A/D Flash USB MCU SIM Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface, or an I2C slave address match occurs, or an I2C bus timeout occurs. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the stack is not full and any of the above described situations occurs, a subroutine call to the respective Interrupt vector, will take place. When the interrupt is serviced, the Serial Interface Interrupt flag, SIMF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. SPIA Interrupt The Serial Peripheral Interface Interrupt, also known as the SPIA interrupt, will take place when the SPIA Interrupt request flag, SPIAF, is set, which occurs when a byte of data has been received or transmitted by the SPIA interface or an SPIA incomplete transfer occurs. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SPIAE, must first be set. When the interrupt is enabled, the stack is not full and any of the above described situations occurs, a subroutine call to the respective Interrupt vector, will take place. When the interrupt is serviced, the Serial Interface Interrupt flag, SPIAF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fPSC, originates from the internal clock source fSYS, fSYS/4 or fSUB and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the Time Base interrupt period is selected using the CLKSEL1~CLKSEL0 bits in the PSCR register. TB0[�:0] TB0ON fPSC/�8 ~ fPSC/�1� fSYS fSYS/4 fSUB M U X fPSC CLKSEL[1:0] M U X Ti�e Base 0 Inte��upt M U X Ti�e Base 1 Inte��upt P�es�ale� fPSC/�8 ~ fPSC/�1� TB1ON TB1[�:0] Time Base Interrupts Rev. 1.10 217 December 15, 2016 HT66FB570 A/D Flash USB MCU PSCR Register Bit 7 6 5 4 3 2 Name — — — — — — R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CLKSEL1~CLKSEL0: Prescaler clock source selection 00: fSYS 01: fSYS/4 1x: fSUB 1 0 CLKSEL1 CLKSEL0 TB0C Register Bit 7 6 5 4 3 2 1 0 Name TB0ON — — — — TB02 TB01 TB00 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7 TB0ON: Time Base 0 Control 0: Disable 1: Enable Bit 6~3 Unimplemented, read as "0" Bit 2~0 TB02~TB00: Select Time Base 0 Time-out Period 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC TB1C Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name TB1ON — — — — TB12 TB11 TB10 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7 TB1ON: Time Base 1 Control 0: Disable 1: Enable Bit 6~3 Unimplemented, read as "0" Bit 2~0 TB12~TB10: Select Time Base 1 Time-out Period 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC 218 December 15, 2016 HT66FB570 A/D Flash USB MCU Multi-function Interrupts Within the device there are up to six Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts, A/D Converter Interrupt, UART Interrupt, EEPROM Interrupt and LVD Interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts will not be automatically reset and must be manually reset by the application program. A/D Converter Interrupt The A/D Converter Interrupt is contained within the Multi-function Interrupt. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the Multi-function Interrupt vector, will take place. When the A/D Converter Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the ADF flag will not be automatically cleared, it has to be cleared by the application program. UART Interrupt The UART interrupt is contained within the Multi-function Interrupt. Several individual UART conditions can generate a UART interrupt. When one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, EMI, multi-function enable bit, MFnE and UART interrupt enable bit, URE, must first be set. When the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the UART Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the URF flag will not be automatically cleared, it has to be cleared by the application program. However, the USR register flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART section. Rev. 1.10 219 December 15, 2016 HT66FB570 A/D Flash USB MCU EEPROM Interrupt The EEPROM interrupt is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupts The Standard and Periodic Type TMs have two interrupts, one comes from the comparator A match situation and the other comes from the comparator P match situation. All of the TM interrupts are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt request flags and two enable control bits. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Rev. 1.10 220 December 15, 2016 HT66FB570 A/D Flash USB MCU Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator output bit change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.10 221 December 15, 2016 HT66FB570 A/D Flash USB MCU Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Crystal Mode Frequency Option 1 Clock Mode Frequency: 1. 12MHz 2. 6MHz Application Circuits PD0 OSC1 PD1 OSC� Inte�nal RC Os�illato� 1�MHz VDD OSC1 100kΩ 0.1µF 500Ω VDD/AVDD/HVDD RES/ICPCK 10kΩ 0.1µF VSS/AVSS OSC Ci��uit XT Ci��uit PD0/PTP�/PTP�I/OSC1 OSC� UBUS UDN/OD0 UDP/OD1 V33O PD�/PTCK1 PD3/PTCK3 PD4/PTCK� PD�/PTP0/PTP0I PD7/PTP1/PTP1I PD�/PTP�/PTP�I PD1/PTP1/PTP1I/OSC� PA0/PTCK0 PA1/SDOA/C0X PA�/SDIA/C0+ PE4/XT� PA3/SCKA/C0PA4/SCSA/STP/STPI/C1X PE3/XT1 PA�/PTP0/PTP0I/C1+ PA�/STCK/C1PA7/INT0/AN7 PB7/PTP4/PTP4I/AN8 PB�/INT1/AN� PB�/AN� PE0/VDDIO/VREF PB4/STP/STPI/AN4 PE�/AN17 PB3/SCS/AN3 PE�/AN1� PB�/SCK/AN� PE�~PE7 PB1/SDI/SCL/AN1 PB0/SDO/SDA/AN0 PF0/PTP3/PTP3I PF1/PTP3/PTP3I PC0/PTP4/PTP4I/AN8 PF�~PF7 PC1/PTCK4/AN9 C�ystal Os�illato� �/1�MHz (USB Mode) OSC Circuit PE3 XT1 PE4 XT� XT1 3�7�8Hz XT� Inte�nal RC Os�illato� 3�kHz C�ystal Os�illato� 3�7�8Hz XT Circuit PC�/AN10~PC3/AN11 PG0~PG� PC4/TX/AN1� PG3/AN�3~PG7/AN19 PC�/RX/AN13 PC�/AN14~PC7/AN1� Rev. 1.10 222 December 15, 2016 HT66FB570 A/D Flash USB MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.10 223 December 15, 2016 HT66FB570 A/D Flash USB MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one Bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry Bit from where it can be examined and the necessary serial Bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual Bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data Bits. Bit Operations The ability to provide single Bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port Bit programming where individual Bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-Bit output port, manipulate the input data to ensure that other Bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these Bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.10 224 December 15, 2016 HT66FB570 A/D Flash USB MCU Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected 1 1Note 1 1 1Note 1 1 1Note 1 1 1Note 1Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic Add Data Memory to ACC ADD A,[m] ADDM A,[m] Add ACC to Data Memory ADD A,x Add immediate data to ACC ADC A,[m] Add Data Memory to ACC with Carry ADCM A,[m] Add ACC to Data memory with Carry SUB A,x Subtract immediate data from the ACC SUB A,[m] Subtract Data Memory from ACC SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory SBC A,x Subtract immediate data from ACC with Carry SBC A,[m] Subtract Data Memory from ACC with Carry SBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory DAA [m] Decimal adjust ACC for Addition with result in Data Memory Logic Operation AND A,[m] Logical AND Data Memory to ACC OR A,[m] Logical OR Data Memory to ACC XOR A,[m] Logical XOR Data Memory to ACC ANDM A,[m] Logical AND ACC to Data Memory ORM A,[m] Logical OR ACC to Data Memory XORM A,[m] Logical XOR ACC to Data Memory AND A,x Logical AND immediate Data to ACC OR A,x Logical OR immediate Data to ACC XOR A,x Logical XOR immediate Data to ACC CPL [m] Complement Data Memory CPLA [m] Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.10 225 December 15, 2016 HT66FB570 A/D Flash USB MCU Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None None 2Note None 1 1Note 1Note 1 1Note 1 1 None None None TO, PDF None None TO, PDF Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m] SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if Data Memory is not zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt Table Read Operation TABRD [m] Read table (specific page) to TBLH and Data Memory Miscellaneous NOP CLR [m] SET [m] CLR WDT SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT" instruction the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after the "CLR WDT" instructions is executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 226 December 15, 2016 HT66FB570 A/D Flash USB MCU Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected 2 2Note 2 2Note 2 2Note 2 2Note 2Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 2 2 2 2Note 2Note 2Note 2Note 2 Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 2 2Note 2 2Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 2 2Note 2 2Note 2 2Note 2 2Note None None C C None None C C Move Data Memory to ACC Move ACC to Data Memory 2 2Note None None Clear bit of Data Memory Set bit of Data Memory 2Note 2Note None None Arithmetic Add Data Memory to ACC LADD A,[m] LADDM A,[m] Add ACC to Data Memory LADC A,[m] Add Data Memory to ACC with Carry LADCM A,[m] Add ACC to Data memory with Carry LSUB A,[m] Subtract Data Memory from ACC LSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory LSBC A,[m] Subtract Data Memory from ACC with Carry LSBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory LDAA [m] Decimal adjust ACC for Addition with result in Data Memory Logic Operation LAND A,[m] Logical AND Data Memory to ACC LOR A,[m] Logical OR Data Memory to ACC LXOR A,[m] Logical XOR Data Memory to ACC LANDM A,[m] Logical AND ACC to Data Memory LORM A,[m] Logical OR ACC to Data Memory LXORM A,[m] Logical XOR ACC to Data Memory LCPL [m] Complement Data Memory LCPLA [m] Complement Data Memory with result in ACC Increment & Decrement LINCA [m] LINC [m] LDECA [m] LDEC [m] Rotate LRRA [m] LRR [m] LRRCA [m] LRRC [m] LRLA [m] LRL [m] LRLCA [m] LRLC [m] Data Move LMOV A,[m] LMOV [m],A Bit Operation LCLR [m].i LSET [m].i Rev. 1.10 227 December 15, 2016 HT66FB570 A/D Flash USB MCU Mnemonic Description Cycles Flag Affected Branch LSZ [m] LSZA [m] LSNZ [m] LSZ [m].i LSNZ [m].i LSIZ [m] LSDZ [m] LSIZA [m] LSDZA [m] Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if Data Memory is not zero Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note None None None None None None None None None Read table to TBLH and Data Memory 3Note None 2Note 2Note 2Note 2 None None None None Table Read LTABRD [m] Miscellaneous LCLR [m] LSET [m] LSWAP [m] LSWAPA [m] Clear Data Memory Set Data Memory Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. Any extended instruction which changes the contents of the PCL register will also require three cycles for execution. Rev. 1.10 228 December 15, 2016 HT66FB570 A/D Flash USB MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC ADD A,x Description Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C, SC Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.10 Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z 229 December 15, 2016 HT66FB570 A/D Flash USB MCU Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CALL addr Description Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) CPLA [m] Description Operation Affected flag(s) DAA [m] Description Operation Affected flag(s) Rev. 1.10 Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C 230 December 15, 2016 HT66FB570 A/D Flash USB MCU DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z Operation Affected flag(s) Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z HALT Description Operation Operation Affected flag(s) Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None JMP addr Description Rev. 1.10 231 December 15, 2016 HT66FB570 A/D Flash USB MCU NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z Operation Affected flag(s) OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) Rev. 1.10 Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None 232 December 15, 2016 HT66FB570 A/D Flash USB MCU RLA [m] Description Operation Affected flag(s) RLC [m] Description Operation Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) Rev. 1.10 Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C 233 December 15, 2016 HT66FB570 A/D Flash USB MCU RRCA [m] Description Operation Affected flag(s) SBC A,[m] Description Operation Affected flag(s) SBC A, x Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) SDZA [m] Description Operation Affected flag(s) Rev. 1.10 Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ Subtract immediate data from ACC with Carry The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC - [m] - C OV, Z, AC, C, SC, CZ Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None 234 December 15, 2016 HT66FB570 A/D Flash USB MCU SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SNZ [m] Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) Rev. 1.10 Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m]≠ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ 235 December 15, 2016 HT66FB570 A/D Flash USB MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C, SC, CZ SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SUB A,x Description Operation Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) Rev. 1.10 Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None 236 December 15, 2016 HT66FB570 A/D Flash USB MCU TABRD [m] Description Operation Affected flag(s) XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Rev. 1.10 Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z 237 December 15, 2016 HT66FB570 A/D Flash USB MCU Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Description Operation Affected flag(s) LADCM A,[m] Description Operation Affected flag(s) LADD A,[m] Description Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC LADDM A,[m] Description Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC Operation Affected flag(s) LAND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z LCLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None LCLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None LANDM A,[m] Description Rev. 1.10 238 December 15, 2016 HT66FB570 A/D Flash USB MCU LCPL [m] Description Operation Affected flag(s) LCPLA [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C LDEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z LDECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z LINC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z LINCA [m] Description Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z LDAA [m] Description Operation Operation Affected flag(s) Rev. 1.10 239 December 15, 2016 HT66FB570 A/D Flash USB MCU LMOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None LMOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None LOR A,[m] Description Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z Operation Affected flag(s) LORM A,[m] Description Operation Affected flag(s) LRL [m] Description Operation Affected flag(s) LRLA [m] Description Operation Affected flag(s) LRLC [m] Description Operation Affected flag(s) LRLCA [m] Description Operation Affected flag(s) Rev. 1.10 Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C 240 December 15, 2016 HT66FB570 A/D Flash USB MCU LRR [m] Description Operation Affected flag(s) LRRA [m] Description Operation Affected flag(s) LRRC [m] Description Operation Affected flag(s) LRRCA [m] Description Operation Affected flag(s) LSBC A,[m] Description Operation Affected flag(s) LSBCM A,[m] Description Operation Affected flag(s) Rev. 1.10 Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ 241 December 15, 2016 HT66FB570 A/D Flash USB MCU LSDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None LSET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None LSET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None LSIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None LSDZA [m] Description Operation Operation Affected flag(s) LSIZA [m] Description Operation Affected flag(s) LSNZ [m].i Description Operation Affected flag(s) Rev. 1.10 Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None 242 December 15, 2016 HT66FB570 A/D Flash USB MCU LSNZ [m] Description Operation Affected flag(s) LSUB A,[m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m] ≠ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ LSWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None LSWAPA [m] Description Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None LSUBM A,[m] Description Operation Affected flag(s) LSZ [m] Description Operation Affected flag(s) LSZA [m] Description Operation Affected flag(s) Rev. 1.10 Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None 243 December 15, 2016 HT66FB570 A/D Flash USB MCU LSZ [m].i Description Operation Affected flag(s) LTABRD [m] Description Operation Affected flag(s) LXOR A,[m] Description Operation Affected flag(s) LXORM A,[m] Description Operation Affected flag(s) Rev. 1.10 Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z 244 December 15, 2016 HT66FB570 A/D Flash USB MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • The Operation Instruction of Packing Materials • Carton information Rev. 1.10 245 December 15, 2016 HT66FB570 A/D Flash USB MCU 48-pin LQFP (7mm×7mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.020 BSC — D2 0.170 — 0.205 E2 0.079 — — F 0.007 0.009 0.011 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.10 Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.50 BSC — D2 4.31 — 5.21 E2 2.00 — — F 0.17 0.22 0.27 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 246 December 15, 2016 HT66FB570 A/D Flash USB MCU 64-pin LQFP (7mm×7mm) Outline Dimensions Symbol Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.016 BSC — F 0.005 0.007 0.009 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.10 Dimensions in inch Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.40 BSC — F 0.13 0.18 0.23 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 247 December 15, 2016 HT66FB570 A/D Flash USB MCU Copyright© 2016 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 248 December 15, 2016