AD AD8327 5 v catv line driver coarse step output power control Datasheet

a
FEATURES
Supports DOCSIS Standard for Reverse Path
Transmission
Gain Programmable in 6.02 dB Steps over a 48.16 dB
Range
Low Distortion at 60 dBmV Output
–63 dBc SFDR at 21 MHz
–57 dBc SFDR at 42 MHz
Output Noise Level
–47 dBmV in 160 kHz
Maintains 75 ⍀ Output Impedance
Transmit Enable and Transmit Disable Modes
Upper Bandwidth: 160 MHz (Full Gain Range)
5 V Supply Operation
Supports SPI Interfaces
5 V CATV Line Driver Coarse Step
Output Power Control
AD8327
FUNCTIONAL BLOCK DIAGRAM
VCC (5 PINS)
VIN+
DIFF OR
SINGLE
INPUT
AMP
VIN–
Distortion performance of –63 dBc is achieved with an output
level up to 60 dBmV at 21 MHz bandwidth. A key performance
and cost advantage of the AD8327 results from the ability to
maintain a constant 75 Ω output impedance during Transmit
Enable and Transmit Disable conditions. In addition, this
device has a sleep mode function that reduces the quiescent
current to 5 mA.
ATTENUATION
CORE
VERNIER
POWER
AMP
VOUT
ZOUT = 75⍀
8
DECODE
R2
ZIN (SINGLE) = 800⍀
ZIN (DIFF) = 1.6k⍀
8
DATA LATCH
POWER-DOWN
LOGIC
CXR
8
SHIFT
REGISTER
DATEN
DATA
CLK
GND (5 PINS)
TXEN
SLEEP
–50
GENERAL DESCRIPTION
VOUT = 60dBmV @ MAX GAIN
–55
DISTORTION – dBc
The AD8327 comprises a digitally controlled variable attenuator
of 0 dB to –48.16 dB, which is preceded by a low noise, fixed
gain buffer and followed by a low distortion, high power amplifier.
The AD8327 accepts a differential or single-ended input
signal. The output is specified for driving a 75 Ω load, such
as coaxial cable.
AD8327
R1
APPLICATIONS
Gain-Programmable Line Driver
DOCSIS High-Speed Data Modems
Interactive Cable Set-Top Boxes
PC Plug-in Cable Modems
General-Purpose Digitally Controlled Variable Gain Block
The AD8327 is a low-cost, digitally controlled, variable gain
amplifier optimized for coaxial line driving applications such as
cable modems that are designed to the MCNS-DOCSIS
upstream standard. An 8-bit serial word determines the desired
output gain over a 48.16 dB range resulting in gain changes of
6.02 dB/major carry.
BYP
HD3
–60
HD2
–65
–70
–75
5
15
25
35
45
55
FUNDAMENTAL FREQUENCY – MHz
65
Figure 1. Harmonic Distortion vs. Frequency
The AD8327 is packaged in a low-cost 20-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD8327–SPECIFICATIONS (T = 25ⴗC, V = 5 V, R = 75 ⍀, V
A
Parameter
INPUT CHARACTERISTICS
Specified AC Voltage
Noise Figure
Input Resistance
S
L
IN(DIFFERENTIAL)
Conditions
= 30 dBmV)
Min
POUT = 60 dBmV, Max Gain
Max Gain, f = 10 MHz
Single-Ended Input
Differential Input
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB)
Bandwidth Roll-Off
Bandwidth Peaking
Output Noise Spectral Density
1 dB Compression Point
Differential Output Impedance
OVERALL PERFORMANCE
Second Order Harmonic Distortion
Third Order Harmonic Distortion
Adjacent Channel Power
Gain Linearity Error
Output Settling
Due to Gain Change (TGS)
Due to Input Change
Isolation in Transmit Disable Mode
POWER CONTROL
Transmit Enable Settling Time (TON)1
Transmit Disable Settling Time (TOFF)1
Transmit Enable Settling Time (TON)2
Transmit Disable Settling Time (TOFF)2
Between Burst Transients2
Gain Code = 10000000 (128 Decimal)
Gain Code = 00000000 (0 Decimal)
47.16
29
–19.16
48.16
30
–18.16
6.02
All Gain Codes
f = 65 MHz
All Gain Codes
Max Gain, f = 10 MHz
160
0.4
0
–32
Min Gain, f = 10 MHz
–47
Transmit Disable Mode (TXEN = 0),
f = 10 MHz
Max Gain, f = 10 MHz
Transmit Enable (TXEN = 1) and
Transmit Disable Mode (TXEN = 0)
–66
f = 21 MHz, VOUT = 60 dBmV @ Max Gain
f = 42 MHz, VOUT = 60 dBmV @ Max Gain
f = 65 MHz, VOUT = 60 dBmV @ Max Gain
f = 21 MHz, VOUT = 60 dBmV @ Max Gain
f = 42 MHz, VOUT = 60 dBmV @ Max Gain
f = 65 MHz, VOUT = 60 dBmV @ Max Gain
Adjacent Channel Width = Transmit Channel
Width = 160 KSYM/SEC
f = 10 MHz, Code to Code
Unit
dBmV
dB
Ω
Ω
pF
49.16 dB
31
dB
–17.16 dB
dB/Major
Carry
14.8
MHz
dB
dB
dBmV in
160 kHz
dBmV in
160 kHz
dBmV in
160 kHz
dBm
75 ± 20%
Ω
–63
–61
–54
–63
–57
–57
–62
dBc
dBc
dBc
dBc
dBc
dBc
dBc
± 0.25
dB
Min to Max Gain
Max Gain, VIN = 30 dBmV
Max Gain, TXEN = 0 V, f = 42 MHz,
VIN = 30 dBmV
60
30
–52
ns
ns
dBc
Max Gain, VIN = 0 V
Max Gain, VIN = 0 V
Max Gain, VIN = 0 V
Max Gain, VIN = 0 V
Equivalent Output = 31 dBmV
Equivalent Output = 60 dBmV
300
40
2
1.7
3
25
2
ns
ns
µs
µs
mV p-p
mV p-p
µs
Ramp Setting2
POWER SUPPLY
Operating Range
Quiescent Current
Max
30
13.2
800
1600
2
Input Capacitance
GAIN CONTROL INTERFACE
Gain Range
Maximum Gain
Minimum Gain
Gain Scaling Factor
Typ
Transmit Enable Mode (TXEN = 1) @ Dec 128
Transmit Enable Mode (TXEN = 1) @ Dec 0
Transmit Disable Mode @ All Gain Codes
Sleep Mode @ All Gain Codes
OPERATING TEMPERATURE
RANGE
4.75
75
40
10
3
–40
5
105
60
15
5
5.25
135
80
20
7
V
mA
mA
mA
mA
+85
°C
NOTES
1
For Transmit Enable or Transmit Disable transitions using a 0 pF capacitor (at CXR pin) to ground.
2
For Transmit Enable or Transmit Disable transitions using a 100 pF capacitor (at CXR pin) to ground.
Specifications subject to change without notice.
–2–
REV. 0
AD8327
LOGIC INPUTS (TTL/CMOS-Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, V
Parameter
Min
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN
Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN
Logic “1” Current (VINH = 5 V) TXEN
Logic “0” Current (VINL = 0 V) TXEN
Logic “1” Current (VINH = 5 V) SLEEP
Logic “0” Current (VINL = 0 V) SLEEP
2.1
0
0
–600
50
–250
50
–250
TIMING REQUIREMENTS
Typ
= 5 V: Full Temperature Range)
Max
Unit
5.0
0.8
20
–100
190
–30
190
–30
V
V
nA
nA
µA
µA
µA
µA
(Full Temperature Range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
Parameter
Min
Clock Pulsewidth (tWH)
Clock Period (tC)
Setup Time SDATA vs. Clock (tDS)
Setup Time DATEN vs. Clock (tES)
Hold Time SDATA vs. Clock (tDH)
Hold Time DATEN vs. Clock (tEH)
Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)
16.0
32.0
5.0
15.0
5.0
3.0
Typ
tDS
VALID DATA WORD G1
MSB. . . .LSB
SDATA
VALID DATA WORD G2
tC
tWH
CLK
tES
tEH
8 CLOCK
CYCLES
DATEN
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
tOFF
TXEN
tGS
tON
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
VALID DATA BIT
SDATA MSB
MSB-1
tDS
MSB-2
tDH
CLK
Figure 3. SDATA Timing
REV. 0
CC
–3–
Max
Unit
10
ns
ns
ns
ns
ns
ns
ns
AD8327
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage +VS
Pins 4, 6, 11, 12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltages
Pins 17, 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.5 V
Pins 1, 2, 3, 19, 20 . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 mW
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
SDATA
1
20
DATEN
CLK
2
19
SLEEP
TXEN
3
18
VIN–
VCC
4
17
VIN+
GND
5
VCC
AD8327
16 VCC
TOP VIEW
6 (Not to Scale) 15 GND
CXR
7
14 BYP
GND
8
13 GND
GND
9
12
VCC
VOUT 10
11
VCC
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
SDATA
2
CLK
3
4, 6, 11, 12, 16
5, 8, 9, 13, 15
7
10
14
17
TXEN
VCC
GND
CXR
VOUT
BYP
VIN+
18
19
VIN–
SLEEP
20
DATEN
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the
internal register with the MSB (Most Significant Bit) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit masterslave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.
Logic “0” disables transmission. Logic “1” enables transmission.
Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.
Common External Ground Reference
Transmit Enable/Disable Timing Capacitor. This pin is decoupled with a 100 pF capacitor to GND.
Output Signal
Internal Bypass. This pin must be externally ac-coupled (0.1 µF capacitor).
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF
capacitor.
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.
Low Power Sleep Mode. Logic 0 enables Sleep mode, where ZOUT goes to 200 Ω and supply
current is reduced to 5 mA. Logic 1 enables normal operation.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic
0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.
ORDERING GUIDE
Model
Temperature Range
Package Description
␪JA
Package Option
AD8327ARU
AD8327ARU-REEL
AD8327-EVAL
–40°C to +85°C
–40°C to +85°C
20-Lead TSSOP
20-Lead TSSOP
Evaluation Board
85°C/W*
85°C/W*
RU-20
RU-20
*Thermal Resistance measured on SEMI standard 4-layer board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8327 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
Typical Performance Characteristics–AD8327
0
+VS
10␮F
ISOLATION – dBc
–20
0.1␮F
0.1␮F
VCC
VIN–
VIN
AD8327
165⍀
0.1␮F
VIN+
0.1␮F BYP CXR
–30
–40
–50
–60
–70
75⍀
GND
MAX GAIN
–80
100pF
0.1␮F
TXEN = 0
VIN = 30dBmV
–10
MIN GAIN
–90
1
1000
TPC 4. Isolation in Transmit Disable Mode
vs. Frequency
TPC 1. Basic Test Circuit
40
0.6
f = 65MHz
0.5
128D
30
64D
0.4
32D
20
GAIN ERROR – dB
100
10
FREQUENCY – MHz
0.3
16D
GAIN – dB
f = 42MHz
0.2
0.1
10
08D
04D
0
02D
0
f = 10MHz
01D
–10
–0.1
00D
f = 5MHz
–20
–0.2
–30
–0.3
0
16
32
48
64
80
96
GAIN CONTROL – Decimal Code
112
1
128
90
160
TXEN = 0
155
85
150
TXEN = 1
140
135
+VS
130
0.1␮F
VIN
AD8327
165⍀
VIN+
120
TXEN = 1
75
70
65
VIN–
125
TXEN = 0
80
145
IMPEDANCE – ⍀
IMPEDANCE – ⍀
1000
TPC 5. AC Response
TPC 2. Gain Error vs. Gain Control
OUT
0.1␮F
GND
0.1␮F
60
75⍀
55
115
1
10
FREQUENCY – MHz
100
1
10
FREQUENCY – MHz
TPC 6. Output Impedance vs. Frequency
TPC 3. Input Impedance vs. Frequency
REV. 0
10
100
FREQUENCY – MHz
–5–
100
AD8327
–50
–50
VOUT = 60dBmV @ MAX GAIN
VOUT = 61dBmV @ MAX GAIN
–55
DISTORTION – dBc
DISTORTION – dBc
VOUT = 61dBmV
@ MAX GAIN
–55
VOUT = 60dBmV
@ MAX GAIN
–60
VOUT = 59dBmV
@ MAX GAIN
–65
–60
–65
VOUT = 59dBmV @ MAX GAIN
–70
–75
VOUT = 58dBmV @ MAX GAIN
VOUT = 58dBmV
@ MAX GAIN
–70
–80
5
15
5
65
25
35
45
55
FUNDAMENTAL FREQUENCY – MHz
TPC 7. Second Order Harmonic Distortion vs. Frequency
for Various Output Levels
–60
–65
DISTORTION – dBc
DISTORTION – dBc
FO = 21MHz
VOUT = 60dBmV @ MAX GAIN
–55
–60
HD2
–70
–75
–80
–65
HD2
–70
–75
HD3
–80
HD3
–85
–85
0
16
32
48
64
80
96
GAIN CONTROL – Decimal Code
112
–90
128
0
TPC 8. Harmonic Distortion vs. Gain Control
16
32
48
64
80
96
GAIN CONTROL – Decimal Code
112
128
TPC 11. Harmonic Distortion vs. Gain Control
–50
–50
FO = 42MHz
VOUT = 60dBmV @ MAX GAIN
–55
FO = 65MHz
VOUT = 60dBmV @ MAX GAIN
–55
HD2
–60
–60
DISTORTION – dBc
DISTORTION – dBc
65
–50
FO = 5MHz
VOUT = 60dBmV @ MAX GAIN
–55
HD2
–65
–70
–75
HD3
–65
HD3
–70
–75
–80
–80
–85
–85
–90
25
35
45
55
FUNDAMENTAL FREQUENCY – MHz
TPC 10. Third Order Harmonic Distortion vs. Frequency
for Various Output Levels
–50
–90
15
–90
0
16
32
48
64
80
96
GAIN CONTROL – Decimal Code
112
128
0
TPC 9. Harmonic Distortion vs. Gain Control
16
32
48
64
80
96
GAIN CONTROL – Decimal Code
112
128
TPC 12. Harmonic Distortion vs. Gain Control
–6–
REV. 0
AD8327
–10
60
CH PWR
ACP UP
ACP LOW
–20
9.0dBm
–62dBc
–62.5dBc
40
–40
30
–50
20
VOUT – dBmV
–30
–60
–70
–80
–100
C11
C11
CENTER 21MHz
C0
C0
Cu1
0
–10
75kHz/DIV
Cu1
–30
–40
41.0
SPAN 750kHz
TPC 13. Adjacent Channel Power
41.2
41.4
41.6
41.8 42.0 42.2 42.4
FREQUENCY – MHz
42.6
42.8
43.0
TPC 16. Two-Tone Intermodulation Distortion
–30
–25
f = 10MHz
@ MAX GAIN, TXEN = 1
–30
OUTPUT NOISE – dBmV in 160kHz
TXEN = 1
OUTPUT NOISE – dBmV in 160kHz
10
–20
–90
–110
VOUT = 60dBmV
@ MAX GAIN
50
–34
–38
–42
–46
–35
–40
–45
@ MIN GAIN, TXEN = 1
–50
–55
–60
–65
ALL GAIN CODES, TXEN = 0
–70
–50
0
16
32
48
64
80
96
GAIN CONTROL – Decimal Code
112
–75
128
TPC 14. Output Referred Noise vs. Gain Control
5
25
35
45
FREQUENCY – MHz
55
65
TPC 17. Output Referred Noise vs. Frequency for Various
Gain Codes
35
120
VOUT = 60dBmV
@ MAX GAIN
CL = 0pF
QUIESCENT SUPPLY CURRENT – mA
TXEN = 1
30
CL = 10pF
GAIN – dB
15
25
+VS
CL = 20pF
10␮F
20
0.1␮F
VCC
0.1␮F
VIN–
VIN
15
0.1␮F
AD8327
165⍀
CL
VIN+
0.1␮F
0.1␮F
BYP CXR
GND
75⍀
100pF
110
100
90
80
70
60
CL = 50pF
10
1
100
10
FREQUENCY – MHz
50
1000
0
TPC 15. AC Response for Various Capacitor Loads
REV. 0
16
32
48
64
80
96
GAIN CONTROL – Decimal Code
112
TPC 18. Supply Current vs. Gain Code
–7–
128
AD8327
which amplifies these currents to the appropriate levels necessary to
drive a 75 Ω load. The output stage maintains 75 Ω output
impedance, eliminating the need for external matching resistors.
APPLICATIONS
General Application
The AD8327 is primarily intended for use as the upstream power
amplifier (PA), also known as a line driver, in DOCSIS (Data
Over Cable Service Interface Specification) certified cable
modems and CATV set-top boxes. The upstream signal is either
a QPSK or QAM signal generated by a DSP, a dedicated QPSK/
QAM modulator, or a DAC.
SPI Programming and Gain Adjustment
The AD8327 is controlled through a serial peripheral interface
(SPI) of three digital data lines: CLK, DATEN, and SDATA.
Changing the gain requires eight bits of data to be streamed into
the SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the DATEN pin, which activates
the CLK line. With the CLK line activated, data on the SDATA
line is clocked into the serial shift register, Most Significant Bit
(MSB) first, on the rising edge of the CLK pulses. The 8-bit
data word is latched into the attenuator core on the rising edge
of the DATEN line. This provides control over the changes in
the output signal level. The serial interface timing for the AD8327
is shown in Figures 2 and 3. The programmable gain range of
the AD8327 is –18.16 dB to +30 dB with steps of 6.02 dB per
major carry. This provides a total gain range of 48.16 dB.
The AD8327 was characterized with a TOKO transformer
(TOKO#617DB-A0070) on the input, and the stated gain
values account for the losses due to the transformer. Table I
shows the possible gain states.
In all cases the signal must be low-pass filtered before being
applied to the PA in order to filter out-of-band noise and higher
order harmonics from the amplified signal. Due to the varying
distances between the cable modem and the headend, the
upstream PA must be capable of varying the output power by
applying gain or attenuation. The varying output power of the
AD8327 ensures that the signal from the cable modem will have
the proper level once it arrives at the headend. The upstream
signal path commonly includes a diplexer and cable splitters.
The AD8327 has been designed to overcome losses associated
with these passive components in the upstream cable path.
Circuit Description
The AD8327 is composed of three analog functions in the powerup or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differential configuration, it is imperative that the input signals be 180
degrees out of phase and of equal amplitude. The preamp stage
drives a DAC, which provides the AD8327’s attenuation (eight
bits or 48.16 dB). The signals in the preamp and DAC gain
blocks are differential to improve the PSRR and linearity.
A differential current is fed from the DAC into the output stage,
Input Bias, Impedance, and Termination
The VIN+ and VIN– inputs have a dc bias level of VCC/2, therefore
the input signal should be ac-coupled using 0.1 µF capacitors as
seen in the typical application circuit (see Figure 4). The differential input impedance of the AD8327 is approximately 1.6 kΩ,
while the single-ended input impedance is 800 Ω.
Table I. Gain States
Decimal Code
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Gain
0
1
2
4
8
16
32
64
128
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
–18.16
–12.14
–6.12
–0.10
5.92
11.94
17.96
23.98
30
–8–
REV. 0
AD8327
VCC
10␮F
SLEEP
ENB
1
SDATA
CLK
2
3
4
TXEN
0.1␮F
5
6
7
0.1␮F
100pF
8
9
10
0.1␮F
AD8327
SDATA
CLK
TXEN
VCC
GND
VCC
20
ENB
SLEEP
VIN–
VIN+
VCC
CXR
GND
GND
VOUT
VIN–
19
18
17
ZIN = 150⍀
165⍀
16
0.1␮F
15
14
13
12
11
GND
BYP
GND
VCC
VCC
0.1␮F
VIN+
0.1␮F
0.1␮F
0.1␮F
0.1␮F
TO DIPLEXER ZIN = 75⍀
Figure 4. Typical Application Circuit
Single-Ended Inverting Input
R13 =
When operating the AD8327 in a single-ended input mode VIN+
and VIN– should be terminated as illustrated in Figure 5. On the
AD8327 evaluation boards, this termination method requires
the removal of R13–R16 and R20, as well as the addition of a 0 Ω
jumper at R17. Table II shows the correct values for R11 and R12
for some common input configurations. Other input impedance configurations may be accommodated using the equations
in Figure 5. The inverting and noninverting inputs of the AD8327
must be balanced for all input configurations
R12 =
ZIN ⴛ 800⍀
800⍀ – ZIN
R11 =
ZIN ⴛ R12
R12 + ZIN
–
1600⍀ – ZIN
VIN+
R13
AD8327
ZIN
Figure 6. Single to Differential Input
Differential Signal Source
The AD8327 evaluation board is also capable of accepting a
differential input signal. Remove R11–R12, R14–R15, and R20,
and place 0 Ω jumpers for R16–R17. See Table II for common
values of R13, or calculate other input configurations using the
equation in Figure 7.
AD8327
R12
+
R13 =
ZIN
R11
R13
ZIN
Differential Input from Single-Ended Source
The default configuration of the evaluation board implements a
differential signal drive from a single-ended signal source. A
TOKO 1:1 transformer is included on the board for this purpose
(T3). Enabling the evaluation board for single to differential input
conversion requires R11–R12 and R16–R17 to be removed, and
0 Ω jumpers must be installed on the placeholders for R14, R15,
and R20. Table II provides typical R13 values for common
input configurations. Other input impedances may be calculated
using the equation in Figure 6. Refer to Figure 10 for evaluation
board schematic. To utilize the transformer for converting a singleended source into a differential signal, the input signal must
be applied to VIN+.
ZIN ⴛ 1600⍀
1600⍀ – ZIN
VIN+
Figure 5. Single-Ended Inverting Input
REV. 0
ZIN ⴛ 1600⍀
AD8327
VIN–
Figure 7. Differential Input
Output Bias, Impedance, and Termination
The output of the AD8327 has a dc bias level of approximately
VCC/2; therefore, it should be ac-coupled before being applied to
the load. The output impedance of the AD8327 is internally
maintained at 75 Ω, regardless of whether the amplifier is in
transmit enable or transmit disable mode. This eliminates the
need for external back termination resistors. If the output signal
is being evaluated using standard 50 Ω test equipment, a minimum loss 75 Ω to 50 Ω pad must be used to provide the test
circuit with the proper impedance match.
–9–
AD8327
Asynchronous Power-Down
Table II. Common Input Terminations
The asynchronous TXEN pin is used to place the AD8327 into
between-burst mode, while maintaining a differential output
impedance of 75 Ω. Applying Logic 0 to the TXEN pin activates
the on-chip reverse amplifier, providing an 86% reduction in
consumed power. For 5 V operation, the supply current is typically
reduced from 105 mA to 15 mA. In this mode of operation,
between-burst noise is minimized and the amplifier can no longer
transmit in the upstream direction. In addition to the TXEN
pin, the AD8327 also incorporates an asynchronous SLEEP pin,
which may be used to further reduce the supply current to
approximately 5 mA. Applying Logic 0 to the SLEEP pin places
the amplifier into SLEEP mode. Transitioning into or out of
SLEEP mode may result in a transient voltage at the output of
the amplifier.
Differential Input Termination
ZIN (⍀)
R11
R12
R13 (⍀)
50
75
100
150
Open
Open
Open
Open
Open
Open
Open
Open
52.1
78.7
107
165
Single-Ended Input Termination
ZIN (⍀)
R11 (⍀)
R12 (⍀)
R13
50
75
25.5
39.2
53.6
82.5
Open
Open
Power Supply
Distortion, Adjacent Channel Power, and DOCSIS
The 5 V supply should be delivered to each of the VCC pins via a
low impedance power bus to ensure that each pin is at the same
potential. The power bus should be decoupled to ground using
a 10 µF tantalum capacitor located close to the AD8327ARU.
In addition to the 10 µF capacitor, each VCC pin should be
individually decoupled to ground with 0.1 µF ceramic chip capacitors located close to the pins. The bypass pin, labeled BYP (Pin 14),
should also be decoupled with a 0.1 µF capacitor. The PCB
should have a low impedance ground plane covering all unused
portions of the board, except in areas of the board where input
and output traces are in close proximity to the AD8327. All
AD8327 ground pins must be connected to the ground plane to
ensure proper grounding of all internal nodes.
In order to deliver the DOCSIS required +58 dBmV of QPSK
signal and +55 dBmV of 16 QAM signal, the PA is required to
deliver up to +60 dBmV and +57 dBmV respectively. This level is
required to compensate for losses associated with the diplex filter
or other passive components that may be included in the upstream
path of cable modems or set-top boxes. It should be noted that
the AD8327 was characterized with the TOKO 617DB-A0070
transformer on the input to generate a differential input signal.
TPC 7 and TPC 10 show the AD8327 second and third order
harmonic distortion performance versus fundamental frequency
for various output power levels. These figures are useful for
determining the in-band harmonic levels from 5 MHz to 65 MHz.
Harmonics higher in frequency (above 42 MHz for DOCSIS
and above 65 MHz for EuroDOCSIS) will be sharply attenuated
by the low-pass filter function of the diplexer.
CXR Pin
The AD8327 features internal circuitry that controls burst
transients. This feature uses a 100 pF capacitor connected to
Pin 7 of the AD8327, to slow down the turn-on transient and
minimize between-burst transients.
Another measure of signal integrity is adjacent channel power,
commonly referred to as ACP. DOCSIS section 4.2.10.1.1 states,
“Spurious emissions from a transmitted carrier may occur in an
adjacent channel that could be occupied by a carrier of the same or
different symbol rates.” TPC 13 shows the measured ACP for a
+57 dBmV 16 QAM signal taken at the output of the AD8327
evaluation board, through a 75 Ω to 50 Ω matching pad (5.7 dB of
loss). The transmit channel width and adjacent channel width in
TPC 13 correspond to symbol rates of 160 KSYM/S. Table III shows
the ACP results for the AD8327 driving a 16 QAM, +57 dBmV
signal for all conditions in DOCSIS Table 4-7 “Adjacent Channel
Spurious Emissions.”
Signal Integrity Layout Considerations
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. It is also critical that
all differential signal paths be symmetrical in length and width.
In addition, the input and output traces should be kept far apart,
to minimize coupling (crosstalk) through the board. Following
these guidelines will optimize the overall performance of the
AD8327 in all applications.
Table III. Adjacent Channel Power
Initial Power-Up
When the supply voltage is first applied to the AD8327, the gain
of the amplifier is initially set to gain code 0. As power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0) to prevent forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the
desired level by following the procedure provided in the SPI
Programming and Gain Adjustment section. The TXEN pin
can then be brought from Logic 0 to Logic 1, enabling forward
signal transmission at the desired gain level.
–10–
ADJACENT CHANNEL SYMBOL RATE
TRANSMIT
SYMBOL
RATE
160 KSYM/SEC
160 KSYM/SEC 320 KSYM/SEC 640 KSYM/SEC 1280 KSYM/SEC 2560 KSYM/SEC
ACP
(dBc)
ACP
(dBc)
ACP
(dBc)
ACP
(dBc)
ACP
(dBc)
–62
–63
–65
–66
–66
320 KSYM/SEC
–62
–63
–64
–66
–66
640 KSYM/SEC
–63
–62
–63
–65
–66
1280 KSYM/SEC
–64
–63
–63
–63
–64
2560 KSYM/SEC
–66
–63
–63
–62
–63
REV. 0
AD8327
Noise and DOCSIS
Running AD8327 Software
At minimum gain, the AD8327 output noise spectral density is
11 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8,“Spurious
Emissions in 5 MHz to 42 MHz,” specifies the output noise for
various symbol rates. The calculated noise in dBmV for
160KSYM/SECOND is:
To load the control software, go to START, PROGRAMS,
CABDRIVE_27, or select the AD8327.exe from the installed
directory. Once loaded, select the proper parallel port to communicate with the AD8327 (Figure 8).

2


 20 log   11 nV  × 160 kHz   + 60 = –47 dBmV

  Hz 
 



Comparing the computed noise power of –47 dBmV to the
+8 dBmV signal yields –55 dBc, which meets the required level
set forth in DOCSIS Table 4-8. As the AD8327 gain is increased
above this minimum value, the output signal increases at a faster
rate than the noise, resulting in a signal to noise ratio that improves
with gain. In transmit disable mode, the output noise spectral
density is 1.3 nV/√Hz, which results in –66 dBmV when computed
over 160 KSYM/S. The noise power was measured directly at the
output of the AD8327AR-EVAL board.
Evaluation Board Features and Operation
The AD8327 evaluation board (Part #AD8327AR-EVAL) and
control software can be used to control the AD8327 upstream
cable driver via the parallel port of a PC. A standard printer
cable connected between the parallel port of the personal computer is used to feed all the necessary data to the AD8327 using
the Windows-based control software. This package provides a
means of evaluating the amplifier with a convenient way to
program the gain/attenuation, as well as offering easy control of
the asynchronous TXEN and SLEEP pins. With this evaluation
kit, the AD8327 can be evaluated in either a single-ended or
differential input configuration. A schematic of the evaluation
board is provided in Figure 10.
Figure 8. Parallel Port Selection
Controlling Gain/Attenuation of the AD8327
The slide bar controls the gain/attenuation of the AD8327,
which is displayed in dB and in V/V. The gain scales 6 dB per
major carry. The gain code from the position of the slide bar is
displayed in decimal, binary, and hexadecimal (Figure 9).
Overshoot on PC Printer Ports
The data lines on some PC parallel printer ports have excessive
overshoot that may cause communications problems when presented to the CLK pin of the AD8327. The evaluation board
was designed to accommodate a series resistor and shunt capacitor (R2 and C5 in Figure 10) to filter the CLK signal if required.
Installing Visual Basic Control Software
Install the “CabDrive_27” software by running “setup.exe” on
disk one of the AD8327 Evaluation Software. Follow on-screen
directions and insert disk two when prompted. Choose installation directory, and then select the icon in the upper left
to complete installation.
Figure 9. Control Software Interface
REV. 0
–11–
AD8327
Transmit Enable and Sleep Mode
Memory Functions
The Transmit Enable and Transmit Disable buttons select the
mode of operation of the AD8327 by asserting logic levels on
the asynchronous TXEN pin. The Transmit Disable button
applies Logic 0 to the TXEN pin, disabling forward transmission while maintaining a 75 Ω back termination. The Transmit
Enable button applies Logic 1 to the TXEN pin, enabling the
AD8327 for forward transmission. Checking the “Enable
SLEEP Mode” checkbox applies logic “0” to the asynchronous
SLEEP pin, setting the AD8327 for SLEEP mode.
The MEMORY section of the software provides a way to
alternate between two gain settings. The “X->M1” button
stores the current value of the gain slide bar into memory
while the “RM1” button recalls the stored value, returning
the gain slide bar to the stored level. The same applies to the
“X->M2” and “RM2” buttons.
DATEN
TP9 VCC
TP10
TP11
TP12
SDATA
C12
10␮F
Z1
1
2
3
4
5
6
7
8
9
10
TXEN
SLEEP
C1
0.1␮F
TP1
C2
0.1␮F
SDATA DATEN 20
SLEEP 19
CLK
TXEN
VIN– 18
VIN+ 17
VCC
GND
VCC 16
GND 15
VCC
BYP
14
CXR
GND 13
GND
VCC 12
GND
VCC 11
VOUT
TP2
TSSOP20
AGND
C11
0.1␮F
P1
1
P1
2
P1
3
P1
4
P1
5
P1
6
P1
7
P1
8
P1
9
P1
10
P1
11
P1
12
P1
13
P1
14
P1
15
P1
16
P1
17
P1
18
R1
0⍀
R3
0⍀
6
4 T3
3
4 T4
2
C8
0.1␮F
3
1
PRI SEC
PRI SEC
DNI
TP24
C15
0.1␮F
AGND
2
1
5
R13
78.7⍀
C10
0.1␮F
R21
DNI
AGND
TOKO1
R20
0⍀
R14
0⍀
VIN+
R16
DNI
R11
DNI
TP22
0⍀
AGND
HPF
9
TP6
C4
DNI
R2
0⍀
TP7
R15
0⍀
TP4
VCC
P1
TP5
R19
DNI
VIN–
R12
DNI
C7
0.1␮F AGND
TP3
R17
DNI
AGND
C3
100pF
AGND
TP23
C16
0.1␮F
AGND
CLK
TP8
C6
DNI
C5
DNI
P1
20
21
P1
22
P1
23
P1
24
P1
25
P1
26
P1
27
P1
28
P1
29
P1
30
P1
31
P1
32
P1
33
P1
34
P1
35
P1
36
HPP
AGND
1
DEVICE = 2LUGPWR
19
P1
TB1
TP16
TP14
LPP
CBL
5
TP21
COM
CX6002 3 10–18
DNI
AGND
R6
DNI
R7
0⍀
R8
DNI
TP20
CABLE
C14
0.1␮F
R9
0⍀
R5
DNI
TP15
R10
DNI
AGND
AGND
AGND
Figure 10. Evaluation Board Schematic
–12–
REV. 0
AD8327
Figure 11. Evaluation Board Layout—Top Silkscreen
REV. 0
–13–
AD8327
Figure 12. Evaluation Board Layout—Component Side
–14–
REV. 0
AD8327
Figure 13. Evaluation Board Layout—Internal Ground Plane
REV. 0
–15–
AD8327
Figure 14. Evaluation Board Layout—Internal Power and Ground Plane
–16–
REV. 0
AD8327
Figure 15. Evaluation Board Layout—Circuit Side
REV. 0
–17–
AD8327
Figure 16. Evaluation Board Layout—Bottom Silkscreen
–18–
REV. 0
AD8327
EVALUATION BOARD BILL OF MATERIALS
AD8327 Evaluation Board Rev. B, Single-Ended-to-Differential Input—Revised–February 21, 2001
Qty.
Description
Ref Description
1
1
2
7
11
1
2
1
1
1
1
4
1
1
1
1
4
4
2
2
2
2
10 µF 25 V. ‘D’ size tantalum chip capacitor
100 pF 0603 ceramic chip capacitor
0.1 µF 50 V. 1206 size ceramic chip capacitor
0.1 µF 25 V. 0603 size ceramic chip capacitor
0 Ω 5% 1/8 W. 1206 size chip resistor
78.7 Ω 1% 1/8 W. 1206 size chip resistor
Yellow Test Point
Red Test Point
Black Test Point
Centronics-type 36-pin Right-Angle Connector
Terminal Block 2-Pos Green ED1973-ND
SMA End launch Jack (E F JOHNSON # 142-0701-801)
1:1 Transformer TOKO # 617DB – A0070
PULSE Diplexer*
AD8327 (TSSOP) UPSTREAM Cable Driver
AD8327 REV. C Evaluation PC board
#4–40 × 1/4 inch STAINLESS panhead machine screw
#4–40 × 3/4 inch long aluminum round stand-off
# 2–56 × 3/8 inch STAINLESS panhead machine screw
# 2 steel flat washer
# 2 steel internal tooth lockwasher
# 2 STAINLESS STEEL hex. machine nut
C12
C3
C15, C16
C1, C2, C7–C11
R1–R3, R7, R9, R14, R15, R20
R13
TP23, TP24
TP9
TP10–TP12 (GND)
P1
TB1
VIN–, VIN+, CABLE_0, HPF
T3
Z2
Z1
Evaluation PC board
(P1 Hardware)
(P1 Hardware)
(P1 Hardware)
(P1 Hardware)
NOTES
*PULSE Diplexer part numbers B5008 (42 MHz), CX6002 (42 MHz), B5009 (65 MHz).
DO NOT INSTALL C4, C5, C6, R6, R7, R8, R10–R12, R16, R17, R21, T9, TP1–TP8, TP14–TP16, TP20–TP22.
SMA’s TXEN, CLK, SLEEP, DATEN, SDATA, HPF_0, Z2.
REV. 0
–19–
AD8327
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C02653–.8–10/01(0)
20-Lead TSSOP
(RU-20)
0.260 (6.60)
0.252 (6.40)
20
11
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
10
PIN 1
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
0.006 (0.15)
0.002 (0.05)
–20–
REV. 0