MMDF4P03HD Preferred Device Power MOSFET 4 A, 30 V, P−Channel SO−8, Dual Dual MOSFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc−dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. • Low RDS(on) Provides Higher Efficiency and Extends Battery Life • Logic Level Gate Drive − Can Be Driven by Logic ICs • Miniature SO−8 Surface Mount Package − Saves Board Space • Diode Is Characterized for Use In Bridge Circuits • Diode Exhibits High Speed, With Soft Recovery • IDSS Specified at Elevated Temperature • Mounting Information for SO−8 Package Provided http://onsemi.com 4 AMPERES 30 VOLTS RDS(on) = 85 mW P−Channel D D G G MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) S Symbol Value Unit Drain−to−Source Voltage VDSS 30 Vdc Gate−to−Source Voltage − Continuous VGS ± 20 Vdc Drain Current − Continuous @ TA = 25°C Drain Current − Single Pulse (tp ≤ 10 ms) ID IDM 4.0 20 Adc Apk Source Current − Continuous @ TA = 25°C IS 1.7 Adc Total Power Dissipation @ TA = 25°C (Note 1) PD 2.0 Watts TJ, Tstg − 55 to 150 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 W) EAS 450 mJ Thermal Resistance − Junction−to−Ambient RθJA 62.5 °C/W TL 260 °C Rating Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, (1/8″ from Case for 10 s) S MARKING DIAGRAM 8 8 1 DP0303 AYWW SO−8, Dual CASE 751 STYLE 11 A Y WW 1 = Assembly Location = Year = Work Week PIN ASSIGNMENT Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1 Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. Source−1 1 8 Drain−1 Gate−1 2 7 Drain−1 Source−2 3 6 Drain−2 Gate−2 4 5 Drain−2 Top View ORDERING INFORMATION Device MMDF4P03HDR2 Package Shipping † SO−8 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 3 1 Publication Order Number: MMDF4P03HD/D MMDF4P03HD ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 − − − − − − 1.0 20 − − 100 1.0 − − − − 0.075 0.125 0.085 0.16 gFS − 6.0 − Mhos Ciss − 425 600 pF Coss − 209 300 Crss − 57.2 80 td(on) − 11.7 23.4 tr − 15.8 31.6 td(off) − 167.3 334.6 tf − 102.6 205.2 QT − 14.8 29.6 Q1 − 1.7 − Q2 − 4.7 − Q3 − 3.42 − − − 0.9 0.7 1.2 − trr − 77.4 − ta − 19.9 − tb − 57.5 − QRR − 0.088 − OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc μAdc nAdc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 3.5 Adc) (VGS = 4.5 Vdc, ID = 2.0 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 3.5 Adc) Vdc Ω DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 24 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time (VDD = 15 Vdc, VGS = 10 Vdc, ID = 1.0 Adc, RG = 6.0 Ω) Rise Time Turn−Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 10 Vdc, ID = 3.5 Adc, VGS = 10 Vdc) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 3.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/μs) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 VSD Vdc ns μC MMDF4P03HD TYPICAL ELECTRICAL CHARACTERISTICS VGS = 10 V 6.0 V 5.0 4.1 V 4.5 V 3.9 V 4.3 V 4.0 6.0 TJ = 25°C ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 6.0 3.7 V 3.0 3.5 V 2.0 3.3 V 3.1 V 2.9 V 2.7 V 1.0 0 4.0 3.0 2.0 25°C 1.0 TJ = −55°C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.5 2.0 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) R DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS) R DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS) TJ = 25°C ID = 3 A 0.6 0.5 0.4 0.3 0.2 0.1 0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 3.5 4.0 4.5 5.0 9.0 10 0.18 TJ = 25°C 0.16 VGS = 4.5 V 0.14 0.12 0.10 0.08 10 V 0.06 0.04 1.0 1.5 2.0 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−To−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 100 1.6 1.4 3.0 Figure 2. Transfer Characteristics 0.8 0.7 2.5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics VGS = 0 V VGS = 10 V ID = 1.5 A TJ = 125°C 1.2 IDSS , LEAKAGE (nA) R DS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 100°C VDS ≥ 10 V 5.0 1.0 0.8 0.6 10 100°C 0.4 0.2 0 −50 1.0 −25 0 25 50 75 100 125 0 150 TJ, JUNCTION TEMPERATURE (°C) 5.0 10 15 20 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 30 MMDF4P03HD POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1000 TJ = 25°C C, CAPACITANCE (pF) 800 600 Ciss 400 Coss 200 Crss 0 −10 −5.0 0 VGS 5.0 10 15 20 VDS VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 25 30 30 QT 6.0 VGS 5.0 20 Q2 Q1 4.0 3.0 10 ID = 3 A TJ = 25°C 2.0 1.0 VDS Q3 0 0 2.0 4.0 6.0 8.0 10 12 0 16 14 1000 100 VDD = 15 V ID = 3 A VGS = 10 V TJ = 25°C td(off) tf 10 tr td(on) t, TIME (ns) 7.0 V DS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) MMDF4P03HD 1.0 1.0 10 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 DRAIN−TO−SOURCE DIODE CHARACTERISTICS high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by IS , SOURCE CURRENT (AMPS) 2.5 VGS = 0 V TJ = 25°C 2.0 1.5 1.0 0.5 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current http://onsemi.com 5 MMDF4P03HD di/dt = 300 A/μs I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta t, TIME Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the 10 VGS = 12 V SINGLE PULSE TA = 25°C EAS , SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 1.0 ms 10 ms 1.0 dc 0.1 total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RθJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 1.0 10 100 500 ID = 3 A 450 400 350 300 250 200 150 100 50 0 25 45 65 85 105 125 145 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 6 MMDF4P03HD TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) 1.0E+00 1.0E+01 Figure 14. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 7 1.0E+02 1.0E+03 MMDF4P03HD PACKAGE DIMENSIONS SO−8 CASE 751−07 ISSUE AE −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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