MB95200H/210H Series
F2MC-8FX 8-bit Microcontroller
MB95200H/210H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of this series contain a variety of peripheral resources.
Features
F2MC-8FX CPU core
Low power consumption (standby) mode
Instruction set optimized for controllers
■
Stop mode
■
Multiplication and division instructions
■
Sleep mode
■
16-bit arithmetic operations
■
Watch mode
■
Bit test branch instructions
■
Timebase timer mode
■
Bit manipulation instructions, etc.
I/O port (Max: 17) (MB95F204K/F203K/F202K)
Clock (main OSC clock and sub-OSC clock are only
available in MB95F204H/F204K/F203H/F203K/F202H
/F202K)
■
■
Selectable main clock source
❐ Main OSC clock (up to 16.25 MHz, maximum machine clock
frequency: 8.125 MHz)
❐ External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
❐ Main internal CR clock (1/8/10 MHz ± 3%, maximum machine
clock frequency: 10 MHz)
Selectable subclock source
Sub-OSC clock (32.768 kHz)
❐ External clock (32.768 kHz)
❐ Sub-internal CR clock (Typ: 100 kHz, Min: 50 kHz,
Max: 200 kHz)
❐
Timer
■
8/16-bit composite timer
■
Timebase timer
■
Watch prescaler
Full duplex double buffer
Capable of clock-synchronized serial data transfer and
clock-asynchronized serial data transfer
❐
I/O port (Max: 16) (MB95F204H/F203H/F202H)
■
General-purpose I/O ports (Max):
CMOS I/O: 15, N-ch open drain: 1
I/O port (Max: 5) (MB95F214K/F213K/F212K)
■
General-purpose I/O ports (Max):
CMOS I/O: 3, N-ch open drain: 2
I/O port (Max: 4) (MB95F214H/F213H/F212H)
■
General-purpose I/O ports (Max):
CMOS I/O: 3, N-ch open drain: 1
On-chip debug
■
1-wire serial control
■
Serial writing supported (asynchronous mode)
■
■
Interrupt by edge detection (rising edge, falling edge, and both
edges can be selected)
■
Can be used to wake up the device from different low-power
consumption (standby) modes
■
Built-in low-voltage detector
Clock supervisor counter
Built-in clock supervisor counter function
Programmable port input voltage level
■
CMOS input level / hysteresis input level
Flash memory security function
■
8/10-bit A/D converter
Built-in hardware watchdog timer
Low-voltage detection reset circuit
■
External interrupt
■
General-purpose I/O ports (Max):
CMOS I/O: 15, N-ch open drain: 2
Hardware/software watchdog timer
LIN-UART (MB95F204H/F204K/F203H/F203K/F202H
/F202K)
■
■
Protects the contents of flash memory
8-bit or 10-bit resolution can be selected.
Cypress Semiconductor Corporation
Document Number: 002-07463 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 24, 2017
MB95200H/210H Series
Contents
Product Line-up ................................................................ 3
Packages and Corresponding Products ........................ 4
Differences Among Products And Notes
On Product Selection ....................................................... 4
Pin Assignment ................................................................ 5
Pin Description (MB95200H Series 24 pins) .................. 6
Pin Description (MB95200H Series 20 pins) .................. 8
Pin Description (MB95210H Series) .............................. 10
I/O Circuit Type ............................................................... 11
Notes on Device Handling ............................................. 13
Pin Connection ............................................................... 13
Block Diagram (MB95200H Series) ............................... 15
Block Diagram (MB95210H Series) ............................... 16
CPU Core ......................................................................... 17
I/O Map (MB95200H Series) ........................................... 18
I/O Map (MB95210H Series) ........................................... 22
Document Number: 002-07463 Rev. *B
Interrupt Source Table (MB95200H Series) .................. 26
Interrupt Source Table (MB95210H Series) .................. 27
Electrical Characteristics ............................................... 28
Absolute Maximum Ratings ....................................... 28
Recommended Operating Conditions ....................... 30
DC Characteristics .................................................... 31
AC Characteristics ..................................................... 34
A/D Converter ............................................................ 49
Flash Memory Program/Erase Characteristics .......... 53
Sample Electrical Characteristics ................................. 54
Mask Options .................................................................. 60
Ordering Information ...................................................... 60
Package Dimensions ...................................................... 61
Major Changes ................................................................ 65
Document History ........................................................... 65
Page 2 of 66
MB95200H/210H Series
1. Product Line-up
Part number
Parameter
Type
MB95
F204H
MB95
F203H
MB95
F202H
MB95
F204K
MB95
F203K
MB95
F202K
MB95
F214H
MB95
F213H
MB95
F212H
MB95
F214K
MB95
F213K
MB95
F212K
Flash memory product
Clock supervisor It supervises the main clock oscillation.
counter
ROM capacity
16 KB
8 KB
4 KB
16 KB
8 KB
4 KB
16 KB
8 KB
4 KB
16 KB
8 KB
4 KB
RAM capacity
496 B
496 B
240 B
496 B
496 B
240 B
496 B
496 B
240 B
496 B
496 B
240 B
Low-voltage
detection reset
No
Yes
Reset input
Dedicated
CPU functions
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
General-purpose I/O ports (Max): 16
I/O
CMOS: 15, N-ch: 1
Timebase timer
Software select
No
Dedicated
Yes
Software select
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 61.5 ns (with machine clock = 16.25 MHz)
: 0.6 µs (with machine clock = 16.25 MHz)
I/O ports (Max): 17
CMOS: 15, N-ch: 2
I/O ports (Max): 4
CMOS: 3, N-ch: 1
I/O ports (Max): 5
CMOS: 3, N-ch: 2
Interrupt cycle : 0.256 ms - 8.3 s (when external clock = 4 MHz)
Hardware/softwa Reset generation cycle
Main oscillation clock at 10 MHz : 105 ms (Min)
re watchdog
The sub-CR clock can be used as the source clock of the hardware watchdog.
timer
Wild register
It can be used to replace three bytes of data.
LIN-UART
A wide range of communication speed can be selected
by a dedicated reload timer.
It has a full duplex double buffer.
Clock-synchronized serial data transfer and
No LIN-UART
clock-asynchronized serial data transfer is enabled.
The LIN function can be used as a LIN master or a LIN
slave.
8/10-bit A/D
converter
6 ch.
8-bit or 10-bit resolution can be selected.
2 ch.
8/16-bit
composite timer
2 ch.
1 ch.
The timer can be configured as an "8-bit timer x 2 channels" or a "16-bit timer x 1 channel".
It has built-in timer function, PWC function, PWM function and input capture function.
Count clock: it can be selected from internal clocks (seven types) and external clocks.
It can output square wave.
6 ch.
2 ch.
External interrupt Interrupt by edge detection (rising edge, falling edge, or both edges can be selected.)
It can be used to wake up the device from standby modes.
On-chip debug
1-wire serial control
It supports serial writing. (asynchronous mode)
(Continued)
Document Number: 002-07463 Rev. *B
Page 3 of 66
MB95200H/210H Series
(Continued)
Part number
Parameter
MB95
F204H
MB95
F203H
MB95
F202H
MB95
F204K
MB95
F203K
MB95
F202K
MB95
F214H
MB95
F213H
MB95
F212H
Watch prescaler
Eight different time intervals can be selected.
Flash memory
It supports automatic programming, Embedded Algorithm,
write/erase/erase-suspend/erase-resume commands.
It has a flag indicating the completion of the operation of Embedded Algorithm.
Number of write/erase cycles: 100000
Data retention time: 20 years
For write/erase, external Vpp(+10 V) input is required.
Flash Security Feature for protecting the contents of the flash
Standby mode
Sleep mode, stop mode, watch mode, timebase timer mode
SDIP-24
SOP-20
Package
MB95
F214K
MB95
F213K
MB95
F212K
DIP-8
SOP-8
2. Packages and Corresponding Products
Part number
MB95
F204H
MB95
F203H
MB95
F202H
MB95
F204K
MB95
F203K
MB95
F202K
MB95
F214H
MB95
F213H
MB95
F212H
MB95
F214K
MB95
F213K
MB95
F212K
24-pin plastic
SDIP
O
O
O
O
O
O
X
X
X
X
X
X
20-pin plastic
SOP
O
O
O
O
O
O
X
X
X
X
X
X
8-pin plastic DIP
X
X
X
X
X
X
O
O
O
O
O
O
8-pin plastic SOP
X
X
X
X
X
X
O
O
O
O
O
O
Package
O: Available
X: Unavailable
3. Differences Among Products And Notes On Product Selection
Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/program.
For details of current consumption, see “18.Electrical Characteristics”.
Package
For details of information on each package, see “ 2.Packages and Corresponding Products” and “22.Package Dimensions”.
Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “18.Electrical Characteristics”.
On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. In addition, if the flash memory
data has to be updated, the RSTX/PF2 pin must also be connected to the same evaluation tool.
Document Number: 002-07463 Rev. *B
Page 4 of 66
MB95200H/210H Series
4. Pin Assignment
X0/PF0
1
24
P12/EC0/DBG
N.C.
2
23
N.C.
X1/PF1
3
(TOP VIEW)
22
P07/INT07
Vss
4
P06/INT06/TO01
X1A/PG2
5
24 pins
(SDIP24)
21
20
P05/INT05/AN05/TO00/HCLK2
X0A/PG1
6
19
P04/INT04/AN04/SIN/HCLK1/EC0
Vcc
7
18
P03/INT03/AN03/SOT
C
8
17
P02/INT02/AN02/SCK
RSTX/PF2
9
16
P01/AN01
TO10/P62
10
15
P00/AN00
N.C.
11
14
N.C.
TO11/P63
12
13
P64/EC1
X0/PF0
1
20
P12/EC0/DBG
X1/PF1
2
19
P07/INT07
Vss
3
(TOP VIEW)
18
P06/INT06/TO01
X1A/PG2
4
P05/INT05/AN05/TO00/HCLK2
X0A/PG1
5
20 pins
17
16
P04/INT04/AN04/SIN/HCLK1/EC0
Vcc
6
15
P03/INT03/AN03/SOT
C
7
14
P02/INT02/AN02/SCK
RSTX/PF2
8
13
P01/AN01
TO10/P62
9
12
P00/AN00
TO11/P63
10
11
P64/EC1
Vss
1
Vcc
2
C
3
RSTX/PF2
4
Document Number: 002-07463 Rev. *B
* The number of usable pins is 20.
(TOP VIEW)
8 pins
8
P12/EC0/DBG
7
P06/INT06/TO01
6
P05/AN05/TO00/HCLK2
5
P04/INT04/AN04/HCLK1/EC0
Page 5 of 66
MB95200H/210H Series
5. Pin Description (MB95200H Series 24 pins)
Pin no.
1
2
3
4
5
6
Pin name
PF0
X0
N.C.
PF1
X1
VSS
PG2
X1A
PG1
X0A
I/O circuit
type*
B
—
B
—
C
C
Function
General-purpose I/O port
Main clock input oscillation pin
It is an internally unconnected pin. Always leave it unconnected.
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
7
VCC
—
Power supply pin
8
C
—
Capacitor connection pin
PF2
9
10
RSTX
P62
General-purpose I/O port
A
D
TO10
11
12
N.C.
P63
14
15
16
P64
EC1
N.C.
P00
AN00
P01
AN01
It is an internally unconnected pin. Always leave it unconnected.
D
General-purpose I/O port
High-current port
8/16-bit composite timer ch. 1 output pin
D
—
E
E
P02
17
INT02
AN02
SCK
General-purpose I/O port
High-current port
8/16-bit composite timer ch. 1 output pin
TO11
13
Reset pin
This is a dedicated reset pin in MB95F202H/F203H/F204H.
General-purpose I/O port
8/16-bit composite timer ch. 1 clock input pin
It is an internally unconnected pin. Always leave it unconnected.
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
E
External interrupt input pin
A/D converter analog input pin
LIN-UART clock I/O pin
(Continued)
Document Number: 002-07463 Rev. *B
Page 6 of 66
MB95200H/210H Series
(Continued)
Pin no.
Pin name
I/O circuit
type*
P03
18
19
INT03
AN03
General-purpose I/O port
E
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
SIN
F
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current port
AN05
External interrupt input pin
E
INT06
External clock input pin
General-purpose I/O port
High-current port
G
TO01
P07
INT07
N.C.
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
G
—
P12
EC0
A/D converter analog input pin
8/16-bit composite timer ch. 0 output pin
P06
24
LIN-UART data input pin
EC0
HCLK2
23
A/D converter analog input pin
External clock input pin
TO00
22
A/D converter analog input pin
LIN-UART data output pin
INT05
21
External interrupt input pin
SOT
HCLK1
20
Function
General-purpose I/O port
External interrupt input pin
It is an internally unconnected pin. Always leave it unconnected.
General-purpose I/O port
H
DBG
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
*: For the I/O circuit types, see “8.I/O Circuit Type”.
Document Number: 002-07463 Rev. *B
Page 7 of 66
MB95200H/210H Series
6. Pin Description (MB95200H Series 20 pins)
Pin no.
Pin name
I/O circuit
type*
1
PF0/X0
B
General-purpose I/O port
This pin is also used as the main clock input oscillation pin.
2
PF1/X1
B
General-purpose I/O port
This pin is also used as the main clock input/output oscillation pin.
3
VSS
—
Power supply pin (GND)
4
PG2/X1A
C
General-purpose I/O port
This pin is also used as the subclock input/output oscillation pin.
5
PG1/X0A
C
General-purpose I/O port
This pin is also used as the subclock input oscillation pin.
6
VCC
—
Power supply pin
7
C
—
Capacitor connection pin
8
PF2/RSTX
A
General-purpose I/O port
This pin is also used as a reset pin.
This pin is a dedicated reset pin in MB95F204H/F203H/F202H.
9
P62/TO10
D
General-purpose I/O port
High-current port
This pin is also used as the 8/16-bit composite timer ch. 1 output.
10
P63/TO11
D
General-purpose I/O port
High-current port
This pin is also used as the 8/16-bit composite timer ch. 1 output.
11
P64/EC1
D
General-purpose I/O port
This pin is also used as the 8/16-bit composite timer ch. 1 clock input.
12
P00/AN00
E
General-purpose I/O port
This pin is also used as the A/D converter analog input.
13
P01/AN01
E
General-purpose I/O port
This pin is also used as the A/D converter analog input.
E
General-purpose I/O port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the LIN-UART clock I/O.
E
General-purpose I/O port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the LIN-UART data output.
F
General-purpose I/O port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the LIN-UART data input.
This pin is also used as the external clock input.
This pin is also used as the 8/16-bit composite timer ch. 0 clock input.
14
15
16
P02/INT02/AN02/SCK
P03/INT03/AN03/SOT
P04/INT04/AN04/SIN
/HCLK1/EC0
Function
(Continued)
Document Number: 002-07463 Rev. *B
Page 8 of 66
MB95200H/210H Series
(Continued)
Pin no.
17
Pin name
P05/INT05/AN05/TO00
/HCLK2
I/O circuit
type*
Function
E
General-purpose I/O port
High-current port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the 8/16-bit composite timer ch. 0 output.
This pin is also used as the external clock input.
18
P06/INT06/TO01
G
General-purpose I/O port
High-current port
This pin is also used as the external interrupt input.
This pin is also used as the 8/16-bit composite timer ch. 0 output.
19
P07/INT07
G
General-purpose I/O port
This pin is also used as the external interrupt input.
20
P12/EC0/DBG
H
General-purpose I/O port
This pin is also used as the DBG input pin.
This pin is also used as the 8/16-bit composite timer ch. 0 clock input.
*: For the I/O circuit types, see “8.I/O Circuit Type”
Document Number: 002-07463 Rev. *B
Page 9 of 66
MB95200H/210H Series
7. Pin Description (MB95210H Series)
Pin no.
Pin name
I/O circuit
type*
1
VSS
—
Power supply pin (GND)
2
VCC
—
Power supply pin
3
C
—
Capacitor connection pin
4
RSTX/PF2
A
General-purpose I/O port
This pin is also used as a reset pin.
This pin is a dedicated reset pin in MB95F214H/F213H/F212H.
5
P04/INT04/AN04/HCLK1
/EC0
E
General-purpose I/O port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the external clock input.
This pin is also used as the 8/16-bit composite timer ch. 0 clock input.
Function
6
P05/AN05/TO00/HCLK2
E
General-purpose I/O port
High-current port
This pin is also used as the A/D converter analog input.
This pin is also used as the 8/16-bit composite timer ch. 0 output.
This pin is also used as the external clock input.
7
P06/INT06/TO01
G
General-purpose I/O port
High-current port
This pin is also used as the external interrupt input.
This pin is also used as the 8/16-bit composite timer ch. 0 output.
8
P12/EC0/DBG
H
General-purpose I/O port
This pin is also used as the DBG input pin.
This pin is also used as the 8/16-bit composite timer ch. 0 clock input.
*: For the I/O circuit types, see “8.I/O Circuit Type”.
Document Number: 002-07463 Rev. *B
Page 10 of 66
MB95200H/210H Series
8. I/O Circuit Type
Type
Circuit
Remarks
Reset input / Hysteresis output
A
Reset output / Digital output
• N-ch open drain output
• Hysteresis input
• Reset output
N-ch
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Clock input
X1
B
• Oscillation circuit
• High-speed side
Feedback resistance: approx. 1 MΩ
• CMOS output
• Hysteresis input
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Port select
R
P-ch
Pull-up control
P-ch
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Clock input
X1A
• Oscillation circuit
• Low-speed side
Feedback resistance: approx. 10 MΩ
C
• CMOS output
• Hysteresis input
• Pull-up control available
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
P-ch
Digital output
N-ch
Digital output
Standby control
Hysteresis input
(Continued)
Document Number: 002-07463 Rev. *B
Page 11 of 66
MB95200H/210H Series
(Continued)
Type
Circuit
Remarks
D
P-ch
Digital output
Digital output
N-ch
• CMOS output
• Hysteresis input
Standby control
Hysteresis input
E
Pull-up control
R
P-ch
Digital output
P-ch
Digital output
N-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Analog input
A/D control
Standby control
Hysteresis input
F
Pull-up control
R
P-ch
Digital output
P-ch
Digital output
N-ch
Analog input
•
•
•
•
CMOS output
Hysteresis input
CMOS input
Pull-up control available
A/D control
Standby control
Hysteresis input
CMOS input
G
Pull-up control
R
P-ch
Digital output
P-ch
Digital output
• Hysteresis input
• CMOS output
• Pull-up control available
N-ch
Standby control
Hysteresis input
H
Standby control
Hysteresis input
• N-ch open drain output
• Hysteresis input
Digital output
N-ch
Document Number: 002-07463 Rev. *B
Page 12 of 66
MB95200H/210H Series
9. Notes on Device Handling
Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a
medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned
in “18.1 Absolute Maximum Ratings” of Electrical Characteristics” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed.
Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating
range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial
frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms
at a momentary fluctuation such as switching the power supply.
Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop
mode.
10. Pin Connection
Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull
up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave
it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it
unconnected.
Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and
conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the
device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between the VCC pin and the VSS pin at a location
close to this device.
DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the DBG pin and
the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
RSTX pin
Connect the RSTX pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the RSTX pin and
the VCC or VSS pin when designing the layout of the printed circuit board.
The RSTX/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output can be enabled by the RSTOE
bit of the SYSC register, and the reset input function or the general purpose I/O function can be selected by the RSTEN bit of the
SYSC register.
Document Number: 002-07463 Rev. *B
Page 13 of 66
MB95200H/210H Series
C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a
capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from
unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between
CS and the VSS pin when designing the layout of a printed circuit board.
• DBG/RSTX/C pin connection diagram
DBG
C
RSTX
Cs
Document Number: 002-07463 Rev. *B
Page 14 of 66
MB95200H/210H Series
11. Block Diagram (MB95200H Series)
F2MC-8FX CPU
PF2*1/RSTX*2
Flash with security function
(16/8/4 KB)
Reset with LVD
PF1/X1*2
RAM (496/240 B)
PF0/X0*2
PG2/X1A*2
Oscillator
circuit
CR
oscillator
Interrupt controller
PG1/X0A*2
(P05*3/TO00)
(P04/HCLK1)
8/16-bit composite timer (0)
Clock control
(P06*3/TO01)
(P05*3/HCLK2)
P12*1/EC0, (P04/EC0)
(P12/DBG)
On-chip debug
P02/INT02-P07/INT07
External interrupt
Internal Bus
(P00/AN00-P05*3/AN05)
Wild register
8/10-bit A/D converter
(P623/TO10)
8/16-bit composite timer (1)
(P02/SCK)
(P03/SOT)
(P63*3/TO11)
P64/EC1
LIN-UART
(P04/SIN)
C
Port
VCC
*1: PF2 and P12 are Nch open drain pins.
VSS
*2: Software option
Port
*3: P05, P06, P62 and P63 are high-current ports.
Document Number: 002-07463 Rev. *B
Page 15 of 66
MB95200H/210H Series
12. Block Diagram (MB95210H Series)
F2MC-8FX CPU
PF2*1/RSTX*2
Flash with security function
(16/8/4 KB)
Reset with LVD
RAM (496/240 B)
CR oscillator
Interrupt controller
(P05*3/TO00)
(P04/HCLK1)
8/16-bit composite timer (0)
Clock control
(P06*3/TO01)
(P05*3/HCLK2)
P12*1/EC0, (P04/EC0)
(P12/DBG)
On-chip debug
P04/INT04, P06*3/INT06
External interrupt
Internal Bus
P05*3/AN05, (P04/AN04)
Wild register
8/10-bit A/D converter
C
Port
VCC
*1: PF2 and P12 are Nch open drain pins.
VSS
*2: Software option
Port
*3: P05 and P06 are high-current ports.
Document Number: 002-07463 Rev. *B
Page 16 of 66
MB95200H/210H Series
13. CPU Core
Memory Space
The memory space of the MB95200H/210H Series is 64 KB in size, and consists of an I/O area, a data area, and a program area.
The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory
maps of the MB95200H/210H Series are shown below.
■
Memory Maps
MB95F204H/F204K
/F214H/F214K
0000H
0080H
0090H
0100H
I/O
RAM 496 B
Register
0200H
0000H
0080H
0090H
0100H
I/O
RAM 496 B
Register
Extension I/O
1000H
0280H
0F80H
MB95F202H/F202K/
F212H/F212K
0000H
0080H
0090H
0100H
I/O
RAM 240 B
Register
0180H
0200H
0280H
0F80H
MB95F203H/F203K/
F213H/F213K
Extension I/O
1000H
0F80H
Extension I/O
1000H
C000H
-
Flash 16 KB
E000H
Flash 8 KB
F000H
FFFFH
Document Number: 002-07463 Rev. *B
FFFFH
Flash 4 KB
FFFFH
Page 17 of 66
MB95200H/210H Series
14. I/O Map (MB95200H Series)
Address
Register
abbreviation
0000H
PDR0
0001H
Register name
R/W
Initial value
Port 0 data register
R/W
00000000B
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
R/W
11111111B
0006H
—
—
—
0007H
SYCC
System clock control register
R/W
XXXXXX11B
0008H
STBC
Standby control register
R/W
00000XXXB
0009H
RSRR
Reset source register
R
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
SYCC2
System clock control register 2
R/W
XX100011B
000EH to
0015H
—
—
—
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH to
0034H
—
—
—
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1 ch. 0
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1 ch. 0
R/W
00000000B
0038H
T11CR1
8/16-bit composite timer 11 status control register 1 ch. 1
R/W
00000000B
0039H
T10CR1
8/16-bit composite timer 10 status control register 1 ch. 1
R/W
00000000B
003AH to
0048H
—
—
—
0049H
EIC10
R/W
00000000B
(Disabled)
Oscillation stabilization wait time setting register
(Disabled)
(Disabled)
(Disabled)
(Disabled)
(Disabled)
External interrupt circuit control register ch. 2/ch. 3
(Continued)
Document Number: 002-07463 Rev. *B
Page 18 of 66
MB95200H/210H Series
Address
Register
abbreviation
004AH
EIC20
004BH
EIC30
004CH to
004FH
—
0050H
SCR
0051H
Register name
R/W
Initial value
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
—
—
LIN-UART serial control register
R/W
00000000B
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART receive/transmit data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H to
006BH
—
—
—
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (Upper)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (Lower)
R/W
00000000B
0070H to
0071H
—
—
—
0072H
FSR
R/W
000X0000B
0073H to
0075H
—
—
—
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
R/W
00000000B
(Disabled)
(Disabled)
(Disabled)
Flash memory status register
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer (DP)
(Disabled)
Wild register address setting register (Upper) ch. 0
Document Number: 002-07463 Rev. *B
(Continued)
Page 19 of 66
MB95200H/210H Series
p
Address
Register
abbreviation
0F81H
WRARL0
0F82H
WRDR0
0F83H
Register name
R/W
Initial value
Wild register address setting register (Lower) ch. 0
R/W
00000000B
Wild register data setting register ch. 0
R/W
00000000B
WRARH1
Wild register address setting register (Upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (Lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (Upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0 ch. 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0 ch. 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register ch. 0
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register ch. 0
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register ch. 0
R/W
00000000B
0F97H
T11CR0
8/16-bit composite timer 11 status control register 0 ch. 1
R/W
00000000B
0F98H
T10CR0
8/16-bit composite timer 10 status control register 0 ch. 1
R/W
00000000B
0F99H
T11DR
8/16-bit composite timer 11 data register ch. 1
R/W
00000000B
0F9AH
T10DR
8/16-bit composite timer 10 data register ch. 1
R/W
00000000B
0F9BH
TMCR1
8/16-bit composite timer 10/11 timer mode control register ch. 1
R/W
00000000B
0F9CH to
0FBBH
—
—
—
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH to
0FC2H
—
—
—
0FC3H
AIDRL
R/W
00000000B
0FC4H to
0FE3H
—
—
—
0FE4H
CRTH
Main CR clock trimming register (Upper)
R/W
1XXXXXXXB
0FE5H
CRTL
Main CR clock trimming register (Lower)
R/W
000XXXXXB
(Continued)
(Disabled)
(Disabled)
(Disabled)
A/D input disable register (Lower)
(Disabled)
Document Number: 002-07463 Rev. *B
Page 20 of 66
MB95200H/210H Series
(Continued)
Address
Register
abbreviation
0FE6H to
0FE7H
—
0FE8H
SYSC
0FE9H
Register name
R/W
Initial value
—
—
System configuration register
R/W
11000011B
CMCR
Clock monitoring control register
R/W
XX000000B
0FEAH
CMDR
Clock monitoring data register
R/W
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (Upper)
R/W
XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (Lower)
R/W
XXXXXXXXB
0FEDH
—
—
—
0FEEH
ILSR
R/W
00000000B
0FEFH to
0FFFH
—
—
—
(Disabled)
(Disabled)
Input level select register
(Disabled)
R/W access symbols
R/W : Readable / Writable
R
: Read only
W
: Write only
Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an undefined value is returned.
Document Number: 002-07463 Rev. *B
Page 21 of 66
MB95200H/210H Series
15. I/O Map (MB95210H Series)
Address
Register
abbreviation
0000H
PDR0
0001H
Register name
R/W
Initial value
Port 0 data register
R/W
00000000B
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
R/W
11111111B
0006H
—
—
—
0007H
SYCC
System clock control register
R/W
XXXXXX11B
0008H
STBC
Standby control register
R/W
00000XXXB
0009H
RSRR
Reset source register
R
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
SYCC2
System clock control register 2
R/W
XX100011B
000EH to
0015H
—
(Disabled)
—
—
0016H
—
(Disabled)
—
—
0017H
—
(Disabled)
—
—
0018H to
0027H
—
(Disabled)
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
—
(Disabled)
—
—
002BH
—
(Disabled)
—
—
002CH
PUL0
R/W
00000000B
002DH to
0034H
—
(Disabled)
—
—
0035H
—
(Disabled)
—
—
0036H
T01CR1
8/16-bit composite timer 01 status control register 1 ch. 0
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1 ch. 0
R/W
00000000B
0038H
—
(Disabled)
—
—
0039H
—
(Disabled)
—
—
003AH to
0048H
—
(Disabled)
—
—
0049H
—
(Disabled)
—
—
(Disabled)
Oscillation stabilization wait time setting register
(Disabled)
Port 0 pull-up register
(Continued)
Document Number: 002-07463 Rev. *B
Page 22 of 66
MB95200H/210H Series
Address
Register
abbreviation
004AH
EIC20
004BH
EIC30
004CH to
004FH
—
0050H
Register name
R/W
Initial value
External interrupt circuit control register ch. 4
R/W
00000000B
External interrupt circuit control register ch. 6
R/W
00000000B
(Disabled)
—
—
—
(Disabled)
—
—
0051H
—
(Disabled)
—
—
0052H
—
(Disabled)
—
—
0053H
—
(Disabled)
—
—
0054H
—
(Disabled)
—
—
0055H
—
(Disabled)
—
—
0056H to
006BH
—
(Disabled)
—
—
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (Upper)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (Lower)
R/W
00000000B
0070H to
0071H
—
—
—
0072H
FSR
R/W
000X0000B
0073H to
0075H
—
—
—
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
—
(Disabled)
—
—
007CH
—
(Disabled)
—
—
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (Upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (Lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
(Disabled)
Flash memory status register
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer (DP)
(Disabled)
Document Number: 002-07463 Rev. *B
(Continued)
Page 23 of 66
MB95200H/210H Series
Address
Register
abbreviation
0F83H
WRARH1
0F84H
Register name
R/W
Initial value
Wild register address setting register (Upper) ch. 1
R/W
00000000B
WRARL1
Wild register address setting register (Lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (Upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0 ch. 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0 ch. 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register ch. 0
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register ch. 0
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register ch. 0
R/W
00000000B
0F97H
—
(Disabled)
—
—
0F98H
—
(Disabled)
—
—
0F99H
—
(Disabled)
—
—
0F9AH
—
(Disabled)
—
—
0F9BH
—
(Disabled)
—
—
0F9CH to
0FBBH
—
(Disabled)
—
—
0FBCH
—
(Disabled)
—
—
0FBDH
—
(Disabled)
—
—
0FBEH to
0FC2H
—
(Disabled)
—
—
0FC3H
AIDRL
R/W
00000000B
0FC4H to
0FE3H
—
—
—
0FE4H
CRTH
Main CR clock trimming register (Upper)
R/W
1XXXXXXXB
0FE5H
CRTL
Main CR clock trimming register (Lower)
R/W
000XXXXXB
0FE6H to
0FE7H
—
—
—
0FE8H
SYSC
R/W
11000011B
(Disabled)
A/D input disable register (Lower)
(Disabled)
(Disabled)
System configuration register
Document Number: 002-07463 Rev. *B
(Continued)
Page 24 of 66
MB95200H/210H Series
(Continued)
Register
abbreviation
Address
Register name
R/W
Initial value
0FE9H
CMCR
Clock monitoring control register
R/W
XX000000B
0FEAH
CMDR
Clock monitoring data register
R/W
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (Upper)
R/W
XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (Lower)
R/W
XXXXXXXXB
0FEDH
—
(Disabled)
—
—
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH to
0FFFH
—
(Disabled)
—
—
R/W access symbols
R/W : Readable / Writable
R
: Read only
W
: Write only
Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an undefined value is returned.
Document Number: 002-07463 Rev. *B
Page 25 of 66
MB95200H/210H Series
16. Interrupt Source Table (MB95200H Series)
Interrupt source
Interrupt
request
number
Vector table address
Upper
Lower
Bit name of
interrupt level
setting register
External interrupt ch. 4
IRQ0
FFFAH
FFFBH
L00 [1:0]
External interrupt ch. 5
IRQ1
FFF8H
FFF9H
L01 [1:0]
External interrupt ch. 2
IRQ2
FFF6H
FFF7H
L02 [1:0]
IRQ3
FFF4H
FFF5H
L03 [1:0]
—
IRQ4
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0 (Upper)
IRQ6
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1:0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1:0]
—
IRQ9
FFE8H
FFE9H
L09 [1:0]
—
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
8/16-bit composite timer ch. 1 (Upper)
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
FFDCH
FFDDH
L15 [1:0]
—
IRQ16
FFDAH
FFDBH
L16 [1:0]
—
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
—
IRQ21
FFD0H
FFD1H
L21 [1:0]
8/16-bit composite timer ch. 1 (Lower)
IRQ22
FFCEH
FFCFH
L22 [1:0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1:0]
Priority order of interrupt sources of
the same level
(occurring
simultaneously)
High
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
Document Number: 002-07463 Rev. *B
Low
Page 26 of 66
MB95200H/210H Series
17. Interrupt Source Table (MB95210H Series)
Interrupt source
Interrupt
request
number
Vector table address
Upper
Lower
Bit name of
interrupt level
setting register
External interrupt ch. 4
IRQ0
FFFAH
FFFBH
L00 [1:0]
—
IRQ1
FFF8H
FFF9H
L01 [1:0]
IRQ2
FFF6H
FFF7H
L02 [1:0]
IRQ3
FFF4H
FFF5H
L03 [1:0]
—
IRQ4
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0 (Upper)
IRQ6
FFEEH
FFEFH
L06 [1:0]
—
IRQ7
FFECH
FFEDH
L07 [1:0]
—
IRQ8
FFEAH
FFEBH
L08 [1:0]
—
IRQ9
FFE8H
FFE9H
L09 [1:0]
—
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
—
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
FFDCH
FFDDH
L15 [1:0]
—
IRQ16
FFDAH
FFDBH
L16 [1:0]
—
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
—
IRQ21
FFD0H
FFD1H
L21 [1:0]
—
IRQ22
FFCEH
FFCFH
L22 [1:0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1:0]
—
External interrupt ch. 6
—
—
Document Number: 002-07463 Rev. *B
Priority order of interrupt sources of
the same level
(occurring
simultaneously)
High
Low
Page 27 of 66
MB95200H/210H Series
18. Electrical Characteristics
18.1 Absolute Maximum Ratings
Parameter
Power supply voltage*1
Input voltage*1
1
Output voltage*
Maximum clamp current
Total maximum clamp
current
“L” level maximum output
current
Symbol
Rating
VCC
VSS0.3
VSS6
V
VI1
VSS0.3
VCC0.3
V
Other than PF2*2
VI2
VSS0.3
10.5
V
PF2
VO
VSS0.3
VSS6
V
*2
ICLAMP
-2
+2
mA
Applicable to pins listed in *3
|ICLAMP|
—
20
mA
Applicable to pins listed in *3
IOL1
IOL2
“L” level average current
—
“H” level maximum output
current
15
—
mA
mA
12
IOL
—
100
mA
IOLAV
—
50
mA
IOH1
IOH2
—
IOHAV1
“H” level average current
-15
-15
mA
-4
—
mA
-8
IOHAV2
“H” level total maximum
output current
15
4
IOLAV2
“L” level total average output
current
IOH
—
-100
mA
IOHAV
—
-50
mA
Power consumption
Pd
—
320
mW
Operating temperature
TA
-40
+85
C
Tstg
-55
+150
C
“H” level total average output
current
Storage temperature
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
Document Number: 002-07463 Rev. *B
Other than P05, P06, P62 and P63*4
P05, P06, P62 and P63*4
Other than P05, P06, P62 and P63*4 Average
output current =
operating current operating ratio (1 pin)
P05, P06, P62 and P63*4
Average output current =
operating current operating ratio (1 pin)
Total average output current =
operating current operating ratio
(Total number of pins)
Other than P05, P06, P62 and P63*4
P05, P06, P62 and P63*4
Other than P05, P06, P62 and P63*4 Average
output current =
operating current operating ratio (1 pin)
P05, P06, P62 and P63*4
Average output current =
operating current operating ratio (1 pin)
Total average output current =
operating current operating ratio
(Total number of pins)
Page 28 of 66
MB95200H/210H Series
*1: The parameter is based on VSS = 0.0 V.
*2: VI and VO must not exceed VCC0.3 V. VI must not exceed the rated voltage. However, if the maximum current to/from an input
is limited by means of an external component, the ICLAMP rating is used instead of the VI rating.
*3: Applicable to the following pins: P00 to P07, P62 to P64, PG1, PG2, PF0, PF1 (P00 to P03, P07, P62 to P64, PG1, PG2, PF0 and
PF1 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.)
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV
(High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV
(High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current of stationary
current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential
may pass through the protective diode to increase the potential of the VCC pin, affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied
from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may
not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit:
Input/Output Equivalent Circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
*4: P62 and P63 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.
WARNING:
A semiconductor device may be damaged by applying stress (voltage, current, temperature, etc.) in excess of the
absolute maximum rating. Therefore, ensure that not a single parameter exceeds its absolute maximum rating.
Document Number: 002-07463 Rev. *B
Page 29 of 66
MB95200H/210H Series
18.2 Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Power supply
voltage
Symbol
VCC
Smoothing
capacitor
CS
Operating
temperature
TA
Value
Min
Max
2.4*1*2
5.5*1
2.3
5.5
2.9
5.5
2.3
5.5
0.022
1
-40
+85
+5
+35
Unit
Remarks
In normal operation
V
Other than on-chip debug mode
Hold condition in stop mode
In normal operation
On-chip debug mode
Hold condition in stop mode
µF
C
*3
Other than on-chip debug function
On-chip debug function
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have
a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from
unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between
CS and the VSS pin when designing the layout of a printed circuit board.
DBG / RSTX / C pin connection diagram
*
DBG
C
RSTX
Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/DBG.
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the electrical characteristics of the device are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact sales representatives beforehand.
Document Number: 002-07463 Rev. *B
Page 30 of 66
MB95200H/210H Series
18.3 DC Characteristics
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
“H” level input
voltage
“L” level input
voltage
Open-drain
output
application
voltage
“H” level output
voltage
“L” level output
voltage
Input leak
current (Hi-Z
output leak
current)
Pull-up
resistance
Symbol
Pin name
Condition
Value
Min
Typ
Max
Unit
Remarks
VIHI
P04
*1
0.7 VCC
—
VCC0.3
V
When CMOS input
level (hysteresis input)
is selected
VIHS
P00 to P07, P12,
P62 to P64,
PF0 to PF1,
PG1 to PG2
*1
0.8 VCC
—
VCC0.3
V
Hysteresis input
VIHM
PF2
—
0.7 VCC
—
10.5
V
Hysteresis input*5
VIL
P04
*1
VSS0.3
—
0.3 VCC
V
When CMOS input
level (hysteresis input)
is selected
VILS
P00 to P07, P12,
P62 to P64,
PF0 to PF1,
PG1 to PG2
*1
VSS0.3
—
0.2 VCC
V
Hysteresis input
VILM
PF2
—
VSS0.3
—
0.3 VCC
V
Hysteresis input
PF2, P12
—
VSS0.3
—
VSS+5.5
V
VOH1
Output pins other
than P05, P06,
P62, P63, PF2 and
P12*2
IOH = -4 mA
VCC0.5
—
—
V
VOH2
P05, P06, P62,
P63*2
IOH = -8 mA
VCC0.5
—
—
V
VOL1
Output pins other
than P05, P06,
P62 and P63*2
IOL = 4 mA
—
—
0.4
V
VOL2
P05, P06, P62,
P63*2
IOL = 2 mA
—
—
0.4
V
0.0 V < VI < VCC
-5
—
+5
µA
When pull-up
resistance is disabled
VI = 0 V
25
50
100
k
When pull-up
resistance is enabled
VD
ILI
RPULL
All input pins
P00 to P07, PG1,
PG2*3
(Continued)
Document Number: 002-07463 Rev. *B
Page 31 of 66
MB95200H/210H Series
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Input
capacitance
Symbol
Pin name
Value
Unit
Remarks
Min
Typ
Max
—
5
15
pF
—
13
17
mA
Flash memory
product (except
writing and erasing)
—
33.5
39.5
mA
Flash memory
product (at writing
and erasing)
—
15
21
mA
At A/D conversion
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
—
5.5
9
mA
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = +25 C
—
65
153
µA
ICCLS
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25 C
—
10
84
µA
ICCT
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25C
—
5
30
µA
CIN
Other than VCC
and VSS
ICCS
ICCL
f = 1 MHz
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
ICC
Power supply
current*4
Condition
VCC
(External clock
operation)
(Continued)
Document Number: 002-07463 Rev. *B
Page 32 of 66
MB95200H/210H Series
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Pin name
Value
Unit
Min
Typ
Max
VCC = 5.5 V
FCRH = 10 MHz
FMP = 10 MHz
Main CR clock mode
—
8.6
—
mA
VCC = 5.5 V
Sub-CR clock mode
(divided by 2)
TA = +25 C
—
110
410
µA
VCC = 5.5 V
FCH = 32 MHz
Timebase timer mode
TA = +25 C
—
1.1
3
mA
ICCH
VCC = 5.5 V
Substop mode
TA = +25 C
—
3.5
22.5
µA
ILVD
Current consumption
for low-voltage
detection circuit only
—
37
54
µA
Current consumption
for the internal main
CR oscillator
—
0.5
0.6
mA
Current consumption
for the internal sub-CR
oscillator oscillating at
100 kHz
—
20
72
µA
ICCMCR
VCC
ICCSCR
ICCTS
Power supply
current*4
Condition
ICRH
VCC
(External clock
operation)
VCC
ICRL
Remarks
Main stop mode for
single clock selection
*1: The input level of P04 can be switched between “CMOS input level” and “hysteresis input level”. The input level selection register
(ILSR) is used to switch between the two input levels.
*2: P62 and P63 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.
*3: P00 to P03, P07, PG1 and PG2 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.
*4: The power supply current is determined by the external clock. When the low-voltage detection option is selected, the power-supply
current will be the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to a specified value. In addition,
when both the low-voltage detection option and the CR oscillator are selected, the power supply current will be the sum of adding
up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a
specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and
current consumption therefore increases accordingly.
• See “18.4. AC Characteristics: 18.4.1.Clock Timing” for FCH and FCL.
• See “18.4. AC Characteristics: 18.4.2. Source Clock/Machine Clock” for FMP and FMPL.
*5 : PF2 act as high voltage supply for the flash memory during program and erase. It can tolerate high voltage input. For details, see
section “18.6. Flash Memory Program/Erase Characteristics”.
Document Number: 002-07463 Rev. *B
Page 33 of 66
MB95200H/210H Series
18.4 AC Characteristics
18.4.1 Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
FCH
Pin name
Condition
X0, X1
Remarks
Typ
Max
—
1
—
16.25
X0
X1 open
1
—
12
X0, X1
*
HCLK1,
HCLK2
—
1
—
32.5
MHz
9.7
10
10.3
7.76
8
8.24
0.97
1
1.03
MHz When the main CR clock is used
3.3 V Vcc 5.5 V(-40 C T 40 C)
MHz 2.4 V Vcc 3.3 V(0 C T A 40 C)
A
MHz
9.55
10
10.45
7.64
8
8.36
MHz When the main CR clock is used
3.3 V Vcc 5.5 V (40 C TA 85 C)
MHz
0.955
1
1.045
MHz
9.5
10
10.5
7.6
8
8.4
0.95
1
1.05
MHz When the main CR clock is used
2.4 V Vcc 3.3 V
MHz (-40 C T 0 C, 40 C T 85 C)
A
A
MHz
—
—
MHz When the main oscillation circuit is used
MHz When the main external clock is used
FCL
X0A, X1A
—
32.768
—
kHz
When the sub oscillation circuit is used
32.768
—
kHz
When the sub-external clock is used
FCRL
—
—
50
100
200
kHz
When the sub-CR clock is used
X0, X1
—
61.5
—
1000
ns
When the main oscillation circuit is used
X0
X1 open
83.4
—
1000
ns
When the external clock is used
X0, X1
*
HCLK1,
HCLK2
—
30.8
—
1000
ns
X0A, X1A
—
—
30.5
—
µs
When the subclock is used
X0
X1 open
33.4
—
—
ns
X0, X1
*
HCLK1,
HCLK2
—
12.4
—
—
ns
When the external clock is used, the
duty ratio should range between 40%
and 60%.
X0A
—
—
15.2
—
µs
Clock cycle time
tHCYL
tLCYL
Input clock pulse
width
Unit
Min
Clock frequency
FCRH
Value
tWH1
tWL1
tWH2
tWL2
(Continued)
Document Number: 002-07463 Rev. *B
Page 34 of 66
MB95200H/210H Series
(Continued)
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Pin name
X0
Input clock rise time
and fall time
CR oscillation start
time
Condition
X1 open
Value
Unit
Remarks
5
ns
When the external clock is used
—
5
ns
Min
Typ
Max
—
—
—
X0, X1
*
HCLK1,
HCLK2
—
tCRHWK
—
—
—
—
80
µs
When the main CR clock is used
tCRLWK
—
—
—
—
10
µs
When the sub-CR clock is used
tCR
tCF
* : The external clock signal is input to X0 and the inverted external clock signal to X1.
Document Number: 002-07463 Rev. *B
Page 35 of 66
MB95200H/210H Series
tHCYL
tWH1
tWL1
tCR
tCF
X0, X1, HCLK1, HCLK2
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
Figure of main clock input port external connection
When a crystal oscillator or When the external clock is used
a ceramic oscillator is used
(X1 is open)
X0
X1
X0
When the external clock is
used
X1
X0
When the external clock is
used
X1
HCLK1/HCLK2
Open
FCH
FCH
FCH
FCH
tLCYL
tWH2
tCR
X0A
tWL2
tCF
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
FCL
When the external clock is used
X0A
X1A
Open
FCL
Document Number: 002-07463 Rev. *B
Page 36 of 66
MB95200H/210H Series
18.4.2 Source Clock/Machine Clock
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Source clock cycle
time*1
Symbol
tSCLK
Pin
name
—
FSP
Source clock
frequency
—
FSPL
Machine clock cycle
time*2(minimum
instruction execution
time)
tMCLK
Unit
—
FMPL
Remarks
Min
Typ
Max
61.5
—
2000
ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
100
—
1000
ns
When the main CR clock is used
Min: FCRH = 10 MHz
Max: FCRH = 1 MHz
—
61
—
µs
When the sub-CR clock is used
FCL = 32.768 kHz, divided by 2
—
20
—
µs
When the sub-oscillation clock is used
FCRL = 100 kHz, divided by 2
0.5
—
16.25
1
—
10
MHz When the main CR clock is used
—
16.384
—
kHz
When the sub-oscillation clock is used
—
50
—
kHz
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
100
—
16000
ns
When the main CR clock is used
Min: FSP = 10 MHz
Max: FSP = 1 MHz, divided by 16
61
—
976.5
µs
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25
0.0625
—
10
1.024
—
16.384
kHz
When the sub-oscillation clock is used
3.125
—
50
kHz
When the sub-CR clock is used
FCRL = 100 kHz
MHz When the main oscillation clock is used
—
FMP
Machine clock
frequency
Value
MHz When the main oscillation clock is used
MHz When the main CR clock is used
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio selection bits (SYCC :
DIV1 and DIV0) . This source clock is divided to become a machine clock according to the division ratio set by the machine clock
division ratio selection bits (SYCC : DIV1 and DIV0) . In addition, a source clock can be selected from the following.
• Main clock divided by 2
• Main CR clock
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
Document Number: 002-07463 Rev. *B
Page 37 of 66
MB95200H/210H Series
Schematic diagram of the clock generation block
Divided
by 2
FCH
(main oscillation)
FCRH
(Internal main
CR clock)
FCL
(sub-oscillation)
FCRL
(Internal subCR clock)
SCLK
(source clock)
Divided
by 2
Divided
by 2
MCLK
(machine clock)
Machine clock division
ratio select bits
(SYCC : DIV1, DIV0)
Clock mode select bits
(SYCC2: RCS1, RCS0)
o
Division
circuit
x 1
x 1/4
x 1/8
x1/16
o
Operating voltage - Operating frequency (When TA = -40 C to +85 C)
MB95200H/210H (without the on-chip debug function)
5.5
5.0
A/D converter operation range
Operating voltage (V)
4.0
3.5
3.0
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
Operating voltage - Operating frequency (When TA = +5 oC to +35 oC)
MB95200H/210H (with the on-chip debug function)
5.5
5.0
A/D converter operation range
Operating voltage (V)
4.0
3.5
2.9
3.0
16 kHz
3 MHz
12.5 MHz
16.25 MHz
Source clock frequency (FSP)
Document Number: 002-07463 Rev. *B
Page 38 of 66
MB95200H/210H Series
18.4.3 External Reset
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Value
Symbol
RSTX “L” level pulse
width
tRSTL
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns
In normal operation
Oscillation time of the oscillator*2100
—
µs
In stop mode, subclock mode,
sub-sleep mode, watch mode, and
power on
100
—
µs
In timebase timer mode
*1: See “18.4.2. Source Clock/Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time that the amplitude reaches 90%. The crystal oscillator has an oscillation time of
between several ms and tens of ms. The ceramic oscillator has an oscillation time of between hundreds of µs and several ms.
The external clock has an oscillation time of 0 ms. The CR oscillator clock has an oscillation time of between several µs and
several ms.
In normal operation
tRSTL
RSTX
0.2 VCC
0.2 VCC
In stop mode, sub-clock mode, sub-sleep mode, watch mode, and power-on
tRSTL
RSTX
X0
0.2 VCC
0.2 VCC
90% of
amplitude
Internal
operating
clock
Oscillation
time of
oscillator
Internal reset
Document Number: 002-07463 Rev. *B
100 μs
Oscillation stabilization wait time
Execute instruction
Page 39 of 66
MB95200H/210H Series
18.4.4 Power-on Reset
(VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
Value
Unit
Min
Max
—
—
50
ms
—
1
—
ms
tR
Remarks
Wait time until power-on
tOFF
2.5 V
0.2 V
VCC
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on
reset function. When changing the power supply voltage during the
operation, set the slope of rising to within 30 mV/ms as shown below.
VCC
Limiting the slope of rising within
30 mV/ms is recommended.
2.3 V
Hold condition in stop mode
VSS
18.4.5 Peripheral Input Timing
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Peripheral input “H” pulse width
Peripheral input “L” pulse width
Symbol
Value
Pin name
tILIH
Min
INT02 to INT07, EC0, EC1*2
tIHIL
Max
Unit
2 tMCLK*1
—
ns
*1
—
ns
2 tMCLK
*1: See “18.4.2. Source Clock/Machine Clock” for tMCLK.
*2: INT02, INT03, INT05, INT07 and EC1 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.
tILIH
INT02 to INT07,
EC0, EC1*2
Document Number: 002-07463 Rev. *B
0.8 VCC
tIHIL
0.8 VCC
0.2 VCC
0.2 VCC
Page 40 of 66
MB95200H/210H Series
18.4.6 LIN-UART Timing (Available in MB95F204H/F203H/F202H/F204K/F203K/F202K only)
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.(ESCR register : SCES bit = 0,
ECCR register : SCDE bit = 0)
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK SOT delay time
tSLOVI
SCK, SOT
Valid SIN SCK
tIVSHI
SCK, SIN
SCK valid SIN hold time
tSHIXI
SCK, SIN
Serial clock “L” pulse width
tSLSH
SCK
Serial clock “H” pulse width
tSHSL
SCK
SCK SOT delay time
tSLOVE
SCK, SOT
Valid SIN SCK
tIVSHE
SCK, SIN
SCK valid SIN hold time
tSHIXE
SCK, SIN
Condition
Internal clock
operation output pin:
CL = 80 pF1 TTL
External clock
operation output pin:
CL = 80 pF1 TTL
Value
Unit
Min
Max
5 tMCLK*3
—
ns
-95
+95
ns
*3190
—
ns
0
—
ns
3 tMCLK*3tR
tMCLK*395
—
ns
—
ns
tMCLK
—
2
tMCLK*395
ns
190
—
ns
tMCLK*395
—
ns
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the
serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “18.4.2. Source Clock/Machine Clock” for tMCLK.
Document Number: 002-07463 Rev. *B
Page 41 of 66
MB95200H/210H Series
Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SIN
External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tR
tF
tSLOVE
2.4 V
SOT
0.8 V
tIVSHE
tSHIXE
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SIN
Document Number: 002-07463 Rev. *B
Page 42 of 66
MB95200H/210H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.(ESCR register : SCES bit = 1,
ECCR register : SCDE bit = 0)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Serial clock cycle time
SCK SOT delay time
tSCYC
tSHOVI
Pin name
SCK
SCK, SOT
Valid SIN SCK
tIVSLI
SCK, SIN
SCK valid SIN hold time
tSLIXI
SCK, SIN
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
Unit
Min
Max
5 tMCLK*3
—
ns
-95
+95
ns
tMCLK*3190
—
ns
0
—
ns
SCK
3 tMCLK* tR
—
ns
SCK
*395
—
ns
tSHOVE
SCK, SOT
Valid SIN SCK
tIVSLE
SCK, SIN
tSLIXE
Internal clock
operation output pin:
CL = 80 pF1 TTL
Value
3
SCK SOT delay time
SCK valid SIN hold time
Condition
SCK, SIN
tMCLK
External clock
operation output pin:
CL = 80 pF1 TTL
—
2
tMCLK*395
190
*395
tMCLK
ns
—
ns
—
ns
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the
serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “18.4.2. Source Clock/Machine Clock” for tMCLK.
Document Number: 002-07463 Rev. *B
Page 43 of 66
MB95200H/210H Series
Internal shift clock mode
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SIN
External shift clock mode
tSHSL
0.8 VCC
tSLSH
0.8 VCC
SCK
0.2 VCC
0.2 VCC
0.2 VCC
tF
tR
tSHOVE
2.4 V
SOT
0.8 V
tIVSLE
tSLIXE
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SIN
Document Number: 002-07463 Rev. *B
Page 44 of 66
MB95200H/210H Series
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.(ESCR register : SCES bit = 0,
ECCR register : SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK SOT delay time
tSHOVI
SCK, SOT
Valid SIN SCK
tIVSLI
SCK, SIN
SCK valid SIN hold time
tSLIXI
SCK, SIN
SOT SCK delay time
tSOVLI
Value
Condition
Internal clock
operation output pin:
CL = 80 pF1 TTL
SCK, SOT
Unit
Min
Max
5 tMCLK*3
—
ns
-95
+95
ns
tMCLK*3190
—
ns
0
—
—
ns
3
4 tMCLK*
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the
serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “18.4.2. Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN
0.8 V
tSHOVI
tSOVLI
tSLIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
Document Number: 002-07463 Rev. *B
Page 45 of 66
MB95200H/210H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK SOT delay time
tSLOVI
SCK, SOT
Valid SIN SCK
tIVSHI
SCK, SIN
SCK valid SIN hold time
tSHIXI
SCK, SIN
SOT SCK delay time
tSOVHI
Value
Condition
Internal clock operation
output pin:
CL = 80 pF1 TTL
Unit
Min
Max
5 tMCLK*3
—
ns
-95
+95
ns
tMCLK*3190
—
ns
0
—
SCK, SOT
ns
3
—
4 tMCLK*
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the
serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “18.4.2.Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
tSLOVI
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN
Document Number: 002-07463 Rev. *B
tSHIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
Page 46 of 66
MB95200H/210H Series
18.4.7 Low-voltage Detection
(VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Remarks
Release voltage
VDL
2.52
2.7
2.88
V
At power supply rise
Detection voltage
VDL
2.42
2.6
2.78
V
At power supply fall
Hysteresis width
VHYS
70
100
—
mV
Power supply start voltage
Voff
—
—
2.3
V
Power supply end voltage
Von
4.9
—
—
V
1
—
—
µs
Slope of power supply that the reset release
signal generates
—
3000
—
µs
Slope of power supply that the reset release
signal generates within the rating (VDL+)
300
—
—
µs
Slope of power supply that the reset
detection signal generates
—
300
—
µs
Slope of power supply that the reset
detection signal generates within the rating
(VDL-)
Power supply voltage change
time (at power supply rise)
Power supply voltage change
time (at power supply fall)
tr
tf
Reset release delay time
td1
—
—
300
µs
Reset detection delay time
td2
—
—
20
µs
Document Number: 002-07463 Rev. *B
Page 47 of 66
MB95200H/210H Series
VCC
Von
Voff
time
tf
tr
VDL+
VHYS
VDL-
Internal reset signal
time
td2
Document Number: 002-07463 Rev. *B
td1
Page 48 of 66
MB95200H/210H Series
18.5 A/D Converter
18.5.1 A/D Converter Electrical Characteristics
(VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Value
Symbol
Resolution
Total error
Linearity error
—
Differential linear
error
Unit
Min
Typ
Max
—
—
10
bit
-3
—
+3
LSB
-2.5
—
+2.5
LSB
-1.9
—
+1.9
LSB
Remarks
Zero transition
voltage
VOT
VSS1.5 LSB
VSS0.5 LSB
VSS2.5 LSB
V
Full-scale transition
voltage
VFST
VCC4.5 LSB
VCC2 LSB
VCC0.5 LSB
V
0.9
—
16500
µs
4.5 V VCC 5.5 V
1.8
—
16500
µs
4.0 V VCC 4.5 V
0.6
—
¥
µs
4.5 V VCC 5.5 V, with external
impedance 5.4 kΩ
1.2
—
¥
µs
4.0 V VCC 4.5 V, with external
impedance 2.4 kΩ
Compare time
—
Sampling time
—
Analog input current
IAIN
-0.3
—
+0.3
µA
Analog input voltage
VAIN
VSS
—
VCC
V
Document Number: 002-07463 Rev. *B
Page 49 of 66
MB95200H/210H Series
18.5.2 Notes on Using the A/D Converter
External impedance of analog input and its sampling time
■
The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog
voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore,
to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling
time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer
than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog
input pin.
Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
~ 1.95 kΩ (Max), C ~
4.5 V < VCC < 5.5 V : R ~
~ 17 pF (Max)
4.0 V < VCC < 4.5 V : R ~
~ 8.98 kΩ (Max), C ~
~ 17 pF (Max)
Note: The values are reference values.
Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 20 kΩ]
[External impedance = 0 kΩ to 100 kΩ]
20
External impedance [kΩ]
External impedance [kΩ]
100
90
80
70
60
(VCC >
= 4.5 V)
50
(VCC >
= 4.0 V)
40
30
20
10
18
16
14
12
(VCC >
= 4.5 V)
10
(VCC >
= 4.0 V)
8
6
4
2
0
0
0
2
4
6
8
10
12
14
0
Minimum sampling time [μs]
1
2
3
4
Minimum sampling time [μs]
A/D conversion error
As |VCCVSS| decreases, the A/D conversion error increases proportionately.
Document Number: 002-07463 Rev. *B
Page 50 of 66
MB95200H/210H Series
18.5.3 Definitions of A/D Converter Terms
■
Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
■
Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point
(“00 0000 0000” “00 0000 0001”) of a device to the full-scale transition point (“11 1111 1111“ “11 1111 1110”)
of the same device.
■
Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value.
■
Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a
full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
3FF
Total error
3FF
VFST
3FE
3FE
2.0 LSB
3FD
Digital output
Digital output
3FD
004
VOT
003
Actual conversion
characteristic
{1 LSB x (N-1) + 0.5 LSB}
004
VNT
003
1 LSB
002
Actual conversion
characteristic
002
Ideal characteristic
001
001
0.5 LSB
VSS
Analog input
1 LSB =
VCC
VCC - VSS
(V)
1024
VSS
Analog input
VCC
VNT - {1 LSB x (N - 1) + 0.5 LSB}
Total error of
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT: Voltage at which the digital output transits from (N - 1) to N
(Continued)
Document Number: 002-07463 Rev. *B
Page 51 of 66
MB95200H/210H Series
(Continued)
Zero transition error
Full-scale transition error
004
Ideal characteristic
Actual conversion
characteristic
3FF
Actual conversion
characteristic
Digital output
Digital output
003
002
Actual conversion
characteristic
Ideal
characteristic
3FE
VFST
(measurement
value)
3FD
Actual conversion
characteristic
001
3FC
VOT (measurement value)
VSS
VCC
Analog input
VSS
Linearity error
Differential linearity error
Ideal characteristic
Actual conversion
characteristic
3FF
N+1
3FE
Actual conversion
characteristic
Digital output
3FD
VFST
(measurement
value)
VNT
004
Actual conversion
characteristic
Digital output
{1 LSB x N + VOT}
003
V(N+1)T
N
VNT
N-1
Ideal
characteristic
002
VCC
Analog input
Actual conversion
characteristic
N-2
001
VOT (measurement value)
VSS
Analog input
VCC
VNT - {1 LSB x N + VOT}
Linearity error
=
of digital output N
1 LSB
VSS
Analog input
VCC
V(N+1)T - VNT
Differential linear error
=
- 1
of digital output N
1 LSB
N : A/D converter digital output value
VNT: Voltage at which the digital output transits from (N - 1) to N
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2.0 LSB [V]
Document Number: 002-07463 Rev. *B
Page 52 of 66
MB95200H/210H Series
18.6 Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
Min
Typ
Max
—
1*1
15*2
s
00H programming time prior to erasure is
excluded.
—
32
3600
µs
System-level overhead is excluded.
9.5
10
10.5
V
The erase/program voltage must be applied to the
PF2 pin in erase/program.
—
—
5.0
mA
Erase/program cycle
—
100000
—
cycle
Power supply voltage at
erase/program
3.0
—
5.5
V
Flash memory data retention time
20*3
—
—
year
Chip erase time
Byte programming time
Erase/program voltage
Current drawn on PF2
Current consumption of PF2 pin during flash
memory program/erase
Average TA = +85C
*1: TA = +25°C, VCC = 5.0 V, 100000 cycles
*2: TA = +85°C, VCC = 4.5 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from the result of a high
temperature accelerated test by using the Arrhenius equation with the average temperature being +85°C) .
Document Number: 002-07463 Rev. *B
Page 53 of 66
MB95200H/210H Series
19. Sample Electrical Characteristics
Power supply current•temperature
ICC - VCC
TA=+25°C, FMP=2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
ICC - TA
VCC=5.5 V, FMP=10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
20
15
15
FMP=16 MHz
10
FMP=10 MHz
FMP=8 MHz
5
ICC[mA]
ICC[mA]
FMP=16 MHz
10
FMP=10 MHz
5
FMP=4 MHz
FMP=2 MHz
0
0
2
3
4
5
6
-50
7
0
+50
+100
+150
TA[°C]
ICCS - VCC
TA=+25°C, FMP=2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
ICCS - TA
VCC=5.5 V, FMP=10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
20
20
15
15
ICCS[mA]
ICCS[mA]
VCC[V]
10
10
FMP=16 MHz
FMP=10 MHz
FMP=8 MHz
FMP=4 MHz
FMP=2 MHz
5
0
2
3
4
5
6
FMP=16 MHz
5
FMP=10 MHz
0
-50
7
0
+50
+150
ICCL - VCC
TA=+25°C, FMPL=16 kHz (divided by 2)
Subclock mode with the external clock operating
ICCL - TA
VCC=5.5 V, FMPL=16 kHz (divided by 2)
Subclock mode with the external clock operating
100
100
75
75
ICCL[µA]
ICCL[µA]
+100
TA[°C]
VCC[V]
50
50
25
25
0
0
2
3
4
5
VCC[V]
6
7
-50
0
+50
+100
+150
TA[°C]
(Continued)
Document Number: 002-07463 Rev. *B
Page 54 of 66
MB95200H/210H Series
(Continued)
ICCLS - VCC
TA=+25°C, FMPL=16 kHz (divided by 2)
Subsleep mode with the external clock operating
ICCLS - TA
VCC=5.5 V, FMPL=16 kHz (divided by 2)
Subsleep mode with the external clock operating
75
75
ICCLS[µA]
100
ICCLS[µA]
100
50
50
25
25
0
0
2
3
4
5
6
-50
7
0
+50
100
100
75
75
ICCT[µA]
ICCT[µA]
+150
ICCT - TA
V=5.5 V, FMPL=16 kHz (divided by 2)
Clock mode with the external clock operating
ICCT - VCC
TA=+25°C, FMPL=16 kHz (divided by 2)
Clock mode with the external clock operating
50
25
50
25
0
0
2
3
4
5
6
7
-50
0
VCC[V]
+50
+100
+150
TA[°C]
ICTS - VCC
TA=+25°C, FMP=2, 4, 8, 10, 16 MHz (divided by 2)
Timebase timer mode with the external clock operating
ICTS - TA
V=5.5 V, FMP=10, 16 MHz (divided by 2)
Timebase timer mode with the external clock operating
2.0
2.0
1.5
1.5
1.0
FMP=16 MHz
0.5
FMP=10 MHz
FMP=8 MHz
ICTS[mA]
ICTS[mA]
+100
TA[°C]
VCC[V]
FMP=16 MHz
1.0
FMP=10 MHz
0.5
FMP=4 MHz
FMP=2 MHz
0.0
0.0
2
3
4
5
VCC[V]
6
7
-50
0
+50
+100
+150
TA[°C]
(Continued)
Document Number: 002-07463 Rev. *B
Page 55 of 66
MB95200H/210H Series
ICCH - VCC
TA=+25°C, FMPL=(stop)
Substop mode wtih the external clock stopping
ICCH - TA
V=5.5 V, FMPL=(stop)
Substop mode with the external clock stopping
20
20
15
15
ICCH[µA]
ICCH[µA]
(Continued)
10
10
5
5
0
0
2
3
4
5
6
7
-50
0
VCC[V]
ICCMCR - VCC
TA=+25°C, FMP=1, 8, 10 MHz (no division)
Main clock mode with the internal main CR clock operating
+100
+150
ICCMCR - TA
V=5.5 V, FMPL=1, 8, 10 MHz (no division)
Main clock mode with the internal main CR clock operating
20
20
15
15
10
FMP=10 MHz
FMP=8 MHz
ICCMCR[mA]
ICCMCR[mA]
+50
TA[°C]
5
10
FMP=10 MHz
FMP=8 MHz
5
FMP=1 MHz
FMP=1 MHz
0
0
2
3
4
5
6
7
-50
0
+50
+100
+150
TA[°C]
ICCSCR - VCC
TA=+25°C, FMPL=50 kHz (divided by 2)
Subclock mode with the internal sub-CR clock operating
ICCSCR - TA
VCC=5.5 V, FMPL=50 kHz (divided by 2)
Subclock mode with the internal sub-CR clock operating
200
200
150
150
FMPL=50 kHz
100
50
ICCSCR[µA]
ICCSCR[µA]
VCC[V]
FMPL=50 kHz
100
50
0
0
2
3
4
5
VCC[V]
Document Number: 002-07463 Rev. *B
6
7
-50
0
+50
+100
+150
TA[°C]
Page 56 of 66
MB95200H/210H Series
Input voltage
VIHS - VCC and VILS - VCC
TA=+25°C
5
5
4
4
VIHI
3
VIHS
VIHS/VILS[V]
VIHI/VILI[V]
VIHI - VCC and VILI - VCC
TA=+25°C
VILI
2
3
VILS
2
1
1
0
0
2
3
4
5
6
7
2
3
VCC[V]
4
5
6
7
VCC[V]
VIHM - VCC and VILM - VCC
TA=+25°C
5
VIHM/VILM[V]
4
3
VIHM
VILM
2
1
0
2
3
4
5
6
7
VCC[V]
Document Number: 002-07463 Rev. *B
Page 57 of 66
MB95200H/210H Series
Output voltage
(VCC-VOH2) - IOH
TA=+25°C
(VCC-VOH1) - IOH
TA=+25°C
1.0
1.0
0.8
VCC-VOH2[V]
VCC-VOH1[V]
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0.0
0.0
0
-2
-4
-6
-8
0
-10
-2
-4
-8
-10
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
VOL2 - IOL
TA=+25°C
VOL1 - IOL
TA=+25°C
1.0
1.0
0.8
0.8
0.6
0.6
VOL2[V]
VOL1[V]
-6
IOH[mA]
IOH[mA]
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
0.4
0.2
0.4
0.2
0.0
0.0
0
2
4
6
8
10
0
2
4
6
IOL[mA]
IOL[mA]
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
Document Number: 002-07463 Rev. *B
8
10
12
Page 58 of 66
MB95200H/210H Series
Pull-up
RPULL - VCC
TA=+25°C
250
RPULL[kΩ]
200
150
100
50
0
2
3
4
5
6
VCC[V]
Document Number: 002-07463 Rev. *B
Page 59 of 66
MB95200H/210H Series
20. Mask Options
No.
1
2
Part Number
MB95F204H
MB95F203H
MB95F202H
MB95F214H
MB95F213H
MB95F212H
MB95F204K
MB95F203K
MB95F202K
MB95F214K
MB95F213K
MB95F212K
Selection Method
Setting disabled
Setting disabled
Low-voltage detection reset
•With low-voltage detection reset
•Without low-voltage detection reset
Without low-voltage detection reset
With low-voltage detection reset
Reset
•With dedicated reset input
•Without dedicated reset input
With dedicated reset input
Without dedicated reset input
21. Ordering Information
Part Number
Package
MB95F204HP-G-SH-SNE2
MB95F204KP-G-SH-SNE2
MB95F203HP-G-SH-SNE2
MB95F203KP-G-SH-SNE2
MB95F202HP-G-SH-SNE2
MB95F202KP-G-SH-SNE2
24-pin plastic SDIP
(DIP-24P-M07)
MB95F204HPF-G-SNE2
MB95F204KPF-G-SNE2
MB95F203HPF-G-SNE2
MB95F203KPF-G-SNE2
MB95F202HPF-G-SNE2
MB95F202KPF-G-SNE2
20-pin plastic SOP
(FPT-20P-M09)
MB95F214HPH-G-SNE2
MB95F214KPH-G-SNE2
MB95F213HPH-G-SNE2
MB95F213KPH-G-SNE2
MB95F212HPH-G-SNE2
MB95F212KPH-G-SNE2
8-pin plastic DIP
(DIP-8P-M03)
MB95F214HPF-G-SNE2
MB95F214KPF-G-SNE2
MB95F213HPF-G-SNE2
MB95F213KPF-G-SNE2
MB95F212HPF-G-SNE2
MB95F212KPF-G-SNE2
8-pin plastic SOP
(FPT-8P-M08)
Document Number: 002-07463 Rev. *B
Page 60 of 66
MB95200H/210H Series
22. Package Dimensions
24-pin plastic SDIP
Lead pitch
1.778 mm
Package width ×
package length
6.40 mm × 22.86 mm
Sealing method
Plastic mold
Mounting height
4.80 mm Max
(DIP-24P-M07)
24-pin plastic SDIP
(DIP-24P-M07)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
#22.86±0.10(.900±.004)
24
13
BTM E-MARK
INDEX
6.40±0.10
(.252±.004)
1
7.62(.300)
TYP.
12
0.50(.020)
MIN
4.80(.189)MAX
+0.10
+0.20
0.25 –0.04
+.008
+.004
3.00 –0.30 .118 –.012
1.778(.070)
C
.010 –.002
1.00±0.10
(.039±.004)
2008-2010 FUJITSU SEMICONDUCTOR LIMITED D24066S-c-1-2
+0.09
0.43 –0.04
+.004
.017 –.002
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
Document Number: 002-07463 Rev. *B
Page 61 of 66
MB95200H/210H Series
20-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
7.50 mm × 12.70 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
2.65 mm Max
(FPT-20P-M09)
20-pin plastic SOP
(FPT-20P-M09)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
0.25
#12.70±0.10(.500±.004)
.010
20
+0.07
–0.02
+.003
–.001
11
BTM E-MARK
+0.40
#7.50±0.10 10.2 –0.20
(.295±.004) .402 +.016
–.008
INDEX
Details of "A" part
+0.13
2.52 –0.17
(Mounting height)
+.005
.099 –.007
1
"A"
10
+0.09
1.27(.050)
0.40 –0.05
+.004
0.25(.010)
M
0~8°
.016 –.002
+0.47
0.80 –0.30
+.019
.031 –.012
0.20±0.10
(.008±.004)
(Stand off)
0.10(.004)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F20030S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
Document Number: 002-07463 Rev. *B
Page 62 of 66
MB95200H/210H Series
8-pin plastic DIP
Lead pitch
2.54 mm
Sealing method
Plastic mold
(DIP-8P-M03)
8-pin plastic DIP
(DIP-8P-M03)
9.40
.370
8
+0.40
–0.30
+.016
–.012
5
INDEX
6.35±0.25
(.250±.010)
1
4
7.62(.300)
TYP.
4.36(.172)MAX
0.50(.020)
MIN
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.35
0.46±0.08
(.018±.003)
0.89 –0.30
+.014
.035 –.012
+0.30
0.99 –0
.039
C
+.012
–0
+0.30
1.52 –0
15° MAX
+.012
.060 –0
2.54(.100)
TYP.
2006-2010 FUJITSU SEMICONDUCTOR LIMITED D08008S-c-1-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
Document Number: 002-07463 Rev. *B
Page 63 of 66
MB95200H/210H Series
(Continued)
8-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
5.30 mm × 5.24 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
2.10 mm Max
(FPT-8P-M08)
8-pin plastic SOP
(FPT-8P-M08)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
#5.24±0.10
(.206±.004)
8
5
"A"
BTM E-MARK
#5.30±0.10
(.209±.004)
INDEX
7.80
.307
+0.45
–0.10
+.018
–.004
Details of "A" part
2.10(.083)
MAX
(Mounting height)
1
1.27(.050)
4
0.43±0.05
(.017±.002)
0.20±0.05
(.008±.002)
0~8°
+0.15
0.10 –0.05
+.006
.004 –.002
(Stand off)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F08016S-c-1-2
Document Number: 002-07463 Rev. *B
+0.10
0.75 –0.20
+.004
.030 –.008
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 64 of 66
MB95200H/210H Series
23. Major Changes
Spansion Publication Number: DS07-12623-5E
Page
30
Section
Electrical Characteristics
1. Absolute Maximum Ratings
33
Corrected the maximum value of Open-drain output application voltage.
0.2Vcc → Vss 5.5
36
42
43
58
Changed the characteristics of Input voltage.
Corrected the maximum value of “H” level input voltage for PF2 pin.
VCC 0.3 → 10.5
3. DC Characteristics
39
Change results
Added the footnote *5.
4. AC Characteristics
(1) Clock Timing
Added a figure of HCLK1/HCLK2.
(2) Source Clock/Machine Clock
Corrected the graph of Operating voltage - Operating frequency
(with the on-chip debug function).
(Corrected the pitch)
(3) External Reset
Added “and power on” to the remarks column.
6. Flash Memory Program/Erase
Characteristics
Added the row of “Current drawn on PF2”.
Corrected the minimum value of Power supply voltage at erase/program.
4.5 → 3.0
Note: Please see “Document History” about later revised information.
Document History
Document Title: MB95200H/210H Series F2MC-8FX 8-bit Microcontroller
Document Number: 002-07463
Revision
ECN
Orig. of
Change
Submission
Date
**
–
AKIH
07/16/2010
Migrated to Cypress and assigned document number 002-07463.
No change to document contents or format.
Description of Change
*A
5177811
AKIH
03/18/2016
Updated to Cypress format.
*B
5861642
YSAT
08/24/2017
Adapted new Cypress logo
Document Number: 002-07463 Rev. *B
Page 65 of 66
MB95200H/210H Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs | Training
| Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2008-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be
reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any
claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and
other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-07463 Rev. *B
Revised August 24, 2017
Page 66 of 66