AD AD1986 Ac â 97 soundmax codec Datasheet

AC ’97 SoundMAX CODEC
AD1986
FEATURES
AC `97 2.3 COMPLIANT FEATURES
6 DAC channels for 5.1 surround
S/PDIF output
Integrated headphone amplifiers
Variable rate audio
Double rate audio (Fs = 96 kHz)
Greater than 90 dB dynamic range
20-bit resolution on all DACs
20-bit resolution on all ADCs
Line-level mono phone input
High quality CD input
Selectable MIC input w/preamp
AUX and line-in stereo inputs
External amplifier power down (EAPD)
Power management modes
Jack sensing and device identification
48-pin LQFP package
ENHANCED FEATURES
Integrated parametric equalizer
Stereo microphone with up to 30 dB gain boost
Integrated PLL for system clocking
Variable sample rate: 7 kHz to 96 kHz
7 kHz to 48 kHz in 1 Hz increments
96 kHz for double rate audio
Jack sense with auto topology switching
Jack presence detection on up to 8 jacks
Three software-controlled VREF_OUT signals
Software-enabled outputs for jack sharing
Auto-down mix and channel spreading
Microphone-to-mono output
Stereo microphone pass-through to mixer
Built-in microphone/center/LFE/line-in sharing
Built-in SURROUND/LINE_IN sharing
Center/LFE line swapping
Microphone swapping
Reduced support component count
General purpose digital output pin (GPO)
Separate LINE_OUT and HP_OUT pins
Headphone drivers on LINE_OUT and HP_OUT pins
Independent headphone/LINE_OUT operation
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD1986
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 4
Surround DAC PCM Rate (Register 0x2E) ............................ 30
Specifications..................................................................................... 5
C/LFE DAC PCM Rate (Register 0x30) .................................. 30
AC ’97 Timing Parameters .......................................................... 9
ADC PCM Rate (Register 0x32) .............................................. 30
Absolute Maximum Ratings.......................................................... 12
C/LFE DAC Volume (Register 0x36)....................................... 31
Environmental Conditions........................................................ 12
Surround DAC Volume (Register 0x38) ................................. 31
ESD Caution................................................................................ 12
SPDIF Control (Register 0x3A)................................................ 32
Pin Configuration And Function Description ........................... 13
EQ Control Register (Register 0x60) ....................................... 33
AC ’97 Registers .............................................................................. 15
EQ Data Register (Register 0x62) ............................................ 34
Register Details ............................................................................... 17
Misc Control Bits 2 (Register 0x70)......................................... 34
Reset (Register 0x00).................................................................. 17
Jack Sense (Register 0x72)......................................................... 35
Master Volume (Register 0x02) ................................................ 17
Serial Configuration (Register 0x74)....................................... 37
Headphone Volume (Register 0x04)........................................ 18
Misc Control Bits 1 (Register 0x76)......................................... 39
Mono Volume (Register 0x06).................................................. 18
Advanced Jack Sense (Register 0x78) ...................................... 40
PC Beep (Register 0x0A)........................................................... 19
Misc Control Bits 3 (Register 0x7A)........................................ 41
Phone Volume (Register 0x0C) ................................................ 19
Vendor ID Registers (Register 0x7C to 0x7E) ........................ 42
Microphone Volume (Register 0x0E) ...................................... 20
CODEC Class/Revision Register (Register 0x60).................. 42
Line In Volume (Register 0x10)................................................ 21
PCI Subsystem Vendor ID Register (Register 0x62, Page 01)
....................................................................................................... 43
CD Volume (Register 0x12) ...................................................... 21
AUX Volume (Register 0x16) ................................................... 22
Front DAC Volume (Register 0x18)......................................... 22
ADC Select (Register 0x1A)...................................................... 23
ADC Volume (Register 0x1C) .................................................. 24
General-Purpose (Register 0x20)............................................. 25
Audio Int and Paging (Register 0x24) ..................................... 25
Power-Down Ctrl/Stat (Register 0x26).................................... 26
Ext’d Audio ID (Register 0x28)................................................. 27
Ext’d Audio Stat/Ctrl (Register 0x2A)...................................... 28
PCI Subsystem Device ID Register (Register 0x64, Page 01)43
Function Select Register (Register 0x66, Page 01)................. 43
Information and I/O Register (Register 0x68, Page 01)........ 44
Sense Register (Register 0x6A, Page 01) ................................. 46
Jack Presence Detection................................................................. 48
Audio Jack Styles (NC/NO) ...................................................... 48
Microphone Selection/Mixing...................................................... 49
Outline Dimensions ....................................................................... 50
Ordering Guide .......................................................................... 50
Front DAC PCM Rate (Register 0x2C) ................................... 29
REVISION HISTORY
10/04—Initial Version: Revision 0
Rev. 0 | Page 2 of 52
AD1986
NOTES
•
REDUCED SUPPORT COMPONENTS
The AD1986’s many improvements reduce external support
components for particular applications.
•
•
•
Multiple Microphone Sourcing: The MIC_1/2, LINE_IN
and C/LFE pins may all be selected as sources for
microphone input (boost amplifier).
Multiple VREF_OUT Pins: Each microphone-capable pin
group (MIC_1/2, LINE_IN and C/LFE) has separate,
software controllable VREF_OUT pins, reducing the need
for external biasing components.
Internal Microphone Mixing: Any combination of the
MIC_1/2, LINE_IN and C/LFE pins may be summed to
produce the microphone input. This removes the need for
external mixing components in those applications that
externally mixed microphone sources.
•
•
•
Rev. 0 | Page 3 of 52
Advanced Jack Presence Detection: Using two CODEC
pins, eight resistors and isolated switch jacks, the AD1986
can detect jack insertion on eight separate jacks. Previous
CODECs would have required 8 CODEC pins and
16 resistors.
Internal Microphone/Line In/C/LFE Sharing: On systems
that share the microphone with the C/LFE jack there are
no external components required. The micro-phone
selector can select the LINE_IN pins in those cases where
the microphone and line input devices are swapped.
Internal Line In/Microphone/Surround Sharing: On
systems that share the line in with the surround jack there
are no external components required.
Dual Headphone Amplifiers: The AD1986 can drive
headphones out of the HP_OUT or LINE_OUT pins.
AD1986
FUNCTIONAL BLOCK DIAGRAM
SPDIF_OUT
AC97CK
SPDIF TX
PLL
AD1986
MICROPHONE
SELECTOR/
MIXING AND
GAIN BLOCK
MIC_2
CODEC CORE
M
20-BIT
Σ-∆ ADC
G
M
20-BIT
Σ-∆ ADC
LINE
IN
SELECT
A
SPRD
MZ
CENTER_OUT
A
M
GA
24-BIT
Σ-∆ DAC
SPRD
MZ
M
GA
24-BIT
Σ-∆ DAC
MZ
A
SURR_OUT_R
MZ
A
HP_OUT_L
HP_OUT_R
HP
HP
M
M
M
A
A
A
A
LOSEL
HP
M
HPSEL
LINE_OUT_R
HP
HPSEL
LINE_OUT_L
M
M
M
GA
GA
GA
M
M
GA
M
M
GA
GA
M
M
GA
M
M
M
M
A
Σ
Σ
Σ
M
G = GAIN
A = ATTENUATION
M = MUTE
Z = HI-Z
PC BEEP
GENERATOR
M
GA
24-BIT
Σ-∆ DAC
EQ
M
GA
24-BIT
Σ-∆ DAC
EQ
M
GA
24-BIT
Σ-∆ DAC
M
GA
GPIO
EAPD
24-BIT
Σ-∆ DAC
VOLTAGE
REFERENCE
M
VREF_FILT
Figure 1.
Rev. 0 | Page 4 of 52
SYNC
BITCLK
SDATA_OUT
SDATA_IN
AC '97
CONTROL
REGISTERS
GA
M
LOSEL
SURR_OUT_L
SOSEL
A
SOSEL
M
MIX
GA
MONO_OUT
ADC
SLOT
LOGIC
DAC
SLOT
LOGIC
PCBEEP_IN
LFE_OUT
AC '97 INTERFACE V2.3
G
RESET
ANALOG MIXING CONTROL
JACK SENSE
AUX_L
AUX_R
LINE_IN_L
LINE_IN_R
RECORD
SELECTOR
CD
DIFF AMP
EQ COEF STORAGE
PHONE_IN
CD_L
CD_GND
CD_R
G
Z
G
Z
G
Z
JACK_SENSE_A
JACK_SENSE_B
EAPD
GPO
VREF_OUT
(MIC1/2)
VREF_OUT
(C/LFE)
VREF_OUT
(LINE_IN)
04785-0-003
MIC_1
AD1986
SPECIFICATIONS
Test conditions, unless otherwise noted.
Table 1.
Parameter
Temperature
Digital Supply (DVDD)
Analog Supply (AVDD)
Sample Rate (FS)
Input Signal
Analog Output Pass Band
VIH
VIL
VIH
VIL
Typ
25
3.3 ±10%
5.0 ±10%
48
1,008
20 Hz–20 kHz
2.0
0.8
2.4
0.6
DAC Test Conditions
Calibrated
Output −3 dB Relative to Full Scale
10 kΩ Output Load: Line (Surround), Mono, Center, and LFE
32 Ω Output Load: Headphone
Unit
°C
V
V
kHz
Hz
V
V
V
V
ADC Test Conditions
Calibrated
0 dB PGA Gain
Input −3.0 dB Relative to Full Scale
Table 2. Analog Input
Input Voltage
MIC_1/2, LINE_IN, CD, AUX, PHONE_IN (No Preamp)
C/LFE and SURROUND (When Used as Inputs)
MIC_1/2, LINE_IN, C/LFE With 30 dB Preamp
Min
MIC_1/2, LINE_IN, C/LFE With 20 dB Preamp
MIC_1/2, LINE_IN, C/LFE With 10 dB Preamp
Input Impedance2
Input Capacitance
2
1
2
Typ
1
2.83
0.032
0.089
0.1
0.283
0.316
0.894
20
5
Max
7.5
Unit
VRMS1
V p-p
VRMS
V p-p
VRMS
V p-p
VRMS
V p-p
kΩ
pF
RMS values assume sine wave input.
Guaranteed by design, not production tested.
Table 3. Master Volume
Parameter
Step Size (LINE_OUT, HP Out, Mono Out, SURROUND, CENTER, LFE)
Output Attenuation Range (0 dB to –46.5 dB)
Mute Attenuation of 0 dB Fundamental
2
Min
Typ
−1.5
−6.5
Max
−80
Unit
dB
dB
dB
Table 4. Programmable Gain Amplifier—ADC
Parameter
Step Size
PGA Gain Range Span (0 dB to 22.5 dB)
Min
Rev. 0 | Page 5 of 52
Typ
1.5
22.5
Max
Unit
dB
dB
AD1986
Table 5. Analog Mixer—Input Gain/Amplifiers/Attenuators
Parameter
Signal-to-Noise Ratio (SNR)
CD to LINE_OUT
LINE, AUX, PHONE to LINE_OUT1
MIC_1 or MIC_2 to LINE_OUT1
Step Size: All Mixer Inputs (Except PC Beep)
Step Size: PC Beep
Input Gain/Attenuation Range: All Mixer Inputs (+12 dB to −34.5 dB)
1
Min
Typ
Max
90
88
80
−1.5
−3.0
−46.5
Unit
dB
dB
dB
dB
dB
dB
Guaranteed by design, not production tested.
Table 6. Digital Decimation and Interpolation Filters1
Parameter
Pass Band
Pass Band Ripple
Transition Band
Stop Band
Stop Band Rejection
Group Delay
Group Delay Variation Over Pass Band
Min
0
Typ
0.4 × FS
0.6 × FS
−74
Max
0.4 × FS
±0.09
0.6 × FS
∞
16/FS
0
Unit
Hz
dB
Hz
Hz
dB
S
µs
Table 7. Analog-to-Digital Converters
Parameter
Resolution
Total Harmonic Distortion (THD)
Dynamic Range (−60 dB Input, THD + N referenced to Full Scale, A-Weighted)
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
LINE_IN to Other Inputs
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error
Rev. 0 | Page 6 of 52
Min
Typ
20
−95
−85
−80
−100
±10
Max
−80
±0.5
±5
Unit
Bits
dB
dB
dB
dB
%
dB
mV
AD1986
Table 8. Digital-to-Analog Converters
Parameter
Resolution
Total Harmonic Distortion (LINE_OUT Drive)
Total Harmonic Distortion HP_OUT
Dynamic Range (−60 dB Input, THD + N referenced to Full Scale, A-Weighted)
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk1 (Input L, Zero R, Read R_OUT; Input R, Zero L, Read L_OUT)
1
Min
Typ
24
−92
−75
91
±10
Max
Unit
Bits
dB
dB
dB
%
dB
dB
±0.7
−80
Guaranteed by design, not production tested.
Table 9. Analog Output
Parameter
FULL-SCALE OUTPUT VOLTAGE: SURROUND, CENTER/LFE, MONO_OUT
Output Impedance1
External Load Impedance1
Output Capacitance1
External Load Capacitance
FULL-SCALE OUTPUT VOLTAGE: HP_OUT, LINE_OUT
Min
Typ
1
2.83
300
Max
10
15
1,000
1
2.83
Output Impedance1
External Load Impedance1
Output Capacitance1
External Load Capacitance1
VREF_FILT, AVDD = 5.0 V
AVDD = 3.3 V
VREF_OUT(MIC, C/LFE, LIN) (xVREF [2:0] = 001)
(xVREF [2:0] = 100, AVDD = 5.0 V)
(xVREF [2:0] = 100, AVDD = 3.3 V)
(xVREF [2:0] = 010)
Current Drive
Mute Click (Muted Output, Unmuted Midscale DAC Output)
1
32
15
2.050
2.250
1.125
2.250
3.700
2.250
0.0
1,000
2.450
5
±5
Unit
VRMS
V p-p
Ω
kΩ
pF
pF
VRMS
V p-p
Ω
Ω
pF
pF
V
V
V
V
V
V
mA
mV
Table 10. Static Digital Specifications—AC ’97
Parameter
High Level Input Voltage (VIH), Digital Inputs
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH), IOH = 2 mA
Low Level Output Voltage (VOL), IOL = 2 mA
Input Leakage Current
Output Leakage Current
Input/Output Pin Capacitance
Min
0.65 × DVDD
Typ
Max
0.35 × DVDD
0.90 × DVDD
−10
−10
Rev. 0 | Page 7 of 52
0.10 × DVDD
10
10
7.5
Unit
V
V
V
V
µA
µA
pF
AD1986
Table 11. Power Supply (Quiescent State)
Parameter
Power Supply Range—Analog (AVDD) ±10%
Power Supply Range—Digital (DVDD) ±10%
Power Dissipation—Analog (AVDD)/Digital (DVDD)
Analog Supply Current—Analog (AVDD)
Digital Supply Current—Digital (DVDD)
Power Supply Rejection (100 mV p–p Signal @ 1 kHz)
Min
4.5
2.97
Typ
Max
5.5
3.63
365/171.6
73
52
40
Unit
V
V
mW
mA
mA
dB
Table 12. Power-Down States—AC ’97 (Quiescent State)
Parameter
ADC
FRONT DAC
CENTER DAC
SURROUND DAC
LFE DAC
ADC + ALL DACs
Mixer
ADC + Mixer
ALL DACs + Mixer
ADC + ALL DACs + Mixer
Standby
Headphone Standby
LINE_OUT HP Standby
Set Bits
PR0
PR1
PRI
PRJ
PRK
PR1, PR0, PRI, PRJ, PRK
PR2
PR2, PR0
PR2, PR1, PRI, PRJ, PRK
PR2, PR1, PR0, PRI, PRJ, PRK
PR5, PR4, PR3, PR2, PR1(IJK), PR0
PR6
LOHPEN = 0
DVDDTyp
53.0
53.7
62.0
53.5
62.0
27.0
36.6
27.6
12.6
2.4
0.0
55.0
62.0
AVDD Typ
45.7
47.7
53.2
47.1
52.8
14.5
53.2
45.7
33.0
14.5
0.05
53.2
53.2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Max
Unit
MHz
60
%
Table 13. Clock Specifications—AC ’971
Parameter
Input Clock Frequency (Reference Clock Mode)
Min
Recommended Clock Duty Cycle
40
1
Typ
14.31818
48.000
50
Refer to AC ’97, Revision 2.3 specifications for details of clock detection at startup. AD1986 CODEC clock source detection must follow AC ’97, Revision 2.3 guidelines.
Rev. 0 | Page 8 of 52
AD1986
AC ’97 TIMING PARAMETERS
Guaranteed over operating temperature range. Refer to the AC ’97 specifications (Revision 2.3, Release 1.0) for further information. The
specification can be downloaded from http://developer.intel.com/ial.scalableplatforms/audio.
tRST2CLK
tRST_LOW
04785-0-005
RESET
BIT_CLK
Figure 2. Cold Reset Timing (CODEC is Supplying the BIT_CLK Signal)
Table 14.
Symbol
tRST_LOW
tRST2CLK
Parameter
Recommended During Active (Low) RESET Signal
RESET Inactive (High) to BIT_CLK Active
tSYNC_HIGH
Min
1.0
162.8
Typ
Max
400,000
Unit
µS
nS
tSYNC2CLK
04785-0-006
SYNC
BIT_CLK
Figure 3. Warm Reset Timing
Table 15.
Symbol
tSYNC_HIGH
tSYNC2CLK
Parameter
Sync Active (High) Pulse Width
Sync Inactive to BITCLK Startup Delay
Min
Typ
1.3
Max
162.8
Unit
µS
nS
RESET
SDATA_OUT
SYNC
Hi-Z
tOFF
04785-0-007
tSETUP2RST
BIT_CLK, EAPD,
SPDIF_OUT,
SDATA_IN,
DIGITAL I/O
Figure 4. ATE Test Mode
Table 16.
Symbol
tSETUP2RST
tOFF
Parameter
Setup to RESET Inactive (SYNC, SDATA_OUT)
Rising Edge of RESET to Hi-Z Delay
Rev. 0 | Page 9 of 52
Min
15
Typ
Max
25
Unit
nS
nS
AD1986
tCLK_LOW
BIT_CLK
tCLK_HIGH
tCLK_PERIOD
tSYNC_LOW
04785-0-008
SYNC
tSYNC_HIGH
tSYNC_PERIOD
Figure 5. Bit Clock and Sync Timing
Table 17.
Symbol
tSYNC_HIGH
tCLK_LOW
tCLK_PERIOD
tSYNC_HIGH
tSYNC_LOW
tSYNC_PERIOD
1
2
Parameter
BITCLK High Pulse Width
BITCLK Low Pulse Width
BITCLK Period
BIT_CLK Frequency
BIT_CLK Frequency Accuracy
BIT_CLK Jitter1, 2
Sync Active (High) Pulse Width
Sync Inactive (Low) Pulse Width
Sync Period
Sync Frequency
Min
40.5
39.7
Typ
Max
41.7
40.6
81.4
12.288
±1.0
750
1.3
19.5
20.8
48.0
Units
nS
nS
nS
MHz
ppm
ps
µS
µS
µS
kHz
Guaranteed by design, but not production tested.
Output jitter directly dependent on input clock jitter.
SLOT 1
SLOT 2
WRITE TO
03 26
DATA
PR4
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
BIT_CLK NOT TO SCALE
04785-0-009
tS2_PDOWN
Figure 6. Link Low Power Mode Timing
Table 18.
Symbol
tS2_PDOWN
Parameter
End of Slot 2 to BIT_CLK, SDATA_IN Low
Rev. 0 | Page 10 of 52
Min
0
Typ
Max
1.0
Units
µS
AD1986
BIT_CLK
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
SYNC
SDATA_OUT
04785-0-010
SDATA_IN
Figure 7. Signal Rise and Fall Times
Table 19.
Symbol
tRISECLK
tFALLCLK
tRISESYNC
tRISESYNC
tRISEDIN
tRISEDIN
tRISEDOUT
tRISEDOUT
Parameter
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
Min
2
2
2
2
2
2
2
2
Typ
4
4
4
4
4
4
4
4
Max
6
6
6
6
6
6
6
6
Unit
nS
nS
nS
nS
nS
nS
nS
nS
tCO
tSETUP
BIT_CLK
VIH
VIL
SDATA_OUT
VOH
SDATA_IN
SYNC
04785-0-011
VOL
tHOLD
Figure 8. Link Low Power Mode Timing (Detail)
Table 20.
Symbol
tCO
tSETUP
tHOLD
VIH
VIL
VOH
VOL
Parameter
Propagation Delay
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
Digital Signal High Level Input Voltage
Digital Signal Low Level Input Voltage
Digital Signal High Level Output Voltage
Digital Signal Low Level Output Voltage
Min
Typ
Max
25
4
3
0.65 DVDD
0.35 DVDD
0.9 DVDD
0.1 DVDD
Rev. 0 | Page 11 of 52
Unit
nS
nS
nS
V
V
V
V
AD1986
ABSOLUTE MAXIMUM RATINGS
ENVIRONMENTAL CONDITIONS
Table 21.
Power Supply
Digital (DVDD)
Analog (AVDD)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Commercial
Industrial
Storage Temperature
Min
−0.3
−0.3
−0.3
−0.3
Max
+3.6
+6.0
±10.0
AVDD + 0.3
DVDD + 0.3
0
–40
−65
+70
+85
+150
Unit
V
V
mA
V
V
°C
Ambient Temperature Rating
TAMB = TCASE − (PD × θCA)
TCASE = case temperature in °C
PD = power dissipation in W
θCA = thermal resistance (case-to-ambient)
θJA = thermal resistance (junction-to-ambient)
θJC = thermal resistance (junction-to-case)
Table 22. Thermal Resistance
°C
Package
LQFP
θJA
76.2°C/W
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 12 of 52
θJC
17°C/W
θCA
59.2°C/W
AD1986
MONO_OUT
AVDD
HEADPHONE_L
AVSS
HEADPHONE_R
AVDD
LINE_OUT_L
AVSS
LINE_OUT_R
AVDD
EAPD
S/PDIF_OUT
PIN CONFIGURATION AND FUNCTION DESCRIPTION
48 47 46 45 44 43 42 41 40 39 38 37
DVDD 1
AC97CK 2
PIN 1
IDENTIFIER
36
SURR_OUT_R
35
SURR_OUT_L
GPO 3
34
AVDD
DVSS 4
33
VREF_OUT (C/LFE)
32
LFE_OUT
31
CENTER_OUT
30
AVSS
29
VREF_OUT (LINE_IN)
DVDD 9
28
VREF_OUT (MIC_1/2)
SYNC 10
27
VREF_FILT
RESET 11
26
AVSS
PCBEEP 12
25
AVDD
SDATA_OUT 5
AD1986
BIT_CLK 6
TOP VIEW
(Not to Scale)
DVSS 7
SDATA_IN 8
04785-0-001
LINE_IN_R
LINE_IN_L
MIC_2
MIC_1
CD_R
CD_GND
CD_L
JACK_SENSE_B
JACK_SENSE_A
AUX_R
AUX_L
PHONE_IN
13 14 15 16 17 18 19 20 21 22 23 24
Figure 9. Pin Configuration
Table 23. Pin Function Descriptions
Mnemonic
AC ’97CK
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
Pin Number
2
5
6
8
10
11
Input/Ouput
I
I
O
I/O
I
I
Description
External Clock In (14.31818 MHz).
AC Link Serial Data Output. Input Stream.
AC Link Bit Clock. 12.288 MHz Serial Data Clock.
AC Link Serial Data Input. Output Stream.
AC Link Frame Sync .
AC Link Reset. Master Hardware Reset.
Table 24. Digital Input/Output
Mnemonic
S/PDIF_OUT
EAPD
GPO
Pin
Number
48
47
3
Input/
Output
O
O
O
Description
S/PDIF Output.
External Amplifier Power-Down Output.
General-Purpose Output pin. A digital signal that can be used to control external circuitry.
Table 25. Jack Sense
Mnemonic
JACK_SENSE_A
JACK_SENSE_B
Pin Number
16
17
Input/Ouput
I
I
Rev. 0 | Page 13 of 52
Description
JackSense 0–3 Input
Jack Sense 4–7 Input
AD1986
Table 26. Analog Input/Output
Mnemonic
PCBEEP
PHONE_IN
AUX_L
AUX_R
CD_L
CD_GND
CD_R
MIC_1
MIC_2
LINE_IN_L
LINE_IN_R
CENTER_OUT
LFE_OUT
HEADPHONE_L
HEADPHONE_R
LINE_OUT_L
LINE_OUT_R
MONO_OUT
SURR_OUT_L
SURR_OUT_R
Pin
Number
12
13
14
15
18
19
20
21
22
23
24
31
32
39
41
43
45
37
35
36
Input/
Ouput
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
O
O
O
O
O
I/O
I/O
Description
Analog PC Beep Input. Routed to all output capable pins when RESET is asserted.
Monaural Line Level Input.
Auxiliary Left Channel Input.
Auxiliary Right Channel Input.
CD-Audio-Left Channel.
CD-Audio-Analog-Ground-Reference (for Differential CD Input).
CD-Audio-Right Channel.
Microphone 1 or Line-In-Left Input (See LISEL Bits in Register 0x76).
Microphone 2 or Line-In-Right Input (See LISEL Bits in Register 0x76).
Line-In-Left Channel or Microphone 1 Input (See OMS Bits in Register 0x74).
Line-In-Right Channel or Microphone 2 Input (See OMS Bits in Register 0x74).
Center-Channel Output or Microphone 1 Input (See OMS Bits in Register 0x74).
Low-Frequency-Enhanced Output or Microphone 2 Input (See OMS Bits in Register 0x74).
Headphone-Out-Left Channel (See HPSEL Bits in Register 0x76).
Headphone-Out-Right Channel (See HPSEL Bits in Register 0x76).
Line-Out (Front)—Left Channel (See LOSEL Bit in Register 0x76) (HP Drive-Capable).
Line-Out (Front)—Right Channel (See LOSEL Bit in Register 0x76) (HP Drive-Capable).
Monaural Output to Telephony Subsystem Speakerphone.
Surround-Left Channel Output or Line-In-Left Input (See LISEL and SOSEL Bits in Register 0x76).
Surround-Right Channel Output or Line-In-Right Input (See LISEL and SOSEL Bits in
Register 0x76).
Table 27. Filter/Reference
Mnemonic
VREF_FILT
VREF_OUT (MIC)
VREF_OUT
(LINE_IN)
VREF_OUT (C/LFE)
Pin
Number
27
28
29
Input/
Ouput
O
O
O
Description
Voltage Reference Filter.
Programmable Voltage Reference Output (Intended for MIC Bias on the MIC_1/2 Channels).
Programmable Voltage Reference Output (Intended for MIC Bias on the LINE_IN Channels).
33
O
Programmable Voltage Reference Output (Intended for MIC Bias on the C/LFE Channels).
Table 28. Power and Ground
Mnemonic
DVDD
DVSS
AVDD
AVSS
Pin Number
1
9
4
7
25
34
38
42
46
26
30
40
44
Input/
Ouput
Description
Digital Supply Voltage (3.3 V).
Digital Supply Return (Ground).
Analog Supply Voltage (5.0 V or 3.3 V). AVDD supplies should be well filtered because supply
noise will degrade audio performance.
I
Analog Supply Return (Ground).
Rev. 0 | Page 14 of 52
AD1986
AC ’97 REGISTERS
Table 29. Register Map
Reg Name
0x00 Reset
D15
x
D14
SE4
D13
SE3
D12
SE2
D11
SE1
D10
SE0
D9
ID9
D8
ID8
D7
ID7
D6
ID6
D5
ID5
D4
ID4
D3
ID3
D2
ID2
D1
ID1
D0
ID0
Default
0x0290
0x02 Master Volume
LM
x
x
LV4
LV3
LV2
LV1
LV0
RM
x
x
RV4
RV3
RV2
RV1
RV0
0x8080
0x04 Headphones Volume LM
x
x
LV4
LV3
LV2
LV1
LV0
RM
x
x
RV4
RV3
RV2
RV1
RV0
0x8080
0x06 Mono Volume
M
x
x
x
x
x
x
x
x
x
x
V4
V2
V2
V1
V0
0x8000
0x0A PC Beep
M
A/DS
x
F7
F6
F5
F4
F3
F2
F1
F0
V3
V2
V1
V0
x
0x8000
0x0C Phone Volume
M
x
x
x
x
x
x
x
x
x
x
V4
V3
V2
V1
V0
0x8008
0x0E Microphone Volume
LM
x
x
LV4
LV3
LV2
LV1
LV0
RM
M20
x
RV4
RV3
RV2
RV1
RV0
0x8888
0x10 Line In Volume
LM
x
x
LV4
LV3
LV2
LV1
LV0
RM
x
x
RV4
RV3
RV2
RV1
RV0
0x8888
0x12 CD Volume
LM
x
x
LV4
LV3
LV2
LV1
LV0
RM
x
x
RV4
RV3
RV2
RV1
RV0
0x8888
0x16 AUX Volume
LM
x
x
LV4
LV3
LV2
LV1
LV0
RM
x
x
RV4
RV3
RV2
RV1
RV0
0x8888
0x18 Front DAC Volume
LM
x
x
LV4
LV3
LV2
LV1
LV0
RM
x
x
RV4
RV3
RV2
RV1
RV0
0x8888
0x1A ADC Select
x
x
x
x
x
LS2
LS1
LS0
x
x
x
x
x
RS2
RS1
RS0
0x0000
0x1C ADC Volume
LM
x
x
x
LV3
LV2
LV1
LV0
RM
x
x
x
RV3
RV2
RV1
RV0
0x8080
0x20 General Purpose
x
x
x
x
DRSS1 DRSS0 MIX
MS
LPBK
x
x
x
x
x
x
x
0x0000
0x24 Audio Int. and Paging I4
I3
I2
I1
I0
x
x
x
x
x
x
x
PG3
PG2
PG1
PG0
0xxx00
0x26 Power-Down Ctrl/Stat EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
x
x
x
x
REF
ANL
DAC
ADC
0x000x
0x28 Ext’d Audio ID
ID11
ID0
x
x
REV1
REV0
AMAP
LDAC
SDAC CDAC DSA1
x
SPDF
DRA
VRA
0x0BC7
0x2A Ext’d Audio Stat/Ctrl
x
x
PRK
PRJ
PRI
SPCV
x
LDAC
SDAC CDAC SPSA1 SPSA0
x
SPDIF
DRA
VRA
0x0xx0
0x2C Front DAC PCM Rate
R15
R14
R13
R12
R11
R10
R09
R08
R07
R06
R05
R04
R03
R02
R01
R00
0xBB80
0x2E Surr. DAC PCM Rate
R15
R14
R13
R12
R11
R10
R09
R08
R07
R06
R05
R04
R03
R02
R01
R00
0xBB80
0x30 C/LFE DAC PCM Rate
R15
R14
R13
R12
R11
R10
R09
R08
R07
R06
R05
R04
R03
R02
R01
R00
0xBB80
0x32 ADC PCM Rate
R15
R14
R13
R12
R11
R10
R09
R08
R07
R06
R05
R04
R03
R02
R01
R00
0xBB80
0x36 C/LFE DAC Volume
LFEM
x
x
LFE4
LFE3
LFE2
LFE1
LFE0
CNTM x
x
CNT4
CNT3
CNT2
CNT1
CNT0
0x8888
0x38 Surround DAC Volume LM
x
x
LV4
LV3
LV2
LV1
LV0
RM
x
x
RV4
RV3
RV2
RV1
RV0
0x8888
0x3A SPDIF Control
V
VCFG
SPSR
x
L
CC6
CC5
CC4
CC3
CC2
CC1
CC0
PRE
COPY
/AUDIO PRO
0x2000
0x60 EQ Control
EQM
x
x
x
x
x
x
x
SYM
CHS
BCA5
BCA4
BCA3
BCA2
BCA1
BCA0
0x8080
0x62 EQ Data
CFD15
CFD14
CFD13
CFD12 CFD11 CFD10 CFD9
CFD8
CFD7
CFD6 CFD5
CFD4
CFD3
CFD2
CFD1
CFD0
0xxxxx
0x70 Misc. Control Bits 2
x
x
x
MVREF2 MVREF1 MVREF0 x
x
MMDIS x
x
0x0000
0x72 Jack Sense
JS1 SPRD JS1 DMX JS0 DMX JS MT2 JS MT1 JS MT0 JS1 EQB JS0 EQB x
0x74 Serial Configuration
SLOT16 REGM2
0x76 Misc. Control Bits 1
DACZ
REGM1 REGM0 REGM3 OMS2
OMS1
AC97NC2 MSPLT
SODIS3 CLDIS
x
0x78 Advanced Jack Sense JS7ST
JS7INT
JS6INT JS5ST
JS5INT JS4ST
0x7A Misc. Control Bits 3
HPSEL1 HPSEL0 LOSEL
JSINVB
JS6ST
OMS0
x
DSA0
JSMAP CVREF2 CVREF1 CVREF0 x
JS1 MD JS0 MD JS1 ST JS0 ST JS1 INT JS0 INT 0x0000
SPOVR LBKS1 LBKS0 INTS
DMIX1 DMIX0 SPRD
2CMIC SOSEL SRU
JS4INT JS4-7H x
JSINVA LVREF2 LVREF1 LVREF0 x
CSWP
SPAL
SPDZ
SPLNK 0x1001
LISEL1 LISEL0 MBG1 MBG0 0x6010
JS3MD JS2MD JS3ST
JS2ST
JS3INT JS2INT 0xxxxx
x
x
LOHPEN GPO
MMIX
x
S5
x
0x0000
0x7C Vendor ID1
F7
F6
F5
F4
F3
F2
F1
F0
S7
S6
S4
S3
S2
S1
S0
0x4144
0x7E Vendor ID2
T7
T6
T5
T4
T3
T2
T1
T0
REV7
REV6 REV5
REV4
REV3
REV2
REV1
REV0
0x5378
0x601 CODEC Class/Rev
0x621 PCI SVID
x
PVI15
x
PVI14
x
PVI13
CL4
PVI12
CL3
PVI11
CL2
PVI10
CL1
PVI9
CL0
PVI8
RV7
PVI7
RV6
PVI6
RV5
PVI5
RV4
PVI4
RV3
PVI3
RV2
PVI2
RV1
PVI1
RV0
PVI0
0x0002
0xFFFF
0x641 PCI SID
PI15
PI14
PI13
PI12
PI11
PI10
PI9
PI8
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
0xFFFF
Rev. 0 | Page 15 of 52
AD1986
Reg Name
0x661 Function Select
D15
x
D14
x
D13
x
D12
x
D11
x
D10
x
D9
x
D8
x
D7
x
D6
x
D5
x
D4
FC3
D3
FC2
D2
FC1
D1
FC0
D0
T/R
Default
0x0000
0x681 Function Information G4
G3
G2
G1
G0
INV
DL4
DL3
DL2
DL1
DL0
IV
x
x
x
FIP
0xXxxx
0x6A1 Sense Register
ST1
ST0
S4
S3
S2
S1
S0
OR1
OR0
SR5
SR4
SR3
SR2
SR1
SR0
0xXxxx
ST2
1
CODEC is always master, ID bits are read-only 0 (zeros).
Bits for the AD198x are backwards-compatible only, AC97NC and MSPLT are read-only 1 (ones).
3
SODIS/SOSEL were LODIS/LOSEL in the AD1985. Most AD1985 configurations swapped LINE_OUT and SURROUND pins; these bits really operated as SO not LO.
2
Rev. 0 | Page 16 of 52
Preliminary Technical Data
AD1986
REGISTER DETAILS
RESET (REGISTER 0x00)
Writing any value to this register performs a register reset, which causes all registers to revert to their default values. The serial
configuration (0x74) register will not reset the SLOT16, REGM [2:0], SPOVR, SPAL, SPDZ, and SPLNK. These bits are reset on a hard,
hardware, or power-on reset. The REGM and serial configuration bits are only reset only by an external hardware reset.
The AC ’97, Revision 2.3, Page 1 registers CODEC class/rev (0x601), PCI SVID (0x621), PCI SID (0x641), function information (0x681—
per supported function), and sense register ST [3:0] bits (0x6A1 D [15:13]—per supported function) are only reset on a power-on reset.
To satisfy the AC ’97, Revision 2.3 requirements, these registers/bits are sticky across all software and hardware resets.
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
Reg
0x00
Name
Reset
D15
x
D14
SE4
D13
SE3
D12
SE2
D11
SE1
D10
SE0
D9
ID9
D8
ID8
D7
ID7
D6
ID6
D5
ID5
D4
ID4
D3
ID3
D2
ID2
D1
ID1
D0
ID0
Default
0x0290
Table 30.
Register
ID [9:0] (RO)
(Identify
Capability)
SE [4:0] (RO)
(Stereo
Enhancement)
x
Function
The ID decodes the capabilities of the AD1986 based on the functions.
Bit
Function
ID0
Dedicated MIC PCM In channel
ID1
Reserved (per AC ’97, Revision 2.3)
ID2
Bass and treble control
ID3
Simulated stereo (mono to stereo)
ID4
Headphone out support
ID5
Loudness (bass boost) support
ID6
18-bit DAC resolution
ID7
20-bit DAC resolution
ID8
18-bit ADC resolution
ID9
20-bit ADC resolution
The AD1986 does not provide hardware 3D stereo enhancement
(all bits are zero).
AD1986
ID [9:0]
0
0
0
0
1
0x290
0
0
1
0
1
Default: 0x00
Reserved.
Default: 0
MASTER VOLUME (REGISTER 0x02)
This register controls the LINE_OUT, SURROUND, and CENTER/LFE outputs’ mute and volume controls in unison. Each volume subregister contains five bits, generating 32 volume steps of −1.5 dB each for a range of 0 dB to −46.5dB.
The headphone output (HP_OUT) mute and volume are controlled separately by the headphones volume register (0x04).The monaural
output (MONO_OUT) mute and volume is controlled separately by the mono volume register (0x06). To control the LINE_OUT,
SURROUND, and CENTER/LFE volumes separately use the front DAC volume register (0x18) for LINE_OUT; the surround DAC
Volume register (0x38) for SURROUND; and the C/LFE DAC volume register (0x36) for CENTER/LFE.
Reg
0x02
Name
Master
Volume
D15
LM
D14
x
D13
x
D12
LV4
D11
LV3
D10
LV2
D9
LV1
D8
LV0
Rev. 0 | Page 17 of 52
D7
RM
D6
x
D5
x
D4
RV4
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x8080
AD1986
Preliminary Technical Data
Table 31.
Register
L/RV [4:0]
(Left/Right
Volume)
Function
Left/right volume controls the left/right channel output gains from 0 dB to –46.5 dB.
The least significant bit represents –1.5 dB.
L/RM
L/RV [4:0]
Function
0
0 0000
0 dB
0
0 1111
−22.5 dB attenuation
0
1 1111
−46.5 dB attenuation
1
x xxxx
Muted
Mutes the left/right channels independently.
L/RM
(Left/right mute)
x
Default
Default
Default: muted (0x1)
Reserved.
Default: 0
HEADPHONE VOLUME (REGISTER 0x04)
This register controls the HP_OUT mute and volume controls. Each volume subregister contains five bits, generating 32 volume steps of
−1.5 dB each for a range of 0 dB to −46.5 dB.
Reg
0x04
Name
Headphones
Volume
D15
LM
D14
x
D13
x
D12
LV4
D11
LV3
D10
LV2
D9
LV1
D8
LV0
D7
RM
D6
x
D5
x
D4
RV4
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x8080
Table 32.
Register
L/RV [4:0]
(Left/Right
Volume)
L/RM
(Left/Right Mute)
x
Function
Left/right volume controls the left/right channel output gains from 0 dB to –46.5 dB.
The least significant bit represents –1.5 dB.
L/RM
L/RV [4:0]
Function
0
0 0000
0 dB
0
0 1111
−22.5 dB attenuation
0
1 1111
−46.5 dB attenuation
1
x xxxx
Muted
Mutes the left/right channels independently.
Default
Default
Default: muted (0x1)
Reserved.
Default: 0
MONO VOLUME (REGISTER 0x06)
This register controls the MONO_OUT mute and volume control. The volume register contains five bits, generating 32 volume steps of
−1.5 dB each for a range of 0 dB to −46.5 dB.
Reg
0x06
Name
Mono Volume
D15
M
D14
x
D13
x
D12
x
D11
x
D10
x
D9
x
D8
x
D7
x
D6
x
D5
x
D4
V4
D3
V3
D2
V2
D1
V1
D0
V0
Default
0x8000
Table 33.
Register
V [4:0]
(Volume)
M (Mute)
x
Function
Volume controls the output gain from 0 dB to –46.5 dB. The least significant bit represents -1.5 dB.
M
V [4:0]
Function
Default
0
0 0000
0 dB
Default
0
0 1111
−22.5 dB attenuation
0
1 1111
−46.5 dB attenuation
1
x xxxx
Muted
Mutes the output.
Default: muted (0x1)
Reserved.
Default: 0
Rev. 0 | Page 18 of 52
Preliminary Technical Data
AD1986
PC BEEP (REGISTER 0x0A)
This controls the level of the Analog PC beep or the level and frequency of the Digital PC beep. The volume register contains four bits,
generating 16 volume steps of −3.0 dB each for a range of 0 dB to −45.0 dB. The tone frequency can be set between 47 Hz to 12,000 Hz or
disabled.
Per Intel’s BIOS writer’s guide, the PC beep signal should play via headphone out, line out, and mono out paths. BIOS algorithms should
unmute the PC beep register and the path to each output, and set the volume levels for playback.
When the AD1986 is in reset (the external RESET pin is low), the PCBEEP_IN pin is connected internally to all of the device output pins
(HEADPHONE L/R, LINE_OUT L/R, MONO_OUT, SURROUND L/R, and CENTER/LFE). There are no amplifiers or attenuators on
this path and the external circuitry connected to this pin should anticipate the drive requirements for the multiple output sources.
Headphones connected to output pins will substantially load the signal.
Reg
0x0A
Name
PC
Beep
D15
M
D14
A/DS
D13
x
D12
F7
D11
F6
D10
F5
D9
F4
D8
F3
D7
F2
D6
F1
D5
F0
D4
V3
D3
V2
D2
V1
D1
V0
D0
x
Default
0x8000
Table 34.
Register
V [3:0]
(Analog or
Digital
Volume)
Function
Controls the gain into the output mixer from 0 dB to −45.0 dB. The least significant bit represents −3.0 dB. The gain default
is 0 dB and muted.
M
V3...V0
Function
Default
0
0000
0 dB
Default
0
1111
−45 dB attenuation
1
xxxx
Muted
F [7:0]
(PC Beep
Frequency)
The result of dividing the 48 kHz clock by four times this number, allowing tones from 47 Hz to 12 kHz. A value of 0x00
disables internal PC beep generation. The digitally-generated signal is close to a square wave and is not intended to be a
high quality signal.
F7...F0
Function
0000
Disabled
Default
0001
12,000 Hz tone
1111
47 Hz tone
Default: digitally-selected
Selects either the digital PC beep generator (= 0) or analog PCBEEP pin (= 1). When the
(0x0)
CODEC is in reset mode the analog PCBEEP pin is routed to the outputs via a high
impedance path. Once ot of reset, this bit must be programmed to a 1 to pass through any
signals on the analog PCBEEP pin. Designers may choose not to connect the analog PCBEEP
pin and use the digital PC beep generator solely.
When this bit is set to 1, the PC beep signal (analog or digital) is muted.
Default: muted (0x1)
A/DS
(PC Beep
Source)
M
(PC Beep
Mute)
x
Reserved.
Default: 0
PHONE VOLUME (REGISTER 0x0C)
This register controls the PHONE_IN mute and gain to the analog mixer section. The volume register contains five bits, generating
32 volume steps of 1.5 dB each for a range of 12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).
Reg
0x0C
Name
Phone
Volume
D15
M
D14
x
D13
x
D12
x
D11
x
D10
x
D9
x
D8
x
Rev. 0 | Page 19 of 52
D7
x
D6
x
D5
x
D4
V4
D3
V3
D2
V2
D1
V1
D0
V0
Default
0x8008
AD1986
Preliminary Technical Data
Table 35.
Register
V [4:0]
(Volume)
Function
Controls the gain of this input to the analog mixer from 12.0 dB to −34.5 dB. The least significant bit represents −1.5 dB.
MV
[4:0]
Function
Default
0
0 0000
12 dB gain
0
0 1000
0 dB
Default
0
1 1111
−34.5 dB attenuation
1
x xxxx
Muted
Mutes the input to the analog mixer.
Default: muted (0x1)
Reserved.
Default: 0
M (Mute)
x
MICROPHONE VOLUME (REGISTER 0x0E)
This register controls the MIC_1 (left) and MIC_2 (right) channels’ gain, boost, and mute to the analog mixer section. The volume
register contains five bits, generating 32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the
record ADC gain (see Register 0x1C).
In typical stereo microphone applications, the signal paths must be identical and should be set to the same gain, boost, and mute values.
With stereo controls, this input is capable of nonmicrophone sources by disabling the microphone boost (M20 Bit = 0).
Reg
0x0E
Name
Microphone
Volume
D15
LM
D14
x
D13
x
D12
LV4
D11
LV3
D10
LV2
D9
LV1
D8
LV0
D7
RM
D6
M20
D5
x
D4
RV4
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x8888
Table 36.
Register
L/RV [4:0]
(Left/Right
Volume)
M20
(MIC_1/2
Gain
Boost)
L/RM
(Left/Right
Mute)
x
Function
Controls the left/right channel gains of this input to the analog mixer from +12 dB to −34.5 dB. The least significant bit
represents −1.5 dB.
L/RM
L/RV [4:0]
Function
Default
0
0 0000
12 dB gain
0
0 1000
0 dB
Default
0
1 1111
−34.5 dB attenuation
1
x xxxx
Mute
Enables additional gain to increase the microphone sensitivity. This controls the boost of both the MIC_1 and MIC_2 channels.
The nominal gain boost by default is 20 dB; however, MBG0 [1:0] bits (Register 0x76), allow changing the gain boost to 10 dB
or 30 dB if necessary.
M20
MGB0 [1:0]
Boost Gain
0
xx
0 dB gain
Default: disabled
1
00
20 dB gain
Default
1
01
10 dB gain
1
x xxxx
Mute
Mutes the left/right channels independently.
Default: muted (0x1)
Reserved.
Default: 0
Rev. 0 | Page 20 of 52
Preliminary Technical Data
AD1986
LINE IN VOLUME (REGISTER 0x10)
This register controls the LINE_IN gain and mute to the analog mixer section. The volume register contains five bits, generating
32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).
Reg
0x10
Name
Line In
Volume
D15
LM
D14
x
D13
x
D12
LV4
D11
LV3
D10
LV2
D9
LV1
D8
LV0
D7
RM
D6
x
D5
x
D4
RV4
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x8888
Table 37.
Register
L/RV [4:0]
(Left/Right
Volume)
L/RM
(Left/Right
Mute)
x
Function
Controls the left/right channel gains of this input to the analog mixer from 12 dB to −34.5 dB. The least significant bit
represents −1.5 dB.
L/RM
L/RV [4:0]
Function
Default
0
0 0000
12 dB gain
0
0 1000
0 dB
Default
0
1 1111
−34.5 dB attenuation
1
x xxxx
Muted
Mutes the left/right channels independently.
Default: muted (0x1)
Reserved.
Default: 0
CD VOLUME (REGISTER 0x12)
This register controls the CD gain and mute to the analog mixer section. The volume register contains five bits, generating 32 volume
steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).
Many operating systems will play CDs directly using the digital data from the CD tracks. This control will only affect CD audio playback
if it is enabled for analog and this input is connected to the CD player analog connection.
Reg
0x12
Name
CD Volume
D15
LM
D14
x
D13
x
D12
LV4
D11
LV3
D10
LV2
D9
LV1
D8
LV0
D7
RM
D6
x
D5
x
D4
RV4
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x8888
Table 38.
Register
L/RV [4:0]
(Left/Right
Volume)
L/RM
(Left/Right
Mute)
x
Function
Controls the left/right channel gains of this input to the analog mixer from +12 dB to –34.5 dB. The least significant bit
represents –1.5 dB.
L/RM
L/RV [4:0]
Function
Default
0
0 0000
12 dB gain
0
0 1000
0 dB
Default
0
1 1111
−34.5 dB attenuation
1
x xxxx
Muted
Mutes the left/right channels independently.
Default: muted (0x1)
Reserved.
Default: 0
Rev. 0 | Page 21 of 52
AD1986
Preliminary Technical Data
AUX VOLUME (REGISTER 0x16)
This register controls the AUX_IN gain and mute to the analog mixer section. The volume register contains five bits, generating
32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).
Reg
0x16
Name
AUX
Volume
D15
LM
D14
x
D13
x
D12
LV4
D11
LV3
D10
LV2
D9
LV1
D8
LV0
D7
RM
D6
x
D5
x
D4
RV4
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x8888
Table 39.
Register
L/RV [4:0]
(Left/Right
Volume)
L/RM
(Left/Right
Mute)
x
Function
Controls the left/right channel gains of this input to the analog mixer from +12 dB to −34.5 dB. The least significant bit
represents −1.5 dB.
L/RM
L/RV [4:0]
Function
Default
0
0 0000
12 dB gain
0
0 1000
0 dB
Default
0
1 1111
−34.5 dB attenuation
1
x xxxx
Mute
Mutes the left/right channels independently.
Default: muted (0x1)
Reserved.
Default: 0
FRONT DAC VOLUME (REGISTER 0x18)
This register controls the front DAC gain and mute to the analog mixer section. The volume register contains five bits, generating
32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB.
Reg
0x18
Name
Front DAC
Volume
D15
LM
D14
x
D13
x
D12
LV4
D11
LV3
D10
LV2
D9
LV1
D8
LV0
D7
RM
D6
x
D5
x
D4
RV4
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x8888
Table 40.
Register
L/RV [4:0]
(Left/Right Volume)
L/RM
(Left/Right Mute)
x
Function
Controls the left/right channel gains of this input to the analog mixer from +12 dB to −34.5 dB. The least significant
bit represents −1.5 dB.
L/RM
L/RV [4:0]
Function
Default
0
0 0000
+12 dB gain
0
0 1000
0 dB
Default
0
1 1111
−34.5 dB attenuation
1
x xxxx
Mute
Mutes the left/right channels independently.
Default: muted (0x1)
Reserved.
Default: 0
Rev. 0 | Page 22 of 52
Preliminary Technical Data
AD1986
ADC SELECT (REGISTER 0x1A)
This register selects the record source for the ADC, independently for the right and left channels. The default value is 0x0000, which
corresponds to the MIC_1/2 input for both channels.
Reg
0x1A
Name
ADC
Select
D15
x
D14
x
D13
x
D12
x
D11
x
D10
LS2
D9
LS1
D8
LS0
D7
x
D6
x
D5
x
D4
x
D3
x
D2
RS2
D1
RS1
Table 41.
Register
LS [2:0]
(Left Record Select)
RS [2:0]
(Right Record Select)
LS [2:0]
000
001
010
011
100
101
110
111
RS [2:0]
000
001
010
011
100
101
110
111
Left Record Source
MIC_1/2 selector left channel
CD_IN
Muted
AUX_IN
LINE_IN
Stereo output mix
Mono output mix
PHONE_IN
Right Record Source
MIC_1/2 selector left channel
CD_IN
Muted
AUX_IN
LINE_IN
Stereo output mix
Mono output mix
PHONE_IN
Function
Default
Left
Left
Left
Left
Mono
Mono
Default
Right
Right
Right
Right
Mono
Mono
Table 42. Microphone Selector
OMS [2:0]1
000
000
000
000
000
001
001
001
001
001
01x
01x
01x
01x
01x
100
100
100
100
100
MMIX2
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
2CMIC3
0
0
1
1
x
0
0
1
1
x
0
0
1
1
x
0
0
1
1
x
MS4
0
1
0
1
x
0
1
0
1
x
0
1
0
1
x
0
1
0
1
x
Left Channel5
MIC_1
MIC_2
LINE_IN left
LINE_IN right
CENTER
LFE
MIC_1 + CENTER (mixed)
MIC_2 + LFE (mixed)
Right Channel
MIC_1 (default)
MIC_2
MIC_2
MIC_1
MIC_1 + MIC_2 (mixed)
LINE_IN left
LINE_IN right
LINE_IN right
LINE_IN left
Line in—left + right (mixed)
CENTER
LFE
LFE
CENTER
CENTER + LFE (mixed)
MIC_1 + CENTER (mixed)
MIC_2 + LFE (mixed)
MIC_2 + LFE (mixed)
MIC_1 + CENTER (mixed)
MIC_1 + MIC_2 + CENTER + LFE (mixed)
Rev. 0 | Page 23 of 52
D0
RS0
Default
0x0000
AD1986
Preliminary Technical Data
OMS [2:0]1
MMIX2
2CMIC3
MS4
Left Channel5
101
101
101
101
101
110
110
110
110
110
111
111
111
111
111
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
x
0
0
1
1
x
0
0
1
1
x
0
1
0
1
x
0
1
0
1
x
0
1
0
1
x
MIC_1 + LINE_IN left (mixed)
MIC_2 + LINE_IN right (mixed)
MIC_1 + LINE_IN left (mixed)
MIC_2 + LINE_IN right (mixed)
MIC_2 + LINE_IN right (mixed)
MIC_1 + LINE_IN left (mixed)
MIC_1 + MIC_2 + LINE_IN left + LINE right (mixed)
LINE_IN left + CENTER (mixed)
LINE_IN right + LFE (mixed)
LINE_IN left + CENTER (mixed)
LINE_IN right + LFE (mixed)
LINE_IN right + LFE (mixed)
LINE_IN left + CENTER (mixed)
LINE_IN left + LINE_IN right + CENTER + LFE (mixed)
MIC_1 + LINE_IN left + CENTER (mixed)
MIC_2 + LINE_IN right + LFE (mixed)
MIC_1 + LINE_IN left + CENTER (mixed)
MIC_2 + LINE_IN right + LFE (mixed)
MIC_2 + LINE_IN right + LFE (mixed)
MIC_1 + LINE_IN left + CENTER (mixed)
MIC_1 + MIC_2 + LINE_IN left + LINE_IN right + CENTER + LFE (mixed)
Right Channel
1
To select the alternate pins as a microphone source, see the OMS [2:0] bit (Register 0x74).
To mix the left/right MIC channels see MMIX bit (Register 0x7A).
3
For dual MIC recording see 2CMIC bit (Register 0x76) to enable simultaneous recording into L/R channels.
4
To swap left/right MIC channels, see the MS bit (Register 0x20) for MIC_1/2 selection.
5
The MONO_OUT pin may be connected to the left channel of the microphone selector and is affected by these bits.
2
ADC VOLUME (REGISTER 0x1C)
This register controls the mute and gain of the ADC record path. The volume register contains four bits, generating 16 volume steps of
1.5 dB each for a range of 0 dB to 22.5 dB.
Reg
0x1C
Name
ADC Volume
D15
LM
D14
x
D13
x
D12
x
D11
LV3
D10
LV2
D9
LV1
D8
LV0
D7
RM
D6
x
D5
x
D4
x
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x8080
Table 43.
Register
L/RV [4:0]
(Left/Right
Volume)
L/RM
(Left/Right Mute)
x
Function
Controls the left/right channel gains of this input to the analog mixer from 0 dB to 22.5 dB The least significant bit
represents 1.5 dB.
L/RM
L/RV [3:0]
Function
Default
0
0000
0 dB
Default
0
1000
12.0 dB gain
0
1111
22.5 dB gain
1
xxxx
Muted
Mutes the left/right channels independently.
Default: muted (0x1)
Reserved.
Default: 0
Rev. 0 | Page 24 of 52
Preliminary Technical Data
AD1986
GENERAL-PURPOSE (REGISTER 0x20)
This register should be read before writing to generate a mask for only the bit(s) that need to be changed.
Reg
0x20
Name
GeneralPurpose
D15
x
D14
x
D13
x
D12
x
D11
DRSS1
D10
DRSS0
D9
MIX
D8
MS
D7
LPBK
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
x
Default
0x0000
Table 44.
Register
LPBK
(LoopBack
Control)
MS
(MIC
Select)
MIX
(Mono
Output
Select)
DRSS [1:0]
(Double
Rate Slot
Select)
x
Function
This bit enables the digital internal loop back from the ADC to the front DAC. This feature is normally used for
testing and troubleshooting. See LBKS bit in Register 0x74 for changing the loop back path to use the
SURROUND or CENTER/LFE DACs.
Default
Default:
disabled
(0x0)
Used in conjunction with the OMS [2:0] (0x74 D10:08]), 2CMIC (0x76 D06) and MMIX (0x7A D02). Selects which
MIC input goes into the ADC0 record selector’s MIC channel inputs. When set, this bit swaps the left and right
channels. Selects mono output audio source.
MIX
Mono Output Connection
0
MIX—Connected to the mono mixer output.
1
MIC—Connected to the left channel of the MIC selector and swap.
Default
The DRSS bits specify the slots for the n+1 sample outputs. PCM L (n+1) and PCM R (n+1) data are by default
provided in output Slots 10 and 11.
DRSS [1:0]
DRSS [1:0]
Function
00
PCM L, R (n+1) data is on Slots 10 and 11
01
PCM L, R (n+1) data is on Slots 7 and 8
1x
Reserved
Reserved.
Default
Default: 0
AUDIO INT AND PAGING (REGISTER 0x24)
This register controls the audio interrupt and register paging mechanisms.
Reg
0x24
Name
Audio Int and
Paging
D15
I4
D14
I3
D13
I2
D12
I1
D11
I0
D10
x
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
PG3
D2
PG2
D1
PG1
D0
PG0
Default
0xxx00
Table 45.
Register
PG [3:0]
(Page Selector
(Read/Write))
I0
(Interrupt Enable
(Read/Write))
Function
This register is used to select a descriptor of 16 word pages between Registers 0x60 to 0x6F. A value of 0x0 is used to
select vendor specific space to maintain compatibility with AC ’97 Revision 2.2 vendor specific registers. System
software can determine implemented pages by writing the page number and reading the value back. If the value read
back does not match the value written, the page is not implemented. All implemented pages must be in consecutive
order (i.e. Page 0x2 cannot be implemented without Page 0x1).
PG [3:0]
Addressing Page Selection
Default
000 (Page 0)
Page 0 (vendor) registers
Default
001 (Page 1)
Page ID 01, registers defined in AC ’97, Revision 2.3
Page 0xh–0xF
Reserved
Software should not unmask the interrupt unless ensured by the AC ’97 controller that no conflict is possible with
modem Slot 12—GPI functionality. AC ’97 Revision 2.2 compliant controllers will not likely support audio CODEC
interrupt infrastructure. In that case, software can poll the interrupt status after initiating a sense cycle and waiting for
sense cycle max delay (defined by software) to determine if an interrupting event has occurred.
I0
Interrupt Mask Status
0
Interrupt generation is masked
Default
1
Interrupt generation is unmasked
Rev. 0 | Page 25 of 52
AD1986
Register
I1
(Sense Cycle
(Read/Write))
I [3:2]
(Interrupt Cause
(RO))
I4
(Interrupt Status
(Read/Write))
x
Preliminary Technical Data
Function
Writing a 1 to this bit causes a sense cycle start if supported. If a sense cycle is in progress, writing a 0 to this bit will
abort the sense cycle. The data in the sense result register (0x6A, Page 01) may or may not be valid, as determined by
the IV bit.
I1
Read
Write
0
Sense cycle completed (or not initiated)
Default
Aborts sense cycle (if in
process)
1
Sense cycle still in process
Initiate sense cycle
These bits will indicate the cause(s) of an interrupt. This information should be used to service the correct interrupting
event(s). If the Interrupt Status (Bit I4) is set, one or both of these bits must be set to indicate the interrupt cause.
Hardware will reset these bits back to zero when the interrupt status bit is cleared.
I2
Interrupt Status
0
Sense status has not changed (did not cause interrupt). Default
1
Sense cycle completed or new sense information is available
I3
0
GPIO status change did not cause interrupt
1
GPIO status change caused interrupt
Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt
enable (I0) status. An interrupt in the GPI in Slot 12 in the AC link will follow this bit change when interrupt enable (I0)
is unmasked. If this bit is set, one or both of I3 or I2 must be set to indicate the interrupt cause.
I4
Read
Write
0
Interrupt clear
Default
No operation
1
Interrupt generated
Clears interrupt
Reserved.
Default: 0
POWER-DOWN CTRL/STAT (REGISTER 0x26)
The ready bits are read only; writing to REF, ANL, DAC, and ADC has no effect. These bits indicate the status for the AD1986
subsections. If the bit is 1 then that subsection is ready. ‘Ready’ is defined as the subsection able to perform in its nominal state.
Reg
0x26
Name
PowerDown
Ctrl/Stat
D15
EAPD
D14
PR6
D13
PR5
D12
PR4
D11
PR3
D10
PR2
D9
PR1
D8
PR0
D7
x
D6
x
D5
x
Table 46.
Register
ADC (RO)
(ADC Section
Status (RO))
ADC (RO)
((Front DAC
Status (RO))
ANL (RO)
(Analog
Amplifiers,
Attenuators and
Mixers Status
(RO))
ADC
0
1
ADC Status
ADC not ready
ADC sections ready to transmit data
DAC
0
1
ANL
0
1
Front DAC Status
ADC not ready
ADC sections ready to transmit data
Analog Status
Analog amplifiers, attenuators and mixers not ready
Analog amplifiers, attenuators and mixers ready
Rev. 0 | Page 26 of 52
D4
x
D3
REF
D2
ANL
D1
DAC
D0
ADC
Default
0x000x
Preliminary Technical Data
Register
REF (RO)
(Voltage
References, VREF
and VREF_OUT
status (read
only))
PR0
PR1
PR2
PR3
PR4
PR5
PR6
EAPD
x
AD1986
ADC
ADC Status
VREF_OUT pin output states controlled by the CVREF, MVREF, and LVREF controls in Register 0x70.
REF
VREF Status
0
Voltage References, VREF and VREF_OUT not ready.
1
Voltage References, VREF, and VREF_OUT up to nominal level.
All ADCs and input selectors’ power down: clearing this bit enables VREF regardless of the state of PR3.
Default: all ADCs and input muxs powered on (0x0).
All DACs power down. Also powers down the EQ circuitry. Clearing this bit enables VREF regardless of the state of PR3.
Default: all DACs and EQ powered on (0x0).
Analog mixer power down. (valid if PR7 = 0).
Default: analog mixer powered on (0x0).
All VREF and VREF_OUT pins power down. May be used in combination with PR2 or by itself. If all the ADCs and DACs are
not powered down, setting this bit will have no effect on the VREF and will only power down VREF_OUT.
Default: All VREFand VREF_OUT pins powered on (0x0).
AC-Link Interface power down. The reference and the mixer can be either up or down, but all power-up sequences
must be allowed to run to completion before PR5 and PR4 are both set. In multiple-CODEC systems, the master
CODEC’s PR4 bit controls the slave CODEC. In the slave CODEC the PR4 bit has no effect except to enable or disable PR5.
Default: AC-link Interface powered on (0x0).
Internal Clocks disabled.
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down (e.g. PR0, PR1, PR4). The reference and the
mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4
are both set. In multiple CODEC systems, the master CODEC’s PR5 controls the slave CODEC. PR5 is effective in the slave
CODEC if the master's PR5 bit is clear.
Default: internal clocks enabled (0x0).
Powers down the headphone amplifiers.
Default: HP amp powered on (0x0).
EAPD
EAPD Pin Status
0
Sets the EAPD pin low, enabling an external power amplifier.
Default
1
Sets the EAPD pin high, shutting the external power amplifier off.
Reserved.
Default: 0
EXT’D AUDIO ID (REGISTER 0x28)
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates one
or more of the extended audio features are supported.
Reg
0x28
Name
Ext’d Audio ID
D15
ID1
D14
ID0
D13
x
D12
X
D11
REV1
D10
REV0
D9
AMAP
D8
LDAC
D7
SDAC
D6
CDAC
D5
DSA1
D4
DSA0
D3
x
D2
SPDF
D1
DRA
D0
VRA
Table 47.
Register
VRA (RO)
SPDIF (RO)
DRA (RO)
DSA [1:0]
Description
Variable rate PCM audio: read only
SPDIF support: read only
Double rate audio: read only
DAC slot assignment (read/write)
Front DAC
DSA [1:0]
Left
Right
00
3
4
01
7
8
10
6
9
11
10
11
Setting
=1
=1
=1
Function
Variable rate PCM audio supported
SPDIF transmitter supported (IEC958)
Double rate audio supported for DAC0 L/R
Surround DAC
Left
Right
7
8
6
9
10
11
3
4
Rev. 0 | Page 27 of 52
C/LFE DAC
Left
Right
6
9
10
11
3
4
7
8
Default
Default
Default
0x0BC7
AD1986
Register
CDAC (RO)
SDAC (RO)
LDAC (RO)
AMAP (RO)
REV [1:0] (RO)
ID [1:0] (RO)
x
Preliminary Technical Data
Description
PCM CENTER DAC: read only
PCM Surround DAC: read only
PCM LFE DAC: read only
Slot DAC mappings: read only
AC97 version: read only
CODEC configuration: read only
Reserved
Setting
=1
=1
=1
=1
= 10
= 00
Function
PCM center DAC supported
CM Surround DACs supported
PCM LFE DAC supported
CODEC ID based slot/DAC mappings
CODEC is AC ’97, Revision 2.3 compliant
Primary AC ‘97
Default: 0
EXT’D AUDIO STAT/CTRL (REGISTER 0x2A)
The extended audio status and control register is a read/write register that provides status and control of the extended audio features.
Reg
0x2A
Name
Ext’d Audio Stat/Ctrl
D15
x
D14
x
D13
PRK
D12
PRJ
D11
PRI
D10
SPCV
D9
x
D8
LDAC
D7
SDAC
D6
CDAC
D5
SPSA1
D4
SPSA0
D3
x
D2
SPDIF
D1
DRA
D0
VRA
Default
0x0xx0
Table 48.
Register
VRA
(Variable Rate
Audio)
DRA
(Double Rate
Audio)
SPDIF
SPSA [1:0]
(SPDIF Slot
Assignment
Bits:
(Read/Write))
CDAC (RO)
(CENTER DAC
Status (RO))
Function
Enables variable rate audio mode. Enables sample rate registers and SLOTREQ signaling.
VRA
VRA State
Default
0
Disabled, sample rate 48 kHz for all ADCs and DACs
Default
1
Enabled, ADCs and DACs can be set to variable sample rates
DRA = 1. Enables double-rate audio mode in which data from PCM L and PCM R in Output Slots 3 and 4 is used in
conjunction with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate designated by the
PCM front sample rate control register. When using the double rate audio, only the front DACs are supported and all other
DACs (surround, center, and LFE) are automatically powered down. The slot that contains the additional data is
determined by the DRSS[1:0] bits (0x20 D [11:10]). Note that DRA can be used without VRA; in which case the converter
rates are forced to 96 kHz if DRA = 1.
DRA
DRA State
Default
0
Disabled, DACs sample at the programmed rate
Default
1
Enabled, DACs sample at twice (2×) the programmed rate
SPDIF transmitter subsystem enable/disable bit (read/write)
This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set
high, if the SPDIF pin (48) is pulled down at power-up enabling the CODEC transmitter logic. If the SPDIF pin is floating or
pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a low, indicating that the SPDIF
transmitter is not available. This bit must always be read back, to verify that the SPDIF transmitter is actually enabled.
SPDIF
Function
0
Disables the S/PDIF transmitter
Default
1
Enables the S/PDIF transmitter
AC '97 Revision 2.2 AMAP compliant default SPDIF slot assignments.
SPSA [1:0]
S/PDIF Slot Assignment
00
3 and 4
Default
01
7 and 8
10
6 and 9
11
10 and 11
CDAC
CENTER DAC Status
0
CENTER DAC not ready
1
CENTER DAC section ready to receive data
0
Surround DAC not ready
1
Surround DAC section ready to receive data
Rev. 0 | Page 28 of 52
Preliminary Technical Data
Register
LDAC (RO)
(LFE DAC
Status (RO))
SPCV (RO)
(SPDIF
Configuration
Valid (RO))
PRI
(Center DAC
Power-Down)
PRJ
(Surround
DACs PowerDown)
PRK
(LFE DAC
Power-Down)
x
AD1986
Function
LDAC
LFE DAC Status
0
LFE DAC not ready
1
LFE DAC section ready to receive data
Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed
SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status.
SPCV
S/PDIF Configuration Status
0
Invalid SPDIF configuration {SPSA, SPSR, DAC slot rate, DRS}
1
Valid SPDIF configuration
Actual status reflected in the CDAC (0x3A D06) bit.
PRI
CENTER DAC Power Status
0
Power-on CENTER DAC
Default
1
Power-down CENTER DAC
Actual status reflected in the SDAC bit.
PRJ
Surround DACs Power Control
0
Power-on surround DACs
Default
1
Power-down surround DACs
Actual status reflected in the LDAC bit.
PRK
LFE DACs Power Control
0
Power-on LFE DAC
Default
1
Power-down LFE DAC
Reserved.
Default: 0
FRONT DAC PCM RATE (REGISTER 0x2C)
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit
(0x2A D00) is 0 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.
To use 96 kHz in AC ’97 mode set the double rate audio (DRA) bit (0x2A D01). When using DRA in AC ’97, only the front DACs are
supported and all other DACs (surround, center, and LFE) are automatically powered down.
Reg
0x2C
Name
Front DAC PCM
Rate
D15
R15
D14
R14
D13
R13
D12
R12
D11
R11
D10
R10
D9
R9
D8
R8
D7
R7
D6
R6
D5
R5
D4
R4
D3
R3
D2
R2
D1
R1
D0
R0
Default
0xBB80
Table 49.
Register
R [15:0]
(Sample
Rate)
Function
The sampling frequency range is from 7 kHz (0x01B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to VRA, then the
sample rates are reset to 48k.
Rev. 0 | Page 29 of 52
AD1986
Preliminary Technical Data
SURROUND DAC PCM RATE (REGISTER 0x2E)
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit
(0x2A D00) is 0, this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.
If the DRA bit (0x2A D01) is set, the surround DAC is inoperative and automatically powered down.
Reg
0x2E
Name
SURR_1 DAC PCM
Rate
D15
R15
D14
R14
D13
R13
D12
R12
D11
R11
D10
R10
D9
R9
D8
R8
D7
R7
D6
R6
D5
R5
D4
R4
D3
R3
D2
R2
D1
R1
D0
R0
Default
0xBB80
Table 50.
Register
R [15:0]
(Sample
Rate)
Function
The sampling frequency range is from 7 kHz (0x01B58) to 48 kHz (0xBB80) in 1 Hz increments. If zero is written to VRA then the
sample rates are reset to 48k.
C/LFE DAC PCM RATE (REGISTER 0x30)
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit
(0x2A D00) is 0 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.
If the DRA bit (0x2A D01) is set, the C/LFE DAC is inoperative and automatically powered down.
Reg
0x30
Name
C/LFE DAC
PCM Rate
D15
R15
D14
R14
D13
R13
D12
R12
D11
R11
D10
R10
D9
R9
D8
R8
D7
R7
D6
R6
D5
R5
D4
R4
D3
R3
D2
R2
D1
R1
D0
R0
Default
0xBB80
Table 51.
Register
R [15:0]
(Sample
Rate)
Function
The sampling frequency range is from 7 kHz (0x01B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to VRA then the
sample rates are reset to 48k.
ADC PCM RATE (REGISTER 0x32)
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit (0x2A
D00) is 0 (zero) this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.
Reg
0x32
Name
ADC 0 PCM
Rate
D15
R15
D14
R14
D13
R13
D12
R12
D11
R11
D10
R10
D9
R9
D8
R8
D7
R7
D6
R6
D5
R5
D4
R4
D3
R3
D2
R2
D1
R1
D0
R0
Default
0xBB80
Table 52.
Register
R [15:0]
(Sample
Rate)
Function
The sampling frequency range is from 7 kHz (0x01B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to VRA then the
sample rates are reset to 48k.
Rev. 0 | Page 30 of 52
Preliminary Technical Data
AD1986
C/LFE DAC VOLUME (REGISTER 0x36)
This register controls the CENTER/LFE DAC gain and mute to the output selector section. The volume register contains five bits,
generating 32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB.
Note that the left/right association of the CENTER and LFE channels can be swapped at the CODEC outputs by setting the CSWP bit in
Register 74h. These controls remain unchanged regardless of the state of CSWP.
Reg
0x36
Name
C/LFE
DAC
Volume
D15
LFEM
D14
x
D13
x
D12
LFE4
D11
LFE3
D10
LFE2
D9
LFE1
D8
LFE0
D7
CNTM
D6
x
D5
x
D4
CNT4
D3
CNT3
D2
CNT2
D1
CNT1
D0
CNT0
Default
0x8888
Table 53.
Register
CNT [4:0]
(Center Volume)
CNTM
(Center Mute)
LFE [4:0]
(LFE Volume)
LFEM
(LFE Mute)
x
Function
Controls the gain of the CENTER channel to the output selector section from +12.0 dB to −34.5 dB. The least significant
bit represents −1.5 dB.
CNTM
CNT [4:0]
Function
Default
0
0 0000
+12 dB gain
0
0 1000
0 dB attenuation
Default
0
1 1111
−34.5 dB attenuation
1
x xxxx
Muted
Mutes the center channel.
Default: muted (0x1)
Controls the gain of the LFE channel to the output selector section from +12.0 dB to −34.5 dB. The least significant bit
represents −1.5 dB.
LFEM
LFE[4:0]
Function
0
0 0000
+12 dB gain
0
0 1000
0 dB attenuation
Default
0
1 1111
−34.5 dB attenuation
1
x xxxx
Muted
Mutes the LFE channel.
Default: muted (0x1)
Reserved.
Default: 0
SURROUND DAC VOLUME (REGISTER 0x38)
This register controls the SURROUND DAC gain and mute to the output selector section. The volume register contains five bits,
generating 32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB.
Reg
0x18
Name
Surround
DAC
Volume
D15
LM
D14
x
D13
x
D12
LV4
D11
LV3
D10
LV2
D9
LV1
D8
LV0
D7
RM
D6
x
D5
x
D4
RV4
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x8888
Table 54.
Register
L/RV [4:0]
(Left/Right
Volume)
L/RM
(Left/Right
Mute)
x
Function
Controls the left/right channel gains of this input to the output selector section from +12 dB to -34.5 dB. The least
significant bit represents −1.5 dB.
L/RM
L/RV [4:0]
Function
Default
0
0 0000
+12 dB gain
0
0 1000
0 dB
Default
0
1 1111
−34.5 dB attenuation
1
x xxxx
Muted
Mutes the left/right channels independently.
Default: muted (0x1)
Reserved.
Default: 0
Rev. 0 | Page 31 of 52
AD1986
Preliminary Technical Data
SPDIF CONTROL (REGISTER 0x3A)
Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe
in the V-case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in
Register 0x2A is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission.
Reg
0x3A
Name
SPDIF
Control
D15
V
D14
VCFG
D13
SPSR
D12
x
D11
L
D10
CC6
D9
CC5
D8
CC4
D7
CC3
D6
CC2
D5
CC1
D4
CC0
D3
PRE
D2
COPY
D1
/AUDIO
D0
PRO
Default
20000x
Table 55.
Register
PRO
(Professional)
/AUDIO
(Nonaudio)
COPY
(Copyright)
PRE
(Pre-emphasis)
CC [6:0]
(Category Code)
L
(Generation Level)
SPSR
(SPDIF Transmit
Sample Rate)
VCFG
(Validity Force Bit)
V
(Validity)
x
Function
Indicates professional use of the audio stream.
PRO
State
0
Consumer use of channel
1
Professional use of channel
Indicates that the data is PCM or another format (such as AC3).
/AUDIO
State
0
Data in PCM format
1
Data in non-PCM format
Allows receivers to make copies of the digital data.
COPY
State
0
Copyright asserted
1
Copyright not asserted
Disables filter pre-emphasis.
PRE
State
0
Filter pre-emphasis is 50/15 µsec
1
No pre-emphasis
Programmed according to IEC standards, or as appropriate.
Default
Default
Default
Default
Default
Programmed according to IEC standards, or as appropriate.
Chooses between 48.0 kHz and 44.1 kHz S/PDIF transmitter rate.
SPSR
Transmit Sample Rate
0
44.1 kHz
1
48.0 kHz
Default
When asserted, this bit forces the SPDIF stream validity flag (bit < 28 > within each SPDIF L/R subframe) to be controlled by
the validity bit (D15) in Register 0x3A (SPDIF control register).
Reset Default: 0
VCFG
V
Validity Bit State
0
0
Managed by CODEC error detection logic
Default
0
1
Forced high, indicating subframe data is
invalid
1
0
Forced low, indicating subframe data is valid
1
1
Forced high, indicating subframe data is
invalid
This bit affects the validity flag, (bit <28 > transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to
maintain connection during error or mute conditions. Note that the VCFG bit (0x3A D14) will force the validity flag high (valid)
or low (invalid). See the VCFG bit description.
V
State
0
Each SPDIF subframe (L+R) has bit <28> set to 1
Default
This tags both samples as invalid
1
Each SPDIF subframe (L+R) has bit <28> set to 0 for valid data and 1 for invalid data (error condition)
Reserved.
Default: 0
Rev. 0 | Page 32 of 52
Preliminary Technical Data
AD1986
EQ CONTROL REGISTER (REGISTER 0x60)
Register 0x60 is a read/write register that controls equalizer function and data setup. The register also contains the Biquad and coefficient
address pointer, which is used in conjunction with the EQ data register (0x78) to setup the equalizer coefficients. The reset default
disables the equalizer function until the coefficients can be properly set up by the software and sets the symmetry bit to allow equal
coefficients for left and right channels.
Reg
0x60
Name
EQ
Control
D15
EQM
D14
x
D13
x
D12
x
D11
x
D10
x
D9
x
D8
x
D7
SYM
D6
CHS
D5
BCA5
D4
BCA4
D3
BCA3
D2
BCA2
D1
BCA1
D0
BCA0
Table 56. Biquad and Coefficient Address Pointer
BCA [5,0]
Biquad 0
Biquad 0
Biquad 0
Biquad 0
Biquad 0
Coef a0
Coef a1
Coef a2
Coef b1
Coef b2
BCA [5,0] = 011011
BCA [5,0] = 011010
BCA [5,0] = 011001
BCA [5,0] = 011101
BCA [5,0] = 011100
Biquad 1
Biquad 1
Biquad 1
Biquad 1
Biquad 1
Coef a0
Coef a1
Coef a2
Coef b1
Coef b2
BCA [5,0] = 100000
BCA [5,0] = 011111
BCA [5,0] = 011110
BCA [5,0] = 100010
BCA [5,0] = 100001
Biquad 2
Biquad 2
Biquad 2
Biquad 2
Biquad 2
Coef a0
Coef a1
Coef a2
Coef b1
Coef b2
BCA [5,0] = 100101
BCA [5,0] = 100100
BCA [5,0] = 100011
BCA [5,0] = 100111
BCA [5,0] = 100110
Biquad 3
Biquad 3
Coef a0
Coef a1
BCA [5,0] = 101010
BCA [5,0] = 101001
Biquad 3
Biquad 3
Biquad 3
Biquad 4
Biquad 4
Biquad 4
Biquad 4
Biquad 4
Coef a2
Coef b1
Coef b2
Coef a0
Coef a1
Coef a2
Coef b1
Coef b2
BCA [5,0] = 101000
BCA [5,0] = 101100
BCA [5,0] = 101011
BCA [5,0] = 101111
BCA [5,0] = 101110
BCA [5,0] = 101101
BCA [5,0] = 110001
BCA [5,0] = 110000
Biquad 5
Biquad 5
Biquad 5
Biquad 5
Biquad 5
Coef a0
Coef a1
Coef a2
Coef b1
Coef b2
BCA [5,0] = 110100
BCA [5,0] = 110011
BCA [5,0] = 110010
BCA [5,0] = 110110
BCA [5,0] = 110101
Biquad 6
Biquad 6
Biquad 6
Biquad 6
Biquad 6
Coef a0
Coef a1
Coef a2
Coef b1
Coef b2
BCA [5,0] = 111001
BCA [5,0] = 111000
BCA [5,0] = 110111
BCA [5,0] = 111011
BCA [5,0] = 111010
Table 57.
Register
CHS
(Channel
Select)
SYM
(Symmetry)
EQM
(Equalizer
Mute)
x
Function
Swaps the blocks that are used for symmetry coefficients. Only valid when the SYM bit is set.
CHS
Function
Default
0
Selects left channel coefficients data block
Default
1
Selects right channel coefficients data block
When set to 1 this bit indicates that the left and right channel coefficients are equal.
This shortens the coefficients setup sequence since only the left channel coefficients need to be addressed and setup. The
right channel coefficients are simultaneously copied into memory.
SYM
Function
0
Left and right channels can use different coefficients
1
Indicates that the left and right channel coefficients are equal
Default
When set to 1, this bit disables the equalizer function (allows all data pass-through). The reset default sets this bit to 1
disabling the equalizer function until the biquad coefficients can be properly set.
EQM
Function
0
EQ is enabled.
1
EQ is disabled. Data will pass-thru without change.
Default
Reserved.
Default: 0
Rev. 0 | Page 33 of 52
Default
0x8080
AD1986
Preliminary Technical Data
EQ DATA REGISTER (REGISTER 0x62)
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from the
address pointed by the BCA bits in the EQ CNTRL register (0x60). Data will only be written to memory, if the EQM bit (Register 0x60
bit 15) is asserted.
Reg
0x62
Name
EQ
Data
D15
CFD15
D14
CFD14
D13
CFD13
D12
CFD12
D11
CFD11
D10
CFD10
D9
CFD9
D8
CFD8
D7
CFD7
D6
CFD6
D5
CFD5
D4
CFD4
D3
CFD3
D2
CFD2
D1
CFD1
D0
CFD0
Default
0xxxxx
Table 58.
Register
CFD [15:0]
(Coefficient
Data)
Function
The biquad coefficients are fixed point format values with 16 bits of resolution. The CFD15 bit is the MSB and the CFD0 bit is
the LSB.
MISC CONTROL BITS 2 (REGISTER 0x70)
Reg
0x70
Name
Misc Control
Bits 2
D15
x
D14
x
D13
x
D12
MVREF
2
D11
MVREF
1
D10
MVREF
0
D9
x
D8
x
D7
MMDIS
D6
x
D5
JSMAP
D4
CVREF
2
D3
CVREF
1
D2
CVREF
0
D1
x
D0
x
Default
0x0000
Table 59.
Register
CVREF [2:0]
(C/LFE VREF_OUT
Control)
JSMAP
(Jack Sense Mapping)
MMDIS
(Mono Mute Disable)
MVREF [2:0]
(MIC VREF_OUT)
x
Function
Sets the voltage/state of the C/LFE VREF_OUT signal. VREF_OUT is used to power microphone style devices
plugged into the connected jack circuitry. The VREF_OUT pin must be connected to both the left and right
channels through external resistors to function properly. Selections other than those defined are invalid and
should not be programmed.
C/LFE VREF_OUT Setting
5.0 AVDD
3.3 V AVDD
Default
CVREF [2:0]
000
Hi-Z
Hi-Z
Default
001
2.25 V
2.25 V
010
0V
0V
100
3.70 V
2.25 V
The AD1986 supports two different methods of mapping the JACK_SENSE_A/B resistor tree to bits JS [7:0]. Use
these bits to change from the default mapping to the alternate method.
JSMAP
Function
0
Default Jack Sense mapping
Default
1
Alternate Jack Sense mapping
Disables the automatic muting of the MONO_OUT pin by jack sense events (see advanced jack sense bits JS [3:0]
(0x76 D [05:04], 0x72 D [05:04]).
MMDIS
Function
0
Automute can occur
Default
1
Automute disabled
Sets the voltage/state of the microphone VREF_OUT signal. VREF_OUT is used to power microphone style devices
plugged into the connected jack circuitry. The VREF_OUT pin must be connected to both the left and right
channels through external resistors to function properly. Selections other than those defined are invalid and
should not be programmed.
MIC_1/2 VREF_OUT Setting
MVREF [2:0]
5.0 AVDD
3.3 V AVDD
000
Hi-Z
Hi-Z
Default
001
2.25 V
2.25 V
010
0V
0V
100
3.70 V
2.25 V
Reserved.
Default: 0
Rev. 0 | Page 34 of 52
Preliminary Technical Data
AD1986
JACK SENSE (REGISTER 0x72)
All register bits are read/write except for JS0ST and JS1ST, which are read only. Important: Please refer to Table 72 to understand how
JACK_SENSE_A and JACK_SENSE_B codec pins translate to JS1and JS0.
Reg
0x72
Name
Jack
Sense
D15
JS1
SPRD
D14
JS1
DMX
D13
JS0
DMX
D12
JSMT
2
D11
JSMT
1
D10
JSMT
0
D9
JS1
EQB
D8
JS0
EQB
D7
x
D6
x
D5
JS1
MD
D4
JS0
MD
D3
JS1
ST
D2
JS0
ST
D1
JS1
INT
D0
JS0
INT
Default
0x0000
Table 60.
Register
JS0INT
(JS0
Interrupt
Status)
JS1INT
(JS1
Interrupt
Status)
JS0ST (RO)
(JS0 State
(RO))
JS1ST (RO)
(JS1 State
(read only))
JS0MD
(JS0 MODE)
JS1MD
(JS1 MODE)
JS0EQB
(JS0 EQ
Bypass
Enable)
JS1EQB
(JS1 EQ
Bypass
Enable)
Function
Indicates JS0 has generated an interrupt. Remains set until the software services JS0 interrupt; i.e., JS0 ISR should clear this
bit by writing a 0 to it.
1. Interrupts are generated by valid state changes of JS pins.
2. Interrupt to the system is actually an OR combination of this bit and JS3 JS0 INT.
3. The interrupt implementation path is selected by the INTS bit (Register 0x74).
4. It is also possible to generate a software system interrupt by writing a 1 to this bit.
JS0INT
Read
Write
0
JS0 did not generate interrupt
No operation
1
JS0 generated interrupt
Clears JS0INT bit
Indicates JS1 has generated an interrupt. Remains set until the software services JS1 interrupt; i.e., JS1 ISR should clear this
bit by writing a 0 to it. See JS0INT description above for additional details.
JS1INT
Read
Write
0
JS1 did not generate interrupt
No operation
1
JS1 generated interrupt
Clears JS1INT
This bit always reports the logic state of JS0.
On MIC jack sensing: depending on the applications circuit, the logic state for jack sense pins can be the opposite of that on
other jacks. Software needs to be aware of this is interpreting the JS event as a plug in our out event.
JS0ST
Function
Default
0
JS0 is low (0)
1
JS0 is high (1)
This bit always reports the logic state of JS1. MIC jack sensing: depending on the applications circuit, the logic state for JS
pins can be the opposite to the other jacks.
JS1ST
Function
0
JS1 is low (0)
1
JS is high (1)
This bit selects the operation mode for JS0.
JS0MD
Function
0
Jack sense mode—JS0INT must be polled by software
Default
1
Interrupt mode—CODEC will generate an interrupt on JS0 event
This bit selects the operation mode for JS1.
JS1MD
Function
0
Jack sense mode—JS1INT must be polled by software
Default
1
Interrupt mode—CODEC will generate an interrupt on JS1 event
This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 will cause the EQ to be bypassed.
JS0EQB
Function
0
JS0 does not affect EQ
Default
1
JS0 = 1 will cause the EQ to be bypassed
This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1=1 will cause the EQ to be bypassed.
JS1EQB
Function
0
JS1 does not affect EQ
Default
1
JS1 = 1 will cause the EQ to be bypassed
Rev. 0 | Page 35 of 52
AD1986
Register
JSMT [2,0]
(JS Mute
Enable
selector)
JS0DMX
(JS0 DownMix Control
Enable)
JS1DMX
(JS1 DownMix Control
Enable)
JSSPRD
(JS Spread
control
enable)
x
Preliminary Technical Data
Function
These 3 bits select and enable the jack sense muting action. See Table 61.
This bit enables JS0 to control the down-mix function. This function allows a digital mix of 6-channel audio into 2-channel
audio. The mix can then be routed to the stereo LINE_OUT or HP_OUT jacks. When this bit is set to 1, JS0 = 1 will activate the
down-mix conversion. See DMIX description in Register 0x76. The DMIX bits select the down-mix implementation type and
can also force the function to be activated.
JS0DMX
Function
0
JS0 does not affect down mix
Default
1
JS0 = 1 activates the 6- to 2-channel down mix
This bit enables JS1 to control the down-mix function (see the JS0DMx description above). When this bit is set to 1, JS1 = 1
will activate the down-mix conversion.
JS1DMX
Function
0
JS1 does not affect down-mix
Default
1
JS1 = 1 activates the 6- to 2-channel down-mix
This bit enables the 2-channel to 6-channel audio spread function when JSs are active (Logic State 1). Note that the SPRD bit
can also force the Spread function without being gated by the jack senses. Please see this bit’s description in Register 0x76
for a better understanding of the Spread function.
JSSPRD
Function
0
JS1 does not affect spread
Default
1
J10 = 1 activates spread
Reserved.
Default: 0
Table 61. Jack Sense Mute Selections (JSMT)
REF
0
1
2
3
4
5
JS1
OUT (0)
OUT (0)
IN (1)
IN (1)
OUT (0)
OUT (0)
JS0
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
JSMT2
0
0
0
0
0
0
JSMT1
0
0
0
0
0
0
JSMT0
0
0
0
0
1
1
HP
OUT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LINE
OUT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
C/LFE
OUT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
SURR
OUT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
MONO
OUT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
6
7
8
IN (1)
IN (1)
OUT (0)
OUT (0)
IN (1)
OUT (0)
0
0
0
0
0
1
1
1
0
ACTIVE
ACTIVE
FMUTE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
ACTIVE
ACTIVE
FMUTE
FMUTE
FMUTE
ACTIVE
9
OUT (0)
IN (1)
0
1
0
FMUTE
ACTIVE
FMUTE
FMUTE
ACTIVE
10
11
IN (1)
IN (1)
OUT (0)
IN (1)
0
0
1
1
0
0
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
12
13
14
15
16
OUT (0)
OUT (0)
IN (1)
IN (1)
OUT (0)
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
**
**
**
**
ACTIVE
**
**
**
**
FMUTE
**
**
**
**
FMUTE
**
**
**
**
FMUTE
**
**
**
**
ACTIVE
17
OUT (0)
IN (1)
1
0
0
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
18
IN (1)
OUT (0)
1
0
0
ACTIVE
FMUTE
FMUTE
FMUTE
FMUTE
19
IN (1)
IN (1)
1
0
0
ACTIVE
FMUTE
FMUTE
FMUTE
FMUTE
Rev. 0 | Page 36 of 52
NOTES
JS0 and JS1 ignored
JS0 no mute action
JS1 mutes mono and enables
LINE_OUT + SURR_OUT +
C/LFE
STANDARD 6 CHAN CONFIG
JS0 no mute action, SWAPPED
HP_OUT and LINE_OUT
JS1 mutes mono and enables
HP_OUT + SURR_OUT + C/LFE
STANDARD 6 CHAN CONFIG
no swap
**RESERVED
JS0 = 0 and JS1 = 0
enables MONO
JS1 = 1 enabled
FRONT only
JS0 = 1 and JS1 = 0
enables all rear
6 CHAN CONFIG with front
jack wrap back
Preliminary Technical Data
AD1986
REF
20
21
JS1
OUT (0)
OUT (0)
JS0
OUT (0)
IN (1)
JSMT2
1
1
JSMT1
0
0
JSMT0
1
1
HP
OUT
FMUTE
FMUTE
LINE
OUT
FMUTE
FMUTE
C/LFE
OUT
FMUTE
FMUTE
SURR
OUT
FMUTE
FMUTE
MONO
OUT
ACTIVE
ACTIVE
22
23
IN (1)
IN (1)
OUT (0)
IN (1)
1
1
0
0
1
1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
24
25
26
27
28
29
30
31
OUT (0)
OUT (0)
IN (1)
IN (1)
OUT (0)
OUT (0)
IN (1)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
NOTES
JS0 no mute action
JS1 mutes mono and enables
all rear.
STANDARD 6 CHAN CONFIG
swapped HP_OUT and
LINE_OUT
**RESERVED
**RESERVED
FMUTE = Output is forced to mute independent of the respective volume register setting.
ACTIVE = Output is not muted and its status is dependent on the respective volume register setting.
OUT = Nothing is plugged into the jack and therefore the JS status is 0 (via the load resistor pull-down action).
IN = Jack has plug inserted and therefore the JS status is 1 (via the CODEC JS pin internal pull-up).
SERIAL CONFIGURATION (REGISTER 0x74)
When Register 0x00 is written (soft reset) the SLOT 16, REGM [2:0], SPOVR, SPAL, SPDZ, and SPLNK bits do not reset. All bits are reset
on a hardware reset or power-on reset.
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x74
Serial
Configuration
SLOT
16
REGM2
REGM1
REGM0
REGM3
OMS2
OMS1
OM0
SPOVR
LBKS1
LBKS0
INTS
CSWP
SPAL
SPDZ
SP
LNK
0x1001
Table 62.
Register
SPLNK
(S/PDIF
LINK)
SPDZ
(S/PDIF
DACZ)
SPAL
(S/PDIF
ADC Loop
Around)
(CSWP
CENTER/LFE
Swap)
INTS
(Interrupt
Mode
Select)
Function
Default
This bit enables the S/PDIF to link with the front DACs for data requesting. When linked the S/PDIF and front DACs should be
set to the same data rate as they both generate data requests at the front DAC’s request rate.
SPLNK
Function
0
S/PDIF and front DACs are not linked
1
S/PDIF and front DACs are linked
Default
Sets data fill mode for S/PDIF transmitter FIFO under-runs. When this bit is set to ON (1) the S/PDIF and ADC rates should be
set to the same rate.
SPDZ
On Under-Runs
0
Repeat last sample out the S/PDIF stream
Default
1
Forces midscale sample out the S/PDIF stream
SPAL
S/PDIF Transmitter Source
0
Connected to the AC-LINK stream
Default
1
Connected to the digital ADC stream
Swaps the CENTER/LFE channels. Some systems have a swapped external connection for the CENTER and LFE channels.
Setting this bit will swap these channels internal to the CODEC. Note that the CENTER and LFE controls do not change and
remain at the same addresses and bit assignments.
CSWP
CENTER Pin
LFE Pin
0
CENTER channel
LFE channel
Default
1
LFE channel
CENTER channel
This bit selects the audio interrupt implementation path. Note that this bit does not generate an interrupt, rather it steers the
path of the generated interrupt.
INTS
Interrupt Mode
0
Bit 0 SLOT 12 (modem interrupt)
Default
Rev. 0 | Page 37 of 52
AD1986
Register
LBKS [1:0]
Loop-Back
Selection
SPOVR
(S/PDIF
Enable
Override)
OMS [2:0]
Optional
Microphone
Selector
REGM [3:0]
SLOT 16
x
Preliminary Technical Data
Function
Default
1
Slot 6 valid bit (MIC ADC interrupt)
These bits select the internal digital loop-back path when LPBK bit is active (see Register 0x20).
LBKS [1:0]
Interrupt Mode
00
Loop back through the front DACs
Default
01
Loop back through the SURROUND DACs
10
Loop back through the center and LFE DACs (center
DAC loops back from the ADC left channel, the LFE
DAC from the ADC right channel)
11
Reserved
Use this bit to enable S/PDIF operation even if the external S/PDIF detection resistor is not installed.
SPOVR
S/PDIF Detection
0
Default
External resistor determines the presence of
S/PDIF
1
Enable S/PDIF operation
Selects the source of the microphone gain noost amplifiers. These bits work in conjuction with the 2CMIC (0x76 D06),
MS (0x20 D08), and MMIX (0x7A D08) bits.
OMS [2:0]
Left Channel
000
MIC pins
Default
001
LINE_IN pins
01x
C/LFE pins
100
Mix of MIC and C/LFE pins
101
Mix of MIC and LINE_IN pins
110
Mix of LINE_IN and C/LFE pins
111
Mix of MIC, LINE_IN and C/LFE pins
Bit mask indicating which CODEC is being accessed in a chained CODEC configuration.
REGM0—Master CODEC register mask
Default
REGM1—Slave 1 CODEC register mask
REGM2—Slave 2 CODEC register mask
REGM3—Slave 3 CODEC register mask
Enable 16-bit slot mode: SLOT16 makes all AC link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for
DSP serial port interfacing.
SLOT 16
Function
0
Standard AC ’97 operation
Default
1
All ac link S slots are 16 bits
Reserved
Default: 0
Rev. 0 | Page 38 of 52
Preliminary Technical Data
AD1986
MISC CONTROL BITS 1 (REGISTER 0x76)
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
76h
Misc Control Bits 1
DACZ
AC97NC
MSPLT
SODIS
CLDIS
x
DMIX1
DMIX0
SPRD
2CMIC
SOSEL
SRU
LISEL1
LISEL0
MBG1
MBG0
6010
Table 63.
Register
MBG [1:0]
(MIC Boost Gain Select
Register)
LISEL [1:0]
(LINE_IN Selector)
SRU
(Sample Rate Unlock)
SOSEL
(Surround Amplifier
Input Selection)
2CMIC
(2-Channel MIC Select)
SPRD
(Spread Enable)
CLDIS
(C/LFE Output Enable)
Function
These two bits allow changing both MIC preamp gain blocks from the nominal 20 dB gain boost. Both MIC_1/2
and MIC_2 preamps will be set to the same selected gain. This gain setting only takes affect while bit D6 (M20)
on the MIC volume register (0x0E) is set to 1, otherwise the MIC boost blocks have a gain of 0 dB.
MGB [1:0]
Microphone Boost Gain
Default
00
20 dB
Default
01
10 dB
10
30 dB
11
Reserved
Selects the source of the internal LINE_IN signals.
LISEL [1:0]
LINE_IN Selection
00
LINE_IN pins
Default
01
SURROUND pins—Places SURROUND outputs in Hi-Z state
1x
MIC_1/2 pins
Controls all DAC sample rate locking.
SRU
Surround State
0
All DAC sample rates are locked to the front sample rate
1
Front, surround and LFE sample rates can be set independently
Default
Selects either the surround DAC or analog mixer as the source driving the SURROUND output pin amplifier.
SOSEL
Surround Source
0
Surround DACs
Default
1
Analog Mixer
Used in conjunction with the OMS [2:0] (0x74 D10:08]), MS (0x20 D08), and MMIX (0x7A D02) bits to set the
microphone selection. This bit enables simultaneous recording from MIC_1 and MIC_2 inputs, using a stereo
microphone array. If the MMIX (0x7A D02) bit is set this bit is ignored.
2CMIC
2 Channel MIC State
0
Both outputs are driven by the left channel of the selector
Default
1
Stereo operation, the left and right channels are driven
separately
This bit enables spreading of 2-channel media to all 6-output channels. This function is implemented in the
analog section by using the output selector controls lines for the center/LFE, surround and LINE_OUT output
channels. The jack sense pins can also be setup to control (gate) this function depending on the JSSPRD bit (see
Register 0x72). The SPRD bit operates independently and does not affect the LOSEL and HPSEL operation.
SPRD
Spread State
0
No spreading occurs unless activated by jack sense
Default
1
The SPDR selector drives the center and LFE outputs from the
MONO_OUT
Controls the Hi-Z state of the SURROUND_L/R output pins. Pins are placed into a Hi-Z mode by software control
or when they are selected as inputs to the MIC_1/2 selector (see the OMS [2:0] bits 740x D [10:08]).
CLDIS
C/LFE Output State
0
Outputs enabled
Default
1
Outputs tristated
Rev. 0 | Page 39 of 52
AD1986
Preliminary Technical Data
Register
DMIX [1:0]
(DOWN MIX Mode
Select)
SODIS
(Surround Output
Enable)
MSPLT (RO)
(Mute Split)
AC ‘97NC (RO)
(AC ‘97 No Compatibility
Mode)
DACZ
(DAC Zero-Fill)
x
Function
Provides analog down-mixing of the center, LFE and/or surround channels into the mixer channels. This allows
the full content of 5.1 or quad media to be played through stereo headphones or speakers. The jack sense pins
can also be setup to control (gate) this function depending on the JS0DMx and JS1DMx bits (0x72 D [14:13]).
DMIX [1:0]
Down-Mix State
0x
No down-mix unless activated by jack sense
Default
10
Selects 6-to-4 down-mix. The center and LFE channels are
summed equally into the Mixer L/R channels
11
Selects 6-to-2 down-mix. In addition to the center and LFE
channels, the SURROUND channels are summed into the
mixer L/R channels
Controls the Hi-Z state of the SURROUND output pins. Pins are placed into a Hi-Z mode by software control or
when they are selected as inputs to the LINE_IN selector (see the LISEL [1:0] bits 0x76 D [03:02]).
CLDIS
SURROUND_OUT State
0
Outputs enabled
Default
1
Outputs tri-stated (Hi-Z)
Separates the left and right mutes on all volume registers. This bit is read-only 1 (one) on the AD1986 indicating
that mute split is always enabled.
Changes addressing to ADI model (vs. true AC ’97 definition). This bit is read-only 1 (one) on the AD1986
indicating that ADI addressing is always enabled.
Determines DAC data fill under starved condition.
DACZ
DAC Fill State
0
DAC data is repeated when DACs are starved for data
1
DAC data is zero-filled when DACs are starved for data
Reserved.
Default
Default: 0
ADVANCED JACK SENSE (REGISTER 0x78)
All register bits are read/write except for JSxST bits, which are read-only. Important: Please refer to Table 72 to understand how
JACK_SENSE_A and JACK_SENSE_B codec pins translate to JS7…JS2.
Reg
0x78
Name
Advanced
Jack Sense
D15
JS7
ST
D14
JS7
INT
D13
JS6
ST
D12
JS6
INT
D11
JS5
ST
D10
JS5
INT
D9
JS4
ST
D8
JS4
INT
D7
JS47H
D6
x
D5
JS3
MD
D4
JS2
MD
D3
JS3
ST
D2
JS2
ST
D1
JS3
INT
D0
JS2
INT
Default
0xxxxx
Table 64.
Register
JS [7:2] INT
JS [7:4] ST (RO)
JS [3:2] MD
Function
Indicates JSx has generated an interrupt. Remains set until the software services JSx interrupt; i.e., JSx ISR should clear
this bit by writing a 0 to it.
1. Interrupts are generated by valid state changes of JSx.
2. Interrupt to the system is actually an OR combination of this bit and JS7 JS0 INT.
3. Interrupt implementation path is selected by the INTS bit (Register 0x74).
4. It is also possible to generate a software system interrupt by writing a 1 to this bit.
JS [7:4] INT
Read
Write
Default
0
JSx logic is not interrupting
Clears JSx interrupt
Default
1
Sx logic interrupted
Generates a software interrupt
This bit always reports the logic state of JS7 thru 4 detection logic.
JS [7:4] ST
Jack State
0
No jack present
1
Jack detected
This bit selects the operation mode for JS2 and JS3.
JS [3:2] MD
Interrupt Mode
0
Jack Sense Mode—jack sense state requires software polling
Default
1
Interrupt Mode—jack sense evetns will generate interrupts
Rev. 0 | Page 40 of 52
Preliminary Technical Data
Register
JS4–7H
Interrupt
Mode Select
AD1986
Function
This bit selects the audio interrupt implementation path (for JS4 to 7). This bit does not generate an interrupt, rather it
steers the path of the generated interrupt.
JS4 to 7H
Interrupt Mode—JS4 to 7
0
Bit 0 SLOT 12 (modem interrupt)
Default
1
Slot 6 valid bit (MIC ADC interrupt)
Reserved
Default: 0
x
MISC CONTROL BITS 3 (REGISTER 0x7A)
Reg
Name
0x7A
Misc Control Bits 3 JSINVB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
HPSEL1
HPSEL0
LOSEL
JSINVA
LVREF 2
LVREF1
LVREF 0
x
x
x
LOHPEN
GPO
MMIX
x
x
0x0000
Table 65.
Register
MMIX
GPO
LOHPEN
LVREF [2:0]
(Line In
VREF_OUT)
LOSEL
(LINE_OUT
Amplifiers
Input Select)
JSINVA
Jack Sense
Invert
Function
Used in conjunction with the OMS [2:0] (0x74 D10:08), MS (0x20 D08), and 2CMIC (0x76 D06) bits to mix the microphone
selector left/right channels. If the MMIX bit is set, the 2CMIC and MS bits are ignored.
MMIX
Function
Default
0
Microphone channels are not mixed
Default
1
The left/right channels from the microphone selector are mixed
Sets the state of the GPO pin
GPO
Function
0
GPO pin is at logic low (DVSS)
Default
1
GPO pin is at logic high (DVDD)
Enables the headphone drive on the LINE_OUT pins. Disabling the headphone drive is the same as powering it down (see
the PR6 bit (0x26 D14)).
LOHPEN
Function
0
LINE_OUT headphone drive is disabled
Default
1
LINE_OUT headphone drive is enabled
Sets the voltage/state of the LINE_IN VREF_OUT signal. VREF_OUT is used to power microphone style devices plugged into
the connected jack circuitry. The VREF_OUT pin must be connected to both the left and right channels through external
resistors to function properly. Selections other than those defined are invalid and should not be programmed.
LINE_IN VREF_OUT Setting
3.3 V AVDD
LVREF [2:0]
5.0 AVDD
000
Hi-Z
Hi-Z
Default
001
2.25 V
2.25 V
010
0V
0V
100
3.70 V
2.25 V
This bit allows the LINE_OUT output amplifiers to be driven by the mixer or the surround DACs. The main purpose for this is
to allow swapping of the frontand surround channels to make better use of the SURR/HP_OUT output amplifiers. This bit
should normally be used in tandem with the HPSEL bit (see below).
LOSEL
LINE_OUT Select
0
Default
LINE_OUT amplifiers are driven by the
analog mixer outputs
1
LINE_OUT amplifiers are driven by the
surround DAC
SENSE_A: Select the style of switches used on the audio jacks connected to Sense A.
JSINVA
Jack Sense Invert—SENSE_A
0
1
SENSE_A configured for normallyopen (NO) switches
SENSE_A configured for normally-closed
(NC) switches
Rev. 0 | Page 41 of 52
Default
AD1986
Register
HPSEL [1:0]
(Headphone
Amplifier
Input Select)
JSINVB
(Jack Sense
Invert)
x
Preliminary Technical Data
Function
This bit allows the headphone power amps to be driven from the surround DACs, C/LFE DACs, or from the mixer outputs.
HPSEL [1:0]
HP_OUT Selection
00
Default
Outputs are driven by the mixer
outputs
01
Outputs are driven by the surround
DACs
1x
Outputs are driven by the C/LFE DACs
SENSE_B: Select the style of switches used on the audio jacks connected to Sense B.
JSINVB
Jack Sense Invert—SENSE_B
0
Default
JACK_SENSE_B configured for normallyopen (NO) switches
1
JACK_SENSE_B configured for normallyclosed (NC) switches
Reserved.
Default: 0
VENDOR ID REGISTERS (REGISTER 0x7C to 0x7E)
Reg
0x7C
0x7E
Name
Vendor
ID 1
Vendor
ID 2
D15
F7
D14
F6
D13
F5
D12
F4
D11
F3
D10
F2
D9
F1
D8
F0
D7
S7
D6
S6
D5
S5
D4
S4
D3
S3
D2
S2
D1
S1
D0
S0
Default
0x4144
T7
T6
T5
T4
T3
T2
T1
T0
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
0x5378
D7
RV7
D6
RV6
Table 66.
Register
S [7:0]
F [7:0]
T [7:0]
REV [7:0]
Function
This register is ASCII encoded to A.
This register is ASCII encoded to D.
This register is ASCII encoded to S.
This register is set to 0x78, identifying the AD1986.
CODEC CLASS/REVISION REGISTER (REGISTER 0x60)
Reg
0x601
Name
CODEC
Class/Rev
D15
x
D14
x
D13
x
D12
CL4
D11
CL3
D10
CL2
D9
CL1
D8
CL0
D5
RV5
D4
RV4
D3
RV3
D2
RV2
D1
RV1
D0
RV0
Default
0x0002
Table 67.
Register
RV [7:0]
(Revision ID:
(RO))
CL [4:0]
(CODEC
Compatibility
Class (RO))
x
Function
These bits specify a device specific revision identifier. The vendor chooses this value. Zero is an acceptable
value. This field should be viewed as a vendor defined extension to the CODEC ID. This number changes
with new CODEC stepping of the same CODEC ID. This number will increment with each stepping/rev. of
the CODEC chip.
The AD1986 will return 0x00 from this register. This is a CODEC vendor specific field to define software
compatibility for the CODEC. Software reads this field together with CODEC vendor ID (Register 7C–0x7E)
to determine vendor specific programming interface compatibility. Software can rely on vendor specific
register behavior to be compatible among vendor CODECs of the same class.
0x00
Field not implemented
0x01-0x1F
Vendor specific compatibility class code
Reserved.
Rev. 0 | Page 42 of 52
Default
Default: 0
Preliminary Technical Data
AD1986
PCI SUBSYSTEM VENDOR ID REGISTER (REGISTER 0x62, PAGE 01)
This register is only reset by power-on. It is used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specification)
and must not be reset by soft or hardware resets.
Reg
0x621
Name
PCI
SVID
D15
PVI15
D14
PVI14
D13
PVI13
D12
PVI12
D11
PVI11
D10
PVI10
D9
PVI9
D8
PVI8
D7
PVI7
D6
PVI6
D5
PVI5
D4
PVI4
D3
PVI3
D2
PVI2
D1
PVI1
D0
PVI0
Default
0xFFFF
Table 68.
Register
PVI [15:0]
PCI Sub
System
Vendor ID
Function
Optional per AC ‘97 specifications, should be implemented as read/write on AD1986.
This field provides the PCI subsystem vendor ID of the audio or modem subassembly vendor (i.e., CNR manufacturer,
motherboard vendor). This is NOT the CODEC vendor PCI vendor ID or the AC ’97 controller PCI vendor ID. If data is not
available it should return 0xFFFF.
PCI SUBSYSTEM DEVICE ID REGISTER (REGISTER 0x64, PAGE 01)
This register is only reset by power-on. It is used by the BIOS to store configuration information (per AC’97 v2.3 specification) and must
not be reset by soft or hardware resets.
Reg
0x641
Name
PCI SID
D15
PI15
D14
PI14
D13
PI13
D12
PI12
D11
PI11
D10
PI10
D9
PI9
D8
PI8
D7
PI7
D6
PI6
D5
PI5
D4
PI4
D3
PI3
D2
PI2
D1
PI1
D0
PI0
Default
0xFFFF
Table 69.
Register
PI [15:0]
(PCI Vendor
ID)
Function
Optional per AC ‘97 specifications, should be implemented as read/write on the AD1986. This field provides the PCI
subsystem ID of the audio or modem subassembly (i.e., CNR model, motherboard SKU). This is NOT the CODEC vendor PCI
ID or the AC ’97 controller PCI ID. Information in this field must be available, because the AC ’97 controller reads when the
CODEC ready is asserted in the AC link. If data is not available it should return FFFFh.
FUNCTION SELECT REGISTER (REGISTER 0x66, PAGE 01)
This register is used to select which function (analog I/O pins), information and I/O (0x6801), and sense (0x6A01) registers apply to it.
The AD1986 associates FC = 0x0 with surround functions and FC = 0x01 with front functions. These are changed in the AD1986 to align
with the new device pin-out and to separate LINE_OUT functions.
Reg
0x661
Name
Function
Select
D15
x
D14
x
D13
x
D12
x
D11
x
D10
x
D9
x
D8
x
Rev. 0 | Page 43 of 52
D7
x
D6
x
D5
x
D4
FC3
D3
FC2
D2
FC1
D1
FC0
D0
T/R
Default
0x0000
AD1986
Preliminary Technical Data
Table 70.
Register
T/R
(FIP or Ring
Selection Bit)
FC [3:0]
Function Code
Bits
x
Function
This bit sets which jack conductor the sense value is measured from. Software will program the corresponding rng/tp
selector bit together with the I/O number in bits FC [3:0]. Once software programs the value and properly reads it back to
confirm selection and implementation, it will access the rest of the bits fields in the descriptor. Mono inputs and outputs
should report the relevant function and sense information when T/R is set to 0 (tip). The FIP bit should report 0 (Page
0x01, Register 0x68, Bit 0 reports no function information present) when T/R is set to a 1 on a mono input or output.
T/R
Function
0
Tip (left channel)
Default
1
Ring (right channel)
These bits specify the type of audio function described by this page. These bits are read/write and represent current
AC ’97 Revision 2.2 defined I/O capabilities. Software will program the corresponding I/O number in this field together
with the tip/ring selector bit T/R. Once software programs the value and properly reads it back to confirm selection and
implementation, it will access the rest of the bits fields in the descriptor.
FC [3:0]
Function
0x0
DAC 1 (master out). maps to front DACs (L/R)
Default
0x1
DAC 2 (AUX out). maps to surround DACs (L/R)
0x2
DAC 3 (C/LFE). maps to C/LFE DACs
0x3
S/P-DIF out
0x4
Phone in
0x5
MIC_1 (Mic select = 0)
0x6
MIC_2 (Mic select = 1)
0x7
Line in
0x8
CD in
0x9
Video in
Not supported on the AD1986
0xA
Aux in
0xB
Mono out
0xC
Headphone ut
0xD–0xF
Reserved
Reserved.
Default: 0
INFORMATION AND I/O REGISTER (REGISTER 0x68, PAGE 01)
This address represents multiple registers (one for each supported function code (FC [3:0] bits (0x66 D [04:01])). These values are only
reset by power-on. It is used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specifications) and must not be reset
by soft or hardware resets.
Reg
0x681
Name
Information
and I/O
D15
G4
D14
G3
D13
G2
D12
G1
D11
G0
D10
INV
D9
DL4
D8
DL3
D7
DL2
D6
DL1
D5
DL0
D4
IV
D3
x
D2
x
D1
x
D0
FIP
Default
0xxxxx
Table 71.
Register
FIP (RO)
(Function
Information
Present)
Function
CODEC default. When set to a 1, this bit indicates that the G [4:0], INV, DL [4:0] (in Register 0x681), and ST [2:0] (in
Register 0x6A1) bits are supported and are read/write capable. This bit set to a 0 indicates that the G [4:0], INV, DL [4:0], and
ST [2:0] bits are not supported, and are read-only with a value of 0. Mono inputs and outputs should report the relevant
function and sense information when T/R is set to 0 (tip). The FIP bit should report 0 (Page 0x01, Register 0x68, Bit 0 reports
no function information present) when T/R is set to a 1 on a mono input or output.
FIP
Function
0
Function information not supported
Power-on default
1
Function information supported
Rev. 0 | Page 44 of 52
Preliminary Technical Data
Register
IV
(Information
Valid Bit)
DL [4:0]
(Buffer
Delays,
Read/Write)
INV
(Inversion
Bit,
Read/Write,
CODEC
Default)
G [4:0]
(Gain Bits
(Read/Write))
AD1986
Function
Indicates whether a sensing method is provided by the CODEC and if information field is valid. This field is updated by the
CODEC.
IV
Function
0
After CODEC reset de-assertion, it indicates the CODEC does NOT provide sensing logic and this bit will be
Read-Only. After a sense cycle is completed indicates that no information is provided on the sensing method.
1
After CODEC reset de-assertion, it indicates the CODEC provides sensing logic for this I/O and this bit is
Read/Write. After clearing this bit by writing 1, when a sense cycle is completed indicates that there is valid
information in the remaining descriptor bits. Writing 0 to this bit has no effect.
A number representing a delay measurement for the input and output channels. The default value is the delay internal to
the CODEC. The BIOS may add to this value the known delays external to the CODEC, such as for an external amplifier, logic,
etc. Software will use this value to accurately calculate audio stream position with respect to what is been reproduced or
recorded. These values are in 20.83 microsecond (1/48000 second) units. For output channels, this timing is from the end of
AC link frame in which the sample is provided, until the time the analog signal appears at the output pin. For input streams,
this is from when the analog signal is presented at the pin until the representative sample is provided on the AC link. Analog
to analog paths are not considered in this measurement. The measurement is a typical measurement, at a 48 KHz sample
rate, with minimal in-CODEC processing (i.e., 3D effects are turned off.) An example of an audio output delay is filter group
delay and FIFO or other sample buffers in the path. So when an audio PCM sample is written to the CODEC in an AC ’97
frame it will be delayed before the output pin is updated to that value.
DL [4:0]
Function
0x00
Information not provided
0x01-0x1E
Buffer delay: 20.83 µs per unit
0x1F
Reserved
Indicates that the CODEC presents a 180 degree phase shift to the signal. This bit is only reset by a power-on reset, since it is
typically written by the system BIOS and is not reset by CODEC hard or soft resets as long as power remains applied to the
CODEC.
INV
Function
0
No phase shift
1
Signal is shifted by 180° from the source signal
The CODEC updates these bits with the gain value (dB relative to level-out) in 1.5 dBV increments, not including the volume
control gains. For example, if the volume gain is to 0 dB, then the output pin should be at the 0 dB level. Any difference in
the gain is reflected here. When relevant, the BIOS updates this bit to take into consideration external amplifiers or other
external logic that it knows about. G [3:0] indicates the magnitude of the gain. G [4] indicates whether the value is a gain or
attenuation—essentially it is a sign bit. These bits are only reset by a power-on reset as they are typically written by the
system BIOS and are not reset by CODEC hard or soft resets as long as power remains applied to the CODEC.
G4
G [3:0]
Gain/Attenuation (dB Relative to Level-Out)
0
0000
0 dB
0001
+1.5 dB
0
...
+1.5 dB × G [3:0]
1111
+24.0 dB
0001
−1.5 dB
1
...
−1.5 dB × G [3:0]
1111
−24.0 dB
x
Reserved
Default: 0
Rev. 0 | Page 45 of 52
AD1986
Preliminary Technical Data
SENSE REGISTER (REGISTER 0x6A, PAGE 01)
This address represents multiple registers (one for each supported function code (FC [3:0] bits (0x66 D [04:01])). The ST [2:0] bits are
only reset by power-on. They are used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specifications) and must
not be reset by soft, hard or hardware resets. The remaining bits are the result of the last sense operation performed by the impedance
sensing circuitry.
Reg
0x6A1
Name
Sense
Register
D15
ST2
D14
ST1
D13
ST0
D12
S4
D11
S3
D10
S2
D9
S1
D8
S0
D7
OR1
D6
OR0
D5
SR5
D4
SR4
D3
SR3
D2
SR2
D1
SR1
D0
SR0
Default
0xxxxx
Table 72.
Register
SR [5:0] (RO)
(Sense Result
Bits, RO)
OR [1:0] (RO)
(Order Bits)
S [4:0] (RO)
S [4:0] (RO)
Function
These bits are used to report a vendor specific fingerprint or value. (resistance, impedance, reactance,
etc. Used with the OR bits which are the multiplying factor.
Default
Default: 0
These bits indicate the order the sense result bits SR [5:0] are using. For example, if measuring resistance SR = 1/OR =
11: the result is 1 KΩ.
OR [1:0]
Order Value
00
100—SR bits indicate the actual impedance in ohms
Default
01
101—SSR bits indicate the impedance in ohms × 10
10
102—SR bits indicate the impedance in ohms × 100
11
103—SSR bits indicate the impedance in ohms × 1,000
Sensed bits meaning relates to the I/O being sensed as input or output. Read only. Sensed bits (when output sense
cycle initiated). This field allows for the reporting of the type of output peripheral/device plugged in the jack. Values
specified below should be interrogated with the SR [5:0] and OR [1:0] for accurate reporting.
S [4:0]
Sense Value
0x00
Data not valid. Indicates that the reported value(s) is invalid
0x01
No connection. Indicates that there are no connected devices
Default
0x02
Indicates a specific fingerprint value for devices that are not specified or are
unknown
0x03
Speakers (8 Ω)
0x04
Speakers (4 Ω)
0x05
Powered speakers
0x06
Stereo headphone
0x07
SPDIF out (electrical)
0x08
SPDIF out (TOS)
0x09
Mono headset (mono speaker left channel and mic. Read Functions 5 and 6 for
matching microphone)
0x0A
Allows a vendor to report sensing other type of devices/peripherals. SR [5:0]
together with OR [1:0] provide information regarding the type of device sensed
0x0B–0x0E
Reserved
0x0F
Unknown (use fingerprint)
0x10–0x1F
Reserved
Sensed bits (when input sense cycle initiated). This field allows for the reporting of the type of input peripheral/device
plugged in the jack. Values specified below should be interrogated with the SR [5:0] and OR [1:0] bits for accurate
reporting.
ST [2:0]
Sense Value
0x10
Data not valid. Indicates that the reported value(s) is invalid
0x11
No connection. Indicates that there are no connected devices
Default
0x12
Indicates a specific fingerprint value for devices that are not specified or are
unknown
0x13
Microphone (mono)
Rev. 0 | Page 46 of 52
Preliminary Technical Data
Register
ST [2:0]
(Connector/Jack
location Bits,
Read/Write)
AD1986
Function
0x14
0x15
0x16
0x17
0x18
0x19
Default
Microphone (stereo)
Stereo line in (CE device attached)
Mono line in (CE device attached)
SPDIF In (electrical)
SPDIF In (TOS)
Headset (mono speaker left channel and mic.) Read Functions 0 to 3 for matching
DAC out
0x1A
Allows a vendor to report sensing other types of devices/peripherals. SR [5:0]
together with OR [1:0] provide information regarding the type of device sensed
0x1B–0x1E
Reserved
0x1F
Unknown (use fingerprint)
This field describes the location of the jack in the system. This field is updated by the BIOS. This bits is only reset by a
power-on reset as it is typically written by the system BIOS and is not reset by CODEC hard or soft resets as long as
power remains applied to the CODEC.
ST [2:0]
0x0
Jack Location
Rear I/O panel
0x1
0x2
0x3
0x4–0x6
0x7
Front panel
Motherboard
Dock/external
Reserved
No connection/unused I/O
Power-on
default
Rev. 0 | Page 47 of 52
AD1986
Preliminary Technical Data
JACK PRESENCE DETECTION
sense style for SENSE_B is controlled by the JSINVB bit
(Register 0x7A D15). Writing a 1 to these bits will configure the
corresponding sense circuit for normally closed instead of
normally open switch types.
The AD1986 uses two jack sense lines for presence detection on
up to eight external jacks. These lines, combined with the
device detection circuitry, enable software to determine
whether there is a device plugged into the circuit and what type
of device it is. With this feature, software can reconfigure jacks
and amplifiers as necessary to insure proper audio operation.
Wrap-back jacks cannot be used in microphone-capable circuits. For this reason isolated switches are recommended. The
codec defaults to sensing NO style switches and this method is
preferred.
Jack presence is detected using a resistor tree arrangement. Up
to four jacks can be sensed on a single sense line by using a
different value resistance for each jack between the sense line
and ground (AVSS). Each sense line must have a single 2.49k 1%
resistor connected between the sense line and AVDD. The
specific resistor values for each jack are shown in Table 73. One
percent tolerance resistors should be used for all jack presence
circuitry to insure accurate detection.
Normally-Open Switches
If a connection is not present, do not install the sense resistor
pertaining to that connection.
If a connection is present, but there is no related switch (such
as an internal connection), install the sense resistor pertaining
to that connection.
AUDIO JACK STYLES (NC/NO)
Normally Closed Switches
The jack sense lines on the AD1986 can be programmed for use
with normally-open (NO) or normally closed (NC) switch
types. Current standard stereo audio jacks have wrap-back pins
that are normally closed. New audio jacks use isolated, normally
open switches, which are required for resistive ladder jack
presence detection. Each sense group (A or B) must have the
same style of jack for presence detection to function correctly.
However, the group (A or B) sense type can be programmed
separately to accommodate systems with different styles of jacks
on the front versus rear panel.
Connections capable of MIC bias require isolated switches to
function correctly. When using normally closed, wrap-back
switches, the jack resistor must be split into two values. One
value connects the sense line to the jack switch and the other
connects the related audio connection to AVSS. The total
resistance (sense line to AVSS) must equal the value specified in
Table 73.
If a connection is not present, install the sense resistors
pertaining to that connection.
The AD1986 defaults to the isolated, normally open switch
types on power up. The jack sense style for SENSE_A is
controlled by the JSINVA bit (Register. 0x7A D11). The jack
If a connection is present, but there is no related switch (such
as an internal connection), do not install the sense resistors
pertaining to that connection.
Table 73. Jack Sense Mapping
Resister (1% tolerance)
4.99k
10.0k
20.0k
40.2k
Mnemonic
LINE IN
MIC_1/2
HP_OUT
JACK_SENSE_A
Jack
D
C
B
A
JS
JS7
JS4
JS5
JS1
Rev. 0 | Page 48 of 52
Mnemonic
LINE OUT
C/LFE
SURROUND
AUX IN
JACK_SENSE_B
Jack
H
G
F
E
JS
JS0
JS3
JS2
JS6
Preliminary Technical Data
AD1986
MICROPHONE SELECTION/MIXING
MIC 1
CENTER
NID: 0x0F
LINE IN L
MIC Select: OMS[2:0]
0x74 D10-D08
DEF=000 (MIC 1/2)
000-MIC 1/2
001-Line In
01x-C/LFE
100-MIC+C/LFE
101-MIC+Line In
110-C/LFE+Line In
111-MIC+C/LFE+Line
G
MIC LEFT
NID: 0x11
MIC Boost: AC97
M20 0x0E D6 DEF=0
MGB[1:0] 0x76 D[1:0] DEF=00
MGB
M20
0
1
1
1
1
[1:0]
xx
00
01
10
11
Gain
0dB
+20dB
+10dB
+30dB
reserved
NID: 0x2B
Azalia
MGBL[1:0] 0x70 D[1:0]
MGBR[1:0} 0x70 D[14:13]
MIC 2
LFE
MGBL/R
[1:0]
00
01
10
11
LINE IN R
NID: 0x27
Gain
0dB
+10dB
+20dB
+30dB
MIC Swap: AC97
MS 0x20 D08 DEF=0
2CMIC 0x76 D06 DEF=0
MMIX 0x7A D02 DEF=0
Azalia
MSWP[2:0] 0x7A D02:00
MMIX
MSWP2
0
0
0
0
1
2CMIC
MSWP1
0
0
1
1
x
G
NID: 0x28
NID: 0x29
NID: 0x2A
Figure 10. Microphone Selection/Mixing Block Diagram
Rev. 0 | Page 49 of 52
MS
MSWP0
0
1
0
1
x
Right
MIC 1
MIC 2
MIC 2
MIC 1
MIC 1+2
Left
MIC 1
MIC 2
MIC 1
MIC 2
MIC 1+2
MIC RIGHT
AD1986
Preliminary Technical Data
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
1.45
1.40
1.35
0.15
0.05
PIN 1
SEATING
PLANE
10°
6°
2°
7.00
BSC SQ
TOP VIEW
0.20
0.09
(PINS DOWN)
VIEW A
7°
3.5 °
0°
0.08 MAX
COPLANARITY
SEATING
PLANE
25
12
13
0.50
BSC
VIEW A
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 11. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD1986JSTZ1
AD1986JSTZ1-REEL
AD1986BSTZ1
AD1986BSTZ1-REEL
1
Temperature Range
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
Package Description
48-Lead LQFP, Tray
48-Lead LQFP, Reel
48-Lead LQFP, Tray
48-Lead LQFP, Reel
Z = Pb-free part.
Rev. 0 | Page 50 of 52
Package Option
ST-48
ST-48
ST-48
ST-48
Preliminary Technical Data
AD1986
NOTES
Rev. 0 | Page 51 of 52
AD1986
Preliminary Technical Data
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered
trademarks are the property of their respective owners.
D04785-0-10/04(0)
Rev. 0 | Page 52 of 52