Mitsubishi M2V56D30AKT-75 256m double data rate synchronous dram Datasheet

DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit,
M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit,
M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40AKT achieves very
high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard
Operating Frequencies
Speed
Grade
Clock Rate
CL=2 *
CL=2.5 *
-75A
133MHz
133MHz
-75
100MHz
133MHz
-10
100MHz
125MHz
* CL = CAS(Read) Latency
MITSUBISHI ELECTRIC
1
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256M Double Data Rate Synchronous DRAM
PIN CONFIGURATION(TOP VIEW)
CLK,/CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-7
DQS
DM
Vref
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Data Strobe
: Write Mask
: Reference Voltage
PIN PITCH 0.4 mm
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
64pin STSOP
X4
X8
X 16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A0-12
BA0,1
Vdd
VddQ
Vss
VssQ
MITSUBISHI ELECTRIC
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSSQ
UDQS
NC
VREF
VSS
UDM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
VSS
DQ7
NC
VSSQ VSSQ
NC
NC
DQ6
DQ3
VDDQ VDDQ
NC
NC
DQ5
NC
VSSQ VSSQ
NC
NC
DQ4
DQ2
VDDQ VDDQ
NC
NC
VSSQ VSSQ
DQS
DQS
NC
NC
VREF VREF
VSS
VSS
DM
DM
/CLK /CLK
CLK
CLK
CKE
CKE
NC
NC
A12
A12
A11
A11
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
VSS
VSS
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
2
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL
CLK, /CLK
TYPE
Input
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
Input
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-15(x16),
DQ0-7(x8),
Input / Output
Data Input/Output: Data bus
Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
DQ0-3(x4),
DQS
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
Vref
Input
SSTL_2 reference voltage.
MITSUBISHI ELECTRIC
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DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
DQ0 - 15
UDQS,LDQS
I/O Buffer
QS Buffer
BLOCK DIAGRAM
DLL
Memory
Memory
Memory
Memory
Array
Array
Array
Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
A 0-12
/CS
BA0,1
/RAS /CAS
/ WE
C L K /C L K C K E
Type Designation Code
UDM,
LDM
This rule is applied to only Synchronous DRAM family.
M 2 S 56 D 3 0 A TP –75A
Speed Grade
10: 125 MHz@CL=2.5,100MHz@CL=2.0
75: 133 MHz@CL=2.5,100MHz@CL=2.0
75 A: 133MHz@CL=2.5,133MHz@CL=2.0
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
n
Organization 2
2: x4, 3: x8, 4: x16
D DR Synchronous DRAM
Density 56: 256M bits
Interface
V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
4
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
BASIC FUNCTIONS
The M2S56D20/30/40AKT provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CLK
CLK
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This co mmand also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
COMMAND TRUTH TABLE
CKE
CKE
A10
A0-9,
n-1
n
/AP
11-12
DESEL
H
X
X
X
No Operation
NOP
H
X
X
X
Row Address Entry &
Bank Activate
H
H
V
V
V
L
H
L
V
L
X
L
L
H
L
X
H
X
H
L
H
L
L
V
L
V
H
H
L
H
L
L
V
H
V
READ
H
H
L
H
L
H
V
L
V
READA
H
H
L
H
L
H
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
COMMAND
MNEMONIC
/CS
/RAS
/CAS
/WE
BA0,1
Deselect
X
H
X
X
X
H
X
L
H
H
ACT
H
H
L
L
Single Bank Precharge
PRE
H
H
L
Precharge All Banks
PREA
H
H
Column Address Entry
& Write
WRITE
H
WRITEA
Column Address Entry
& Write with
note
Auto-Precharge
Column Address Entry
& Read
Column Address Entry
& Read with
Auto-Precharge
Burst Terminate
TERM
H
H
L
H
H
L
X
X
X
1
Mode Register Set
MRS
H
H
L
L
L
L
L
L
V
2
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for
read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 ,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the
op-code to be written to the selected Mode Register.
MITSUBISHI ELECTRIC
6
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
FUNCTION TRUTH TABLE
Current State
IDLE
/ C S /RAS
Command
Action
Notes
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
ILLEGAL
2
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL
2
L
L
H
H
BA, RA
ACT
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE / PREA
NOP
4
L
L
L
H
X
REFA
Auto-Refresh
5
MRS
Mode Register Set
5
L
ROW ACTIVE
/ C A S / W E Address
L
L
L
Op-Code, ModeAdd
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
NOP
L
H
L
H
BA, CA, A10
READ / READA
L
H
L
L
BA, CA, A10
WRITE / WRITEA
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
READ(Auto-
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
Precharge
L
H
H
H
X
NOP
NOP (Continue Burst to END)
Disabled)
L
H
H
L
BA
TERM
Terminate Burst
L
H
L
H
BA, CA, A10
READ / READA
Op-Code, ModeAdd
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
2
Terminate Burst, Latch CA, Begin
New Read, Determine Auto-
3
Precharge
L
H
L
L
BA, CA, A10
WRITE / WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
Op-Code, ModeAdd
MITSUBISHI ELECTRIC
2
7
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
FUNCTION TRUTH TABLE (continued)
Command
Action
WRITE(AutoPrecharge
Current State
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
Disabled)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA
L
H
L
L
BA, CA, A10
WRITE / WRITEA
L
L
H
H
BA, RA
ACT
Write, Determine Auto-Precharge
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
READ with
Auto-Precharge
WRITE with
Auto-Precharge
/CS /RAS /CAS /WE Address
Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge
Terminate Burst, Latch CA, Begin
Notes
3
3
2
L
L
L
L
H
X
X
X
Op-Code, ModeMRS
Add
X
DESEL
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA
ILLEGAL for Same Bank
6
L
H
L
L
BA, CA, A10
WRITE / WRITEA
ILLEGAL for Same Bank
6
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
Precharge / ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, ModeMRS
Add
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
L
L
H
H
L
L
L
H
H
L
H
BA, CA, A10
BA, CA, A10
BA, RA
READ / READA
WRITE / WRITEA
ACT
ILLEGAL for Same Bank
ILLEGAL for Same Bank
Bank Active / ILLEGAL
7
7
2
L
L
H
L
BA, A10
PRE / PREA
Precharge / ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, ModeMRS
Add
MITSUBISHI ELECTRIC
ILLEGAL
NOP (Continue Burst to END)
ILLEGAL
8
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
FUNCTION TRUTH TABLE (continued)
Current State
PRECHARGING
ROW
ACTIVATING
WRITE RECOVERING
/CS /RAS /CAS /WE Address
Command
Action
Notes
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
BA
TERM
ILLEGAL
2
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL
2
L
L
H
H
BA, RA
ACT
ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
NOP (Idle after tRP)
4
L
L
L
H
X
REFA
ILLEGAL
ILLEGAL
L
L
L
L
Op-Code, ModeMRS
Add
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
BA
TERM
ILLEGAL
2
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL
2
L
L
H
H
BA, RA
ACT
ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
H
X
X
X
Op-Code, ModeMRS
Add
X
DESEL
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
ILLEGAL
2
L
L
H
L
L
H
X
H
BA, CA, A10
BA, RA
READ / WRITE
ACT
ILLEGAL
ILLEGAL
2
2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
Op-Code, ModeMRS
Add
L
L
L
MITSUBISHI ELECTRIC
ILLEGAL
NOP
ILLEGAL
9
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
FUNCTION TRUTH TABLE (continued)
Current State
REFRESHING
/ C S /RAS /CAS / W E Address
Command
Action
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
ILLEGAL
L
L
L
L
Op-Code, ModeMRS
Add
MODE
REGISTER
H
X
X
X
X
DESEL
NOP (Row Active after tRSC)
L
H
H
H
X
NOP
NOP (Row Active after tRSC)
SETTING
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, ModeMRS
Add
Notes
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Refer to Read with Auto -Precharge in page 24.
7. Refer to Write with Auto-Precharge in page 26.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
10
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
FUNCTION TRUTH TABLE for CKE
Current State
SELFREFRESHING
POWER
DOWN
ALL BANKS
IDLE
CKE n-1
CKE n
/CS
/RAS
/CAS
/WE
Address
Action
Notes
H
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
L
X
ILLEGAL
1
L
H
L
H
L
X
X
ILLEGAL
1
L
H
L
L
X
X
X
ILLEGAL
1
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
1
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
H
X
X
X
X
X
Refer to Function Truth Table
2
H
L
L
L
L
H
X
Enter Self-Refresh
2
H
L
H
X
X
X
X
Enter Power Down
2
H
L
L
H
H
H
X
Enter Power Down
2
H
L
L
H
H
L
X
ILLEGAL
2
H
L
L
H
L
X
X
ILLEGAL
2
H
L
L
L
X
X
X
ILLEGAL
2
L
X
X
X
X
X
X
Refer to Current State =Power Down
2
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle
3
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle
3
L
L
X
X
X
X
X
Maintain CLK Suspend
ANY STATE
other than listed
above
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MITSUBISHI ELECTRIC
11
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
SIMPLIFIED STATE DIAGRAM
POWER
APPLIED
POWER
PRE
PREA
SELF
CHARGE
ON
REFRESH
ALL
REFS
MRS
REFSX
MODE
MRS
REGISTER
AUTO
REFA
IDLE
REFRESH
SET
CKEL
CKEH
Active
POWER
ACT
Power
DOWN
Down
CKEL
CKEH
ROW
BURST
ACTIVE
STOP
WRITE
READ
READ
WRITE
WRITEA
READA
READ
WRITE
WRITEA
READ
TERM
READA
READA
WRITEA
READA
PRE
PRE
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
MITSUBISHI ELECTRIC
12
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS for the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the DDR SDRAM is idle state and ready for normal operation.
MODE REGISTER
CLK
Burst Length, Burst Type and /CAS Latency can be
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when both banks are in idle state. After tMRD
from a MRS command, the DDR SDRAM is ready for new
command.
/CLK
BA1 BA0 A12 A11 A10 A 9
A8
A7
A6
A5
A4
A3
A2
/CS
/RAS
/CAS
/WE
A1
A0
BA0
BA1
0
0
0
0
0
Latency
Mode
0
DR
LTMODE
0
CL
0 0 0
/CAS Latency
R
0 0 1
0 1 0
R
2
0 1 1
1 0 0
R
R
1 0 1
R
1 1 0
1 1 1
2.5
R
BT
BL
A11-A0
Burst
Length
Burst Type
DLL Reset
0
NO
1
YES
V
BL
0 0 0
BT=0
R
BT=1
R
0 0 1
0 1 0
2
4
2
4
0 1 1
1 0 0
8
R
8
R
1 0 1
R
R
1 1 0
1 1 1
R
R
R
R
0
Sequential
1
Interleaved
R: Reserved for Future Use
MITSUBISHI ELECTRIC
13
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended
mode register (EMRS). The extended mode register stores these data
until the next EMRS command, which may be issued when all banks are
in idle state. After tMRD from a EMRS command, the DDR SDRAM is
ready for new command.
CLK
/CLK
/CS
/RAS
/CAS
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
/WE
BA0
0
1
0
0
0
0
0
0
0
0
0
0
0
DS
DD
BA1
V
A11-A0
DLL Disable
Drive
Strength
MITSUBISHI ELECTRIC
0
DLL Enable
1
DLL Disable
0
Normal
1
Weak
14
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
/CLK
CLK
Command
Read
Write
Y
Y
Address
DQS
Q0 Q1 Q2 Q3
DQ
CL= 2
BL= 4
Initial Address
/CAS
Latency
D0 D1 D2 D3
Burst
Burst
Length
Length
BL
Column Addressing
A2
A1
A0
Sequential
Interleaved
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
MITSUBISHI ELECTRIC
15
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 3.7
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 3.7
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ VddQ+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
1000
mW
Topr
Operating Temperature
0 ~ 70
o
Tstg
Storage Temperature
-65 ~ 150
o
o
Ta = 25 C
C
C
DC OPERATING CONDITIONS
(Ta=0 ~ 70 o C, unless otherwise noted)
Symbol
Parameter
Vdd
Limits
Unit
Notes
Min.
Typ.
Max.
Supply Voltage
2.3
2.5
2.7
V
VddQ
Supply Voltage for Output
2.3
2.5
2.7
V
Vref
Input Reference Voltage
0.49*VddQ
0.50*VddQ
0.51*VddQ
V
VIH(DC)
High-Level Input Voltage
Vref + 0.15
VddQ+0.3
V
VIL(DC)
Low-Level Input Voltage
-0.3
Vref - 0.15
V
VIN(DC)
Input Voltage Level, CLK and /CLK
-0.3
VddQ + 0.3
V
0.36
VddQ + 0.6
V
7
Vref - 0.04
Vref + 0.04
V
6
VID(DC) Input Differential Voltage, CLK and /CLK
VTT
I/O Termination Voltage
5
CAPACITANCE
(Ta=0 ~ 70 o C, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Test Condition
Limits
Delta
Unit
Min. Max. Cap.(Max.)
Symbol
Parameter
CI(A)
Input Capacitance, address pin
VI=1.25v
2.0
3.0
CI(C)
Input Capacitance, control pin
f=100MHz
2.0
3.0
CI(K)
Input Capacitance, CLK pin
VI=25mVrms
2.0
3.0
CI/O
I/O Capacitance, I/O, DQS, DM pin
4.0
5.0
MITSUBISHI ELECTRIC
Notes
pF
11
pF
11
0.25
pF
11
0.50
pF
11
0.50
16
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70 o C, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Symbol
IDD0
Parameter/Test Conditions
Organization
OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN; t CK
= t CK MIN; DQ, DM and DQS inputs changing twice per clock cycle; address
-75
-10
x4
105
105
100
x8
110
110
105
x16
120
120
115
x4
110
110
105
x8
115
115
110
x16
135
135
130
x4/x8/x16
20
20
20
x4/x8/x16
40
40
40
x4/x8/x16
30
30
30
and control inputs changing once per clock cycle
OPERATING CURRENT: One Bank; Active-Read-Precharge;
IDD1
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA;
Address and control inputs changing once per clock cycle
IDD2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; powerdown mode; CKE <VIL (MAX); t CK = t CK MIN
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
IDD2F CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs changing
Limits(Max.)
-75A
Unit
Notes
once per clock cycle
IDD3P
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; powerdown mode; CKE < VIL (MAX); t CK = t CK MIN
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One
IDD3N
60
60
55
x4/x8/x16
65
65
60
75
75
70
x4
150
150
140
mA
bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM and
DQS inputs changing twice per clock cycle; address and other control inputs
changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank active;
IDD4R Address and control inputs changing once per clock cycle;CL=2.5; t CK = t CK
MIN; IOUT = 0 mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active;
IDD4W Address and control inputs changing once per clock cycle; CL=2.5; t CK = t CK
MIN;DQ, DM and DQS inputs changing twice per clock cycle
x8
170
170
160
x16
210
210
200
x4
145
145
135
x8
165
165
155
x16
200
200
180
IDD5
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
x4/x8/x16
185
185
175
IDD6
SELF REFRESH CURRENT: CKE < 0.2V
x4/x8/x16
3
3
3
IDD7
OPERATING CURRENT-Four bank Operation: Four bank interleaving with
BL=4 -Refer to the Notes 20
x4
250
250
230
20
x8
260
260
240
20
x16
290
290
280
20
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70 o C, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Symbol
Parameter / Test Conditions
VIH(AC) High-Level Input Voltage (AC)
Limits
Min.
Vref + 0.31
VIL(AC) Low-Level Input Voltage (AC)
VID(AC) Input Differential Voltage, CLK and /CLK
VIX(AC) Input Crossing Point Voltage, CLK and /CLK
IOZ
II
Max.
0.7
Unit
V
Vref - 0.31
V
VddQ + 0.6
V
7
V
8
0.5*VddQ - 0.2 0.5*VddQ + 0.2
Off-state Output Current /Q floating Vo=0~VddQ
-5
5
µ A
Input Current / VIN=0 ~ VddQ
-2
2
µ A
IOH
Output High Current (VOUT = VTT+0.84V)
-16.8
mA
IOL
Output High Current (VOUT = VTT-0.84V)
16.8
mA
MITSUBISHI ELECTRIC
Notes
17
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
AC TIMING REQUIREMENTS
(Ta=0 ~ 70 o C, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
-75A
AC Characteristics Parameter
-75
-10
Min.
Max
Min.
Max
Min.
Max
DQ Output Valid data delay time from CLK//CLK
-0.75
0.75
-0.75
0.75
-0.8
0.8
tDQSCK DQ Output Valid data delay time from CLK//CLK
tAC
Unit
ns
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
tCH
CLK High level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCL
CLK Low level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CL=2.5
7.5
15
7.5
15
8
15
ns
tCK
CLK cycle time
CL=2
7.5
15
10
15
10
15
ns
tDS
tDH
Input Setup time (DQ,DM)
0.5
Notes
0.5
0.6
ns
Input Hold time(DQ,DM)
0.5
0.5
0.6
ns
DQ and DM input pulse width (for each input)
1.75
1.75
2
ns
tHZ
Data-out-high impedance time from CLK//CLK
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
14
tLZ
Data-out-low impedance time from CLK//CLK
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
14
0.6
ns
tDIPW
tDQSQ
DQ Valid data delay time from DQS
0.5
tHP
Clock half period
tCLmin or
tCHmin
tQH
Output DQS valid window
tHP-0.75
tDQSS
Write command to first DQS latching transition
0.75
0.5
tCLmin or
tCHmin
tCLmin or
tCHmin
tHP-0.75
1.25
0.75
ns
tHP-1.0
1.25
0.75
ns
1.25
tCK
tDQSH
DQS input High level width
0.35
0.35
0.35
tCK
tDQSL
DQS input Low level width
0.35
0.35
0.35
tCK
tDSS
DQS falling edge to CLK setup time
0.2
0.2
0.2
tCK
tDSH
DQS falling edge hold time from CLK
0.2
0.2
0.2
tCK
tMRD
Mode Register Set command cycle time
15
15
15
ns
0
0
0
ns
16
tCK
15
tWPRES Write preamble setup time
tWPST
Write postamble
0.4
tWPRE
Write preamble
0.25
0.6
0.25
0.25
tCK
tIS
Input Setup time (address and control)
0.9
0.9
1.1
ns
19
tIH
Input Hold time (address and control)
0.9
0.9
1.1
ns
19
tRPST
Read postamble
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tRPRE
Read preamble
0.9
1.1
0.9
1.1
0.9
1.1
tCK
MITSUBISHI ELECTRIC
0.4
0.6
0.4
0.6
18
DDR SDRAM (Rev.1.0)
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
Jul. '01 Preliminary
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70 o C, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
-75A
AC Characteristics Parameter
-75
-10
Min.
Max
Min.
Max
Min.
Max
120,000
45
120,000
50
120,000
Unit
tRAS
Row Active time
45
tRC
Row Cycle time(operation)
65
65
70
ns
tRFC
Auto Ref. to Active/Auto Ref. command period
75
75
80
ns
tRCD
ns
Row to Column Delay
20
20
20
ns
tRP
Row Precharge time
20
20
20
ns
tRRD
Act to Act Delay time
15
15
15
ns
tWR
Write Recovery time
15
15
15
ns
tDAL
Auto Precharge write recovery + precharge time
35
35
35
ns
tWTR
Internal Write to Read Command Delay
1
1
1
tCK
tXSNR
Exit Self Ref. to non-Read command
75
75
80
ns
tXSRD
Exit Self Ref. to -Read command
200
200
200
tCK
tXPNR
Exit Power down to command
1
1
1
tCK
tXPRD
Exit Power down to -Read command
tREFI
Average Periodic Refresh interval
Notes
1
1
1
tCK
18
7.8
7.8
7.8
µs
17
Output Load Condition
V REF
DQS
DQ
V TT = V REF
50 Ω
VOUT
V REF
Zo=50 Ω
30pF
V REF
Output Timing
Measurement
Reference Point
MITSUBISHI ELECTRIC
19
DDR SDRAM (Rev.1.0)
Jul. '01 Preliminary
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the
range between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in th e SSTL_2 Standard (i.e. the receiver will effectively
switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed +2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system su pply for signal termination resistors, is expected to be
set equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level
of the same.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized.
11. This parameter is sampled. VddQ = 2.5V+0.2V, Vdd = 2.5V + 0.2V , f = 100 MHz, Ta = 25 o C, VOUT(DC) =
VddQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in loading (to facilitate trace matching at the board level).
12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK
cross; the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,
CKE< 0.3VddQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before
this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time,
depending on tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
19. For command/address and CK & /CK slew rate > 1.0V/ns.
20. IDD7 : Operating current:Four Bank
For Bank are being interleaved with tRC(min),Burst Mode,Address and Control inputs on NOP edge are not
changing.Iout = 0mA
Timing patterns:
tCK=min,tRRD=2*tCK,BL=4,tRCD=3*tCK,Read with Autoprecharge
Read:A0 N A1 R0 A2 R1 N R3 A0 N A1 R0 – repeat the same timing with random address changing
*100% of data changing at every burst
Legend: A=Activate,R=Read,P=Precharge,N=NOP
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Read Operation
tCK
tCH
tCL
/CLK
CLK
tIS
tIH
Cmd &
Valid Data
Add.
VREF
tDQSCK
tRPST
tRPRE
DQS
tQH
tDQSQ
DQ
tAC
Write Operation / tDQSS=max.
/CLK
CLK
tDQSS
DQS
tWPST
tDSS
tWPRES
tDQSL
tWPRE
tDQSH
tDS
tDH
DQ
Write Operation / tDQSS=min.
/CLK
CLK
tDSH
tDQSS
tWPST
DQS
tWPRES
tWPRE
tDQSL
tDS
tDQSH
tDH
DQ
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OPERATIONAL DESCRIPTION
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activate d by the ACT command with
the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum activation
interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the
precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same time. After
tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=8, CL=2)
/CLK
CLK
2 ACT command / tRCmin
tRCmin
Command
ACT
ACT
READ
tRRD
A0-9,11
Xa
PRE
tRP
tRAS
Xb
ACT
Y
tRCD
Xb
BL/2
A10
Xa
Xb
0
BA0,1
00
01
00
1
Xb
01
DQS
DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
Precharge all
A precharge command can be issued at BL/2 from a read command without data loss.
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READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is available
after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length
is BL. The start address is specified by A11,A9-A0(x4)/A9 -A0(x8)/A8-A0(x16), and the address
sequence of burst data is defined by the Burst Type. A READ command may be applied to any
active bank, so the row precharge time (tRP) can be hidden behind continuous output data by
interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge
(READA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till
the internal precharge is complete. The internal precharge starts at BL/2 after READA. The next
ACT command can be issued after (BL/2+tRP) from the previous REA DA.
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK
CLK
Command
ACT
R E A D ACT
READ
PRE
tRCD
A0-9,11
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
BA0,1
00
00
10
10
0
00
DQS
DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Qb7
Qb8
Burst Length
/CAS latency
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READ with Auto-Precharge (BL=8, CL=2,2.5)
0
1
2
3
4
5
6
7
8
9
10
11
12
/CLK
CLK
BL/2 + tRP
Command
ACT
READA
tRCD
BL/2
A0-9,11
Xa
Y
A10
Xa
1
BA0,1
00
00
tRP
DQS
CL=2
DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa0
Qa1
Qa2
Qa5
Qa6
Qa7
Qa4
Qa5
Qa6
DQS
CL=2.5
DQ
Qa3
Qa7
Internal Precharge Start Timing
Asserted
Command
For Different Bank
3
4
5
6
7
8
9
10
READ
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
READA
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
WRITE(CL=2)
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
WRITE(CL=2.5)
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
WRITEA(CL=2)
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
WRITEA(CL=2.5)
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
ACT
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
PCG
Legal
Legal
Legal
Legal
Legal
Legal
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Legal
Operating description when new command asserted.
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WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from
the WRITE command with data strobe input, following (BL-1) data are written into RAM, when
the Burst Length is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16),
and the address sequence of burst data is defined by the Burst Type. A WRITE command may be
applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input
data by interleaving the multiple banks. From the last data to the PRE command, the write recovery
time (tWRP) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The next ACT command can be issued after tDAL from the last input data
cycle.
Multi Bank Interleaving WRITE (BL=8)
/CLK
CLK
Command
ACT
A0-9,11
Xa
A10
BA0,1
WRITE
WRITE
ACT
PRE
tRCD
tRCD
D
PRE
D
Ya
Xb
Yb
Xa
Xa
0
Xb
0
0
0
00
00
10
10
00
10
DQS
DQ
Da0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Db0
MITSUBISHI ELECTRIC
Db1
Db2
Db3
Db4
Db5
Db6
Db7
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WRITE with Auto -Precharge (BL=8)
0
1
2
3
4
5
6
7
8
9
10
11
12
/CLK
CLK
Command
ACT
WRITEA
ACT
tDAL
tRC
A0-9,11
Xa
Y
Xb
A10
Xa
1
Xb
BA0,1
00
00
00
D
DQS
DQ
Da0
Da1
Da2
Da3
Asserted
Da4
Da5
Da6
Da7
For Different Bank
Command
3
4
5
6
7
8
9
10
READ
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
READA
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
WRITE
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
WRITEA
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
ACT
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
PCG
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Operating description when new command asserted.
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BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Read Interrupted by Read (BL=8, CL=2)
/CLK
CLK
Command
A0-9,11
READ READ
READ
READ
Yi
Yj
Yk
Yl
A10
0
0
0
0
BA0,1
00
00
10
01
DQS
DQ
Qai0
Qai1
Qaj0
Qaj1
Qaj2
Qaj3 Qak0
Qak1
Qak2
Qak3
Qak4
Qak5
Qal0
Qal1
Qal2
Qal3
Qal4
Qal5
Qal6
Qal7
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to PRE interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
DQ
Command
CL=2.5
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
PRE
DQS
DQ
Command
READ
PRE
DQS
DQ
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Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
DQ
Command
CL=2.0
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
PRE
READ
DQS
DQ
Command
READ
PRE
DQS
DQ
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[Read Interrupted by Burst Stop]
Burst read operation can be interrupted by a burst stop command( TERM). READ to TERM interval
is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to TERM interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
TERM
READ
DQS
DQ
Command
CL=2.5
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q4
Q4
Q5
TERM
DQS
DQ
Command
R E A D TERM
DQS
DQ
Command
Q0
READ
Q1
TERM
DQS
Q0
DQ
Command
CL=2.0
READ
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q5
TERM
DQS
DQ
Command
R E A D TERM
DQS
DQ
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[Read Interrupted by Write with TERM]
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
CL=2.5
READ
TERM
DQS
Q0
DQ
Command
CL=2.0
WRITE
READ
Q1
TERM
Q2
Q3
D0
D1
D2
D3
D4
D5
D5
D6
D7
WRITE
DQS
DQ
Q0
Q1
Q2
Q3
MITSUBISHI ELECTRIC
D0
D1
D2
D3
D4
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[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is allowed.
WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=8)
/CLK
CLK
Command
WRITE WRITE
WRITE
WRITE
A0-9,11
Yi
Yj
Yk
Yl
A10
0
0
0
0
BA0,1
00
00
10
00
DQS
DQ
Dai0
Dai1
Daj0
Daj1
Daj2
Daj3
Dak0 Dak1
Dak2
Dak3 Dak4
Dak5
Dal0
Dal1
Dal2
Dal3
Dal4
Dal5
Dal6
Dal7
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column
access is allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The
input data on DQ at the interrupting READ cycle is "don't care". tWTR is referenced from the first
positive edge after the last data input.
Write Interrupted by Read (BL=8, CL=2.5)
/CLK
CLK
Command
A0-9,11
A10
BA0,1
WRITE
READ
Yi
Yj
0
0
00
00
DM
tWTR
QS
DQ
Dai0
Dai1
Qaj0
Qaj1
Qaj2
MITSUBISHI ELECTRIC
Qaj3
Qaj4
Qaj5
Qaj6
Qaj7
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[Write interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same or all bank. Random column
access is allowed. tWR is referenced from the first positive CLK edge after the last data input.
Write Interrupted by Precharge (BL=8, CL=2.5)
/CLK
CLK
Command
A0-9,11
A10
BA0,1
WRITE
PRE
Yi
0
00
00
tWR
DM
QS
DQ
Dai0
Dai1
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[Initialize and Mode Register sets]
Initialize and MRS
/CLK
CLK
CKE
Command
NOP
PRE
A0-9,11
A10
1
BA0,1
EMRS
MRS
Code
Code
Code
Code
10
0 0
PRE
AR
AR
MRS
ACT
Xa
1
Code
Xa
0 0
Xa
DQS
DQ
tMRD
tMRD
tRP
Extended Mode
Mode Register Set,
Register Set
Reset DLL
tRFC
tRFC
tMRD
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H)
command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh
256Mbits memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing
an auto refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum
tRFC . Any command must not be supplied to the device before tRFC from the REFA command.
Auto-Refresh
/CLK
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
tRFC
A0-11
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
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[SELF REFRESH]
Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the selfrefresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are
disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the
self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting
CKE for longer than tXSNR/tXSRD.
Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-11
X
Y
BA0,1
X
Y
tXSNR
tXSRD
Self Refresh Exit
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[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous inp ut except during the selfrefresh mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time
is NOT required in the condition of the stable CLK operation during the power down mode.
Power Down by CKE
/CLK
CLK
Standby Power Down
CKE
Command
PRE
NOP
NOP
Valid
tXPNR/tXPRD
Active Power Down
CKE
Command
ACT
NOP
NOP
Valid
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM
to write mask latency is 0.
DM Function(BL=8,CL=2)
/CLK
CLK
Command
READ
WRITE
DM
Don't Care
DQS
DQ
D0
D1
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
masked by DM=H
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Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,
but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal
injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii)
prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor
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MITSUBISHI ELECTRIC
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Revision History
Rev.
Date
1.0
Jul. ’01
Description
-New registration (Jul. ‘01)
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