Not recommended for new designs, replace with CAT25640 CAT25C64 64K-Bit SPI Serial CMOS EEPROM FEATURES DESCRIPTION ■ 10 MHz SPI compatible The CAT25C64 is a 64K-Bit SPI Serial CMOS EEPROM internally organized as 8Kx8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C64 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C64 is designed with software and hardware write protection features including Block write protection. The device is available in 8-pin DIP and SOIC packages. ■ 1.8 to 5.5 volt operation ■ Hardware and software protection ■ Low power CMOS technology ■ SPI modes (0,0 &1,1) ■ Commercial, industrial and automotive temperature ranges ■ 1,000,000 program/erase cycles ■ 100 year data tetention ■ Self-timed write cycle ■ 8-pin DIP and SOIC ■ 64-Byte page write buffer ■ Block write protection – Protect 1/4, 1/2 or all of EEPROM array PIN CONFIGURATION FUNCTIONAL SYMBOL VCC PDIP (P, L) SOIC (S, V) CS 1 8 VCC SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI CS CAT25C64 WP SI SO HOLD SCK PIN FUNCTIONS Pin Name Function SO Serial Data Output SCK Serial Clock WP Write Protect VCC +1.8V to +5.5V Power Supply VSS Ground CS Chip Select SI Serial Data Input HOLD Suspends Serial Input © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice VSS 1 Doc. No. 1112, Rev. B CAT25C64 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS(1) .................. –2.0V to +VCC +2.0V VCC with Respect to VSS ................................ –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (3) TDR(3) Parameter Min. Endurance Max. Units 1,000,000 Cycles/Byte 100 Years Data Retention D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Test Conditions Units ICC1 Power Supply Current (Operating Write) 10 VCC = 5V @ 10MHz SO = open; CS = Vss mA ICC2 Power Supply Current (Operating Read) 2 VCC = 5.0V FCLK = 10MHz mA ISB(4) Power Supply Current (Standby) 1 CS = VCC VIN = VSS or VCC µA ILI Input Leakage Current 2 ILO Output Leakage Current 3 VIL(5) Input Low Voltage -1 VCC x 0.3 V (5) Input High Voltage VCC x 0.7 VCC + 0.5 V VIH VOL1 Output Low Voltage VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage 0.4 VCC - 0.8 0.2 VCC-0.2 µA VOUT = 0V to VCC, CS = 0V 2.7V ≤ VCC < 5.5V IOL = 3.0mA IOH = -1.6mA 1.8V ≤ VCC < 2.7V IOL = 150µA IOH = -100µA µA V V V V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range. (5) VIL min and VIH max are reference values only and are not tested. Doc. No. 1112, Rev. B 2 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C64 PIN CAPACITANCE (1) Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted). Symbol Test Conditions Max. Conditions Units COUT Output Capacitance (SO) 8 VOUT=0V pF CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 VIN=0V pF A.C. CHARACTERISTICS CAT25C64-1.8 SYMBOL PARAMETER CAT25C64 VCC = 1.8V - 5.5V VCC = 2.5V - 5.5V Min. Min. Max. Max. VCC = 4.5V - 5.5V Min. Max. Test Conditions UNITS tSU Data Setup Time 50 50 20 ns tH Data Hold Time 50 50 20 ns tWH SCK High Time 250 125 40 ns tWL SCK Low Time 250 125 40 ns fSCK Clock Frequency DC tLZ HOLD to Output Low Z 50 tRI(1) Input Rise Time tFI(1) Input Fall Time tHD HOLD Setup Time 100 100 40 ns tCD HOLD Hold Time 100 100 40 ns tWC(3) Write Cycle Time 1 DC 10 MHz 50 50 ns 2 2 2 µs 2 2 2 µs 10 3 DC 10 250 CL = 50pF ms 40 (2) ns tV Output Valid from Clock Low tHO Output Hold Time tDIS Output Disable Time 250 250 75 ns tHZ HOLD to Output High Z 150 100 50 ns tCS CS High Time 500 250 100 ns tCSS CS Setup Time 500 250 100 ns tCSH CS Hold Time 500 250 100 ns 0 125 5 0 0 ns Power-Up Timing(4)(5) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) AC Test Conditions: Input Pulse Voltages: 0.3VCC to 0.7VCC Input rise and fall times: ≤10ns Input and output reference voltages: 0.5VCC Output load: current source IOL max/IOH max; CL=50pF (3) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. (4) This parameter is tested initially and after a design or process change that affects the parameter. (5) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 1112, Rev. B CAT25C64 FUNCTIONAL DESCRIPTION PIN DESCRIPTION The CAT25C64 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C64 to interface directly with many of today’s popular microcontrollers. The CAT25C64 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C64. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C64. During a read cycle, data is shifted out on the falling edge of the serial clock. After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize Figure 1. Sychronous Data Timing tCS VIH CS VIL tCSS tCSH VIH tWH SCK VIL tH tSU VIH tWL VALID IN SI VIL tRI tFI tV VOH SO tHO tDIS HI-Z HI-Z VOL Note: Dashed Line= mode (1, 1) — — — — INSTRUCTION SET Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory Doc. No. 1112, Rev. B 4 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C64 will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. the communication between the microcontroller and the 25C64. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. CS CS: Chip Select CS is the Chip select pin. CS low enables the CAT25C64 and CS high disables the CAT25C64. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway). The CAT25C64 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. HOLD HOLD: Hold The HOLD pin is used to pause transmission to the CAT25C64 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to Vcc or tied to Vcc through a resistor. Figure 9 illustrates hold timing sequence. WP WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low STATUS REGISTER 7 6 5 4 3 2 1 0 WPEN X X X BP1 BP0 WEL RDY BLOCK PROTECTION BITS Status Register Bits BP1 BP0 Array Address Protected Protection 0 0 None No Protection 0 1 1800-1FFF Quarter Array Protection 1 0 1000-1FFF Half Array Protection 1 1 0000-1FFF Full Array Protection WRITE PROTECT ENABLE OPERATION WPEN WP WEL Protected Blocks 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Unprotected Blocks Status Register Doc. No. 1112, Rev. B CAT25C64 The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register (including the block protect bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero. STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C64 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch . When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. DEVICE OPERATION Write Enable and Disable The CAT25C64 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to thedevice. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. The BP0 and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected the user may only read from the protected portion of the array. These bits are non-volatile. Figure 2. WREN Instruction Timing CS SCK SI 0 0 0 0 0 1 1 0 HIGH IMPEDANCE SO Note: Dashed Line= mode (1, 1) — — — — Figure 3. WRDI Instruction Timing CS SCK SI SO Note: Dashed Line= mode (1, 1) — — — — Doc. No. 1112, Rev. B 0 0 0 0 0 1 0 0 HIGH IMPEDANCE 6 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C64 READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C64, followed by the 16-bit address(the three Most Significant Bits are don’t care. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address (1FFFh) is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The readoperation is terminated by pulling the CS high. WRITE Sequence The CAT25C64 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25C64. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C64. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to thearray because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field Figure 4. Read Instruction Timing CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 2 1 SCK OPCODE SI 0 0 0 0 0 0 1 BYTE ADDRESS* 1 DATA OUT HIGH IMPEDANCE SO 7 6 5 4 3 0 MSB *Please check the instruction set table for address Note: Dashed Line= mode (1, 1) — — — — Figure 5. RDSR Instruction Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 11 7 6 5 4 12 13 14 2 1 SCK OPCODE SI 0 0 0 0 0 DATA OUT SO HIGH IMPEDANCE 0 MSB Note: Dashed Line= mode (1, 1) — — — — © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 7 Doc. No. 1112, Rev. B CAT25C64 to 64 bytes of data to the CAT25C64. After each byte of data is received, six lower order address bits are internally incremented by one; the high order bits of address will remain constant. The only restriction is that the 64 bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. The CAT25C64 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. location selected by the block protection level. Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address (the three Most Significant Bits are don’t care), and then the data to be written. Programming will start after the CS is brought high. Figure 6 illustrates byte write sequence. During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction. DESIGN CONSIDERATIONS The CAT25C64 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready Page Write The CAT25C64 features page write capability. After the first initial byte the host may continue to write up Figure 6. Write Instruction Timing CS 0 1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28 29 30 31 SCK OPCODE SI 0 0 0 0 0 DATA IN 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ADDRESS HIGH IMPEDANCE SO Note: Dashed Line= mode (1, 1) – – – – Figure 7. WRSR Instruction Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 1 7 6 5 4 12 13 14 15 2 1 0 SCK OPCODE SI 0 0 0 0 0 DATA IN 0 0 3 MSB SO HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) — — — — Doc. No. 1112, Rev. B 8 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C64 state and receive an instruction. After a successful byte/ page write or status register write the CAT25C64 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and program-ming is continued. On power up, SO is in a high impedance. When powering down, the supply should be taken down to 0V, so that the CAT25C64 will be reset when power is ramped back up. If this is not possible, then, following a brown-out episode, the CAT25C64 can be reset by refreshing the contents of the Status Register (See Application Note AN10). Figure 8. Page Write Instruction Timing CS 0 1 2 3 4 5 6 7 8 21 22 23 24-31 32-39 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1 SCK DATA IN OPCODE SI 0 0 0 0 0 0 1 0 ADDRESS Data Byte 1 Data Byte 2 Data Byte 3 Data Byte N 0 7..1 HIGH IMPEDANCE SO Note: Dashed Line = mode (1, 1) – – – – Figure 9. HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ HIGH IMPEDANCE SO tLZ Note: Dashed Line= mode (1, 1) — — — — Figure 10. WP Timing tWPS tWPH CS tCSH SCK WP WP Note: Dashed Line= mode (1, 1) — — — — © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. 1112, Rev. B CAT25C64 PACKAGE INFORMATION 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L) E1 E D A2 A A1 L e eB b2 b SYMBOL MIN A A1 A2 b b2 D D2 E E1 e eB L 0.120 0.015 0.115 0.014 0.045 0.355 0.300 0.300 0.240 0.115 NOM MAX 0.210 0.130 0.018 0.060 0.365 0.310 0.250 0.100 BSC 0.130 0.195 0.022 0.070 0.400 0.325 0.325 0.280 0.430 0.150 Notes: 1. Complies with JEDEC Standard MS001. 2. All dimensions are in inches. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 Doc. No. 1112, Rev. B 10 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C64 8-LEAD 150 MIL WIDE SOIC (S, V) E1 E D C A θ1 e A1 L b SYMBOL MIN A1 A2 b C D E E1 e f θ1 0.0040 0.0532 0.013 0.0075 0.1890 02284 0.149 NOM MAX 0.0098 0.0688 0.020 0.0098 0.1968 0.2440 0.1574 0.050 BSC 0.0099 0° 0.0196 8° Notes: 1. Complies with JEDEC specification MS-012 dimensions. 2. All linear dimensions in millimeters. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. 1112, Rev. B CAT25C64 TAPE AND REEL Direction of Feed Device Orientation SPROKET HOLE TOP COVER TAPE THICKNESS (t1) 0.10mm (0.004) MAX THICK DEVICE ORIENTATION EMBOSSED CARRIER PIN 1 EMBOSSMENT PIN 1 TDFN PIN 1 SOIC TSSOP (1) Reel Dimensions T 40mm (1.575) MIN. ACCESS HOLE AT SLOT LOCATION B* A D* C FULL RADIUS* N TAPE SLOT IN CORE FOR TAPE START. 2.5mm (0.098) MIN WIDTH 10mm (0.394) MIN DEPTH * DRIVE SPOKES OPTIONAL, IF USED ASTERISKED DIMENSIONS APPLY. G (MEASURED AT HUB) Embossed Carrier Dimensions TAPE SIZE 12MM A MAX QTY/REEL B MIN C D* MIN 330 (13.00) 3000 1.5 (0.059) 12.80 (0.504) 13.20 (0.5200) N MIN 20.2 50 (0.795) (1.969) G T MAX 12.4 (0.488) 14.4 (0.558) _18.4_ (0.724) Component/Tape Size Cross-Reference Component Package Type Tape Size (W) Part Pitch (P) 8L SOIC S, V 12mm 8mm Notes: (1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses. Doc. No. 1112, Rev. B 12 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C64 Embossed Carrier Dimensions (12 Pape Only) K D 10 PITCHES CUMULATIVE TOLERANCE ON TAPE 0.2mm( 0.008) P0 T P2 TOP COVER TAPE E (2) A0 F W (2) K0 B1 B0 P CENTER LINES OF CAVITY EMBOSSMENT FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC ABOUT B0 D1 FOR COMPONENTS 2.0mm X 1.2mm AND LARGER USER DIRECTION OF FEED Embossed Tape—Constant Dimensions(1) Tape Sizes D E P0 T Max. D1 Min. 12mm 1.5 (0.059) 1.6 (0.063) 1.65 (0.065) 1.85 (0.073) 3.9 (0.153) 4.1 (0.161) 400 (0.016) 1.5 (0.059) A0 B0 K0(2) Embossed Tape—Variable Dimensions(1) Tape Sizes B1 Max. F K Max. P2 R Min. W P 12mm 8.2 (0.0323) 5.45 (0.0215) 5.55 (0.0219) 4.5 (0.177) 1.95 (0.077) 2.05 (0.081) 30 (1.181) 11.7 (0.460) 12.3 (0.484) 7.9 (0.275) 8.1 (0.355) Note: (1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses. (2) A0 B0 K0 are determined by component size. The clearance between the component and the cavity must be within 0.05 (0.002) min. to 0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035) max. for 16mm tape, and 0.05 (0.002) min. to 1.00 (0.039) max. for 24mm tape and larger. The component cannot rotate more than 20° within the determined cavity, see Component Rotation. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. 1112, Rev. B CAT25C64 ORDERING INFORMATION Prefix Device # CAT Optional Company ID 25C64 Product Number Suffix S -1.8 – GT3 I Temperature Range Blank = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) A = Automotive (-40°C to +105°C) E = Extended (-40°C to +125°C) Package P: PDIP S: SOIC L: PDIP (Lead-free, Halogen-free) V: SOIC, JEDEC (Lead-free, Halogen-free) Operating Voltage Blank = 2.5 to 5.5V 1.8 = 1.8 to 5.5V Lead Finish/Tape & Reel G: NiPdAu Lead Plating T: Tape & Reel 3: 3000/Reel Notes: (1) The device used in the above example is a 25C64SI-1.8GT3 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel) Doc. No. 1112, Rev. B 14 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C64 PACKAGE MARKING 8-Lead PDIP 8-Lead SOIC VV 25C64LI YYWWC VV 25C64VI YYWWC CSI = Catalyst Semiconductor, Inc. VV = Voltage Range 1.8V - 5.5V = 18 2.5V - 5.5V = Blank 25C64L = Device Code I = Temperature Range YY = Production Year WW = Production Week C = Product Revision © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CSI = Catalyst Semiconductor, Inc. VV = Voltage Range 1.8V - 5.5V = 18 2.5V - 5.5V = Blank 25C64V = Device Code I = Temperature Range YY = Production Year WW = Production Week C = Product Revision 15 Doc. No. 1112, Rev. B REVISION HISTORY Date 12/22/2005 03/21/06 Rev. A B Reason Initial Issue Update D.C. Operating Characteristics Update A.C. Characteristics Update Pin Description Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ MiniPot™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 1112 B 03/21/06