AD ADA4410-6 Integrated video filter with selectable cutoff Datasheet

Integrated Video Filter with Selectable Cutoff
Frequencies for RGB, HD/SD Y, C, and CV
ADA4410-6
FEATURES
Sixth-order filters with selectable cutoff frequencies
36 MHz, 18 MHz, 9 MHz
Many video standards supported
RGB/YPbPr/YUV/SD/YC/CV
Ideal for resolutions up to 1080i
−1 dB bandwidth of 30 MHz for HD
2:1 multiplexers on all inputs
Selectable gain: ×2 or ×4
DC output offset adjust: ±0.5 V, input referred
Excellent video specifications
NTSC differential gain: 0.11%
NTSC differential phase: 0.25°
Low input bias current: 6.6 μA
Wide supply range: +4.5 V to ±5 V
Rail-to-rail output
Typical output swing of 4.5 V p-p on single 5 V supply
Disable feature
FUNCTIONAL BLOCK DIAGRAM
Y1/G1 IN
Y2/G2 IN
Pb1/B1 IN
Pb2/B2 IN
Pr1/R1 IN
Pr2/R2 IN
36MHz,
18MHz,
9MHz
×2
×4
Y/G OUT
36MHz,
18MHz,
9MHz
×2
×4
Pb/B OUT
36MHz,
18MHz,
9MHz
×2
×4
Pr/R OUT
×2
×4
Y OUT
×2
CV OUT
×2
×4
C OUT
HD INPUT SELECT
DC
OFFSET
LEVEL1
ADA4410-6
LEVEL2
CUTOFF SELECT
2
GAIN SELECT
Y1 IN
APPLICATIONS
Y2 IN
9MHz
Set-top boxes
DVD players and recorders
HDTVs
C1 IN
The ADA4410-6 is a comprehensive integrated filtering solution
that is carefully designed to give designers the flexibility to
easily filter and drive many types of video signals, including
high definition video. In the RGB/component channels, the
cutoff frequencies of the sixth-order filters can be selected by
two logic pins to obtain four filter combinations that are tuned
for RGB, high definition, and standard definition video. Cutoff
frequencies range from 9 MHz to 36 MHz.
The ADA4410-6 also provides filtering for the legacy standard
S-video and composite video signals. With a differential gain of
0.11% and a differential phase of 0.25°, the ADA4410-6 is an
excellent choice for any composite video (CV) application.
The ADA4410-6 offers gain and output offset voltage
adjustments. With a single logic pin, the gain of the part can be
selected to be ×2 or ×4. Output offset voltage is continuously
adjustable over an input-referred range of ±500 mV by applying
a differential voltage to an independent offset control input.
C2 IN
9MHz
05265-001
GENERAL DESCRIPTION
SD INPUT SELECT
DISABLE
Figure 1.
The ADA4410-6 offers 2:1 multiplexers on its inputs that can be
used in applications where multiple sources of video exist.
The ADA4410-6 can operate on a single +5 V supply as well as
±5 V supplies. Single-supply operation is ideal for applications
where power consumption is critical. The disable feature allows
for further power conservation by reducing the supply current
to typically 15 μA when a particular device is not in use.
Dual-supply operation is best for applications where the
negative-going excursions of the signal must swing at or below
ground while maintaining excellent video performance. The
output buffers have the ability to drive two 75 Ω doubly
terminated cables that are either dc- or ac-coupled.
The ADA4410-6 is available in a 32-lead LFCSP and operates in
the extended industrial temperature range of −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2006 Analog Devices, Inc. All rights reserved.
ADA4410-6
TABLE OF CONTENTS
Features .............................................................................................. 1
Overview ..................................................................................... 13
Applications....................................................................................... 1
Multiplexer Select Inputs........................................................... 13
General Description ......................................................................... 1
Throughput Gain........................................................................ 13
Functional Block Diagram .............................................................. 1
Disable ......................................................................................... 13
Revision History ............................................................................... 2
Cutoff Frequency Selection....................................................... 13
Specifications..................................................................................... 3
Output DC Offset Control ........................................................ 13
Absolute Maximum Ratings............................................................ 7
Input and Output Coupling ...................................................... 14
Thermal Resistance ...................................................................... 7
Printed Circuit Board Layout ................................................... 15
ESD Caution.................................................................................. 7
Video Encoder Reconstruction Filter...................................... 15
Pin Configuration and Function Descriptions............................. 8
Outline Dimensions ....................................................................... 16
Typical Performance Characteristics ............................................. 9
Ordering Guide .......................................................................... 16
Theory of Operation ...................................................................... 12
Applications..................................................................................... 13
REVISION HISTORY
3/06—Rev. A to Rev. B
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Figure 4 through Figure 9 ........................................... 9
Changes to Figure 10...................................................................... 10
Changes to Ordering Guide .......................................................... 16
Updated Outline Dimensions ....................................................... 16
8/05—Rev. 0 to Rev. A
Changes to Features, General Description, and Figure 1.............1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Figure 4...........................................................................9
Changes to Theory of Operation Section.................................... 12
Changes to Overview, Throughput Gain, and Output DC
Offset Control Sections.................................................................. 13
Renamed Gain Select Section Throughput Gain Section ........ 13
Added Composite Video Path Gain Section............................... 13
Changes to Table 6 and Table 7 .................................................... 13
Changes to Figure 24 Caption ...................................................... 14
Changes to Input and Output Coupling Section........................ 14
Added Figure 25 and Figure 26; Renumbered Sequentially ..... 14
Changes to Figure 27...................................................................... 15
1/05—Revision 0: Initial Version
Rev. B | Page 2 of 16
ADA4410-6
SPECIFICATIONS
VS = 5 V, @ TA = 25°C, VO = 1.4 V p-p, G = ×2, RL = 150 Ω, unless otherwise noted.
Table 1.
Parameter
OVERALL PERFORMANCE
Offset Error
Max Voltage Across LEVEL1 and LEVEL2 Inputs
Input Voltage Range, All Inputs
Output Voltage Swing, All Outputs
Linear Output Current per Channel
Integrated Voltage Noise, Referred to Input
Filter Input Bias Current
Total Harmonic Distortion at 1 MHz
RGB/YPbPr CHANNEL DYNAMIC PERFORMANCE
−1 dB Bandwidth
−3 dB Bandwidth
Out-of-Band Rejection
Crosstalk
Input Mux Isolation
Propagation Delay
Group Delay Variation
Y/C SD CHANNEL DYNAMIC PERFORMANCE
−1 dB Bandwidth
−3 dB Bandwidth
Out-of-Band Rejection
Propagation Delay
Group Delay Variation
Crosstalk
Input Mux Isolation
Y/C, CV OUTPUT VIDEO PERFORMANCE
Differential Gain
Differential Phase
CONTROL INPUT PERFORMANCE
Input Logic 0 Voltage
Input Logic 1 Voltage
Input Bias Current
DISABLE PERFORMANCE
DISABLE Assert Voltage
DISABLE Assert Time
DISABLE Deassert Time
DISABLE Input Bias Current
Input-to-Output Isolation—Disabled
Test Conditions/Comments
Min
Input referred, all channels except CV
Input referred, CV
Positive swing
Negative swing
VS− − 0.1
VS+ − 0.35
Typ
Max
Unit
10
12
±500
32
40
mV
mV
mV
V
V
V
mA
μVrms
μA
%
VS+ − 2.0
All channels except CV
All channels
FC = 36 MHz, FC = 18 MHz/FC = 9 MHz
VS+ − 0.25
VS− + 0.10
30
500
6.6
0.01/0.07
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
f = 75 MHz
f = 5 MHz, FC = 36 MHz
f = 1 MHz, RSOURCE = 300 Ω
f = 16 MHz, FC = 36 MHz
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
31
15
8
36
18
9
−42
−68
86
20.5
9.5
16.5
29.5
MHz
MHz
MHz
MHz
MHz
MHz
dB
dB
dB
ns
ns
ns
ns
f = 1 MHz
f = 1 MHz, RSOURCE = 75 Ω
7.5
9
−56
72
30
−72
77
MHz
MHz
dB
ns
ns
dB
dB
NTSC
NTSC
0.09
0.37
%
Degrees
34
16
8
−33
8
f = 27 MHz
f = 1 MHz
All inputs except DISABLE
All inputs except DISABLE
All inputs except DISABLE
15
0.8
2.0
7
VS+ − 0.5
100
130
12
100
Rev. B | Page 3 of 16
VS− + 0.3
15
20
V
V
μA
V
ns
ns
μA
dB
ADA4410-6
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current—Disabled
PSRR, Positive Supply
PSRR, Negative Supply
Test Conditions/Comments
Min
Typ
4.5
All channels except CV
CV channel
All channels except CV
CV channel
Rev. B | Page 4 of 16
62
59
55
52
82
15
72
66
62
56
Max
Unit
12
88
150
V
mA
μA
dB
dB
dB
dB
ADA4410-6
VS = ±5 V, @ TA = 25°C, VO = 1.4 V p-p, G = ×2, RL = 150 Ω, unless otherwise noted.
Table 2.
Parameter
OVERALL PERFORMANCE
Offset Error
Max Voltage Across LEVEL1 and LEVEL2 Inputs
Input Voltage Range, All Inputs
Output Voltage Swing, All Outputs
Linear Output Current per Channel
Integrated Voltage Noise, Referred to Input
Filter Input Bias Current
Total Harmonic Distortion at 1 MHz
RGB/YPbPr CHANNEL DYNAMIC PERFORMANCE
−1 dB Bandwidth
−3 dB Bandwidth
Out-of-Band Rejection
Crosstalk
Input Mux Isolation
Propagation Delay
Group Delay Variation
Y/C SD CHANNEL DYNAMIC PERFORMANCE
−1 dB Bandwidth
−3 dB Bandwidth
Out-of-Band Rejection
Propagation Delay
Group Delay Variation
Crosstalk
Input Mux Isolation
Y/C, CV OUTPUT VIDEO PERFORMANCE
Differential Gain
Differential Phase
CONTROL INPUT PERFORMANCE
Input Logic 0 Voltage
Input Logic 1 Voltage
Input Bias Current
DISABLE PERFORMANCE
DISABLE Assert Voltage
DISABLE Assert Time
DISABLE Deassert Time
DISABLE Input Bias Current
Input-to-Output Isolation—Disabled
Test Conditions/Comments
Min
Input referred, all channels except CV
Input referred, CV
Positive swing
Negative swing
VS− − 0.1
VS+ − 0.35
Typ
Max
Unit
14
15
±500
33.5
42.5
mV
mV
mV
V
V
V
mA
μVrms
μA
%
VS+ − 2.0
All channels except CV
All channels
FC = 36 MHz, FC = 18 MHz/FC = 9 MHz
VS+ − 0.25
VS− + 0.3
30
500
6.3
0.01/0.07
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
f = 75 MHz
f = 5 MHz, FC = 36 MHz
f = 1 MHz, RSOURCE = 300 Ω
f = 5 MHz, FC = 36 MHz
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
29
15
8
35.5
18
9.5
−41.5
−68
86
21
7.5
14
26
MHz
MHz
MHz
MHz
MHz
MHz
dB
dB
dB
ns
ns
ns
ns
f = 1 MHz
f = 1 MHz, RSOURCE = 75 Ω
7.5
9
−57
64
26
−72
77
MHz
MHz
dB
ns
ns
dB
dB
NTSC
NTSC
0.11
0.25
%
Degrees
33.0
16.5
8
−33
8
f = 27 MHz
f = 1 MHz
All inputs except DISABLE
All inputs except DISABLE
All inputs except DISABLE
15
0.8
2.0
7
VS+ − 0.5
75
125
35
100
Rev. B | Page 5 of 16
VS− + 0.5
15
45
V
V
μA
V
ns
ns
μA
dB
ADA4410-6
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current—Disabled
PSRR, Positive Supply
PSRR, Negative Supply
Test Conditions/Comments
Min
Typ
4.5
All channels except CV
CV channel
All channels except CV
CV channel
Rev. B | Page 6 of 16
62
59
55
52
86
15
72
66
62
56
Max
Unit
12
93
150
V
mA
μA
dB
dB
dB
dB
ADA4410-6
ABSOLUTE MAXIMUM RATINGS
Rating
12 V
See Figure 2
–65°C to +125°C
–40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane.
Table 4. Thermal Resistance
Package Type
5 mm × 5 mm, 32-Lead LFCSP
θJA
43
θJC
5.1
Unit
°C/W
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to load drive
depends upon the particular application. For each output, the
power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipations due to each individual load. RMS
voltages and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through-holes, ground, and power planes,
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θJA.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 32-lead LFCSP
(43°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θJA values are approximations.
4.5
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4410-6
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4410-6. Exceeding a
junction temperature of 150°C for an extended time can result
in changes in the silicon devices, potentially causing failure.
4.0
3.5
LFCSP
3.0
2.5
2.0
1.5
1.0
–40
05265-002
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
MAXIMUM POWER DISSIPATION (W)
Table 3.
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 16
ADA4410-6
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32
1
25
24
PIN 1
INDICATOR
ADA4410-6
8
9
17
16
05265-003
(Not to Scale)
Figure 3. 32-Lead LFCSP Pin Configuration, Top View
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Mnemonic
Pb1/B1_HD
GND
Pr1/R1_HD
F_SEL_A
F_SEL_B
Y2/G2_HD
GND
Pb2/B2_HD
GND
Pr2/R2_HD
MUX_SD
Y1_SD
Y2_SD
C1_SD
C2_SD
VCC
VEE
CV_OUT
C_SD_OUT
Y_SD_OUT
G_SEL
Pr/R_HD_OUT
Pb/B_HD_OUT
Y/G_HD_OUT
VEE
VCC
DISABLE
LEVEL2
LEVEL1
MUX_HD
Y1/G1_HD
GND
Description
Channel 1 Pb/B High Definition Input
Signal Ground Reference
Channel 1 Pr/R High Definition Input
Filter Cutoff Select Input A
Filter Cutoff Select Input B
Channel 2 Y/G High Definition Input
Signal Ground Reference
Channel 2 Pb/B High Definition Input
Signal Ground Reference
Channel 2 Pr/R High Definition Input
Standard Definition Input Mux Select Line
Channel 1 Y Standard Definition Input
Channel 2 Y Standard Definition Input
Channel 1 C Standard Definition Input
Channel 2 C Standard Definition Input
Positive Power Supply
Negative Power Supply
Composite Video Output
C Standard Definition Output
Y Standard Definition Output
Gain Select
Pr/R High Definition Output
Pb/B High Definition Output
Y/G High Definition Output
Negative Power Supply
Positive Power Supply
Disable/Power Down/Logic Reference
DC Level Adjust Pin 2
DC Level Adjust Pin 1
High Definition Input Mux Select Line
Channel 1 Y/G High Definition Input
Signal Ground Reference
Rev. B | Page 8 of 16
ADA4410-6
TYPICAL PERFORMANCE CHARACTERISTICS
FC = 9MHz
FC = 36MHz
BLACK LINES: VS = +5V
GRAY LINES: VS = ±5V
1
10
FREQUENCY (MHz)
100
Figure 7. Frequency Response vs. Power Supply and Cutoff Frequency (G = ×4)
6.5
12.5
6.0
12.0
5.5
11.5
FC = 9MHz
5.0
FC = 36MHz
GAIN (dB)
4.5
FC = 18MHz
4.0
FC = 9MHz
10.5
FC = 18MHz
1
10
FREQUENCY (MHz)
9.0
100
BLACK LINES: VS = +5V
GRAY LINES: VS = ±5V
1
10
FREQUENCY (MHz)
100
GAIN (dB)
Figure 8. Frequency Response Flatness vs. Cutoff Frequency (G = ×4)
05265-053
9
6
3
0
FC = 18MHz
–3
–6
–9
–12
FC = 9MHz
–15
FC = 36MHz
–18
–21
–24
–27
–30
–33
–36
–39
–42 BLACK LINES: V = 2V p-p
O
–45 GRAY LINES: V = 0.1V p-p
O
–48
1
10
100
FREQUENCY (MHz)
05265-007
9.5
05265-005
BLACK LINES: VS = +5V
GRAY LINES: VS = ±5V
Figure 5. Frequency Response Flatness vs. Cutoff Frequency (G = ×2)
GAIN (dB)
11.0
10.0
3.5
3.0
FC = 36MHz
Figure 6. Frequency Response vs. Cutoff Frequency and Output Amplitude
Rev. B | Page 9 of 16
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
FC = 9MHz
FC = 36MHz
FC = 18MHz
RED LINES: +85°C
GREEN LINES: +25°C
BLUE LINES: –40°C
1
10
FREQUENCY (MHz)
05265-017
GAIN (dB)
Figure 4. Frequency Response vs. Power Supply and Cutoff Frequency (G = ×2)
15
12
9
6
FC = 18MHz
3
0
–3
–6
FC = 9MHz
FC = 36MHz
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39 BLACK LINES: VS = +5V
–42 GRAY LINES: VS = ±5V
–45
1
10
100
FREQUENCY (MHz)
05265-006
FC = 18MHz
GAIN (dB)
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
05265-004
GAIN (dB)
Unless otherwise noted, G = ×2, RL = 150 Ω, VO = 1.4 V p-p, VS = 5 V, TA = 25°C.
100
Figure 9. Frequency Response vs. Temperature and Cutoff Frequency
ADA4410-6
–60
100
BLACK LINES: VS = +5V
GRAY LINES: VS = ±5V
90
–70
80
FC = 9MHz
–75
70
NOISE (dB)
60
50
FC = 18MHz
40
–85
–90
–95
–100
30
FC = 36MHz
10
FREQUENCY (MHz)
–110
0
100
1
Figure 10. Group Delay vs. Frequency, Power Supply, and Cutoff Frequency
CROSSTALK REFERRED TO INPUT (dB)
FC = 36MHz
FC = 9MHz
–60
–70
–80
–90
–100
–110
0.1
RSOURCE = 300Ω
Y1, Pb1 SOURCE CHANNELS
Pr1 RECEPTOR CHANNEL
1
10
FREQUENCY (MHz)
05265-018
CROSSTALK REFERRED TO INPUT (dB)
–40
–50
RSOURCE = 300Ω
MUX INPUT 2 SELECTED
Y1, C1 SOURCE CHANNELS
Y2 RECEPTOR CHANNEL
–60
–70
–80
–90
C2 SOURCE CHANNEL
Y2 RECEPTOR CHANNEL
–100
–110
0.1
100
1
10
FREQUENCY (MHz)
100
Figure 14. SD Channel Crosstalk vs. Frequency
–40
–40
MUX ISOLATION REFERRED TO INPUT (dB)
RSOURCE = 300Ω
UNSELECTED MUX IS DRIVEN
FC = 36MHz
–60
–70
–80
FC = 18MHz
–90
FC = 9MHz
–100
–110
0.1
05265-013
MUX ISOLATION REFERRED TO INPUT (dB)
5
–50
Figure 11. HD Channel Crosstalk vs. Frequency and Cutoff Frequency
–50
4
Figure 13. CV Noise Spectrum
–40
FC = 18MHz
2
3
FREQUENCY (MHz)
05265-019
1
05265-020
–105
05265-008
20
10
–80
1
10
FREQUENCY (MHz)
UNSELECTED MUX IS DRIVEN
–50
–60
RSOURCE = 300Ω
–70
–80
RSOURCE = 75Ω
–90
–100
–110
0.1
100
Figure 12. HD Mux Isolation vs. Frequency and Cutoff Frequency
05265-014
GROUP DELAY (ns)
BANDWIDTH 100kHz TO 4.2MHz
NTC-7 WEIGHT
–65
1
10
FREQUENCY (MHz)
100
Figure 15. SD Mux Isolation vs. Frequency and Source Resistance
Rev. B | Page 10 of 16
ADA4410-6
–5
–5
–15
–25
FC = 18MHz
–35
FC = 36MHz
–45
–55
–65
–75
0.1
1
10
FREQUENCY (MHz)
FC = 36MHz
–55
–65
1
10
FREQUENCY (MHz)
100
Figure 19. Negative Supply PSRR vs. Frequency and Cutoff Frequency
3.5
3.3
3.3
3.1
G=4
VO = 1.4V p-p
3.1
FC = 36MHz
FC = 18MHz
OUTPUT VOLTAGE (V)
2.7
FC = 9MHz
2.5
2.3
2.1
FC = 18MHz
FC = 36MHz
2.7
FC = 9MHz
2.5
2.3
2.1
1.7
200ns/DIV
1.5
1.7
200ns/DIV
1.5
Figure 17. Transient Response vs. Cutoff Frequency (G = ×2)
05265-011
1.9
05265-009
1.9
2.9
Figure 20. Transient Response vs. Cutoff Frequency (G = ×4)
3.5
6
2 × INPUT VOLTAGE
3.3
5
3.1
FC = 18MHz
1% (57ns)
OUTPUT VOLTAGE (V)
2.9
2 × INPUT
2.7
ERROR = 2 × INPUT – OUTPUT (0.5%/DIV)
2.5
2.3
2.1
0.5% (65ns)
4
FC = 36MHz
3
FC = 9MHz
2
1
OUTPUT
50ns/DIV
1.5
0
05265-010
1.7
200ns/DIV
–1
t=0
Figure 21. Overdrive Recovery vs. Cutoff Frequency
Figure 18. Settling Time
NETWORK
ANALYZER Tx
RL = 150Ω
50Ω
DUT
50Ω
NETWORK
ANALYZER Rx
118Ω
86.6Ω
50Ω
MINIMUM-LOSS MATCHING NETWORK LOSS CALIBRATED OUT
Figure 22. Basic Test Circuit for Swept Frequency Measurements
Rev. B | Page 11 of 16
05265-012
1.9
05265-051
OUTPUT VOLTAGE (V)
–45
3.5
2.9
FC = 18MHz
–35
–75
0.1
100
Figure 16. Positive Supply PSRR vs. Frequency and Cutoff Frequency
OUTPUT VOLTAGE (V)
FC = 9MHz
–25
05265-016
PSRR REFERRED TO INPUT (dB)
FC = 9MHz
05265-015
PSRR REFERRED TO INPUT (dB)
–15
ADA4410-6
THEORY OF OPERATION
The ADA4410-6 is an integrated video filtering and driving
solution that offers variable bandwidth to meet the needs of
several different video formats. There are a total of five filter
sections, three for component video and two for Y/C and
composite video. The component video filters have switchable
bandwidths for standard definition interlaced, progressive, and
high definition systems. The Y/C channels have fixed 9 MHz,
3 dB cutoff frequencies and include a summing circuit that
feeds an additional buffer for a composite video output. Each
filter section has a sixth-order Butterworth response that
includes group delay optimization. The group delay variation
from 100 kHz to 36 MHz in the 36 MHz section is 8 ns, which
produces a fast settling pulse response.
The ADA4410-6 is designed to operate in many different video
environments. The supply range is 5 V to 12 V, single supply or
dual supply, and requires a relatively low quiescent current of
15 mA per channel. In single-supply applications, the PSRR is
greater than 70 dB, providing excellent rejection in systems with
supplies that are noisy or under-regulated. In applications
where power consumption is critical, the part can be powered
down to draw 15 μA by pulling the DISABLE pin to the most
positive rail. The ADA4410-6 is also well suited for high
encoding frequency applications because it maintains a stopband attenuation of 50 dB beyond 200 MHz.
The ADA4410-6 is intended to take dc-coupled inputs from an
encoder or other ground-referenced video signals. The ADA4410-6
input is high impedance. No minimum or maximum input
termination is required, though input terminations above 1 kΩ
can degrade crosstalk performance at high frequencies. No
clamping is provided internally. For applications where dc
restoration is required, dual supplies work best. Using a
termination resistance of less than a few hundred ohms to
ground on the inputs and suitably adjusting the level shift
circuitry provides precise placement of the output voltage.
For single-supply applications (VS− = GND), the input voltage
range extends from 100 mV below ground to within 2.0 V of
the most positive supply. Each filter section has a 2:1 input
multiplexer that includes level-shifting circuitry. The levelshifting circuitry adds a dc component to ground-referenced
input signals so that they can be reproduced accurately without
the output buffers hitting the negative rail. Because the filters
have negative rail input and rail-to-rail output, dc level shifting
is generally not necessary, unless accuracy greater than that of
the saturated output of the driver is required at the most negative
edge. This varies with load but is typically 100 mV in a dccoupled, single-supply application. If ac coupling is used, the
saturated output level is higher because the drivers have to
sink more current on the low side. If dual supplies are used
(VS− < GND), no level shifting is required. In dual-supply
applications, the level shifting circuitry can be used to take a
ground-referenced signal and put the blanking level at ground
while the sync level is below ground.
The output drivers on the ADA4410-6 have rail-to-rail output
capabilities. They provide either 6 dB or 12 dB of gain with
respect to the ground pins. Gain is controlled by the external
gain select pin. Each output is capable of driving two ac- or dccoupled 75 Ω source-terminated loads. If a large dc output level
is required while driving two loads, ac coupling should be used
to limit the power dissipation.
Input mux isolation is primarily a function of the source
resistance driving into the ADA4410-6. Higher resistances
result in lower isolation over frequency, while a low source
resistance, such as 75 Ω, has the best isolation performance. In
the SD channels, the isolation variation is most pronounced due
to the stray capacitance that exists between the adjacent input
pins. The HD input pins are not adjacent; therefore, this effect is
less pronounced on the HD channels. See Figure 15 for a
performance comparison of the different source resistances
feeding the SD inputs.
Rev. B | Page 12 of 16
ADA4410-6
APPLICATIONS
OVERVIEW
DISABLE
With its high impedance multiplexed inputs and high output
drive, the ADA4410-6 is ideally suited to video reconstruction
and antialias filtering applications. The high impedance inputs
give designers flexibility with regard to how the input signals
are terminated. Devices with DAC current source outputs that
feed the ADA4410-6 can be loaded in whatever resistance
provides the best performance, and devices with voltage outputs
can be optimally terminated as well. The ADA4410-6 outputs
can each drive up to two source-terminated 75 Ω loads and can
therefore directly drive the outputs from set-top boxes, DVD
players, and the like without the need for a separate output buffer.
The ADA4410-6 includes a disable feature that can be used to
save power when a particular device is not in use. As indicated
in the Overview section, the disable feature is asserted by pulling
the DISABLE pin to the positive supply. Table 6 summarizes the
disable feature operation. The DISABLE pin also functions as a
reference level for the logic inputs and, therefore, must be
connected to ground when the device is not disabled.
Binary control inputs are provided to select cutoff frequency,
throughput gain, and input signal. These inputs are compatible
with 3 V and 5 V TTL and CMOS logic levels, referenced to
GND. The disable feature is asserted by pulling the DISABLE
pin to the positive supply.
The LEVEL1 and LEVEL2 inputs comprise a differential input
that controls the dc level at the output pins.
MULTIPLEXER SELECT INPUTS
Selection between the two multiplexer inputs is controlled by
the logic signals applied to the MUX_SD and MUX_HD inputs.
The MUX_SD input controls the standard definition (SD)
inputs, and the MUX_HD input controls the high definition
(HD) inputs. Table 6 summarizes the multiplexer operation.
THROUGHPUT GAIN
The throughput gain of the ADA4410-6 signal paths can be ×2
or ×4. Gain selection is controlled by the logic signal applied to
the G_SEL pin. Table 6 summarizes how the gain is selected.
Composite Video Path Gain
The composite video signal is produced by passively summing
the C and V outputs (see Figure 1), which have been amplified
by their respective gain stages. Each signal experiences a 6 dB
loss as it passes through the passive summer and is subsequently
amplified by 6 dB in the fixed ×2 stage following the summer.
The net signal gain through the composite video path is therefore
0 dB, and the resulting composite signal present at the ADA4410-6
output is the sum of Y and C with unity gain. The offset voltage
at the composite video output is twice that of the offset on the Y
or C outputs because the offsets on the Y and C outputs are the
same and appear as a common-mode input to the summer. The
voltage between the summing resistors due to the offset voltages
is therefore equal to the output offset voltage on the Y and C
outputs and appears at the composite video output with a gain
of 2 after passing through the fixed ×2 gain stage.
Table 6. Logic Pin Function Description
DISABLE
VS+ =
Disabled
GND =
Enabled
MUX_HD
1 = HD Channel 1
Selected
0 = HD Channel 2
Selected
MUX_SD
1 = SD Channel 1
Selected
0 = SD Channel 2
Selected
G_SEL
1 = ×4
Gain
0 = ×2
Gain
CUTOFF FREQUENCY SELECTION
Four combinations of cutoff frequencies are provided for the
HD video signals. The cutoff frequencies were selected to
correspond with the most commonly deployed HD scanning
systems. Selection between the cutoff frequency combinations is
controlled by the logic signals applied to the F_SEL_A and
F_SEL_B inputs. Table 7 summarizes cutoff frequency selection.
Table 7. Filter Cutoff Frequency Selection
F_SEL_A
0
0
1
1
F_SEL_B
0
1
0
1
Y/G Cutoff
36 MHz
36 MHz
18 MHz
9 MHz
Pb/B Cutoff
36 MHz
18 MHz
18 MHz
9 MHz
Pr/R Cutoff
36 MHz
18 MHz
18 MHz
9 MHz
OUTPUT DC OFFSET CONTROL
The LEVEL1 and LEVEL2 inputs work as a differential inputreferred output offset control. In other words, the output offset
voltage of a given channel (with the exception of the CV
channel) is equal to the difference in voltage between the
LEVEL1 and LEVEL2 inputs multiplied by the overall filter
gain. This relationship is expressed in Equation 1.
VOS (OUT) = (LEVEL1 − LEVEL2)(G)
(1)
where:
LEVEL1 and LEVEL2 are the voltages applied to the respective
inputs.
G is throughput gain.
For example, with the G_SEL input set for ×2 gain, setting
LEVEL1 to 300 mV and LEVEL2 to 0 V shifts the offset voltages
at the ADA4410-6 outputs to 600 mV. This particular setting
can be used in most single-supply applications to keep the
output swings safely above the negative supply rail.
Rev. B | Page 13 of 16
ADA4410-6
The maximum differential voltage that can be applied across the
LEVEL1 and LEVEL2 inputs is ±500 mV. From a single-ended
standpoint, the LEVEL1 and LEVEL2 inputs have the same
range as the filter inputs. See the Specifications tables for the
limits. The LEVEL1 and LEVEL2 inputs must each be bypassed
to GND with a 0.1 μF ceramic capacitor.
In single-supply applications, a positive output offset must be
applied to keep the negative-most excursions of the output
signals above the specified minimum output swing limit.
Figure 23 and Figure 24 illustrate several ways to use the
LEVEL1 and LEVEL2 inputs. Figure 23 shows an example of
how to generate fully adjustable LEVEL1 and LEVEL2 voltages
from ±5 V and single +5 V supplies. These circuits show a
general case, but a more practical approach is to fix one voltage
and vary the other. Figure 24 illustrates an effective way to
produce a 600 mV output offset voltage in a single-supply
application. Although the LEVEL2 input could simply be
connected to GND, Figure 24 includes bypassed resistive
voltage dividers for each input so that the input levels can be
changed, if necessary. Additionally, many in-circuit testers
require that I/O signals not be tied directly to the supplies or
GND. DNP indicates do not populate.
+5V
10kΩ
634Ω
0Ω
DNP
Figure 24. Flexible Circuits to Set the LEVEL1 and LEVEL2 Inputs to Obtain
a 600 mV Output Offset on a Single Supply (G = ×2)
INPUT AND OUTPUT COUPLING
Inputs to the ADA4410-6 are normally dc-coupled. Ac coupling
the inputs is not recommended; however, if ac coupling is
necessary, suitable circuitry must be provided following the ac
coupling element to provide proper dc level and bias currents at
the ADA4410-6 input stages.
The ADA4410-6 outputs can be either ac- or dc-coupled. As
discussed in the Output DC Offset Control section, the CV
output offset is different from the other outputs, and the CV
output is generally ac-coupled.
When driving single ac-coupled loads in standard 75 Ω video
distribution systems, 220 μF coupling capacitors are recommended
for use on all but the chrominance signal output. Because the
chrominance signal is a narrow-band modulated carrier, it has
no low frequency content and can therefore be coupled with a
0.1 μF capacitor.
There are two ac coupling options when driving two loads from
one output. One is to simply use the same value capacitor on
the second load, while the other is to use a common coupling
capacitor that is at least twice the value used for the single load
(see Figure 25 and Figure 26).
75Ω
220µF
75Ω
CABLE
220µF
75Ω
CABLE
75Ω
9.53kΩ
LEVEL1
0.1µF
1kΩ
9.53kΩ
–5V
LEVEL2
75Ω
0.1µF
75Ω
–5V
Figure 25. Driving Two AC-Coupled Loads with Two Coupling Capacitors
SINGLE SUPPLY
+5V
+5V
75Ω
9.09kΩ
LEVEL1
0.1µF
1kΩ
LEVEL2
0.1µF
75Ω
CABLE
470µF
05265-048
9.09kΩ
1kΩ
0.1μF
05265-054
9.53kΩ
LEVEL2
+5V
9.53kΩ
1kΩ
DNP
LEVEL1
DUAL SUPPLY
+5V
+5V
05265-049
As previously discussed, the composite video output is
developed by passively summing the Y and C outputs that have
passed through their respective output gain stages, then multiplying
this sum by a factor of two to obtain the output (see Figure 1).
The offset of this output is equal to 2× that of the other outputs.
Because of this, in many cases, it is necessary to ac-couple the
CV output or ensure that it is connected to an input that is accoupled. This is generally not an issue because it is common
practice to employ ac coupling on composite video inputs.
75Ω
75Ω
75Ω
CABLE
75Ω
05265-055
Figure 23. Generating Fully Adjustable Output Offsets
Figure 26. Driving Two AC-Coupled Loads with One Common Coupling Capacitor
Rev. B | Page 14 of 16
ADA4410-6
PRINTED CIRCUIT BOARD LAYOUT
When the ADA4410-6 receives its inputs from a device with
current outputs, the required load resistor value for the output
current is often different from the characteristic impedance of
the signal traces. In this case, if the interconnections are sufficiently
short (<< 0.1 wavelength), the trace does not have to be terminated
in its characteristic impedance. Figure 27 shows an example in
which the ADA4410-6 input originates from DACs that require
300 Ω load resistors. Traces of 75 Ω can be used in this instance,
provided their lengths are an inch or two at the most. This is
easily achieved because the ADA4410-6 and the device feeding
it are usually adjacent to each other, and connections can be
made that are less than one inch in length.
As with all high speed applications, attention to printed circuit
board layout is of paramount importance. Standard high speed
layout practices should be adhered to when designing with the
ADA4410-6. A solid ground plane is recommended, and
surface-mount ceramic power supply decoupling capacitors
should be placed as close as possible to the supply pins. All of
the ADA4410-6 GND pins should be connected to the ground
plane with traces that are as short as possible. Controlled
impedance traces of the shortest length possible should be used
to connect to the signal I/O pins and should not pass over any
voids in the ground plane. A 75 Ω impedance level is typically
used in video applications. All signal outputs of the ADA4410-6
should include series termination resistors when driving
transmission lines.
VIDEO ENCODER RECONSTRUCTION FILTER
The ADA4410-6 is easily applied as a reconstruction filter at the
DAC outputs of a video encoder. Figure 27 illustrates how to use
the ADA4410-6 in this type of application with an ADV7314 video
encoder in a single-supply application with ac-coupled outputs.
NOTE: EACH POWER SUPPLY PIN MUST HAVE ITS OWN DECOUPLING NETWORK
2.5V/3.3V
(DIGITAL I/O)
2.5V
(DIGITAL)
5kΩ
1.1kΩ
0.01µF
0.1µF
0.1µF
41
AD1580
0.1µF
4.7kΩ
VAA COMP1
46
VREF
RESET
820pF
+
34
3.5pF
4.7kΩ
COMP2
0.01µF
EXT_LF
0.1µF
VDD
1
VDD_IO
I2C
19
SCLK
22
100Ω
SDA
21
100Ω
5kΩ
51-55, 58-62
PIXEL
CLOCKS
32
63
NC
SYNC AND
BLANKING
SIGNALS
MULTIFUNCTIONAL
INPUT
GND_IO
64
RSET2
DGND
11, 57
AGND
40
35
ADA4410-6
11
30
4
6
1
8
3
10
300Ω
47
DISABLE
G_SEL
MUX_SD
MUX_HD
F_SEL_A
F_SEL_B
21
31
DAC F 37
RSET1
27
15
300Ω
S_VSYNC
48
S_BLANK
31
RTC_SCR_TR
LEVEL2
14
DAC E 38
50 S_HSYNC
49
VCC
28
13
300Ω
P_HSYNC
P_VSYNC
25
P_BLANK
VCC
LEVEL1
12
DAC D 39
24
26
29
5
300Ω
23
0.1µF
BINARY
CONTROL
INPUTS
DAC C 42
CLKIN_A
CLKIN_B
634Ω
I2C
BUS
300Ω
S9–S0
0Ω
16
DNP*
DAC B 43
C9–C0
10kΩ
5kΩ
Y9–Y0
14-18, 26-30
DNP*
0.1µF
ALSB 20
DAC A 44
0.1µF
0.1µF
10, 56
RESET
ADV7314
2-9, 12, 13
DIGITAL
VIDEO
BUSES
0.1µF
36
5kΩ 0.01µF
33
4.7µF
45
5V
(ANALOG)
DEVICE
ADDRESS
SELECT
3.04kΩ
CV_OUT 18
220µF
Y_SD_OUT 20
C_SD_OUT
19
75Ω
Y/G_HD_OUT
24
75Ω
0.1µF
C1_SD
C2_SD
220µF
Y1/G1_HD
Y2/G2_HD
Pb1/B1_HD
Pb2/B2_HD
Pb/B_HD_OUT 23
75Ω
220µF
Pr/R_HD_OUT
22
75Ω
220µF
Pr1/R1_HD
Pr2/R2_HD
GND
2, 7, 9, 32
*DO NOT POPULATE
Figure 27. The ADA4410-6 Applied as a Reconstruction Filter Following the ADV7314
Rev. B | Page 15 of 16
75Ω
220µF
Y1_SD
Y2_SD
3.04kΩ
CHANNEL 2
VIDEO INPUTS
75Ω
VEE
17, 25
05265-050
2.5V
(ANALOG)
ADA4410-6
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
32
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
17
16
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 28. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADA4410-6ACPZ-R2 1
ADA4410-6ACPZ-R71
ADA4410-6ACPZ-RL1
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Package Option
CP-32-2
CP-32-2
CP-32-2
Ordering
Quantity
250
1,500
5,000
Z = Pb-free part.
© 2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05265–0–3/06(B)
T
T
Rev. B | Page 16 of 16