ON NCP1212DR2G Current mode pwm controller for both forward and flyback converter Datasheet

NCP1212
Current Mode PWM
Controller for Both Forward
and Flyback Converters
NCP1212 is a high performance current mode PWM controller
specifically designed for off−line and DC−to−DC converter
applications. The device requires very few external components and
offers designer additional protection for better system reliability. The
device features a trimmed oscillator for precise Duty Cycle control,
accurate bandgap voltage reference, high gain error amplifier, current
sensing comparator and a high current totem pole output gate driver
that ideally drives the external power MOSFET. Additionally, the
device has built−in programmable Brownout Detect and Soft−Start
features to enhance system reliability. Also, the 48%/82% selectable
maximum turn on Duty Cycle control and external programmable
switching frequency capabilities make this device an ideal controller
for both forward and flyback configurations. This device is available
in both PDIP−8 and space saving SOIC−8 packages.
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MARKING
DIAGRAM
8
SOIC−8
DSUFFIX
CASE 751
8
1
1
8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Cycle Control
Internal High Accuracy Bandgap Voltage Reference
Current Mode Operation up to 200 kHz
Inherent Feed Forward Compensation
Latching PWM for Cycle−by−Cycle Current Limiting
High Current Totem Pole Output Gate Driver
Low Startup and Operating Current
Internal Undervoltage Lockout with Hysteresis
Internal Leading Edge Blanking for Current Feedback
Direct Interface with Optocoupler for Secondary Sensing
Built−in Soft−Start Function, Programmable by External Capacitor
User Programmable 48%/82% Maximum Duty Cycle Selection
Output Overvoltage Protection Against Open Loop
AC Line Brownout Detect Protection
Output Overload Protection Irrespective of Auxiliary Voltage Level
Pb−Free Packages are Available
Typical Applications
•
•
•
•
8
1
1
A
L, WL
Y, YY
W, WW
G
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Pb−Free Package
PIN CONNECTIONS
FB
1
8
SS/DMAX
BOK
2
7
VCC
CS
3
6
DRV
CT
4
5
GND
(Top View)
ORDERING INFORMATION
Device
ATX PC Power Supply
Universal Input Wall Mount Adaptors
CRT Monitor
All Flyback and Forward SMPS Systems
NCP1212
AWL
YYWWG
PDIP−8
N SUFFIX
CASE 626
Features
• Trimmed Oscillator Charge and Discharge Current for Precise Duty
N1212
ALYW
G
NCP1212DR2
NCP1212DR2G
NCP1212P
NCP1212PG
Package
Shipping †
SOIC−8
2500/Tape & Reel
SOIC−8
(Pb−Free)
2500/Tape & Reel
PDIP−8
50 Units / Rail
PDIP−8
(Pb−Free)
50 Units / Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2005
September, 2005 − Rev. 3
1
Publication Order Number:
NCP1212/D
AC Input
+
−
2
0
X2 Cap
3
1
RFI FILTER
X2 Cap
4
C4
1 nf
BR1
1
2
F1
FUSE
2
R2
3.3 K
VCC
DRV
GND
CS
CT
SS/DMAX
C3
0.1 mf
Form Standby SMPS
Auxiliary Winding
C1
470 mf/400 V
IC1
NCP1212
+
BOK
FB
3
R1
576 K
C2
10 nf/1 kv
C5
0.1 mf
Rsense
0.22/2 W
Q1
4
R3
36 K
D1
MUR180
Figure 1. Typical Application Circuit
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3
2
1
R6
220
C6
R5
100 0.1 mf
D2
MBR3045
U1
TL431
IC2
PC817
T3
R8
300
GND
C7
3300 mf/
10 V
+
5V
NCP1212
Figure 2. Simplified Functional Block Diagram
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3
CT
BOK
CS
FB
−
+
−
±+
+5 V
OSC
Clock
SW2
45 mA
9K
−
+
IMAX
R
−
+
3.2 V
−
+
−
+
Brownout
Detection
1V
−
+
+
−
Current Limit
Max. Duty
Cycle
48% or 82%
300 ns
LEB
1.21 V
3R
−
+
S
8 mA
Q
Q
−
±
+
CLK
Q
Overload
Enable
D
S
−
±+
D
Reset
28 mA
−
+
CLK
+5 V
Q
0.5 V
−
+
5V
S
R
F/F
Overload
Q
Q
−
+
15 V
Totem Pole Drive
Vref
Regulator
UVLO
(10 V)
OVLO
(25 V)
Shutdown
−
+
+5 V
GND
DRV
VCC
SS/DMAX
NCP1212
NCP1212
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PIN FUNCTION DESCRIPTION
Pin
Name
Function
Description
1
FB
Feedback Input
This pin detects voltage feedback from output, can be connected directly to the
optocoupler collector pin.
2
BOK
Brownout Detect
with Hysteresis
This is the inverting input of the brownout detect comparator. The brownout detect
comparator has a detect threshold voltage of 1.21 V. This pin senses the voltage of the
bulk capacitor through a resistor divider network to determine the brownout event. The
hysteresis band is provided by a 45 mA current flows out of this pin to the resistor
network.
3
CS
Current Sense Input
4
CT
Programmed Oscillator
Frequency
5
GND
IC Ground
6
DRV
Gate Driver Output
This is a high current totem pole output. The PWM driving control is provided by this pin.
The current and slew rate capability of this pin are suitable to drive a Power MOSFET.
7
VCC
Positive Supply to IC
This pin is the positive supply of the IC. The driver output gets disabled when the voltage
becomes higher than 25 V and the operating range is between 10 V and 25 V. The
startup voltage is set at 15 V.
8
SS/DMAX
Soft−Start Time
Programming and
Maximum Duty Cycle
Selection
This is a multi−function pin. Soft−start effect is provided during startup with a capacitor
connected to this pin. After soft−start period elapsed, the capacitor is used for timing
control to determine output overload. If only a capacitor is connected to this pin, its final
voltage is X4.3 V and maximum turn−on duty cycle DMAX is set at 82%. Connect a
resistor in parallel with the capacitor can alter the final voltage of this pin. 48% DMAX is
selected if this pin stays at 2.1 V to 2.8 V after soft−start period.
During output on–time of the power switch, this pin receives a voltage proportional to
power switch current set by the current sensing resistor. The information is utilized to
terminate output switch conduction by PWM action or overcurrent limit circuitry.
Connecting a capacitor from CT pin to ground programs the internal oscillator frequency.
The oscillator can operate up to 200 kHz.
−
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
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MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating
Power Supply Voltage (Pin 7)
Input/Output Pins (Pins 1, 2, 3, 4, 8)
Symbol
Value
Unit
VCC
−0.3, 28
V
VIO
−0.3, 6.5
V
Gate Driver Output Pin (Pin 6)
VDRV
−0.3, 14
V
Power Dissipation and Thermal Characteristics
Thermal Resistance, Junction−to−Air, PDIP−8 Version
Thermal Resistance, Junction−to−Air, SOIC−8 Version
RqJ−A
Output Current, Source or Sink
IDRV
1.0
A
Operating Junction Temperature Range
TJ
−40 to +150
°C
Operating Ambient Temperature Range
TA
−25 to +105
°C
Storage Temperature Range
°C/W
100
178
Tstg
−55 to +150
°C
ESD Capability, HBM (All pins except VCC pin) (Note 1)
−
2.0
kV
ESD Capability, Machine Model (All pins except VCC pin) (Note 1)
−
200
V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) v2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) v200 V per JEDEC standard: JESD22−A115.
2. Latchup Current Maximum Rating: "150 mA per JEDEC standard: JESD78.
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NCP1212
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, DMAX = 48%, for min/max values TJ = −25°C to +105°C,
VCC = 16 V unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Oscillation Frequency, TJ = 25°C (DMAX = 48%, CT = 1.0 nF)
FOSC−48
81
90
99
kHz
Oscillation Frequency, TJ = 25°C (DMAX = 82%, CT = 1.0 nF)
FOSC−82
72
80
88
kHz
Frequency Change against Supply Voltage
(VCC = 13 V to 25 V, TJ = 25°C)
DFOSC−V
−
0.02
−
%
Frequency Change against Temperature
(VCC = 16 V, TJ = −25°C to 105°C)
DFOSC−T
−
5.0
−
%
Maximum Current Sense Input Threshold
VCS
0.96
1.0
1.16
V
Propagation Delay (Current Sense to Gate after LEB Blanking)
TPLH
−
150
200
ns
Leading Edge Blanking Time
TLEB
−
300
−
ns
ISS
5.0
8.0
11
mA
OSCILLATOR SECTION
CURRENT SENSE SECTION
SOFT−START SECTION
Soft−Start Charge Current
ISD−ISS
15
20
26
mA
48% Duty Cycle Selection Input Voltage Threshold
VD48
−
2.5
−
V
82% Duty Cycle Selection Input Voltage Threshold
VD82
−
3.0
−
V
Gate Drive Sink Capability, VCC = 15 V, VDRV = 1.0 V
IOL
−
100
−
mA
Gate Drive Source Capability, VCC = 15 V, VDRV = 5.0 V (Note 4)
IOH
−
300
−
mA
Gate Drive Voltage (From 1.0 V to 11 V) Rise Time (CL = 1.0 nF, TJ = 25°C)
Tr
−
25
50
ns
Gate Drive Voltage (From 11 V to 1.0 V) Fall Time (CL = 1.0 nF, TJ = 25°C)
Tf
−
25
50
ns
VCCTH
13.5
15
16.5
V
VCC Overvoltage Lockout Threshold
VCCOVLO
22.5
25
27.5
V
VCC Undervoltage Lockout Threshold
VCCUVLO
8.5
10
11.5
V
Power Supply Current, before Startup (VCC = 12 V)
IC1
−
0.15
0.26
mA
Power Supply Current, Operating
IC2
−
3.0
5.0
mA
Power Supply Current, Shutdown (VCC = 15 V)
IC3
−
3.0
−
mA
Brownout Input Threshold Voltage
VBOK
1.14
1.21
1.27
V
Brownout Hysteresis Current
IBOK
38
45
54
mA
Maximum Duty Cycle at Soft−Start Pin Voltage between 2.1 V and 2.8 V
(2.1 V v VDMAX v 2.8 V)
DMAX48
47
48
50
%
Maximum Duty Cycle at Soft−Start Pin Voltage Higher than 3.0 V
(VDMAX w 3.0 V)
DMAX82
79
82
88
%
Overload Timing Discharge Current (Note 3)
GATE DRIVER SECTION
IC POWER SUPPLY SECTION
VCC Startup Threshold Voltage
BROWNOUT DETECT SECTION (BOK)
MAXIMUM DUTY CYCLE SECTION
3. ISD is an internal current source not accessible externally.
4. The output voltage is internally clamped by 13.5 V Zener.
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NCP1212
FOSC−82, OSCILLATOR FREQUENCY (kHz)
95
90
85
80
DMAX = 48%
CT = 1 nF
75
−25
1
27
53
79
105
100
90
80
70
60
DMAX = 82%
CT = 1 nF
50
−25
27
53
79
105
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Oscillator Frequency with 48% Duty
Cycle vs. Junction Temperature
Figure 4. Oscillator Frequency with 82% Duty
Cycle vs. Junction Temperature
0.12
VCC = 13V to 25V
1.2
1.15
0.1
0.08
0.06
1.1
1.05
0.04
0.02
0
−25
1.0
0.95
1
27
53
79
105
0.9
−25
TJ, JUNCTION TEMPERATURE (°C)
TLEB, LEADING EDGE BLANKING TIME (ns)
160
120
80
40
1
27
53
27
53
79
105
Figure 6. Maximum Current Sense Input
Threshold Voltage vs. Junction Temperature
200
0
−25
1
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Frequency Change against Supply
Voltage vs. Junction Temperature
TPLH, PROPAGATION DELAY (ns)
1
TJ, JUNCTION TEMPERATURE (°C)
VCS, MAXIMUM CURRENT SENSE INPUT
THRESHOLD (V)
DFOSC−V, FREQUENCY CHANGE (%)
FOSC−48, OSCILLATOR FREQUENCY (kHz)
TYPICAL CHARACTERISTICS
79
105
400
350
300
250
200
150
100
−25
1
27
53
79
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Propagation Delay vs. Junction
Temperature
Figure 8. Leading Edge Blanking Time vs.
Junction Temperature
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6
105
ISS, SOFT−START CHARGE CURRENT
(mA)
9
8.5
8
7.5
7
6
−25
1
27
53
79
105
30
25
20
15
10
5
0
−25
79
105
2
1
1
27
53
79
105
1.2
1.1
VDRV = 1V
1
0.9
0.8
0.7
−25
TJ, JUNCTION TEMPERATURE (°C)
IOL, GATE DRIVE SINK CURRENT (mA)
VDRV = 5V
250
VCC = 15 V
80 ms Pulsed Load
120 Hz Rate
200
150
VDRV = 8V
1
27
53
27
53
79
105
Figure 12. Output Sink Resistance vs.
Junction Temperature
350
300
1
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. 82% Duty Cycle Selection Input
Voltage Threshold vs. Junction Temperature
IOH, GATE DRIVE SOURCE CURRENT (mA)
53
Figure 10. Overload Timing Discharge Current
vs. Junction Temperature
3
50
−25
27
Figure 9. Soft−Start Charge Current vs.
Junction Temperature
4
100
1
TJ, JUNCTION TEMPERATURE (°C)
5
0
−25
35
TJ, JUNCTION TEMPERATURE (°C)
ROL, OUTPUT SINK RESISTANCE (W)
VS2, 82% DUTY CYCLE SELECTION
INPUT VOLTAGE THRESHOLD (V)
6.5
ISD−ISS, OVERLOAD TIMING DISCHARGE
CURRENT (mA)
NCP1212
79
105
400
350
VDRV = 5V
300
250
VCC = 15 V
80 ms Pulsed Load
120 Hz Rate
200
150
100
50
−25
VDRV = 1V
1
27
53
79
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Gate Drive Source Capability vs.
Junction Temperature
Figure 14. Gate Drive Sink Capability vs.
Junction Temperature
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7
105
40
30
20
10
0
−25
1
27
53
79
50
Tf, GATE DRIVE VOLTAGE FALL TIME (ns)
50
105
40
30
20
10
0
−25
53
79
Figure 15. Gate Drive Voltage Rise Time vs.
Junction Temperature
Figure 16. Gate Drive Voltage Fall Time vs.
Junction Temperature
1.3
1.2
1.1
1.0
0.9
0.8
−25
1
27
53
79
105
TJ, JUNCTION TEMPERATURE (°C)
50
45
40
35
30
25
−25
2.1V ≤ VDMAX ≤ 2.8V
55
50
45
40
35
30
25
1
27
53
79
1
27
53
79
105
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Brownout Hysteresis Current vs.
Junction Temperature
DMAX82, MAXIMUM DUTY CYCLE (%)
60
105
55
Figure 17. Brownout Input Threshold Voltage
vs. Junction Temperature
DMAX48, MAXIMUM DUTY CYCLE (%)
27
TJ, JUNCTION TEMPERATURE (°C)
1.4
20
−25
1
TJ, JUNCTION TEMPERATURE (°C)
IBOK, BROWNOUT HYSTERESIS CURRENT (mA)
VBOK, BROWNOUT INPUT THRESHOLD
VOLTAGE (V)
Tr, GATE DRIVE VOLTAGE RISE TIME (ns)
NCP1212
105
100
VDMAX≥ 3V
90
80
70
60
50
−25
1
27
53
79
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Maximum Duty Cycle, DMAX48 vs.
Junction Temperature
Figure 20. Maximum Duty Cycle, DMAX82 vs.
Junction Temperature
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105
11
10
9
8
7
6
−25
1
27
53
105
79
VCCTH, VCC Startup THRESHOLD
VOLTAGE (V)
30
27
24
21
18
15
−25
53
79
105
Figure 21. VCC Under Voltage Lockout
Threshold vs. Junction Temperature
Figure 22. VCC Overvoltage Lockout Threshold
vs. Junction Temperature
14
11
8
1
27
53
79
105
200
VCC = 12V
150
100
50
0
−25
TJ, JUNCTION TEMPERATURE (°C)
IC3, POWER SUPPLY SHUTDOWN CURRENT (mA)
4.0
VCC = 16V
3.0
2.0
1.0
27
53
79
27
53
79
105
Figure 24. Power Supply Current Startup vs.
Junction Temperature
5.0
1
1
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. VCC Startup Threshold Voltage vs.
Junction Temperature
IC2, POWER SUPPLY OPERATING CURRENT (mA)
27
TJ, JUNCTION TEMPERATURE (°C)
17
0.0
−25
1
TJ, JUNCTION TEMPERATURE (°C)
20
5
−25
VCCOVLO, VCC OVERVOLTAGE LOCKOUT
THRESHOLD (V)
12
IC1, POWER SUPPLY CURRENT BEFORE
STARTUP (mA)
VCCUVLO, VCC UNDER VOLTAGE LOCKOUT
THRESHOLD (V)
NCP1212
105
TJ, JUNCTION TEMPERATURE (°C)
4.0
3.5
3.0
VCC = 15V
2.5
2.0
1.5
1.0
−25
Figure 25. Power Supply Operating Current vs.
Junction Temperature
1
27
53
79
TJ, JUNCTION TEMPERATURE (°C)
Figure 26. Power Supply Shutdown Current
vs. Junction Temperature
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9
105
NCP1212
Figure 27. Rise Time of Gate Drive Waveform
(CL = 1 nF)
Figure 28. Fall Time of Gate Drive Waveform
(CL = 1 nF)
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
Ramp up to 24 V
Ramp down from 24 V
3.5
IC2, SUPPLY CURRENT (mA)
Ramp up to 24 V
Ramp down from 24 V
3
2.5
2
1.5
1
0.5
0
−0.5
0
5
10
15
20
25
0
5
VCC, SUPPLY VOLTAGE (V)
10
20
Figure 30. Supply Current vs. Supply Voltage
(Duty Cycle = 48% and Output Load = 1 nF)
300
48% DUTY −CYCLE
82% DUTY CYCLE
250
200
150
100
50
0
400
15
VCC, SUPPLY VOLTAGE (V)
Figure 29. Supply Current vs. Supply Voltage
(Duty Cycle = 82% and Output Load = 1 nF)
SWITCHING FREQUENCY (kHz)
IC2, SUPPLY CURRENT (mA)
4
600
800
1000
1200
CT, PIN CAPACITANCE (pF)
Figure 31. Switch Frequency vs. CT Pin Capacitance
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25
NCP1212
DETAILED OPERATING DESCRIPTIONS
INTRODUCTION
switching frequency can be selected by choosing proper
value of timing capacitor, CT. The CT pin waveform is
shown in Figure 32.
The NCP1212 implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint. This device represents an ideal
candidate where low external part−count is the key system
requirement. Additionally, the device provides extensive
value−added functions, Soft−Start, Brownout Detect, etc.,
that can be applied to low−cost AC−DC adaptor
applications. The NCP1212 incorporates all the necessary
functions normally needed in UC384X based power supply
systems: Oscillator section, PWM Latch section, Current
Sense section, Brownout Detect protection, Soft−Start and
Maximum Duty Cycle Selection. With all those functions,
this device becomes a good alternative to UC384X that can
help to improve both performance and system cost. Also, the
innovative Maximum Duty Cycle Selection feature allows
the device applied to both forward and fly−back mode
configurations. Detailed functions of individual internal
blocks are described in below and a simplified functional
block diagram is shown in Figure 2.
3.8 V
82%
2.5 V
48%
48%
1.0 V
Figure 32. CT Pin Waveform for Oscillator
PWM Latch Section
NCP1212 works in current mode. The power switch
current is converted to a positive voltage by inserting a
sensing resistor Rsense between the power switch source and
the ground. The power switch peak current is compared with
the level shifted control input voltage on a cycle−by−cycle
basis. Figure 27 illustrated the internal blocks of the
function. The PWM latch is initialized by the Oscillator set
signal and is terminated by the current sense comparator
when the current exceeds the value dictated by the control
input or current limit level. The current sense Comparator
Latch configuration used ensures that only a single pulse
appears at the output during any given oscillator cycle.
Oscillator Section
The oscillator frequency is programmed by the capacitor
connected to CT pin. The capacitor is charged by a constant
current source to 3.8 V and 2.5 V for 82% and 48%
maximum Duty Cycle condition respectively. Once the
selected voltage is reached, CT is then discharged by another
constant current source down to 1.0 V and this charging and
discharging action will carry on perpetually. Desirable
+5 V
9K
1
4
3R
−
FB
2
PWM Control
Output
+
R
Totem Pole Driver
3
R
300 ns
LEB
CS
−
Current
Limit
+
Rsense
+
−
1V
Reset
Oscillator
F/F
S
Output
Set
Figure 33. PWM Latch Function
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Q
Q
DRV
NCP1212
Current Sense Section
Thus the maximum allowable peak current is given by the
following equation:
The current sense pin, CS detects the voltage drop across
a current sensing resistor, Rsense connected in between the
power MOSFET and Ground. In most cases, a narrow spike
on the leading edge of the current waveform can be observed
and may cause the power supply to exhibit an instability
when the output is lightly loaded. The spike is due to the
power transformer inter−winding capacitance and output
rectifier recovery time which are unavoidable. NCP1212
provides a 300 ns Leading Edge Blanking block to shield off
the spike. With the Leading Edge Blanking function, the CS
pin is not sensitive to the power switch turn−on noise and
spikes, practically in most applications, no filtering network
is required.
In normal operation, voltage developed at the current
sense input is compared with the level shifted control input
voltage and an internal Current Limit Threshold, VCS. In
case the CS input exceeds the Current Limit Threshold,
which is 1.0 V (typ.) in NCP1212, the gate driver output will
be forced to turn off immediately.
Ipk(max) +
1V
Rsense
Soft−Start and Maximum Duty Selection
NCP1212 includes an internal Soft−Start function to
simplify designer’s job hence make this device easy to use.
During the startup phase, a constant current source of 8.0 mA
flows out of the SS/DMAX pin once VCC attains the
minimum startup voltage. The capacitor connected at
SS/DMAX pin is slowly charged up and the voltage
developed plus one diode drop, VSST is compared with the
saw−tooth waveform, CT from the internal oscillator as
shown in Figure 34. Whenever CT voltage is higher than
VSST, gate driver output will be turned off. Since VSST rises
slowly and it controls the output duty gradually increases as
shown in Figure 35. The minimum CT voltage is at 1.0 V,
hence there is no output before SS/DMAX pin attains about
0.4 V (1.0 V–1 diode drop). Soft−Start block will have no
effect to the PWM operation once VSST reaches 3.2 V.
NCP1212
+5 V
8 mA
F/F
Overload
Enable
Q
S
SS/DMAX
Vsst
+
−
Q
Shutdown
3.2 V
CSS
Reset
−
+
From CT
Duty Cycle Control
Figure 34. Soft−Start Operation
CT
VSST
VDRV
Figure 35. Output Pulse Duty Cycle Depends on the SS/DMAX Pin Voltage
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NCP1212
Overload Detection
SS/DMAX pin is also used for the selection of maximum
turn on Duty Cycle. The oscillator circuit is designed to
operate in either 82% or 48% charging time that corresponds
to either 82% or 48% maximum PWM turn on Duty Cycle.
As discussed in the Oscillator Section, saw−tooth waveform
at CT pin is different for 82% and 48% maximum turn on
Duty Cycle and it is shown in Figure 32.
The final voltage at SS/DMAX pin determines the
maximum turn on Duty Cycle. If 82% maximum turn on
duty is desired, simply connect a capacitor from SS/DMAX
pin to ground as shown in Figure 36 and the final voltage on
the capacitor will be 5.0 V minus one diode drop (X4.3 V).
During output overload or short circuit condition, the
PWM controller will pump as much energy as possible to the
secondary side and the power only limited by the
cycle−by−cycle current limit setting. Components in the
power supply circuit such as the power MOSFET and output
rectifier may be damaged by this continuous stress.
Theoretically, fly−back converter has inherent short circuit
protection provided that the PWM controller is supplied by
a fly−back auxiliary winding and it has UVLO function.
Unluckily, it is quite common that the supply will experience
very high leaky voltage spike that prevents the VCC voltage
to fall below UVLO level during short circuit.
NCP1212 is equipped with an integrated overload
detection mechanism, which is irrespective of auxiliary
winding voltage level. Overload shutdown is no longer
bothered by leakage spike hence a reliable overload
protection system can be easily constructed by NCP1212 for
both forward and fly−back configuration. Overload
detection block is shown in Figure 38. Overload condition
is signified by current sense voltage hitting the maximum
allowable voltage, 1.0 V. To avoid false trigger that may
happen during transient load changes, CSS starts to
discharge by 20 mA (ISD−ISS). If overload condition
persists, VSST voltage level drops to 0.5 V and triggers the
overload shutdown. Overload shutdown is only enabled
after the soft−start period.
Due to the overload detection mechanism, it is
mandatory to connect a capacitor at the SS/DMAX pin.
Otherwise overload shutdown may be triggered during
startup phase.
5.0 V
ISS = 0.8 mA
Final Voltage [ 4.3 V
SS/DMAX
CSS
82% Max.
Duty Cycle
Figure 36. 82% Maximum Duty Cycle Selection
For 48% maximum Duty Cycle selection, we need to
adjust the final voltage at SS/DMAX to lower than 3.2 V
minus one diode drop (X2.5 V). This can be achieved by
connecting a resistor in parallel with CSS as shown in
Figure 37. The value of this parallel resistor is given by the
equation in below:
Rduty + 2.5 V
8 mA
5.0 V
ISS = 8 mA
Final Voltage = 2.5 V
SS/DMAX
48% Max.
Duty Cycle
CSS
Rduty
Figure 37. 48% Maximum Duty Cycle Connection
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NCP1212
+5 V
8 mA
±+
−
SS/DMAX
−
+
28 mA
Current Limit
From
Current
Sense
D
Max. Duty
Cycle
48% or 82%
CLK
Q
CLK
Q
+
−
Overload Enable
S
Q
+
3.2 V
−
−
D
Q
1V
DMAX
±+
S
−
OSC
Clock
Shutdown
+ 0.5 V
−
+
+
CT
Overload
Reset
−
−
+
Figure 38. Overload Detection Block Diagram
Brownout Protection
divider formed with RUpper and RLower. Equations to
calculate the resistors are shown below:
NCP1212 has a built−in comparator for brownout
detection as shown in Figure 39. Positive terminal of the
comparator is connected to a +1.21 V bandgap reference.
The IC is prohibited from switching until Brownout Detect
pin exceeds 1.21 V. Once the brownout detect threshold is
exceeded, 45 mA flows out of the pin and the voltage at this
pin is further pushed up to provide hysteresis effect. The
Brownout voltage setting is determined by the potential
RUpper ) RLower +
RLower +
(VBulk_H * VBulk_L)
45 mA
[1.21 V(VBulk_H * VBulk_L)]
(45 mA VBulk_H)
Where VBulk_H and VBulk_L are the desired upper and
lower bulk capacitor voltage for brownout detection.
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NCP1212
+5 V
To Bulk Capacitor
45 mA
±+
−
RUpper
SW2
BOK
−
Output
+
RLower
Brownout Shutdown
+
1.21 V
−
Figure 39. Brownout Detect Block Diagram
Internal 5.0 V Regulator
Overvoltage Protection and Under Voltage Lockout
A low current 5.0 V regulator is available internally for
the device operation and reference voltages generation. This
voltage not accessible externally and is designed to operate
with no external bypass capacitor.
NCP1212 starts operation once VCC reaches 15 V.
Overvoltage Protection (OVP) will be triggered if VCC
exceeds 25 V and on the other hand, Under Voltage Lockout
(UVLO) will take place if VCC drops below 10 V. NCP1212
continues to draw 3.0 mA typical after overload or
overvoltage shutdown is triggered. If the startup resistance
connected to VCC pin is large enough such that VCC voltage
keeps on dropping after shutdown, NCP1212 will restart once
VCC drops below UVLO threshold. If the fault condition
persists, NCP1212 will enter hi−cup operation. In case system
latchoff is required in fault conditions, a smaller startup
resistance can be used to sustain the device operation.
NCP1212 will remain in shutdown mode as long as VCC is
maintained above UVLO threshold after fault is detected.
Totem Pole Output Driver
NCP1212 contains a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to 300 mA peak drive current
and has a typical rise time and fall time of 25 ns with 1.0 nF
load.
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NCP1212
APPLICATION INFORMATION AND TYPICAL WAVEFORMS
The NCP1212 is an ideal choice for next generation
isolated fix switching frequency forward mode converters
that only need few external components to complete the
system. Converting your existing application from using
UC384X controllers to NCP1212 is easy and simple. In
below is a description on how to determine external
components value for a typical application example. For the
schematic of the application, please refer to Figure 1 in this
data sheet.
Finding the external component values can be broken
down into several steps as introduced below:
V1 is the Upper Threshold Voltage in the oscillator
block and which is effectively controlling the PWM
maximum Duty Cycle at gate driver output.
Soft−Start block will have no effect to the PWM
operation once SS/DMAX pin voltage reaches this
threshold. This threshold voltage is 2.5 V with 48%
maximum Duty Cycle;
1. Select the maximum Duty Cycle for forward mode
operation and calculate the Soft−Start time.
For example, the required Soft−Start time is 50 ms,
the timing capacitor, CSS can be calculated as:
V2 is about 0.4 V (1.0 V minus one diode drop)
which is the Lower Voltage Threshold for the PWM
operation. There will be no PWM gate driver output
before SS/DMAX pin voltage attains this threshold.
Select the system, operate in forward mode with
82% maximum Duty Cycle. Only a capacitor is
required at SS/DMAX pin and the Soft−Start time is
determined by the capacitor, CSS. Its value is given
by the equation below:
8 mA 50 ms
CSS +
+ 0.182 mF
2.5 V * 0.4 V
In this case, a 0.22 mF capacitor is used for this
application and the Soft−Start time is calculated as
57.75 ms. The charging waveform at SS/DMAX pin
is shown in Figure 40. From the captured waveform,
the charge time from 0 V to 4.0 V is 115.2 ms and for
the voltage charging up to 2.5 V, i.e. hitting the
Upper Threshold Voltage, the elapsed time is about
70 ms that matched with the theoretical calculation
closely.
I TSS
CSS +
V1 * V2
where:
I is an 8.0 mA constant current source flow out of the
SS/DMAX pin;
TSS is the required Soft−Start time;
115.2 ms
4.0 V
Figure 40. SS/DMAX Pin Charging Waveform
Overload condition is signified by current sense input
voltage hitting the Maximum Current Sense Threshold,
VCS. To avoid false trigger that may happen during transient
load change, CSS starts to discharge by an internal current
source of 20 mA, ISD−ISS and the overload protection will
only be issued until the voltage at SS/DMAX pin falls below
0.5 V. The discharging time, TDIS for 0.22 mF Soft−Start
capacitor is given by:
TDIS +
CSS
where:
CSS is the Soft−Start timing capacitor;
Vref is the internal reference voltage, 5.0 V typical;
VD is the internal diode forward voltage on between the
reference voltage and SS/DMAX pin in IC internal, is 0.6 V
typical;
VOL is the overload threshold voltage. Refer to Figure 39
Overload Detection Block Diagram, the overload threshold
voltage is 0.5 V typical;
(Vref * VD * VOL)
ISD * ISS
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16
NCP1212
ISD−ISS is the internal current source for CSS discharging,
20 mA typical.
The discharging time for 0.22 mF Soft−Start capacitor is:
TDIS +
0.22 mF
The discharging waveform on SS/DMAX pin is shown in
Figure 41. The discharging time from 4.0 V to 0.6 V is
measured as 36 ms from Figure 41. By interpolation,
discharging time can be estimated as about 41.3 ms when
output is overload which agreed with the calculated result.
(5.0 V * 0.6 V * 0.5 V)
+ 42.9 ms
20 mA
36 ms
3.4 V
Figure 41. SS/DMAX Pin Discharging Waveform
2. Determine the PWM Switching Frequency
3. Determine the BOK Thresholds
The switching waveform is generated by the action
of charging and discharging by internal current
sources to a capacitor connected at CT, pin 4. The
relationship of the switching frequency and the value
of CT is governed by the equation below:
FSW +
Brownout detect thresholds are determined by a
resistors network that monitors part of the bulk
capacitor voltage at BOK pin. Equations below
illustrate the calculation of the resistors value for the
network.
Ichg D
CT (Vth * 1)
RUpper ) RLower +
where:
RLower +
Ichg is the charging current to CT, 278 mA typical;
D is the selected Maximum Duty Cycle, 48% or
82%;
(VBulk_H * VBulk_L)
45 mA
[1.21 V(VBulk_H * VBulk_L)]
(45 mA VBulk_H)
Where VBulk_H and VBulk_L are the desired upper
and lower bulk capacitor voltage for brownout
detection.
CT is the capacitor connected to CT pin;
Assume VBulk_H = 212 Vdc and VBulk_L = 186 Vdc,
select 3.3 kW for RLower then RUpper can be
calculated to be 576 kW.
Vth is the threshold voltage for different Maximum
Duty Cycle selection, 2.5 V for 48% Maximum
Duty Cycle and 3.8 V for 82% Maximum Duty
Cycle.
The Switching Frequency against CT is shown in
Figure 31 to help the designers to determine the capacitance
for their selected switching frequency.
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NCP1212
Channel 1: The MOSFET’s VDS Switching Waveform
Channel 2: Primary Bulk Capacitor Voltage
Channel 3: BOK Pin Voltage
Figure 42. Brownout Detect Waveforms
Experimental results for the Brownout action were shown
in Figure 42. From the captured waveforms, it can be noted
that the Brownout Input Threshold Voltage is 1.21 V and
Brownout Hysteresis Voltage is 1.36 V at BOK pin.
sensing resistor is also small for high power
applications, the current sense feedback voltage will
be much smaller than 0.1 V. Consequently, the
control will force to acquire maximum Duty Cycle
operation and the output will increase without
control.
4. Improving Light Load and No Load Regulation for
High Power Applications
In order to improve the poor regulation at light load,
a small circuit is added as shown in Figure 43. With
the additional circuitry, when VFB falls below 0.1 V,
Q2 will drive additional offset current to CS pin and
modify the current sensing voltage, VCS. For VFB
higher than 0.1 V at normal load operation, Q2 will
be turned off due to limited Vbe.
For high power applications, limited by the dynamic
range of the control circuitry, i.e. the control
feedback is limited by the swing of the optocoupler.
When VFB reaches about 0.1 V at light load
conditions, it no longer has the means to further
reduce that voltage because of the saturation of the
optocoupler. At light load or no load conditions, the
primary current is very small and as the current
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NCP1212
VCC
R8
2.5 K
Q1
PNP
+5 V
9K
1
3R
4
2
−
R2
100
3
FB
Output
+
R
Q2
PNP
3K
300 ns
LEB
CS
−
Current
Limit
Output
+
0.1
+
−
2
3
4
1
F/F
R
1V
Output
Q
Reset
OSC
Block
Set
S
Q
Totem Pole
Driver
Figure 43. Suggested Solution for Better Light Load Regulation
The skip mode operation waveform at light load is shown in Figure 44. Where Channel 1 is the gate drive pin waveform and
Channel 2 is the CS input pin waveform.
Figure 44. Skip Mode Switching Waveform at Light Load
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NCP1212
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
X 45 _
DIM
A
B
C
D
G
H
J
K
M
N
S
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP1212
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
N
SEATING
PLANE
D
H
M
K
G
0.13 (0.005)
M
T A
M
B
M
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DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10 _
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
NCP1212
The product described herein (NCP1212), may be covered by one or more of the following U.S. patents: 6,385,060, 6,385,061, and 6,271,735. There may be
other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Email: [email protected]
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ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NCP1212/D