HI-8382, HI-8383 ARINC 429 Differential Line Driver September 2011 GENERAL DESCRIPTION PIN CONFIGURATION The HI-8382 and HI-8383 bus interface products are silicon gate CMOS devices designed as a line driver in accordance with the ARINC 429 bus specifications. VREF 1 The differential outputs of the HI-8382 are independently programmable to either the high speed or low speed ARINC 429 output rise and fall time specifications through the use of two external capacitors. The output voltage swing is also adjustable by the application of an external voltage to the VREF input. The HI-8382 has on-chip Zener diodes in series with a fuse to each differential output protecting the ARINC bus from an overvoltage failure. The outputs each have a series resistance of 37.5 ohms. The HI-8383 is identical to the HI8382 except that the series resistors are 13 ohms and the overvoltage protection circuitry has been eliminated. 16 V1 STROBE 2 15 N/C SYNC 3 Inputs are provided for clocking and synchronization. These signals are AND'd with the DATA inputs to enhance system performance and allow the HI-8382 to be used in a variety of applications. Both logic and synchronization inputs feature built-in 2,000V minimum ESD input protection as well as TTL and CMOS compatibility. (Top View) 14 CLOCK DATA(A) 4 13 DATA(B) CA 5 12 CB AOUT 6 11 BOUT -V 7 10 N/C GND 8 9 +V HI-8382C / CT / CM-01 / CM-03 SMD # 5962-8687901EA 16 - PIN CERAMIC SIDE-BRAZED DIP (See Page 6 for additional package pin configurations) FUNCTION The updated HI-318X and HI-8585 ARINC 429 line drivers are recommended for all new designs where logic signals must be converted to ARINC 429 levels such as a user ASIC, the HI-3282 or HI-8282A ARINC 429 Serial Transmitter/Dual Receiver, the HI-6010 ARINC 429 Transmitter/Receiver or the HI-8783 ARINC interface device. Holt products are readily available for both industrial and military applications. Please contact the Holt Sales Department for additional information, including data sheets for any of the Holt products mentioned above. + HI-8382 _ ARINC 429 DIFFERENTIAL LINE DRIVER FEATURES TRUTH TABLE ! Low power CMOS ! TTL and CMOS compatible inputs SYNC CLOCK DATA(A) DATA(B) AOUT BOUT COMMENTS ! Programmable output voltage swing X L X X 0V 0V NULL ! Adjustable ARINC rise and fall times L X X X 0V 0V NULL ! Operates at data rates up to 100 Kbits H H L L 0V 0V NULL ! Overvoltage protection H H L H -VREF +VREF LOW ! Industrial and extended temperature ranges H H H L +VREF -VREF HIGH ! DSCC SMD part number H H H H 0V 0V NULL ( DS8382 Rev. F ) HOLT INTEGRATED CIRCUITS www.holtic.com 09/11 HI-8382, HI-8383 FUNCTIONAL DESCRIPTION switch capacitors must be done with analog switches that allow voltages below their ground. The SYNC and CLOCK inputs establish data synchronization utilizing two AND gates, one for each data input. Each logic input, including the power enable (STROBE) input, are TTL/CMOS compatible. Besides reducing chip current drain, STROBE also floats each output. However the overvoltage fuses and diodes of the HI-8382 are not switched out. Both ARINC outputs of the HI-8382 are protected by internal fuses capable of sinking between 800 - 900 mA for short periods of time (125µs). Figure 1 illustrates a typical ARINC 429 bus application. Three power supplies are necessary to operate the HI-8382; typically +15V, -15V and +5V. The chip also works with ±12V supplies. The +5V supply can also provide a reference voltage that determines the output voltage swing. The differential output voltage swing will equal 2VREF. If a value of VREF other than +5V is needed, a separate +5V power supply is required for pin V1. With the DATA (A) input at a logic high and DATA (B) input at a logic low, AOUT will switch to the +VREF rail and BOUT will switch to the -VREF rail (ARINC HIGH state). With both data input signals at a logic low state, the outputs will both switch to 0V (ARINC NULL state). POWER SUPPLY SEQUENCING The power supplies should be controlled to prevent large currents during supply turn-on and turn-off. The recommended sequence is +V followed by V1, always ensuring that +V is the most positive supply. The -V supply is not critical and can be asserted at any time. +5V +15V VREF V1 SYNC CLOCK DATA (A) AOUT +V INPUTS The driver output impedance, ROUT, is nominally 75 ohms. The rise and fall times of the outputs can be calibrated through the selection of two external capacitor values that are connected to the CA and CB input pins. Typical values for high-speed operation (100KBPS) are CA = CB = 75pF and for low-speed operation (12.5 to 14KBPS) CA = CB = 500pF. The driver can be externally powered down by applying a logic high to the STROBE input pin. If this feature is not being used, the pin should be tied to ground. The CA and CB pins are inputs to unity gain amplifiers. Therefore they must be allowed to swing to -5V. Provision to VREF +V TO ARINC BUS DATA (B) CA CB STROBE GND -V BOUT -15V Figure 1. ARINC 429 BUS APPLICATION A OUT CA DATA (A) LEVEL SHIFTER AND SLOPE CONTROL (A) CLOCK R OUT / 2 FA OUTPUT DRIVER (A) RL CL SYNC LEVEL SHIFTER AND SLOPE CONTROL (B) DATA (B) V1 CURRENT REGULATOR R OUT / 2 OUTPUT DRIVER (B) Not included on HI-8383 STROBE GND -V FB CB Figure 2. FUNCTIONAL BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 2 OVER VOLTAGE CLAMPS B OUT HI-8382, HI-8383 PIN DESCRIPTIONS SYMBOL FUNCTION VREF POWER DESCRIPTION THE REFERENCE VOLTAGE USED TO DETERMINE THE OUTPUT VOLTAGE SWING STROBE INPUT A LOGIC HIGH ON THIS INPUT PLACES THE DRIVER IN POWER DOWN MODE SYNC INPUT SYNCHRONIZES DATA INPUTS DATA (A) INPUT DATA INPUT TERMINAL A CA INPUT CONNECTION FOR DATA (A) SLEW-RATE CAPACITOR AOUT OUTPUT ARINC OUTPUT TERMINAL A -V POWER -12V to -15V GND POWER 0.0V +V POWER +12V to +15V BOUT OUTPUT ARINC OUTPUT TERMINAL B CB INPUT CONNECTION FOR DATA (B) SLEW-RATE CAPACITOR DATA (B) INPUT DATA INPUT TERMINAL B CLOCK INPUT SYNCHRONIZES DATA INPUTS V1 POWER +5V ±5% ABSOLUTE MAXIMUM RATINGS All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified) PARAMETER Differential Voltage Supply Voltage Voltage Reference Input Voltage Range SYMBOL VDIF CONDITIONS +V -V V1 VREF For ARINC 429 For Applications other than ARINC UNIT 40 V +10.8 to +16.5 -10.8 to -16.5 +5 ±5% +7 V V V +5 ±5% 0 to 6 6 6 V V > GND -0.3 < V1 +0.3 V V VIN See Note: 1 Output Overvoltage Protection See Note: 2 Storage Temperature Range MAXIMUM Voltage between +V and -V terminals Output Short-Circuit Duration Operating Temperature Range OPERATING RANGE TA TSTG Lead Temperature Extended Industrial -55 to +125 -40 to +85 °C °C Ceramic & Plastic -65 to +150 °C Soldering, 10 seconds Junction Temperature TJ Power Dissipation PD 16-Pin Ceramic DIP 28-Pin Ceramic LCC 28-Pin Plastic PLCC 32-Pin CERQUAD Thermal Resistance, (Junction-to-Ambient) ØJA 16-Pin Ceramic DIP 28-Pin Ceramic LCC 28-Pin Plastic PLCC 32-Pin CERQUAD See Note: See Note: See Note: See Note: 3 3 3 3 +275 °C +175 °C 1.725 1.120 2.143 1.725 W W W W 86.5 133.7 70.0 86.5 °C/W °C/W °C/W °C/W Note 1. Heatsinking may be required for Output Short Circuit at +125°C and for 100KBPS at +125°C. Note 2. The fuses used for Output Overvoltage Protection may be blown by the presence of a voltage at either output that is greater than ±12.0V with respect to GND. (HI-8382 only) Note 3. Derate above +25°C, 11.5mW/°C for 16-PIN DIP and 32-PIN CERQUAD, 7.5 mW/°C for 28-PIN LCC, 14.2 mW/°C for 28-PIN PLCC NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HOLT INTEGRATED CIRCUITS 3 HI-8382, HI-8383 DC ELECTRICAL CHARACTERISTICS +V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL Output Voltage High (Output to Ground) ICCOP (+V) ICCOP (-V) ICCOP (V1) ICCOP (VREF) ICCPD (+V) ICCPD (-V) ISC (+V) ISC (-V) IOHSC IOLSC IIH IIL VIH VIL VOH Output Voltage Low (Output to Ground) Supply Current +V (Operating) Supply Current -V (Operating) Supply Current V1 (Operating) Supply Current VREF (Operating) Supply Current +V (Power Down) Supply Current -V (Power Down) Supply Current +V (During Short Circuit Test) Supply Current -V (During Short Circuit Test) Output Short Circuit Current (Output High) Output Short Circuit Current (Output Low) Input Current (Input High) Input Current (Input Low) Input Voltage High Input Voltage Low Output Voltage Null Input Capacitance CONDITION MIN TYP MAX UNITS No Load (0 - 100KBPS) No Load (0 - 100KBPS) +11 No Load (0 - 100KBPS) 500 µA No Load (0 - 100KBPS) 500 µA 475 uA -11 mA STROBE = HIGH STROBE = HIGH -475 Short to Ground (See Note: 1) Short to Ground (See Note: 1) Short to Ground VMIN=0 (See Note: 2) VMIN=0 (See Note: 2) Short to Ground mA uA 150 mA -80 mA -150 mA +80 mA 1.0 µA -1.0 µA 2.0 V 0.5 V No Load (0 -100KBPS) +VREF -.25 +VREF +.25 V VOL No Load (0 -100KBPS) -VREF -.25 -VREF +.25 V VNULL CIN No Load (0-100KBPS) -250 +250 mV 15 See Note 1 pF Note 1. Not tested, but characterized at initial device design and after major process and/or design change which affects this parameter. Note 2. Interchangeability of force and sense is acceptable. AC ELECTRICAL CHARACTERISTICS +V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL Rise Time (AOUT, BOUT) Fall Time (AOUT, BOUT) CONDITION MIN tR CA = CB = 75pF See Figure 3. 1.0 1.0 TYP MAX UNITS 2.0 µs tF CA = CB = 75pF See Figure 3. 2.0 µs Propagtion Delay Input to Output t PLH CA = CB = 75pF See Figure 3. 3.0 µs Propagtion Delay Input to Output t PHL CA = CB = 75pF See Figure 3. 3.0 µs DATA (B) 0V VREF AOUT 0V 2.0V 0.5V 50% DATA (A) 0V 50% 2.0V 0.5V ADJUST BY CA +4.75V to +5.25V ADJUST BY CA -VREF t PHL +VREF BOUT 0V -VREF 50% 50% t PLH -4.75V to -5.25V ADJUST BY CB ADJUST BY CB -4.75V to -5.25V 2VREF tR +4.75V to +5.25V HIGH DIFFERENTIAL OUTPUT 0V +9.5V to +10.5V NULL (AOUT - BOUT) NOTE: OUTPUTS UNLOADED tF -2VRE LOW Figure 3. SWITCHING WAVEFORMS HOLT INTEGRATED CIRCUITS 4 -9.5V to -10.5V HI-8382, HI-8383 HI-8382 PACKAGE THERMAL CHARACTERISTICS MAXIMUM ARINC LOAD PA C K A G E S T Y L E ARINC 429 DATA RATE 1 2 Ta = 125°C Ta = 25°C Ta = 85°C Ta = 125°C 17.6 17.2 17.0 48 107 142 25.4 24.5 24.2 56 11 0 150 Low Speed 17.9 17.4 17.1 41 103 145 High Speed 25.8 24.8 24.4 47 11 2 147 3 4 5, 6, 7 A OUT and B OUT Shorted To Ground PA C K A G E S T Y L E ARINC 429 DATA RATE 1 Low Speed 28 Lead PLCC S U P P LY C U R R E N T ( m A ) 2 J U N C T I O N T E M P, T j ( ° C ) Ta = 25°C Ta = 85°C Ta = 125°C Ta = 25°C Ta = 85°C Ta = 125°C 60.1 55.7 52.4 11 0 157 194 3 High Speed 16 Lead Ceramic SB DIP J U N C T I O N T E M P, T j ( ° C ) Ta = 85°C High Speed 16 Lead Ceramic SB DIP S U P P LY C U R R E N T ( m A ) Ta = 25°C Low Speed 28 Lead PLCC 7 4 63.1 56.3 52.3 100 150 182 Low Speed 62.1 56.2 53.0 90 145 180 High Speed 64.0 56.2 52.2 86 144 176 Notes: 1. All data taken in still air on devices soldered to a single layer copper PCB (3" X 4.5" X .062"). 2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8. 3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF. 4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF as this is considered unrealistic for high speed operation. 5. Similar results would be obtained with AOUT shorted to BOUT. 6. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended. 7. Data will vary depending on air flow and the method of heat sinking employed. ORDERING INFORMATION HI - 838x x x - xx (Ceramic) PART NUMBER TEMPERATURE RANGE FLOW BURN IN Blank -40°C to +85°C I No T -55°C to +125°C T No M-01 -55°C to +125°C M Yes (1) M-03 -55°C to +125°C DSCC Yes (1) & (2) PART NUMBER NOTES PACKAGE DESCRIPTION LEAD FINISH NOTES C 16 PIN CERAMIC SIDE BRAZED DIP (16C) Gold (3) & (1) S 28 PIN CERAMIC LEADLESS CHIP CARRIER (28S) Gold (3) & (1) U 32 PIN CERQUAD (32U) not available with ‘M’ flow PART NUMBER Tin/Lead Solder OUTPUT SERIES RESISTANCE FUSE 8382 37.5 Ohms Yes 8383 13 Ohms No (1) Process Flows M and DSCC always have Tin/Lead (Sn/Pb) solder lead finish. (2) DSCC SMD# 5962-8687901EA. Only available in “C” package with Sn/Pb solder lead finish. (3) Gold terminal finish is Pb-Free, RoHS compliant. HOLT INTEGRATED CIRCUITS 5 HI-8382, HI-8383 HI - 838xJ x x (Plastic) PART NUMBER LEAD FINISH Tin / Lead (Sn / Pb) Solder Blank 100% Matte Tin (Pb-free, RoHS compliant) F PART NUMBER TEMPERATURE RANGE FLOW BURN IN Blank -40°C to +85°C I No T -55°C to +125°C T No PART NUMBER OUTPUT SERIES RESISTANCE FUSE PACKAGE DESCRIPTION 8382J 28 PIN PLASTIC PLCC (28J) (1) 37.5 Ohms Yes 8383J 28 PIN PLASTIC PLCC (28J) (1) 13 Ohms No (1) NOT RECOMMENDED FOR NEW DESIGNS. The newer HI-3182PJxx and HI-3183PJxx are drop-in replacements for the older HI-8382Jxx and HI-8383Jxx respectively. ADDITIONAL PIN CONFIGURATIONS N/C N/C N/C N/C DATA(B) CB N/C N/C BOUT SYNC STROBE N/C VREF V1 N/C N/C (See page 1 for the 16-pin Ceramic Side-Brazed DIP Package ) 4 29 28 27 26 25 24 23 22 21 CLOCK V1 N/C VREF STROBE SYNC N/C 30 31 32 1 2 3 4 HI-8382U HI-8382UT 20 19 18 17 16 15 14 N/C DATA (A) N/C N/C CA N/C N/C N/C N/C +V GND N/C -V N/C 3 2 1 28 27 26 25 CLOCK 5 24 N/C 6 7 8 HI-8382S HI-8382ST 23 DATA (B) 22 CB 9 21 N/C 10 20 N/C 19 N/C 11 5 6 7 8 9 10 11 12 13 N/C AOUT -V GND +V BOUT N/C N/C N/C N/C DATA(A) CA N/C N/C N/C AOUT 12 13 14 15 16 17 18 28-PIN CERAMIC LCC SYNC STROBE N/C VREF V1 N/C N/C 32-PIN J-LEAD CERQUAD 4 N/C DATA (A) N/C N/C CA N/C N/C 3 2 1 2 8 2 7 26 5 25 6 24 7 8 9 HI-8382J HI-8382JT 10 23 22 21 20 11 19 CLOCK N/C DATA (B) CB N/C N/C N/C N/C AOUT -V GND +V BOUT N/C 12 13 14 15 16 17 18 28-PIN PLASTIC PLCC HOLT INTEGRATED CIRCUITS 6 HI-8382, HI-8383 REVISION HISTORY P/N DS8382 Rev Date E F 02/26/09 09/16/11 Description of Change Clarified the temperature ranges, and Note (1) in the Ordering Information. Realigned pin names and numbers with package pin locations in Additional Pin Configuration drawings. HOLT INTEGRATED CIRCUITS 7 HI-8382 PACKAGE DIMENSIONS 16-PIN CERAMIC SIDE-BRAZED DIP inches (millimeters) Package Type: 16C .810 max (20.574) .295 ±.010 (7.493 ±.254) .050 ±.005 (1.270 ±.127) PIN 1 .200 max (5.080) .035 ± .010 (.889 ±.254) BASE PLANE .125 min (3.175) .010 ±.002 (.254 ±.051) SEATING PLANE .018 ± .002 (.457 ±.051) .100 BSC (2.54) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .300 ± .010 (7.620 ±.254) 28-PIN PLASTIC PLCC inches (millimeters) Package Type: 28J PIN NO. 1 PIN NO. 1 IDENT .045 x 45° .045 x 45° .050 (1.27) BSC .453 ± .003 (11.506 ±.076) SQ. .490 ± .005 (12.446 ±.127) SQ. .031 ±.005 (.787 ±.127) .017 ±.004 (.432 ±.102) See Detail A .010 ± .001 (.254 ± .03) .173 ±.008 (4.394 ±.203) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .020 (.508) min .410 ±.020 (10.414 ±.508) HOLT INTEGRATED CIRCUITS 8 DETAIL A R .035 .889 HI-8382 PACKAGE DIMENSIONS 28-PIN CERAMIC LEADLESS CHIP CARRIER inches (millimeters) Package Type: 28S .020 INDEX (.508) .080 ±.020 (2.032 ±.508) PIN 1 PIN 1 .050 ±.005 (1.270 ±.127) .451 ±.009 (11.455 ±.229) SQ. .050 BSC (1.270) .025 ±.003 (.635 ±.076) .008R ± .006 (.203R ±.152) .040 x 45° 3PLS (1.016 x 45° 3PLS) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 32-PIN J-LEAD CERQUAD inches (millimeters) Package Type: 32U 31 32 1 2 .450 ±.008 (11.430 ±.203) .488 ±.008 (12.395 ±.203) .420 ±.012 (10.668 ±.305) .588 ±.008 (14.935 ±.203) .550 ± .009 (13.970 ± .229) .190 max (4.826) .040 typ (1.016) .050 .019 ± .003 BSC (1.270) (.483 ± .076) .520 ±.012 (13.208 ±.305) .083 ±.009 (2.108 ±.229) HOLT INTEGRATED CIRCUITS 9 BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95)