Hynix HY57V161610DTC-10 2 banks x 512k x 16 bit synchronous dram Datasheet

HY57V161610D
2 Banks x 512K x 16 Bit Synchronous DRAM
DESCRIPTION
THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic
applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A
burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a
new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.0V to 3.6V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin
pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of system
clock
•
Data mask function by UDQM/LDQM
•
Internal two banks operation
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
•
Programmable CAS Latency ; 1, 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V161610DTC-5
200MHz
HY57V161610DTC-55
183MHz
HY57V161610DTC-6
166MHz
HY57V161610DTC-7
143MHz
HY57V161610DTC-8
125MHz
HY57V161610DTC-10
100MHz
HY57V161610DTC-15
66MHz
Organization
Interface
Package
2Banks x 512Kbits x 16
LVTTL
400mil
50pin TSOP II
Note :
1. VDD(min) of HY57V161610DTC-5/55 is 3.15V
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for
use of circuits described. No patent licenses are implied
Rev. 4.0/Aug. 02
1
HY57V161610D
PIN CONFIGURATION
V DD
DQ0
DQ1
V SSQ
DQ2
DQ3
V DDQ
DQ4
DQ5
V SSQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
A11
A10
A0
A1
A2
A3
V DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50pin TSOP II
400mil x 825mil
0.8mm pin pitch
V SS
DQ15
DQ14
VSSQ
DQ13
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are referenced to the SDRAM on the rising
edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one of the
states among power down, suspend or self refresh.
CS
Chip Select
Command input enable or mask except CLK, CKE and DQM
BA
Bank Address
Select either one of banks during both RAS and CAS activity.
A0 ~ A10
Address
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation.
Refer function truth table for details
LDQM, UDQM
Data Input/Output Mask
DQM control output buffer in read mode and mask input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuit and input buffer
VDDQ/VSSQ
Data Output Power/Ground
Power supply for DQ
NC
No Connection
No connection
Rev. 4.0/Aug. 02
2
HY57V161610D
FUNCTIONAL BLOCK DIAGRAM
1Mx16 Synchronous DRAM
Row Decoder
Ref. Addr.[0:11]
Address[0:10]
Refresh
Counter
Auto/Self Refresh
Refresh
Interval Timer
Row Addr. Latch/Predecoder
Self Refresh Counter
512Kx16
Bank 0
Sense AMP & I/O gates
Column Decoder
Precharge
CKE
Row Active
CS
RAS
CAS
State Machine
BA(A11)
Address
Register
Column Addr.
Latch & Counter
Column Active
Burst Length
Counter
Overflow
WE
UDQM
Column Decoder
Sense AMP & I/O gates
Row Addr. Latch/Predecoder
LDQM
Mode Register
Rev. 4.0/Aug. 02
Data Input/Output Buffers
CLK
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
512Kx16
Bank 1
Test Mode
I/O Control
3
HY57V161610D
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1
W
Soldering Temperature·Time
TSOLDER
260·10
°C ·Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0°C to 70°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
1, 2, 3
Input high voltage
VIH
2.0
3.0
VDD + 0.3
V
1, 4
Input low voltage
VIL
-0.5
0
0.8
V
1, 5
Note
Note :
1.All voltages are referenced to VSS = 0V.
2.VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2
3.VDD(min) of HY57V161610DTC-5/55 is 3.15V
4.VIH(max) is acceptable 4.6V AC pulse width with ≤ 10ns of duration.
5.VIL(min) is acceptable -1.5V AC pulse width with ≤ 10ns of duration.
AC OPERATING CONDITION (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0V)
Parameter
Symbol
Value
Unit
VIH / VIL
2.4/0.4
V
Vtrip
1.4
V
Input rise / fall time
tR / tF
1
ns
Output timing measurement reference level
Voutref
1.4
V
CL
30
pF
AC input high / low level voltage
Input timing measurement reference level voltage
Output load capacitance for access time measurement
1
Note :
1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF).
For details, refer to AC/DC output load circuit.
2. VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns
3. VDD(min) of HY57V161610DTC-5/55 is 3.15V‘
Rev. 4.0/Aug. 02
4
HY57V161610D
CAPACITANCE (TA=25°C, f=1MHz)
Parameter
Pin
Symbol
Min
Max
Unit
CLK
CI1
2.5
4
pF
Input capacitance
A0 ~ A10, BA
CKE, CS, RAS, CAS, WE, UDQM, LDQM
CI2
2.5
5
pF
Data input / output capacitance
DQ0 ~ DQ15
CI/O
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
30pF
30pF
AC Output Load Circuit
DC Output Load Circuit
DC CHARACTERISTICS I (TA=0°C to 70°C)
Parameter
Symbol
Min.
Max
Unit
Note
Power Supply Voltage
VDD
3.0
3.6
V
1, 2
Input leakage current
IL
-1
1
uA
3
Output leakage current
IO
-1
1
uA
4
Output high voltage
VOH
2.4
-
V
IOH = -4mA
Output low voltage
VOL
-
0.4
V
IOL =+4mA
Note :
1.VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns.
2.VDD(min) of HY57V161610DTC-5/55 is 3.15V
3.VIN = 0 to 3.6V, All other pins are not under test = 0V
4.DOUT is disabled, VOUT=0 to 3.6V
Rev. 4.0/Aug. 02
5
HY57V161610D
DC CHARACTERISTICS II (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0VNote1,2)
Speed
Parameter
Symbol
Test Condition
-5
-55
-6
-7
-8
-10
-15
130
130
120
110
110
110
100
Operating Current
IDD1
Burst Length=1, One bank active
tRAS ≥ tRAS(min),tRP ≥ tRP(min),
IO=0mA
Precharge Standby
Current
in power down mode
IDD2P
CKE ≤ VIL(max), tCK = min.
1
IDD2PS
CKE ≤ VIL(max), tCK = ∞
1
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK =
min
Input signals are changed one time
during 2Clks. All other pins ≥ VDD-0.2V
or ≤ 0.2V
20
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
15
IDD3P
CKE ≤ VIL(max), tCK = min
3.0
IDD3PS
CKE ≤ VIL(max), tCK = ∞
3.0
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK =
min
Input signals are changed one time
during 2CLKs. All other pins ≥ VDD0.2V or ≤ 0.2V
50
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable
30
IDD4
tCK ≥ tCK(min),
tRAS ≥ tRAS(min),
IO=0mA
All banks active
Precharge Standby
Current
in non power down
mode
Active Standby Current
in power down mode
Active Standby Current
in non power down
mode
Burst Mode Operating
Current
Unit
Note
mA
2
mA
mA
mA
mA
CL=3
130
130
120
110
110
90
80
CL=2
-
-
110
110
-
-
-
CL=1
-
-
-
-
-
-
70
130
130
110
110
110
110
100
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
2
mA
3
mA
mA
Note :
1.VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns.
2.VDD(min) of HY57V161610DTC-5/55 is 3.15V
3.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
Rev. 4.0/Aug. 02
6
HY57V161610D
AC CHARACTERISTICS
(TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0VNote1,2)
-5
Parameter
-55
-6
-7
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Note
ns
3
CL=3
tCK3
5
5.5
6
-
7
-
CL=2
tCK2
-
-
10
-
10
-
CL=1
tCK1
-
-
-
-
-
-
Clock high pulse width
tCHW
1.75
2
2
-
2.5
-
ns
4
Clock low pulse width
tCLW
1.75
2
2
-
2.5
-
ns
4
-
5.5
-
6
ns
3
System clock
cycle time
Access time
from clock
CL=3
tAC3
4.5
5
CL=2
tAC2
-
6
-
6
CL=1
tAC1
-
-
-
-
Data-out hold time
tOH
1.5
2
2
-
2.5
-
ns
Data-Input setup time
tDS
1.5
1.5
1.5
-
1.75
-
ns
4
Data-Input hold time
tDH
1
1
1
-
1
-
ns
4
Address setup time
tAS
1.5
1.5
1.5
-
1.75
-
ns
4
Address hold time
tAH
1
1
1
-
1
-
ns
4
CKE setup time
tCKS
1.5
1.5
1.5
-
1.75
-
ns
4
CKE hold time
tCKH
1
1
1
-
1
-
ns
4
Command setup time
tCS
1.5
1.5
1.5
-
1.75
-
ns
4
Command hold time
tCH
1
1
1
-
1
-
ns
4
CLK to data output in low Ztime
tOLZ
2
2
2
-
2
-
ns
CLK to data output in high
Z-time
tOHZ
2
2
6
2
7
ns
Rev. 4.0/Aug. 02
5
2
5.5
7
HY57V161610D
AC CHARACTERISTICS
-8
Parameter
- continued -
(TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0VNote1,2)
-10
-15
Symbol
Min
Max
Min
Max
Min
Max
Unit
Note
ns
3
CL=3
tCK3
8
-
10
-
15
-
CL=2
tCK2
12
-
12
-
15
-
CL=1
tCK1
-
-
-
-
15
-
Clock high pulse width
tCHW
3
-
3
-
3
-
ns
4
Clock low pulse width
tCLW
3
-
3
-
3
-
ns
4
CL=3
tAC3
-
6
-
7
-
7
CL=2
tAC2
-
6
-
7
-
7
ns
3
CL=1
tAC1
-
-
-
-
-
14
Data-out hold time
tOH
2.5
-
2.5
-
2.5
-
ns
Data-Input setup time
tDS
2
-
2.5
-
2.5
-
ns
4
Data-Input hold time
tDH
1
-
1
-
1
-
ns
4
Address setup time
tAS
2
-
2.5
-
2.5
-
ns
4
Address hold time
tAH
1
-
1
-
1
-
ns
4
CKE setup time
tCKS
2
-
2.5
-
2.5
-
ns
4
CKE hold time
tCKH
1
-
1
-
1
-
ns
4
Command setup time
tCS
2
-
2.5
-
2.5
-
ns
4
Command hold time
tCH
1
-
1
-
1
-
ns
4
CLK to data output in low Z-time
tOLZ
2
-
2
-
2
-
ns
CLK to data output in high Z-time
tOHZ
2
8
3
10
3
15
ns
System clock cycle
time
Access time from
clock
Note :
1.VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns.
2.VDD(min) of HY57V161610DTC-5/55 is 3.15V
3.tCK2 is 8.9ns only when tAC2 is 7.9ns in HY57V161610DTC-6 and HY57V161610DTC-7.
4.Assume tR / tF (input rise and fall time ) is 1ns.
Rev. 4.0/Aug. 02
8
HY57V161610D
AC CHARACTERISTICS
(TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0VNote1,2))
-5
Paramter
-6
-7
Unit
Min
Operation
-55
Symbol
Max
Min
Max
Min
Max
Min
Max
tRC
55
55
60
-
70
-
ns
tRRC
55
55
60
-
70
-
ns
RAS to CAS delay
tRCD
15
16.5
18
-
20
-
ns
RAS active time
tRAS
40
40
100K
45
100K
ns
tRP
3
3
3
-
3
-
CLK
RAS to RAS bank active delay
tRRD
2
2
2
-
2
-
CLK
CAS to CAS bank active delay
tCCD
1
1
1
-
1
-
CLK
Write command to data-in delay
tWTL
0
0
0
-
0
-
CLK
Data-in to precharge command
tDPL
1
1
1
-
1
-
CLK
Data-in to active command
tDAL
4
4
4
-
4
-
CLK
DQM to data-in Hi-Z
tDQZ
2
2
2
-
2
-
CLK
DQM to data mask
tDQM
0
0
0
-
0
-
CLK
MRS to new command
tMRD
2
2
2
-
2
-
CLK
Precharge to data output Hi-Z
tPROZ
3
3
3
-
3
-
CLK
Power down exit time
tPDE
1
1
1
-
1
-
CLK
Self refresh exit time
tSRE
1
1
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
ms
Note
RAS cycle time
Auto Refresh
RAS precharge time
Rev. 4.0/Aug. 02
100K
64
38.5
100K
64
3
9
HY57V161610D
AC CHARACTERISTICS
-8
Paramter
- continued -
(TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0VNote1,2)
-10
-15
Symbol
Unit
Min
Max
Min
Max
Min
Max
tRC
70
-
70
-
70
-
ns
tRRC
70
-
80
-
80
-
ns
RAS to CAS delay
tRCD
20
-
20
-
20
-
ns
RAS active time
tRAS
45
100K
45
100K
45
100K
ns
tRP
3
-
2
-
2
-
CLK
RAS to RAS bank active delay
tRRD
2
-
2
-
2
-
CLK
CAS to CAS bank active delay
tCCD
1
-
1
-
1
-
CLK
Write command to data-in delay
tWTL
0
-
0
-
0
-
CLK
Data-in to precharge command
tDPL
1
-
1
-
1
-
CLK
Data-in to active command
tDAL
4
-
3
-
3
-
CLK
DQM to data-in Hi-Z
tDQZ
2
-
2
-
2
-
CLK
DQM to data mask
tDQM
0
-
0
-
0
-
CLK
MRS to new command
tMRD
2
-
2
-
2
-
CLK
Precharge to data output Hi-Z
tPROZ
3
-
3
-
3
-
CLK
Power down exit time
tPDE
1
-
1
-
1
-
CLK
Self refresh exit time
tSRE
1
-
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
-
64
ms
Operation
Note
RAS cycle time
Auto Refresh
RAS precharge time
3
Note :
1. VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns.
2.VDD(min) of HY57V161610DTC-5/55 is 3.15V
3. A new command can be given tRRC after self refresh exit.
DEVICE OPERATING OPTION TABLE
HY57V161610DTC-5
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
200MHz
3CLKs
3CLKs
8CLKs
11CLKs
3CLKs
4.5ns
1.5ns
183MHz
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5ns
2ns
166MHz
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2ns
Rev. 4.0/Aug. 02
10
HY57V161610D
HY57V161610DTC-55
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
183MHz
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5ns
2ns
166MHz
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2ns
143MHz
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2.5ns
HY57V161610DTC-6
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
166MHz
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2ns
143MHz
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2.5ns
125MHz
3CLKs
2CLKs
6CLKs
9CLKs
3CLKs
6ns
2.5ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
143MHz
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2.5ns
125MHz
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
2.5ns
100MHz
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
7ns
2.5ns
HY57V161610DTC-7
HY57V161610DTC-8
125MHz
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
2.5ns
100MHz
3CLKs
2CLKs
5CLKs
7CLKs
2CLKs
7ns
2.5ns
83MHz
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
7ns
2.5ns
tRCD
tRAS
tRC
tRP
tAC
tOH
HY57V161610DTC-10
CAS Latency
100MHz
3CLKs
2CLKs
5CLKs
7CLKs
2CLKs
7ns
2.5ns
83MHz
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
7ns
2.5ns
HY57V161610DTC-15
66MHz
Rev. 4.0/Aug. 02
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
1CLKs
2CLKs
4CLKs
6CLKs
2CLKs
14ns
2.5ns
11
HY57V161610D
COMMAND TRUTH TABLE
Command
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Row Address
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
Read
Read with Auto precharge
Write
H
X
L
H
L
L
X
Write with Auto precharge
A0~A9
A10/
AP
CKEn-1
Column
Address
Column
Address
Precharge All Bank
H
X
L
L
H
L
X
H
U/LDQM
H
Auto Refresh
H
H
L
L
L
Burst-READ-Single-WRITE
H
X
L
L
Entry
H
L
L
H
Exit
L
H
Self Refresh
X
H
H
H
L
V
H
L
V
H
H
X
L
V
X
V
X
H
X
X
L
L
X
A9 Pin High
(Other Pins OP code)
L
L
H
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge power
down
V
L
X
X
1
Entry
L
Note
X
Precharge selected Bank
Burst Stop
BA
X
X
Exit
Entry
L
H
H
L
Clock Suspend
Exit
L
X
H
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. X=Do not care, L=Low, H=High, BA=Bank Address, RA= Row Address, CA=Column Address, Opcode=Operand Code,
NOP=No Operation.
Rev. 4.0/Aug. 02
12
HY57V161610D
PACKAGE INFORMATION
400mil 50pin Thin Small Outline Package (TC)
1Mx16 Synchronous DRAM
UNIT : mm(inch)
11.938(0.4700)
10.262(0.4040)
11.735(0.4620)
10.059(0.3960)
0.8(0.0315 BSC)
0.45(0.0177)
0.30(0.0118)
1.2(0.0472)
1.0(0.0394)
0.150(0.0059)
21.057(0.8290)
20.879(0.8220)
0.646 REF
0.050(0.0020)
GAGE PLANE
0~5deg
0.597(0.0235)
0.406(0.0160)
Rev. 4.0/Aug. 02
0.210(0.0083)
0.120(0.0118)
13
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