ON MC100LVEL13DWG 3.3v ecl dual 1:3 fanout buffer Datasheet

MC100LVEL13
3.3VECL Dual 1:3 Fanout
Buffer
Description
The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer.
The Low Output−Output Skew of the device makes it ideal for
distributing two different frequency synchronous signals.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to VEE, The D input will bias
around VCC/2 and the Q output will go LOW.
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Features
•
•
•
•
•
•
•
•
•
•
•
500 ps Typical Propagation Delays
50 ps Output−Output Skews
ESD Protection: >2 kV Human Body Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 143 devices
•
• Pb−Free Packages are Available*
SO−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL13
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 5
1
Publication Order Number:
MC100LVEL13/D
MC100LVEL13
Q1a Q1a Q2a Q2a VCC Q2b Q2b Q1b Q1b
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
VEE
Table 1. PIN DESCRIPTION
11
PIN
FUNCTION
Qna, Qna
Qnb, Qnb
CLKn, CLKn
VCC
VEE
ECL Differential Clock Outputs
ECL Differential Clock Outputs
ECL Differential Clock Inputs
Positive Supply
Negative Supply
10
Q0a Q0a VCC CLKa CLKa CLKb CLKb VCC Q0b Q0b
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20−Lead SOIC
(Top View)
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction to Ambient)
0 lfpm
500 lfpm
20 SOIC
20 SOIC
90
60
°C/W
°C/W
qJC
Thermal Resistance (Junction to Case)
Standard Board
20 SOIC
30 to 35
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
Pb
Pb−Free
VI VCC
VI VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
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MC100LVEL13
Table 3. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 1)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
30
38
Min
85°C
Typ
Max
30
38
Min
Typ
Max
Unit
32
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 2)
1470
1605
1745
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1490
1825
1490
1825
1490
1825
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
VPP < 500 mV
VPP y 500 mV
1.3
1.5
2.9
2.9
1.2
1.4
2.9
2.9
1.2
1.4
2.9
2.9
V
V
150
mA
IIH
Input HIGH Current
IIL
Input LOW Current
150
CLKn
CLKn
0.5
−300
150
0.5
−300
0.5
−300
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 4. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 4)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
30
38
Min
85°C
Typ
Max
30
38
Min
Typ
Max
Unit
32
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 5)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 5)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
VPP < 500 mV
VPP y 500 mV
−2.0
−1.8
−0.4
−0.4
−2.1
−1.9
−0.4
−0.4
−2.1
−1.9
−0.4
−0.4
V
V
150
mA
IIH
Input HIGH Current
IIL
Input LOW Current
150
CLKn
CLKn
0.5
−300
150
0.5
−300
0.5
−300
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
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MC100LVEL13
Table 5. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 7)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
600
430
TBD
85°C
Typ
Max
Min
620
450
Max
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay CLK to Q/Q
tsk(O)
Output−Output Skew
Any Qa to Qa, Any Qb to Qb
Any Qa to Any Qb
50
75
50
75
50
75
tskew
Duty Cycle Skew |tPLH−tPHL|
50
50
50
tJITTER
Cycle−to−Cycle Jitter
VPP
Input Swing (Note 8)
150
1000
150
1000
150
1000
mV
tr
tf
Output Rise/Fall Times Q
(20% − 80%)
230
500
230
500
230
500
ps
TBD
TBD
Unit
fmax
410
TBD
Typ
500
TBD
GHz
640
TBD
ps
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. VEE can vary ±0.3 V.
8. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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MC100LVEL13
ORDERING INFORMATION
Package
Shipping†
MC100LVEL13DW
SO−20 WB
38 Units / Rail
MC100LVEL13DWG
SO−20 WB
(Pb−Free)
38 Units / Rail
MC100LVEL13DWR2
SO−20 WB
1000 / Tape & Reel
MC100LVEL13DWR2G
SO−20 WB
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100LVEL13
PACKAGE DIMENSIONS
SO−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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