Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 LMH6624 and LMH6626 Single/Dual Ultra Low Noise Wideband Operational Amplifier 1 Features 3 Description • The LMH6624 and LMH6626 devices offer wide bandwidth (1.5 GHz for single, 1.3 GHz for dual) with very low input noise (0.92 nV/√Hz, 2.3 pA/√Hz) and ultra-low dc errors (100 μV VOS, ±0.1 μV/°C drift) providing very precise operational amplifiers with wide dynamic range. This enables the user to achieve closed-loop gains of greater than 10, in both inverting and non-inverting configurations. 1 • • • • • • • • • • • VS = ±6 V, TA = 25°C, AV = 20 (Typical Values Unless Specified) Gain Bandwidth (LMH6624) 1.5 GHz Input Voltage Noise 0.92 nV/√Hz Input Offset Voltage (limit over temp) 700 µV Slew Rate 350 V/μs Slew Rate (AV = 10) 400 V/μs HD2 at f = 10 MHz, RL = 100 Ω −63 dBc HD3 at f = 10 MHz, RL = 100 Ω −80 dBc Supply Voltage Range (Dual Supply) 2.5 V to 6 V Supply Voltage Range (Single Supply) 5 V to 12 V Improved Replacement for the CLC425 (LMH6624) Stable for Closed Loop |AV| ≥ 10 2 Applications • • • • • • • Instrumentation Sense Amplifiers Ultrasound Pre-amps Magnetic Tape & Disk Pre-amps Wide Band Active Filters Professional Audio Systems Opto-electronics Medical Diagnostic Systems The LMH6624 (single) and LMH6626 (dual) traditional voltage feedback topology provide the following benefits: balanced inputs, low offset voltage and offset current, very low offset drift, 81dB open loop gain, 95dB common mode rejection ratio, and 88dB power supply rejection ratio. The LMH6624 and LMH6626 devices operate from ±2.5 V to ±6 V in dual supply mode and from 5 V to 12 V in single supply configuration. LMH6624 is offered in SOT-23-5 and SOIC-8 packages. The LMH6626 is offered in SOIC-8 and VSSOP-8 packages. Device Information(1) PART NUMBER LMH6624 LMH6626 PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm × 1.60 mm SOIC (8) 4.90 mm × 3.91 mm SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Voltage Noise vs. Frequency 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics ±2.5 V .............................. Electrical Characteristics ±6 V ................................. Typical Characteristics .............................................. Detailed Description ............................................ 17 7.1 Overview ................................................................. 17 7.2 Feature Description................................................. 17 7.3 Device Functional Modes........................................ 22 8 Application and Implementation ........................ 23 8.1 Application Information............................................ 23 8.2 Typical Application .................................................. 23 9 Power Supply Recommendations...................... 26 10 Layout................................................................... 26 10.1 Layout Guidelines ................................................. 26 10.2 Layout Example .................................................... 27 11 Device and Documentation Support ................. 28 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 28 28 28 28 28 12 Mechanical, Packaging, and Orderable Information ........................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (March 2013) to Revision G Page • Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information ............................................................................................................... 1 • Added Input Current parameter in Absolute Maximum Ratings ............................................................................................ 4 • Added Operating supply voltage (V+ - V-) parameter in Recommended Operating Conditions............................................ 4 • Revised paragraph beginning with "As seen in ..." in Total Input Noise vs. Source Resistance ........................................ 19 • Changed from 33.5 Ω to 26 Ω in Total Input Noise vs. Source Resistance......................................................................... 19 • Changed from 6.43 kΩ to 3.1 kΩ in Total Input Noise vs. Source Resistance .................................................................... 19 Changes from Revision E (March 2013) to Revision F Page • Changed layout of National Data Sheet to TI format ............................................................................................................. 1 • Changed from 464 Ω to 283 Ω ............................................................................................................................................. 19 2 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 5 Pin Configuration and Functions 5-Pin SOT-23 (LMH6624) Package DBV Top View 1 5 OUT V N/C + -IN V - 1 2 8 - 7 + 6 N/C V + 2 +IN 3 - + +IN 8-Pin SOIC Package D and VSSOP (LMH6626) Package D or DGK Top View 8-Pin SOIC (LMH6624) Package D Top View 4 3 -IN V - 4 5 OUT N/C Pin Functions PIN NUMBER NAME LMH6624 LMH6626 I/O DESCRIPTION DBV D DGK or D -IN 4 2 – I Inverting Input +IN 3 3 – I Non-inverting Input IN A- – – 2 I Inverting Input Channel A IN B- – – 6 I Inverting Input Channel B IN A+ – – 3 I Non-inverting Input Channel A IN B+ – – 5 I Non-inverting Input Channel B N/C – 1, 5, 8 – –– No Connection OUT 1 6 – O Output OUT A – – 1 O Output Channel A OUT B – – 7 O Output Channel B V- 2 4 4 I Negative Supply V+ 5 7 8 I Positive Supply Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 3 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN VIN Differential + − Supply voltage (V - V ) Voltage at Input pins Junction temperature (2) V 13.2 V V ±10 mA Infrared or convection (20 sec.) 235 °C Wave soldering (10 sec.) 260 °C 150 °C 150 °C (2) Storage temperature (1) UNIT ±1.2 V+ +0.5, V− −0.5 Input Current Soldering information MAX -65 Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Machine model (2) ±200 UNIT V Human body model, 1.5 kΩ in series with 100 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. Machine Model, 0 Ω in series with 200 pF. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) Operating temperature (2) Operating supply voltage (V+ - V-) (1) (2) MIN MAX UNIT −40 +125 °C ±2.25 ±6.3 V Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. 6.4 Thermal Information LMH6624 THERMAL METRIC RθJA (1) (2) 4 (1) Junction-to-ambient thermal resistance (2) LMH6626 DBV D DGK D 5 PINS 8 PINS 8 PINS 8 PINS 265 166 235 166 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 6.5 Electrical Characteristics ±2.5 V Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 2.5 V, V− = −2.5 V, VCM = 0 V, AV = +20, RF = 500 Ω, RL = 100 Ω. See (1). PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT DYNAMIC PERFORMANCE −3dB BW fCL VO = 400 mVPP (LMH6624) 90 VO = 400 mVPP (LMH6626) 80 VO = 2 VPP, AV = +20 (LMH6624) 300 VO = 2 VPP, AV = +20 (LMH6626) 290 VO = 2 VPP, AV = +10 (LMH6624) 360 MHz SR Slew rate (4) VO = 2 VPP, AV = +10 (LMH6626) 340 tr Rise time VO = 400 mV Step, 10% to 90% 4.1 ns tf Fall time VO = 400 mV Step, 10% to 90% 4.1 ns ts Settling time 0.1% VO = 2 VPP (Step) 20 ns V/μs DISTORTION and NOISE RESPONSE f = 1 MHz (LMH6624) 0.92 f = 1 MHz (LMH6626) 1.0 f = 1 MHz (LMH6624) 2.3 f = 1 MHz (LMH6626) 1.8 2nd harmonic distortion fC = 10 MHz, VO = 1 VPP, RL 100 Ω −60 dBc 3rd harmonic distortion fC = 10 MHz, VO = 1 VPP, RL 100 Ω −76 dBc en Input referred voltage noise in Input referred current noise HD2 HD3 nV/√Hz pA/√Hz INPUT CHARACTERISTICS VOS IOS IB Input offset voltage VCM = 0 V Average drift (5) VCM = 0 V Input offset current VCM = 0 V Average drift (5) VCM = 0 V +0.95 μV/°C ±0.25 −1.5 -40°C ≤ TJ ≤ 125°C −0.05 −2.0 +1.5 +2.0 2 13 mV μA nA/°C +20 μA Average drift (5) VCM = 0 V 12 nA/°C Common Mode 6.6 MΩ Differential Mode 4.6 kΩ Common Mode 0.9 Differential Mode 2.0 Input capacitance (6) CMRR Common mode rejection ratio (2) (3) (4) (5) (6) +0.75 VCM = 0 V CIN (1) −0.25 −0.95 Input bias current Input resistance (6) RIN −0.75 -40°C ≤ TJ ≤ 125°C -40°C ≤ TJ ≤ 125°C +25 Input Referred, VCM = −0.5 to +1.9 V 87 Input Referred, VCM = −0.5 to +1.75 V 85 -40°C ≤ TJ ≤ 125°C pF 90 dB Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical Values represent the most likely parametric norm. Slew rate is the slowest of the rising and falling slew rates. Average drift is determined by dividing the change in parameter at temperature extremes into the total temperature change. Simulation results. Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 5 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics ±2.5 V (continued) Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 2.5 V, V− = −2.5 V, VCM = 0 V, AV = +20, RF = 500 Ω, RL = 100 Ω. See (1). PARAMETER TEST CONDITIONS MIN (2) TYP (3) 75 79 MAX (2) UNIT TRANSFER CHARACTERISTICS (LMH6624) RL = 100 Ω, VO = −1 V to +1 V AVOL Large signal voltage gain (LMH6626) RL = 100 Ω, VO = −1 V to +1 V Xt Crosstalk rejection -40°C ≤ TJ ≤ 125°C 70 72 -40°C ≤ TJ ≤ 125°C dB 79 67 −75 f = 1 MHz (LMH6626) dB OUTPUT CHARACTERISTICS RL = 100 Ω VO Output swing No Load RO Output impedance Output short circuit current (LMH6624) Sinking to Ground ΔVIN = −200 mV (7) (8) (LMH6626) Sourcing to Ground ΔVIN = 200 mV (7) (8) (LMH6626) Sinking to Ground ΔVIN = −200 mV (7) (8) IOUT Output current -40°C ≤ TJ ≤ 125°C ±1.4 -40°C ≤ TJ ≤ 125°C ±1.5 ±1.0 V ±1.7 ±1.25 f ≤ 100 KHz (LMH6624) Sourcing to Ground ΔVIN = 200 mV (7) (8) ISC ±1.1 10 90 -40°C ≤ TJ ≤ 125°C 75 90 -40°C ≤ TJ ≤ 125°C mA 120 50 60 -40°C ≤ TJ ≤ 125°C 145 75 60 -40°C ≤ TJ ≤ 125°C mΩ 145 120 50 (LMH6624) Sourcing, VO = +0.8 V Sinking, VO = −0.8 V 100 (LMH6626) Sourcing, VO = +0.8 V Sinking, VO = −0.8 V 75 mA POWER SUPPLY PSRR Power supply rejection ratio IS Supply current (per channel) No Load (7) (8) 6 VS = ±2.0 V to ±3.0 V 82 -40°C ≤ TJ ≤ 125°C 90 11.4 -40°C ≤ TJ ≤ 125°C dB 80 16 18 mA Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is 1.5 ms. Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 6.6 Electrical Characteristics ±6 V Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 6 V, V− = −6 V, VCM = 0 V, AV = +20, RF = 500 Ω, RL = 100 Ω. See (1). PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT DYNAMIC PERFORMANCE −3dB BW fCL VO = 400 mVPP (LMH6624) 95 VO = 400 mVPP (LMH6626) 85 VO = 2 VPP, AV = +20 (LMH6624) 350 VO = 2 VPP, AV = +20 (LMH6626) 320 VO = 2 VPP, AV = +10 (LMH6624) 400 MHz SR Slew rate (4) VO = 2 VPP, AV = +10 (LMH6626) 360 tr Rise time VO = 400 mV Step, 10% to 90% 3.7 ns tf Fall time VO = 400 mV Step, 10% to 90% 3.7 ns ts Settling time 0.1% VO = 2 VPP (Step) 18 ns V/μs DISTORTION and NOISE RESPONSE f = 1 MHz (LMH6624) 0.92 f = 1 MHz (LMH6626) 1.0 f = 1 MHz (LMH6624) 2.3 f = 1 MHz (LMH6626) 1.8 2nd harmonic distortion fC = 10 MHz, VO = 1 VPP, RL = 100 Ω −63 dBc 3rd harmonic distortion fC = 10 MHz, VO = 1 VPP, RL = 100 Ω −80 dBc en Input referred voltage noise in Input referred current noise HD2 HD3 nV/√Hz pA/√Hz INPUT CHARACTERISTICS VOS Input offset voltage VCM = 0 V Average drift (5) VCM = 0 V (LMH6624) VCM = 0 V Input offset current IOS (LMH6626) VCM = 0 V Average drift IB (5) +0.5 +0.7 μV/°C ±0.2 −1.1 -40°C ≤ TJ ≤ 125°C −2.0 -40°C ≤ TJ ≤ 125°C 0.05 −2.5 −2.5 VCM = 0 V 1.1 2.5 0.1 mV 2.0 μA 2.5 0.7 13 nA/°C +20 μA VCM = 0 V Average drift (5) VCM = 0 V 12 nA/°C Common Mode 6.6 MΩ Differential Mode 4.6 kΩ Common Mode 0.9 Differential Mode 2.0 Input resistance (6) CIN Input capacitance (6) CMRR Common mode rejection ratio (2) (3) (4) (5) (6) ±0.10 −0.7 Input bias current RIN (1) −0.5 -40°C ≤ TJ ≤ 125°C -40°C ≤ TJ ≤ 125°C +25 Input Referred, VCM = −4.5 to +5.25 V 90 Input Referred, VCM = −4.5 to +5.0 V 87 -40°C ≤ TJ ≤ 125°C pF 95 dB Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical Values represent the most likely parametric norm. Slew rate is the slowest of the rising and falling slew rates. Average drift is determined by dividing the change in parameter at temperature extremes into the total temperature change. Simulation results. Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 7 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics ±6 V (continued) Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 6 V, V− = −6 V, VCM = 0 V, AV = +20, RF = 500 Ω, RL = 100 Ω. See (1). PARAMETER TEST CONDITIONS MIN (2) TYP (3) 77 81 MAX (2) UNIT TRANSFER CHARACTERISTICS (LMH6624) RL = 100 Ω, VO = −3 V to +3 V AVOL Large signal voltage gain (LMH6626) RL = 100 Ω, VO = −3 V to +3 V Xt Crosstalk rejection -40°C ≤ TJ ≤ 125°C 72 74 -40°C ≤ TJ ≤ 125°C dB 80 70 −75 f = 1MHz (LMH6626) dB OUTPUT CHARACTERISTICS VO -40°C ≤ TJ ≤ 125°C ±4.3 (LMH6624) No Load -40°C ≤ TJ ≤ 125°C ±4.65 Output swing (LMH6626) RL = 100 Ω (LMH6626) No Load RO Output impedance Output short circuit current IOUT Output current ±4.8 ±4.3 -40°C ≤ TJ ≤ 125°C ±4.8 -40°C ≤ TJ ≤ 125°C (LMH6624) Sinking to Ground ΔVIN = −200 mV (7) (8) ±4.9 ±5.2 V ±4.8 ±4.2 ±5.2 ±4.65 f ≤ 100 KHz (LMH6624) Sourcing to Ground ΔVIN = 200 mV (7) (8) ISC ±4.4 (LMH6624) RL = 100 Ω 10 100 -40°C ≤ TJ ≤ 125°C 85 100 -40°C ≤ TJ ≤ 125°C (LMH6626) Sourcing to Ground ΔVIN = 200 mV (7) (8) -40°C ≤ TJ ≤ 125°C (LMH6626) Sinking to Ground ΔVIN = −200 mV (7) (8) -40°C ≤ TJ ≤ 125°C mΩ 156 156 85 65 mA 120 55 65 120 55 (LMH6624) Sourcing, VO = +4.3 V Sinking, VO = −4.3 V 100 (LMH6626) Sourcing, VO = +4.3 V Sinking, VO = −4.3 V 80 mA POWER SUPPLY PSRR Power supply rejection ratio IS Supply current (per channel) No Load (7) (8) 8 VS = ±5.4 V to ±6.6 V 82 -40°C ≤ TJ ≤ 125°C 88 12 -40°C ≤ TJ ≤ 125°C dB 80 16 18 mA Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is 1.5 ms. Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 6.7 Typical Characteristics Figure 1. Voltage Noise vs. Frequency 5 4 4 3 3 AV = -10 Normalized Gain (dB) Normalized Gain (dB) Figure 2. Current Noise vs. Frequency 5 2 AV = -20 1 0 -1 AV = -40 -2 AV = -60 -3 AV = -80 -4 AV = -10 2 1 AV = -20 0 -1 AV = -40 -2 AV = -60 -3 AV = -80 -4 AV = -100 -5 AV = -100 -5 1k 1M 100k 10k 10M 100M 1k 1G 10k Frequency (Hz) 1M 10M 100M 1G Frequency (Hz) VS = ±2.5 V VIN = 5 mVpp RL = 100 Ω VS = ±6V VIN = 5 mVpp RL = 100 Ω Figure 3. Inverting Frequency Response Figure 4. Inverting Frequency Response 5 5 4 4 3 3 2 AV = +10 1 0 AV = +200 -1 AV = +100 -2 AV = +40 -3 Normalized Gain (dB) Normalized Gain (dB) 100k 2 AV = +10 1 0 AV = +200 -1 AV = +100 -2 AV = +40 -3 AV = +30 AV = +30 -4 -4 AV = +20 AV = +20 -5 -5 1k 10k 100k 1M 10M 100M 1G 1k Frequency (Hz) 10k 100k 1M 10M 100M 1G Frequency (Hz) VS = ±2.5 V RF = 500 Ω VO = 2 Vpp VS = ±6 V RF = 500 Ω VO = 2 Vpp Figure 5. Non-Inverting Frequency Response Figure 6. Non-Inverting Frequency Response Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 9 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) 70 Gain (dB) 60 0 -40°C -45 25°C PHASE -90 125°C -40°C 50 -135 125°C GAIN 40 -180 25°C 30 -225 20 -270 10 -315 0 100k 1M 10M 100M Phase (°) 80 -360 1G Frequency (Hz) VS = ±2.5 V VS = ±6V RL = 100 Ω Figure 7. Open Loop Frequency Response Over Temperature Figure 8. Open Loop Frequency Response Over Temperature 5 5 33 pF 4 3 10 pF 2 1 5 pF 0 33 pF 4 15 pF Normalized Gain (dB) Normalized Gain (dB) 3 0 pF -1 -2 1 5 pF 0 0 pF -1 -2 -3 -3 -4 -4 -5 -5 1M 10M 1G 100M 1M Frequency (Hz) VS = ±2.5V AV = +10 RF = 250 Ω RISO = 10 Ω RL = 1 kΩ||CL VS = ±6V AV = +10 RF = 250 Ω 5 4 4 5 pF 1 0 -1 10 pF -2 RISO = 10 Ω RL = 1 kΩ||CL 3 Normalized Gain (dB) Normalized Gain (dB) 0 pF 2 1G 100M Figure 10. Frequency Response with Cap. Loading 5 3 10M Frequency (Hz) Figure 9. Frequency Response with Cap. Loading 15 pF -3 0 pF 2 5 pF 1 0 -1 10 pF -2 15 pF -3 33 pF -4 33 pF -4 -5 -5 1M 10M 100M 1G 1M Frequency (Hz) VS = ±2.5 V AV = +10 RF = 250 Ω RISO = 100 Ω RL = 1 kΩ||CL Submit Documentation Feedback 10M 100M 1G Frequency (Hz) VS = ±6 V AV = +10 RF = 250 Ω Figure 11. Frequency Response with Cap. Loading 10 15 pF 10 pF 2 RISO = 10 Ω RL = 1 kΩ||CL Figure 12. Frequency Response with Cap. Loading Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 Typical Characteristics (continued) 5 5 4 4 3 VIN = 20 mV 1 0 -1 -2 VIN = 200 mV Normalized Gain (dB) Normalized Gain (dB) 3 2 -3 2 0 -1 -2 VIN = 200 mV -3 -4 -4 -5 -5 100k VIN = 20 mV 1 1M 10M 100M 100k 1G 1M Frequency (Hz) VS = ±-2.5 V AV = +10 RF = 500 Ω 5 4 4 3 3 2 1 0 VIN = 20 mV -1 -2 VIN = 200 mV Normalized Gain (dB) Normalized Gain (dB) 1G Figure 14. Non-Inverting Frequency Response Varying VIN 5 2 1 VIN = 20 mV 0 -1 -2 -3 -4 VIN = 200 mV -4 -5 -5 100k 1M 10M 100M 1G 100k 1M Frequency (Hz) 1G Figure 16. Non-Inverting Frequency Response Varying VIN (LMH6626) 5 4 3 3 2 1 0 VIN = 20 mV -1 -2 VIN = 200 mV Normalized Gain (dB) 5 4 2 1 VIN = 20 mV 0 -1 -2 -3 -4 VIN = 200 mV -4 -5 100k 100M VS = ±2.5 V AV = +20 RF = 500 Ω Figure 15. Non-Inverting Frequency Response Varying VIN (LMH6624) -3 10M Frequency (Hz) VS = ±2.5 V AV = +20 RF = 500 Ω Normalized Gain (dB) 100M VS = ±6 V AV = +10 RF = 500 Ω Figure 13. Non-Inverting Frequency Response Varying VIN -3 10M Frequency (Hz) -5 1M 10M 100M 1G 100k Frequency (Hz) 1M 10M 100M 1G Frequency (Hz) VS = ±6 V AV = +20 RF = 500 Ω VS = ±6 V AV = +20 RF = 500 Ω Figure 17. Non-Inverting Frequency Response Varying VIN (LMH6624) Figure 18. Non-Inverting Frequency Response Varying VIN (LMH6626) Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 11 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) 160 140 -40°C -40°C 140 120 120 ISOURCE (mA) ISOURCE (mA) 100 125°C 100 25°C 80 60 80 25°C 125°C 60 40 40 20 20 0 0 0 0.5 1 1.5 0 0.5 1 VOUT (V) VS = ±2.5 V VS = ±2.5 V Figure 19. Sourcing Current vs. VOUT (LMH6624) Figure 20. Sourcing Current vs. VOUT (LMH6626) 180 140 -40°C -40°C 160 120 25°C 140 125°C 100 120 ISOURCE (mA) ISOURCE (mA) 1.5 VOUT (V) 25°C 100 80 60 80 125°C 60 40 40 20 20 0 0 0 1 2 3 VOUT (V) 4 5 0 1 2 3 5 VS = ±6 V VS = ±6 V Figure 21. Sourcing Current vs. VOUT (LMH6624) Figure 22. Sourcing Current vs. VOUT (LMH6626) 50 150 100 0 125°C 125°C 50 VOS (PV) VOS (PV) -50 25°C -100 -150 -200 0 25°C -50 -100 -150 -40°C -40°C -250 -200 -250 -300 4 5 6 7 8 9 10 11 12 4 VSUPPLY (V) Submit Documentation Feedback 5 6 7 8 9 10 11 12 VSUPPLY (V) Figure 23. VOS vs. VSUPPLY (LMH6624) 12 4 VOUT (V) Figure 24. VOS vs. VSUPPLY (LMH6626) Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 Typical Characteristics (continued) 140 160 -40°C -40°C 140 120 120 125°C 25°C 100 125°C ISINK (mA) ISINK (mA) 100 80 60 40 25°C 80 60 40 20 20 0 0 -20 0 0.5 1 0 1.5 0.5 VOUT (V) 1 1.5 VOUT (V) VS = ±2.5 V VS = ±2.5V Figure 25. Sinking Current vs. VOUT (LMH6624) Figure 26. Sinking Current vs. VOUT (LMH6626) 180 140 -40°C -40°C 160 120 140 ISINK (mA) 125°C ISINK (mA) 100 120 25°C 100 80 125°C 80 25°C 60 60 40 40 20 20 0 0 0 1 2 3 4 5 0 1 VOUT (V) 3 4 5 VOUT (V) VS = ±6 V VS = ±6 V Figure 27. Sinking Current vs. VOUT (LMH6624) Figure 28. Sinking Current vs. VOUT (LMH6626) 0.2 0 0.15 -20 0.1 -40 Crosstalk (dB) IOS (PA) 2 25°C 0.05 125°C 0 -60 VS = ±2.5 V -80 -0.05 -100 -0.1 -120 -40°C CH 1 OUTPUT CH 2 OUTPUT VS = ±6 V -140 -0.15 4 5 6 7 8 9 10 11 1k 12 10k 100k 1M 10M 100M Frequency (Hz) VSUPPLY (V) VIN = 60 mVpp AV = +20 RL = 100 Ω Figure 29. IOS vs. VSUPPLY Figure 30. Crosstalk Rejection vs. Frequency (LMH6626) Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 13 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) 0 0 -20 -20 HD2 -60 Distortion (dBc) Distortion (dBc) -40 VS = ±6 V, VO = 2 VPP -80 HD3 -100 -40 VS = ±6 V, -60 HD2 VO = 2 VPP -80 VS = ±2.5 V, VO = 1 VPP -100 -120 VS = ±2.5 V, VO = 1 VPP -140 100k 1M 10M HD3 -120 100k 100M 1M Frequency (Hz) 100M 10M Frequency (Hz) AV = +10 RL = 100 Ω AV = +20 RL = 100 Ω Figure 31. Distortion vs. Frequency Figure 32. Distortion vs. Frequency 0 -50 HD2 VS = ±6 V -20 VO = 2 VPP -60 HD2 VS = ±2.5 V, -60 Distortion (dBc) Distortion (dBc) -40 VO = 1 VPP -80 -70 -80 HD3 -100 VS = ±2.5 V -90 HD3 VO = 1 VPP -120 VS = ±6 V, VO = 2 VPP -100 -140 100k 1M 10M 0 100M 20 40 Frequency (Hz) 60 80 AV = +20 RL = 500 Ω VS = ±6 V VO = 2 Vpp Figure 33. Distortion vs. Frequency Figure 34. Distortion vs. Gain 0 0 -20 -20 HD2 -40 Distortion (dBc) Distortion (dBc) fC = 10 MHz HD2 -60 -80 fC = 10 MHz -40 -60 -80 fC = 1 MHz -100 HD3 fC = 1 MHz -100 HD3 -120 -120 0 0.5 1 1.5 2 2.5 3 3.5 4 0 VOUT (V) 4 6 8 10 12 AV = +20 VS = ±6 V RL = 100 Ω Figure 35. Distortion vs. VOUT Peak to Peak Submit Documentation Feedback 2 VOUT (VPP) AV = +20 AV = ±2.5V RL = 100 Ω 14 100 Gain (V/V) Figure 36. Distortion vs. VOUT Peak to Peak Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 200 mV/DIV 200 mV/DIV Typical Characteristics (continued) 10 ns/DIV 10 ns/DIV RL = 100 Ω VS = ±2.5 V VO = 1 Vpp AV = +10 RL = 100 Ω VS = ±6 V VO = 1 Vpp AV = +20 Figure 38. Non-Inverting Large Signal Pulse Response 50 mV/DIV 100 mV/DIV Figure 37. Non-Inverting Large Signal Pulse Response 10 ns/DIV 10 ns/DIV RL = 100 Ω VS = ±2.5 V VO = 200 mv AV = +10 Figure 39. Non-Inverting Small Signal Pulse Response Figure 40. Non-Inverting Small Signal Pulse Response 0 0 +PSRR, AV +10 -10 -20 -20 +PSRR, AV +20 -50 -PSRR, AV +20 -70 PSRR (dB) -40 -60 +PSRR, AV = +10 -40 -30 PSRR (dB) RL = 100 Ω VS = ±6 V VO = 500 mv AV = +20 -60 +PSRR, AV = +20 -80 -PSRR, AV = +10 -100 -80 -120 -90 -PSRR, AV = +20 -PSRR, AV +10 -100 1k 10k 100k 1M 10M 100M 1G -140 1k Frequency (Hz) 10k 100k 1M 10M 100M 1G Frequency (Hz) VS = ±2.5 V VS = ±6 V Figure 41. PSRR vs. Frequency Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Figure 42. PSRR vs. Frequency Submit Documentation Feedback 15 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com 0 0 -10 -10 -20 -20 -30 -30 CMRR (dB) CMRR (dB) Typical Characteristics (continued) -40 AV = +10 -50 -60 -40 -50 AV = +10 -60 -70 -70 AV = +20 -80 AV = +20 -80 -90 -90 1k 1M 100k 10k 10M 100M 1k 100k 10k Frequency (Hz) VS = ±2.5V VIN = 5 mVpp 5 RF = 2 k: RF = 1.5 k: RF = 1.5 k: 3 RF = 1 k: RF = 750 : 1 0 -1 RF = 2 k: 4 Normalized Gain (dB) Normalized Gain (dB) 3 RF = 511 : -2 RF = 1 k: 2 1 RF = 750 : 0 -1 RF = 511 : -2 -3 -3 -4 -4 -5 10M -5 100M 1G 10M VS = ±2.5 V AV = +10 RL = 100 Ω 1G VS = ±6 V AV = +10 V RL = 100 Ω Figure 45. Amplifier Peaking with Varying RF Submit Documentation Feedback 100M Frequency (Hz) Frequency (Hz) 16 100M Figure 44. Input Referred CMRR vs. Frequency 5 2 10M VS = ±6 V VIN = 5 mVpp Figure 43. Input Referred CMRR vs. Frequency 4 1M Frequency (Hz) Figure 46. Amplifier Peaking with Varying RF Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 7 Detailed Description 7.1 Overview The LMH6624 and LMH6626 devices are very wide gain bandwidth, ultra low noise voltage feedback operational amplifiers. Their excellent performances enable applications such as medical diagnostic ultrasound, magnetic tape & disk storage and fiber-optics to achieve maximum high frequency signal-to-noise ratios. The set of characteristic plots in Typical Characteristics illustrates many of the performance trade-offs. The following discussion will demonstrate the proper selection of external components to achieve optimum system performance. 7.2 Feature Description 7.2.1 Bias Current Cancellation To cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain setting (Rg) and feedback (Rf) resistors should equal the equivalent source resistance (Rseq) as defined in Figure 47. Combining this constraint with the non-inverting gain equation also seen in Figure 47, allows both Rf and Rg to be determined explicitly from the following equations: Rf = AVRseq Rg = Rf/(AV-1) (1) (2) When driven from a 0-Ω source, such as the output of an op amp, the non-inverting input of the LMH6624 and LMH6626 should be isolated with at least a 25-Ω series resistor. As seen in Figure 48, bias current cancellation is accomplished for the inverting configuration by placing a resistor (Rb) on the non-inverting input equal in value to the resistance seen by the inverting input (Rf||(Rg+Rs)). Rb should to be no less than 25 Ω for optimum LMH6624 and LMH6626 performance. A shunt capacitor can minimize the additional noise of Rb. Figure 47. Non-Inverting Amplifier Configuration Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 17 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) Figure 48. Inverting Amplifier Configuration 7.2.2 Total Input Noise vs. Source Resistance To determine maximum signal-to-noise ratios from the LMH6624 and LMH6626, an understanding of the interaction between the amplifier’s intrinsic noise sources and the noise arising from its external resistors is necessary. Figure 49 describes the noise model for the non-inverting amplifier configuration showing all noise sources. In addition to the intrinsic input voltage noise (en) and current noise (in = in+ = in−) source, there is also thermal voltage noise (et = √(4KTR)) associated with each of the external resistors. Equation 3 provides the general form for total equivalent input voltage noise density (eni). Equation 4 is a simplification of Equation 3 that assumes Rf||Rg = Rseq for bias current cancellation. Figure 50 illustrates the equivalent noise model using this assumption. Figure 51 is a plot of eni against equivalent source resistance (Rseq) with all of the contributing voltage noise sources of Equation 4. This plot gives the expected eni for a given (Rseq) which assumes Rf||Rg = Rseq for bias current cancellation. The total equivalent output voltage noise (eno) is eni*AV. Figure 49. Non-Inverting Amplifier Noise Model (3) 18 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 Feature Description (continued) Figure 50. Noise Model with Rf||Rg = Rseq (4) As seen in Figure 51, eni is dominated by the intrinsic voltage noise (en) of the amplifier for equivalent source resistances below 26 Ω. Between 26 Ω and 3.1 kΩ, eni is dominated by the thermal noise (et = √(4kT(2Rseq)) of the equivalent source resistance Rseq. Above 3.1 kΩ, eni is dominated by the amplifier’s current noise (in = √2 inRseq). When Rseq = 283 Ω (that is, Rseq = en/√2 in) the contribution from voltage noise and current noise of LMH6624 and LMH6626 is equal. For example, configured with a gain of +20V/V giving a −3 dB of 90 MHz and driven from Rseq = Rf || Rg = 25 Ω (eni = 1.3 nV√Hz from Figure 51), the LMH6624 produces a total output noise voltage (eni × 20 V/V × √(1.57 × 90 MHz)) of 309 μVrms. VOLTAGE NOISE DENSITY (nV/ Hz) 100 et 10 eni en 1 in 0.1 10 100 1k 10k 100k RSEQ (:) Figure 51. Voltage Noise Density vs. Source Resistance If bias current cancellation is not a requirement, then Rf || Rg need not equal Rseq. In this case, according to Equation 3, Rf || Rg should be as low as possible to minimize noise. Results similar to Equation 3 are obtained for the inverting configuration of Figure 48 if Rseq is replaced by Rb and Rg is replaced by Rg + Rs. With these substitutions, Equation 3 will yield an eni referred to the non-inverting input. Referring eni to the inverting input is easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains. Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 19 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) 7.2.3 Noise Figure Noise Figure (NF) is a measure of the noise degradation caused by an amplifier. (5) The Noise Figure formula is shown in Equation 5. The addition of a terminating resistor RT, reduces the external thermal noise but increases the resulting NF. The NF is increased because RT reduces the input signal amplitude thus reducing the input SNR. 2 2 2 2 en + in (RSeq + (Rf||Rg) ) + 4KT (RSeq + (Rf||Rg)) NF = 10 LOG 4KT (RSeq + (Rf||Rg)) (6) The noise figure is related to the equivalent source resistance (Rseq) and the parallel combination of Rf and Rg. To minimize "Noise Figure": • Minimize Rf || Rg • Choose the Optimum RS (ROPT) ROPT is the point at which the NF curve reaches a minimum and is approximated by: ROPT » en in (7) 7.2.4 Low Noise Integrator The LMH6624 and LMH6626 devices implement a deBoo integrator shown in Figure 52. Positive feedback maintains integration linearity. The low input offset voltage of the LMH6624 and LMH6626 devices and matched inputs allow bias current cancellation and provide for very precise integration. Keeping RG and RS low helps maintain dynamic stability. VO #VIN KO KO = 1 + ; sRSC RF RG RB VO RS + VIN C R - 50: 50: RF RF = RB RG RG = RS||R Figure 52. Low Noise Integrator 20 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 Feature Description (continued) 7.2.5 High-gain Sallen-key Active Filters The LMH6624 and LMH6626 devices are well suited for high gain Sallen-Key type of active filters. Figure 53 shows the 2nd order Sallen-Key low pass filter topology. Using component predistortion methods discussed in Application Note OA-21, Component Pre-Distortion for Sallen Key Filters (SNOA369) will enable the proper selection of components for these high-frequency filters. C1 R1 R2 + C2 RF RG Figure 53. Sallen-Key Active Filter Topology 7.2.6 Low Noise Magnetic Media Equalizer The LMH6624 and LMH6626 devices implement a high-performance low noise equalizer for such application as magnetic tape channels as shown in Figure 54. The circuit combines an integrator with a bandpass filter to produce the low noise equalization. The circuit’s simulated frequency response is illustrated in Figure 55. Figure 54. Low Noise Magnetic Media Equalizer Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 21 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) Figure 55. Equalizer Frequency Response 7.3 Device Functional Modes 7.3.1 Single Supply Operation The LMH6624 and LMH6626 devices can be operated with single power supply as shown in Figure 56. Both the input and output are capacitively coupled to set the DC operating point. Figure 56. Single Supply Operation 22 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information A Transimpedance amplifier is used to convert the small output current of a photodiode to a voltage, while maintaining a near constant voltage across the photodiode to minimize non-linearity. Extracting the small signal requires high gain and a low noise amplifier, and therefore, the LMH6624 and LMH6626 devices are ideal for such an application in order to maximize SNR. Furthermore, because of the large gain (RF value) needed, the device used must be high speed so that even with high noise gain (due to the interaction of the feedback resistor and photodiode capacitance), bandwidth is not heavily impacted. Figure 47 implements a high-speed, single supply, low-noise Transimpedance amplifier commonly used with photo-diodes. The transimpedance gain is set by RF. 8.2 Typical Application CF 1.1 pF 5 VDC D1 CD = 10 pF RF 1.2 k Ω ID 5 VDC – R2 2k 5 VDC LMH6624 + RL 500 Ω C1 0.1 µF R1 3k VOUT = 3 VDC - 1200 × I D Figure 57. LMH6624 Application Schematic Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 23 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com Typical Application (continued) 8.2.1 Design Requirements Figure 58 shows the Noise Gain (NG) and transfer function (I-V Gain). As with most Transimpedance amplifiers, it is required to compensate for the additional phase lag (Noise Gain zero at fZ) created by the total input capacitance: CD (diode capacitance) + CCM (LMH6624 CM input capacitance) + CDIFF (LMH6624 DIFF input capacitance) looking into RF. This is accomplished by placing CF across RF to create enough phase lead (Noise Gain pole at fP) to stabilize the loop. OP AMP OPEN LOOP GAIN GAIN (dB) I-V GAIN (:) NOISE GAIN (NG) 1 + sRF (CIN + CF) 1 + sRFCF 1+ CIN CF 0 dB FREQUENCY fz # 1 2SRFCIN fP = 1 GBWP 2SRFCF Figure 58. Transimpedance Amplifier Noise Gain and Transfer Function 8.2.2 Detailed Design Procedure The optimum value of CF is given by Equation 8 resulting in the I-V -3dB bandwidth shown in Equation 9, or around 124 MHz in this case, assuming GBWP = 1.5 GHz, CCM (LMH6624 CM input capacitance) = 0.9 pF, and CDIFF (LMH6624 DIFF input capacitance) = 2 pF. This CF value is a “starting point” and CF needs to be tuned for the particular application as it is often less than 1 pF and thus is easily affected by board parasitics. Optimum CF Value: CF = CIN 2S(GBWP)RF (8) Resulting -3dB Bandwidth: f - 3 dB # GBWP 2 S R F C IN (9) Equation 10 provides the total input current noise density (ini) equation for the basic Transimpedance configuration and is plotted against feedback resistance (RF) showing all contributing noise sources in Figure 59. The plot indicates the expected total equivalent input current noise density (ini) for a given feedback resistance (RF). This is depicted in the schematic of Figure 60 where total equivalent current noise density (ini) is shown at the input of a noiseless amplifier and noiseless feedback resistor (RF). The total equivalent output voltage noise density (eno) is ini*RF. Noise Equation for Transimpedance Amplifier: (10) 24 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 Typical Application (continued) 16 Current Noise Density (pA/ Hz) 14 ini 12 10 8 it en/RF 6 in 4 2 0 100 1k 10k Rf (:) Figure 59. Current Noise Density vs. Feedback Resistance +5VDC D1 RF (Noiseless) CD = 10 pF ID ini Noiseless Op Amp Figure 60. Transimpedance Amplifier Equivalent Input Source Mode From Figure 61, it is clear that with the LMH6624 extremely low-noise characteristics, for RF < 3 kΩ, the noise performance is entirely dominated by RF thermal noise. Only above this RF threshold, the input noise current (in) of LMH6624 becomes a factor and at no RF setting does the LMH6624 input noise voltage play a significant role. This noise analysis has ignored the possible noise gain increase, due to photo-diode capacitance, at higher frequencies. 8.2.3 Application Curve CURRENT NOISE DENSITY (pA/ Hz) 16 14 ini 12 it 10 8 en/RF 6 4 2 in 0 100 1k 10k FEEDBACK RESISTANCE, RF (:) Figure 61. Current Noise Density vs. Feedback Resistance Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 25 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com 9 Power Supply Recommendations The LMH6624 and LMH6626 devices can operate off a single supply or with dual supplies as long as the input CM voltage range (CMIR) has the required headroom to either supply rail. Supplies should be decoupled with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground plane is recommended, and as in most high speed devices, it is advisable to remove ground plane close to device sensitive pins such as the inputs. 10 Layout 10.1 Layout Guidelines TI suggests the copper patterns on the evaluation boards shown in Figure 62 and Figure 63 as a guide for high frequency layout. These boards are also useful as an aid in device testing and characterization. As is the case with all high-speed amplifiers, accepted-practice RF design technique on the PCB layout is mandatory. Generally, a good high frequency layout exhibits a separation of power supply and ground traces from the inverting input and output pins as shown in Figure 62. Parasitic capacitances between these nodes and ground may cause frequency response peaking and possible circuit oscillations. See Application Note OA-15, Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers (SNOA367) for more information. Use high quality chip capacitors with values in the range of 1000 pF to 0.1 µF for power supply bypassing as shown in Figure 62. One terminal of each chip capacitor is connected to the ground plane and the other terminal is connected to a point that is as close as possible to each supply pin as allowed by the manufacturer’s design rules. In addition, connect a tantalum capacitor with a value between 4.7 μF and 10 μF in parallel with the chip capacitor. Signal lines connecting the feedback and gain resistors should be as short as possible to minimize inductance and microstrip line effect as shown in Figure 63. Place input and output termination resistors as close as possible to the input/output pins. Traces greater than 1 inch in length should be impedance matched to the corresponding load termination. Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained to minimize the imbalance of amplitude and phase of the differential signal. Component value selection is another important parameter in working with high speed and high performance amplifiers. Choosing external resistors that are large in value compared to the value of other critical components will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path. Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very low value resistors could load down nodes and will contribute to higher overall power dissipation and high distortion. 26 DEVICE PACKAGE EVALUATION BOARD PART NUMBER LMH6624MF SOT-23–5 LMH730216 LMH6624MA SOIC-8 LMH730227 LMH6626MA SOIC-8 LMH730036 LMH6626MM VSSOP-8 LMH730123 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 LMH6624, LMH6626 www.ti.com SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 10.2 Layout Example Figure 62. LMH6624 and LMH6626 EVM Board Layout Example Figure 63. LMH6624 and LMH6626 EVM Board Layout Example Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 Submit Documentation Feedback 27 LMH6624, LMH6626 SNOSA42G – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation • Absolute Maximum Ratings for Soldering (SNOA549) • Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, Application Note OA-15 (SNOA367) • Semiconductor and IC Package Thermal Metrics (SPRA953) 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMH6624 Click here Click here Click here Click here Click here LMH6626 Click here Click here Click here Click here Click here 11.3 Trademarks All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright © 2002–2014, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6626 PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) LMH6624 MDC Package Type Package Pins Package Drawing Qty ACTIVE DIESALE Y 0 400 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85 Device Marking (4/5) LMH6624MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 LMH6624MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMH66 24MA LMH6624MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMH66 24MA LMH6624MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 A94A LMH6624MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A94A LMH6624MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A94A LMH6626MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMH66 26MA LMH6626MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMH66 26MA LMH6626MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A98A LMH6626MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A98A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6624MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6624MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6624MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6624MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6626MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6626MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMH6626MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6624MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6624MF SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6624MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6624MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMH6626MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6626MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMH6626MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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