Cypress CY7C109B-20VC 128k x 8 static ram Datasheet

009B
CY7C109B
CY7C1009B
128K x 8 Static RAM
Features
• High speed
— tAA = 12 ns
• Low active power
— 495 mW (max. 12 ns)
• Low CMOS standby power
— 55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description
The CY7C109B / CY7C1009B is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW Out-
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable One (CE1) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0
through A16).
Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C109B is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009B is available in
a 300-mil-wide SOJ package. The CY7C1009B and
CY7C109B are functionally equivalent in all other respects.
Logic Block Diagram
Pin Configurations
SOJ
Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
I/O1
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
512 x 256 x 8
ARRAY
I/O3
I/O4
I/O5
OE
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A9
A 10
A 11
A 12
A 13
A14
A15
A16
CE1
CE2
WE
109B–1
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
TSOP I
Top View
(not to scale)
109B–2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
109B–3
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low Power Version
Cypress Semiconductor Corporation
Document #: 38-05038 Rev. **
•
7C109B-12
7C1009B-12
12
90
10
7C109B-15
7C1009B-15
15
80
10
7C109B-20
7C1009B-20
20
75
10
7C109B-25
7C1009B-25
25
70
10
7C109B-35
7C1009B-35
35
60
10
2
2
2
-
-
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
CY7C109B
CY7C1009B
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
Range
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
Commercial
Industrial
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Ambient
Temperature[2]
VCC
0°C to +70°C
5V ± 10%
−40°C to +85°C
5V ± 10%
Current into Outputs (LOW) .........................................20 mA
Electrical Characteristics Over the Operating Range
7C109B-12
7C1009B-12
Parameter
Description
Test Conditions
Min.
Max.
2.4
7C109B-15
7C1009B-15
Min.
Max.
2.4
VOH
Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
VCC
+ 0.3
VIL
Input LOW Voltage[1]
–0.3
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
IOS
Output Short
Circuit Current[3]
VCC = Max.,
VOUT = GND
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
ISB2
0.4
Unit
V
0.4
V
2.2
VCC
+ 0.3
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–5
+5
–5
+5
µA
–300
–300
mA
90
80
mA
Automatic CE
Max. VCC, CE1 > VIH
Power-Down Current or CE2 < VIL,
VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
45
40
mA
Automatic CE
Max. VCC,
Power-Down Current CE1 > VCC – 0.3V,
or CE2 < 0.3V,
—CMOS Inputs
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10
10
mA
2
2
mA
L
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05038 Rev. **
Page 2 of 12
CY7C109B
CY7C1009B
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
Min.
Min.
Min.
Test Conditions
Max.
2.4
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[1]
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
IOS
Output Short
Circuit Current[3]
VCC = Max.,
VOUT = GND
ICC
VCC Operating
Supply Current
ISB1
ISB2
Max.
2.4
Max.
Unit
2.4
0.4
0.4
V
0.4
V
V
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
–1
+1
–1
+1
–1
+1
µA
–5
+5
–5
+5
–5
+5
µA
–300
–300
–300
mA
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
75
70
60
mA
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE1 > VIH
or CE2 < VIL,
VIN > VIH or
VIN < VIL, f = fMAX
30
30
25
mA
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE1 > VCC – 0.3V,
or CE2 < 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10
10
10
mA
2
—
—
mA
L
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
9
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
AC Test Loads and Waveforms
R1 480Ω
R1 480 Ω
5V
ALL INPUT PULSES
5V
OUTPUT
3.0V
90%
OUTPUT
30 pF
R2
255Ω
INCLUDING
JIG AND
SCOPE
(a)
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
GND
≤ 3 ns
10%
90%
10%
≤ 3 ns
10B9–4
109B–5
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Equivalent to:
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05038 Rev. **
Page 3 of 12
CY7C109B
CY7C1009B
Switching Characteristics[5] Over the Operating Range
7C109B-12
7C1009B-12
Parameter
Description
Min.
Max.
7C109B-15
7C1009B-15
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
12
15
ns
tDOE
OE LOW to Data Valid
6
7
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6, 7]
tLZCE
12
15
12
3
15
3
0
CE1 LOW to Low Z, CE2 HIGH to Low Z
tHZCE
CE1 HIGH to High Z, CE2 LOW to High Z
tPU
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
3
[6, 7]
ns
7
3
6
0
ns
ns
7
0
12
ns
ns
0
6
[7]
ns
ns
ns
15
ns
WRITE CYCLE[8]
tWC
Write Cycle Time[9]
12
15
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
10
12
ns
tAW
Address Set-Up to Write End
10
12
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
10
12
ns
tSD
Data Set-Up to Write End
7
8
ns
tHD
Data Hold from Write End
0
0
ns
3
3
ns
tLZWE
tHZWE
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
6
7
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and
the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05038 Rev. **
Page 4 of 12
CY7C109B
CY7C1009B
Switching Characteristics[5] Over the Operating Range (continued)
Parameter
Description
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
Min.
Min.
Min.
Max.
Max.
Min.
Unit
35
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
20
25
35
ns
tDOE
OE LOW to Data Valid
8
10
15
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6, 7]
tLZCE
20
25
20
3
5
0
CE1 LOW to Low Z, CE2 HIGH to Low Z
tHZCE
CE1 HIGH to High Z, CE2 LOW to High Z
tPU
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
5
8
5
0
20
ns
15
10
0
ns
0
10
3
[6, 7]
ns
5
0
8
[7]
35
25
ns
15
0
25
ns
ns
ns
35
ns
WRITE CYCLE[8]
tWC
Write Cycle Time[9]
20
25
35
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
15
20
25
ns
tAW
Address Set-Up to Write End
15
20
25
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
12
15
20
ns
tSD
Data Set-Up to Write End
10
15
20
ns
tHD
Data Hold from Write End
0
0
0
ns
3
5
5
ns
tLZWE
tHZWE
[7]
WE HIGH to Low Z
[6, 7]
WE LOW to High Z
8
10
15
ns
Max
Unit
Data Retention Characteristics Over the Operating Range (Low Power version only)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
Document #: 38-05038 Rev. **
Conditions
No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Min.
2.0
V
150
µA
0
ns
200
µs
Page 5 of 12
CY7C109B
CY7C1009B
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tR
tCDR
CE
109B-6
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
109B–7
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
109B–8
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
Document #: 38-05038 Rev. **
Page 6 of 12
CY7C109B
CY7C1009B
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tSCE
tHA
tAW
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
109B–9
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 15
tHZOE
109B–10
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05038 Rev. **
Page 7 of 12
CY7C109B
CY7C1009B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tHA
tSA
tPWE
WE
tSD
NOTE 15
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
10B9–11
Truth Table
CE1
CE2
OE
WE
H
X
X
X
High Z
Power-Down
Standby (ISB)
X
L
X
X
High Z
Power-Down
Standby (ISB)
L
H
L
H
Data Out
Read
Active (ICC)
L
H
X
L
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05038 Rev. **
I/O0 – I/O7
Mode
Power
Page 8 of 12
CY7C109B
CY7C1009B
Ordering Information
Speed
(ns)
12
15
20
25
35
Ordering Code
Package
Name
Package Type
CY7C109B-12VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C1009B-12VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-12ZC
Z32
32-Lead TSOP Type I
CY7C109B-15VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C109BL-15VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C1009B-15VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-15ZC
Z32
32-Lead TSOP Type I
CY7C109BL-15ZC
Z32
32-Lead TSOP Type I
CY7C109B-15VI
V33
32-Lead (400-Mil) Molded SOJ
CY7C109BL-15VI
V33
32-Lead (400-Mil) Molded SOJ
CY7C1009B-15VI
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-15ZI
Z32
32-Lead TSOP Type I
CY7C109B-20VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C1009B-20VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-20VI
V33
32-Lead (400-Mil) Molded SOJ
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
CY7C109B-20ZC
Z32
32-Lead TSOP Type I
Commercial
CY7C109B-20ZI
Z32
32-Lead TSOP Type I
Industrial
Commercial
CY7C109B-25VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C1009B-25VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-25VI
V33
32-Lead (400-Mil) Molded SOJ
Industrial
CY7C109B-25ZC
Z32
32-Lead TSOP Type I
Commercial
CY7C109B-25ZI
Z32
32-Lead TSOP Type I
Industrial
CY7C109B-35VC
V33
32-Lead (400-Mil) Molded SOJ
Commercial
CY7C1009B-35VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-35VI
V33
32-Lead (400-Mil) Molded SOJ
Document #: 38-05038 Rev. **
Industrial
Page 9 of 12
CY7C109B
CY7C1009B
Package Diagrams
32-Lead (300-Mil) Molded SOJ V32
51-85041-A
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
Document #: 38-05038 Rev. **
Page 10 of 12
CY7C109B
CY7C1009B
Package Diagrams (continued)
32-Lead Thin Small Outline Package Z32
51-85056-C
Document #: 38-05038 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C109B
CY7C1009B
Document Title: CY7C109B, CY7C1009 128K x 8 SRAM
Document Number: 38-05038
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106832
09/22/01
SZV
Change from Spec number: 38-00971 to 38-05038
Document #: 38-05038 Rev. **
Page 12 of 12
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