ICST M2020 Vcso based clock pll Datasheet

Product Data Sheet
Integrated
Circuit
Systems, Inc.
M2020/21
VCSO BASED CLOCK PLL
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
27
26
25
24
23
22
21
20
19
FIN_SEL1
GND
P_SEL2
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
The M2020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting 2.5-10 GB data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M2020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
FIN_SEL0
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
(Top View)
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2020-11-622.0800 or M2021-11-622.0800
◆ LVPECL clock output (CML and LVDS options available)
Input Reference
Clock (MHz)
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
(M2020)
◆ Loss of Lock (LOL) output pin
◆ Narrow Bandwidth control input (NBW pin)
◆ Hitless Switching (HS) options with or without Phase
Build-out (PBO) available for SONET (GR-253) /
SDH (G.813) MTIE and TDEV compliance during
reference clock reselection
M2020
M2021
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
FEATURES
◆ Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz
or 50kHz to 80MHz)
◆ Output frequencies of 15 to 700 MHz *
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
28
29
30
31
32
33
34
35
36
(M2021)
19.44 or 38.88
77.76
155.52
622.08
PLL Ratio
(Pin Selectable)
(M2020)
Output Clock
(MHz)
(M2021)
32 or 16
8
4
1
622.08
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
◆ Industrial temperature grade available
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Loop
Filter
M2020/21
NBW
LOL
MUX
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
0
R Div
VCSO
(1, 4,
16, 64)
1
M Divider
REF_SEL
MR_SEL1:0
Phase
Detector
(1, 4, 16, 64)
2
FIN_SEL1:0
2
P_SEL2:0
3
Mfin Div
(1, 4, 8, 32) or
( 1, 4, 8, 16)
M / R Divider
LUT
P Divider
FOUT0: 1, 4, 8, 32 or TriState
FOUT1: 1, 4, 8 or TriState
Mfin Divider
LUT
FOUT0
nFOUT0
TriState
FOUT1
nFOUT1
P Divider
LUT
Figure 2: Simplified Block Diagram
M2020/21 Datasheet Rev 1.0
Revised 30Jul2004
M2020/21 VCSO Based Clock PLL
Integrated Circuit Systems, Inc.
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M2020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED CLOCK PLL
Product Data Sheet
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
I/O
Configuration
12
13
15
16
17
18
25
FOUT1
nFOUT1
FOUT0
nFOUT0
P_SEL1
P_SEL0
P_SEL2
20
nDIF_REF1
21
DIF_REF1
22
REF_SEL
23
nDIF_REF0
24
DIF_REF0
27
28
29
30
FIN_SEL1
FIN_SEL0
MR_SEL0
MR_SEL1
31
LOL
Output
32
NBW
Input
34, 35, 36
DNC
Ground
Description
Power supply ground connections.
Input
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 6.
Output
Input
Power
Power supply connection, connect to +3.3V.
Output
No internal terminator
Clock output pair 1. Differential LVPECL.
Output
No internal terminator
Clock output pair 0. Differential LVPECL.
Input
, P divider selection. LVCMOS/LVTTL. See Table 5,
Internal pull-down resistor1 Post-PLL
P Divider Look-Up Table (LUT), on pg. 3.
Biased to Vcc/2 2
Input
Reference clock input pair 1. Differential LVPECL or LVDS.
Internal pull-down resistor1 Resistor bias on inverting terminal supports TTL or LVCMOS.
Input
Internal pull-down resistor1
Input
Input
Input
Biased to Vcc/2 2
Internal pull-down resistor 1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
nput clock frequency selection. LVCMOS/LVTTL.
Internal pull-down resistor1 ISee
Table 3, Mfin Divider Look-Up Table (LUT) on pg. 3.
M
and
R divider value selection. LVCMOS/ LVTTL.
Internal pull-down resistor1 See Table 4, M and R Divider Look-Up Table (LUT) on pg. 3.
Internal pull-UP resistor1
Do Not Connect.
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase. 3
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic 1 - Narrow loop bandwidth, RIN = 2100kΩ.
Logic 0 - Wide bandwidth, RIN = 100kΩ.
Internal nodes. Connection to these pins can cause erratic
device operation.
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 8.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See Differential Inputs Biased to VCC/2 on pg. 8.
Note 3: See LVCMOS Output in DC Characteristics on pg. 8.
M2020/21 Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
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Table 2: Pin Descriptions
Revised 30Jul2004
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M2020/21
Integrated
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VCSO BASED CLOCK PLL
Product Data Sheet
DETAILED BLOCK DIAGRAM
RLOOP
CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP
M2020/21
OP_IN
CLOOP
nOP_IN
RPOST
OP_OUT
nOP_OUT
nVC
VC
Hitless Switching (HS) Opt.
NBW
LOL
HS with Phase Build-out Opt.
MUX
DIF_REF0
nDIF_REF0
0
DIF_REF1
nDIF_REF1
1
Phase
Detector
R Div
Loop Filter
Amplifier
M Div
REF_SEL
FIN_SEL1:0
P Divider
(for FOUT0: 1, 4, 8, or 32),
(for FOUT1: 1, 4, or 8)
Mfin Divider
LUT
2
FOUT0
nFOUT0
TriState
FOUT1
nFOUT1
P Divider
LUT
3
P_SEL2:0
VCSO
(1, 4, 8, 32 or
1, 4, 8, 16)
M and R Divider
LUT
2
Phase
Shifter
Mfin Divider
(1, 4, 16, 64)
MR_SEL1:0
SAW Delay Line
Phase
Locked
Loop
(PLL)
RIN
(1, 4,
16, 64)
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
P Divider Look-Up Table (LUT)
Mfin Divider Look-Up Table (LUT)
The FIN_SEL1:0 pins select the Mfin divider value, which
establishes the PLL clock multiplication ratio. Since the
VCSO frequency is fixed, this allows input reference
selection.
Input Ref. Freq. (MHz) 1
Mfin Value
FIN_SEL1:0
M2020-yz-622.0800 or M2021-yz-622.0800
The P_SEL2:0 pins select the P divider values, which set
the output clock frequencies. A P divider of value of 1
will provide a 622.08MHz output when using a 622.08MHz
VCSO, for example. P divider values of 4, 8, or 32 are
also available, plus a TriState mode. The outputs can be
placed into the valid state combinations as listed in
Table 5. (The outputs cannot each be placed into any of
the five available states independently.)
(M2020) (M2021)
0
0
1
1
0
1
0
1
32 or 16
8
4
1
19.44 or 38.88
77.76
155.52
622.08
P_SEL2:0
FOUT0
0
0
0
0
1
1
1
1
Table 3: Mfin Divider Look-Up Table (LUT)
Note 1: Example with M2020-yz-622.0800 or M2021-yz-622.0800
M and R Divider Look-Up Table (LUT)
The MR_SEL1:0 pins select the M and R divider values,
which establish phase detector frequency. A lower
phase detector frequency improves jitter tolerance and
lowers loop bandwidth.
MR_SEL1:0
M
R
01
1
1
0
0
1
4
4
1
0
16
16
1
1
64
64
Description
Output Frequency (MHz)
FOUT1
32
1
0
32
4
1
0
1
1
1
4
1
0
8
8
4
4
1
8
4
0
1 TriState TriState
FOUT0
FOUT1
19.44
19.44
622.08
155.52
77.76
155.52
77.76
N/A
622.08
155.52
622.08
622.08
77.76
155.52
155.52
N/A
Table 5: P Divider Look-Up Table (LUT)
General Guidelines for M and R Divider Selection
•
Table 4: M and R Divider Look-Up Table (LUT)
Note 1: Do not use with FIN_SEL1:0=11; Maximum Phase Detector
Frequency=175MHz
Integrated Circuit Systems, Inc.
0
0
1
1
0
0
1
1
M2020-yz-622.0800 or M2021-yz-622.0800
• A lower phase detector frequency should be used for
Four sets of divider values to enable
adjustment of bandwidth and jitter
tolerance
M2020/21 Datasheet Rev 1.0
P Value
for
for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz.
When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive. The LOL pin
should not be used during loop timing mode.
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M2020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED CLOCK PLL
Product Data Sheet
FUNCTIONAL DESCRIPTION
The M2020/21 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchronized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance and establishes the output
frequency of the VCSO (Voltage Controlled SAW
Oscillator). In a given M2020/21 device, the VCSO
center frequency is fixed. A common center frequency
is 622.08MHz, for SONET for SDH optical network
applications. The VCSO center frequency is specified at
time of order (see “Ordering Information” on pg. 10).
The VCSO has a guaranteed tuning range of ±120 ppm
(commercial temperature grade).
Pin selectable dividers are used within the PLL and
for the output clock. This enables tailoring of device
functionality and performance. The Mfin divider controls
the overall PLL multiplication ratio and thus determines
the input reference clock (see Table 3, on pg. 3). The
M and R dividers control the phase detector frequency
(see Table 4). The P divider scales the VCSO output
enabling lower output frequency selections (Table 5).
The M2020/21 includes a Loss of Lock (LOL) indicator,
which provides status information to system
management software. A Narrow Bandwidth (NBW)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Configuration of a single-ended input has been
facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2,
with 50kΩ to Vcc and 50kΩ to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
LVCMOS/
LVTTL
DIF_REF0
50k Ω
MUX
50kΩ
nDIF_REF0
0
X
VCC
DIF_REF1
VCC
50kΩ
1
127Ω
82Ω
LVPECL
VCC
50k Ω
VCC
127 Ω
50kΩ
82 Ω
50kΩ
nDIF_REF1
REF_SEL
M2020/21
Figure 4: Input Reference Clocks
Differential Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127Ω
and 82Ω resistors) is ideally suited for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50Ω load termination and the VTT bias voltage.
Single-ended Inputs
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide
SONET/SDH MTIE and TDEV compliance during a
reference clock reselection.
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
Allowance for a single-ended input has been facilitated
by a unique input resistor bias scheme, which is
described next and shown in Figure 4.
Input Reference Clocks
PLL Operation
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
The M2020/21 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
M2020/21 Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
The PLL will work correctly, meaning it will phase-lock
the VCSO output to the input reference clock, when the
internal phase detector inputs are able to run at the
same frequency. This means the PLL dividers must be
set appropriately and a suitable reference frequency
must be chosen for the intended output frequency.
When the PLL is not set up appropriately, the VCSO is
forced to its upper or lower operating limit which is
typically about 250 ppm above or below the VCSO
center frequency (no more than 500 ppm above or
below).
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M2020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED CLOCK PLL
Product Data Sheet
In normal phase-locked condition, the instantaneous
phase error is measured by the phase detector and is
converted to charge pump current pulses. These
current pulses are then integrated by the external loop
filter to create a VCSO control voltage. The loop filter
acts as a low pass filter to remove unwanted reference
clock jitter above a determined frequency or PLL
bandwidth. For reference phase jitter frequencies within
the loop bandwidth, phase jitter amplitude is passed on
to the output clock according to the PLL loop frequency
response curve.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, and the input
reference frequency (Fin) is:
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the FOUT and nFOUT pins of the device. A
logic 0 is then present on the clock net. The impedance
of the clock net is then set to 50Ω by the external circuit
resistors. (This is in distinction to a CMOS output in
TriState, in which case the net goes to a high
impedance and the logic value floats.) The 50Ω
impedance level of the LVPECL TriState allows
manufacturing In-circuit Test to drive the clock net with
an external 50Ω generator to validate the integrity of
clock net and the clock load.
Any unused output (single-ended or differential) should
be left unconnected (floating) in system application.
This minimizes output switching current and therefore
minimizes noise modulation of the VCSO.
M
Fvcso = Fin × Mfin × ---R
Example Frequency and Divider Combinations
Using M2021-yz-622.0800
Fvcso =
622.08
Fin
x
38.88
77.76
155.52
622.08
Mfin x M/R
16 x (1/1, 4/4, etc.)
8 x (1/1, 4/4, etc.)
4 x (1/1, 4/4, etc.)
1 x (1/1, 4/4, etc.)
Table 6: Example I/O Clock Frequency Combinations
The M, R, and Mfin dividers can be set by pin configuration using the input pins MR_SEL1, MR_SEL0, FIN_SEL1, and
FIN_SEL0.
Post-PLL Divider
The M2020/21 also features a post-PLL (P) divider.
Through use of the P divider, the device’s output
frequency (Fout) can be that of the VCSO (such as
622.08MHz) or the VCSO frequency divided by 4, 8 or 32
(common optical reference clocks in SONET and SDH
systems).
The P_SEL2:0 pins select the value for the P divider. (See
Table 5 on pg. 3.)
Accounting for the P divider, the complete relationship
between the input clock reference frequency (Fin) and
output clock frequency (Fout) is defined as:
M × Mfin
Fvcso = Fin × ------------------------Fout = ------------------P
R× P
Due to the narrow tuning range of the VCSO (+120ppm
guaranteed), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
M2020/21 Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
Narrow Bandwidth (NBW) Control Pin
A Narrow Loop Bandwidth control pin (NBW pin) is
included to enable adjustment of the PLL loop
bandwidth. In wide bandwidth mode (NBW=0), the
internal resistor Rin is 100kΩ . With the NBW pin
asserted (NBW=1), the internal resistor Rin is changed to
2100kΩ . This lowers the loop bandwidth by a factor of
about 21 (2100 / 100) and lowers the damping factor by
about 4.6 (the square root of 21), assuming the same
external loop filter component values.
Loss of Lock Indicator (LOL) Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives LOL to logic 0. Under
circumstances when the VCSO cannot fully phase lock
to the input (as measured by a greater than 4 ns
discrepancy between the feedback and reference clock
rising edges at the LOL Phase Detector) the LOL output
goes to logic 1. The LOL pin will return back to logic 0
when the phase detector error is less than 2 ns. The
loss of lock indicator is a low current LVCMOS output.
Guidelines for Using LOL
In a given application, the magnitude of peak-to-peak
jitter at the phase detector will usually increase as the R
divider is increased. If the LOL pin will be used to detect
an unusual clock condition, or a clock fault, the
MR_SEL1:0 pins should be set to provide a phase detector
frequency of 5MHz or greater (the phase detector
frequency is equal to Fin divided by the R divider).
Otherwise, false LOL indications may result. A phase
detector frequency of 10MHz or greater is desirable
when reference jitter is over 500ps, or when the device is
used within a noisy system environment. LOL should not
be used when the device is used in a loop timing
application.
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M2020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED CLOCK PLL
Product Data Sheet
Optional Hitless Switching and Phase Build-out
HS/PBO Operation
The M2020/21 is available with a Hitless Switching
feature that is enabled during device manufacturing.
In addition, a Phase Build-out feature is also offered.
These features are offered as device options and are
specified by device order code. Refer to “Ordering
Information” on pg. 10.
Once triggered, the following HS/PBO sequence
occurs:
The Hitless Switching feature (with or without Phase
Build-out) is designed for applications where switching
occurs between two stable system reference clocks. It
should not be used in loop timing applications, or when
reference clock jitter is greater than 1 ns pk-pk. The
Hitless Switching sequence is triggered by the LOL
circuit, which is activated by a 4 ns phase transient. This
magnitude of phase transient can generated by the
CDR (Clock & Data Recovery unit) in loop timing mode,
especially during a system jitter tolerance test. It can
also be generated by some types of Stratum clock
DPLLs (digital PLL), especially those that do not include
a post de-jitter APLL (analog PLL).
When the M2020/21 is operating in wide bandwidth
mode (NBW=0), the optional Hitless Switching function
puts the device into narrow bandwidth mode during the
Hitless Switching sequence. This allows the PLL to lock
the new input clock phase gradually. With proper
configuration of the external loop filter, the output clock
phase change complies with MTIE and TDEV
specifications for GR-253 (SONET) and ITU G.813
(SDH) during input reference clock changes.
1. The HS function disables the PLL Phase Detector
and puts the device into NBW (narrow bandwidth)
mode. The internal resistor Rin is changed to
2100kΩ . See External Loop Filter on pg. 6.
2. If included, the PBO function adds to (builds out) the
phase in the clock feedback path (in VCSO clock
cycle increments) to align the feedback clock with
the (new) reference clock input phase.
3. The PLL Phase Detector is enabled, allowing the
PLL to re-lock.
4. Once the PLL Phase Detector feedback and input
clocks are locked to within 2 ns for eight consecutive
cycles, a timer (WBW timer) for resuming wide
bandwidth (in 175 ns) is started.
5. When the WBW timer times out, the device reverts
to wide loop bandwidth mode (i.e., Rin is returned to
100kΩ) and the HS/PBO function is re-armed.
The LOL pin will indicate lock status on a cycle-to-cycle
basis and may be intermittent until PLL phase lock has
fully stabilized.
External Loop Filter
To provide stable PLL operation, the M2020/21 requires
the use of an external loop filter. This is provided via the
provided filter pins (see Figure 5). The loop filter is
implemented as a differential circuit to minimize system
noise interference. .
RLOOP
The optional proprietary Phase Build-out (PBO)
function enables the PLL to absorb most of the phase
change of the input clock during reference switching.
The PBO function selects a new VCSO clock edge for
the PLL Phase Detector feedback clock, selecting the
edge closest in phase to the new input clock phase.
This reduces re-lock time, the generation of wander,
and extra output clock cycles.
CPOST
RLOOP
OP_IN
nOP_IN
4
9
RPOST
CLOOP
OP_OUT
nOP_OUT
8
VC
6
7
PLL bandwidth is affected by loop filter component
values, “M” and “Mfin” values, and the “PLL Loop
Constants” listed in AC Characteristics on pg. 9.
The HS function (or the combined HS/PBO function)
is armed after the device locks to the input clock reference. Once armed, HS is triggered by the occurance of
a Loss of Lock condition. This would typically occur as a
consequence of a clock reference failure, a clock failure
upstream to the M2020/21, or a M2020/21 clock reference mux reselection.
The MR_SEL1 and MR_SEL0 settings can be used to
actively change PLL loop bandwidth in a given
application. See “M and R Divider Look-Up Table (LUT)”
on pg. 3.
See Table 7, Example Values for Loop Filter External
Components, on pg. 7.
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nVC
5
Figure 5: External Loop Filter
HS/PBO Sequence Trigger Mechanism
Integrated Circuit Systems, Inc.
RPOST
CPOST
The Hitless Switching and Phase Build-out functions
are triggered by the LOL circuit. For proper operation,
a low phase detector frequency must be avoided. See
“Guidelines for Using LOL” on pg. 5 for information
regarding the phase detector frequency.
M2020/21 Datasheet Rev 1.0
CLOOP
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M2020/21
Integrated
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Systems, Inc.
VCSO BASED CLOCK PLL
Product Data Sheet
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
Refer to the M2020/21 product web page at
www.icst.com/products/summary/m2020-2021.htm
for additional product information.
Example Values for Loop Filter External Components 1
for M2020-yz-622.0800 and M2021-yz-622.0800
VCSO Parameters: KVCO = 800kHz/V, RIN = 100kΩ (pin NBW = 0), VCSO Bandwidth = 700kHz.
Purpose
Device Configuration
FVCSO FIN_SEL MRSEL
1:0
1:0
(MHz)
(MHz)
FRef
Frequency
Translation,
General
Usage
R post
0 1
11.5kΩ
2.2µF
32.4kΩ
470p
1kHz
6.0
0.05
0 1
622.08 0 0 2 0 0
23.2kΩ
1.0µF
32.4kΩ
470p
1kHz
6.5
0.06
11.5kΩ
2.2µF
32.4kΩ
470p
1kHz
6.7
0.05
0 0
23.2kΩ
1.0µF
32.4kΩ
470p
1kHz
6.5
0.06
1 0
5.6kΩ
10µF
68kΩ
470p
500Hz
6.3
0.05
0 1
622.08 0 0 2 0 1
8.2kΩ
10µF
100kΩ
470p
360Hz
6.5
0.05
12.0kΩ
10µF
100kΩ
470p
260Hz
6.7
0.05
8.2kΩ
10µF
100kΩ
470p
360Hz
6.5
0.05
622.08 1 0
77.76
622.08 0 1
3
19.44
622.08
Jitter
Attenuation, 77.76
Narrow
38.88 2
Bandwidth
19.44
3
Nominal Performance With These Values
C loop
155.52
38.88 2
Example External Component Values
R loop
622.08 0 0
3
622.08 1 1
622.08 0 1
622.08 0 0
3
0 0
C post PLL Loop Damping Passband
Bandwidth Factor Peaking (dB)
Table 7: Example Values for Loop Filter External Components
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: M2021 only.
Note 3: M2020 only.
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter
Rating
Unit
VI
Inputs
-0.5 to VCC +0.5
V
VO
Outputs
-0.5 to VCC +0.5
V
VCC
Power Supply Voltage
TS
Storage Temperature
4.6
V
-45 to +100
oC
Table 8: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter
VCC
Positive Supply Voltage
TA
Ambient Operating Temperature
Commercial
Industrial
Min
Typ
Max
Unit
3.135
3.3
3.465
V
oC
+70
+85
0
-40
oC
Table 9: Recommended Conditions of Operation
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VCSO BASED CLOCK PLL
Product Data Sheet
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz,
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Power Supply VCC
Positive Supply Voltage
ICC
Power Supply Current
All
Differential
Inputs
VP-P
Peak to Peak Input Voltage
VCMR
Common Mode Input
CIN
Input Capacitance
Differential
Inputs with
Pull-down
IIH
Input High Current (Pull-down)
IIL
Input Low Current (Pull-down)
Differential
Inputs
Biased to
VCC/2
All LVCMOS
/ LVTTL
Inputs
IIH
Input High Current (Biased)
IIL
Input Low Current (Biased)
Rbias
Biased to Vcc/2
VIH
Input High Voltage
VIL
Input Low Voltage
CIN
Input Capacitance
LVCMOS /
LVTTL
Inputs with
Pull-down
LVCMOS /
LVTTL
Inputs with
Pull-UP
Differential
Outputs
IIH
Input High Current (Pull-down)
IIL
Input Low Current (Pull-down)
LVCMOS
Output
Min
Typ
Max
Unit Conditions
3.135
3.3
3.465
V
175
225
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
DIF_REF0, DIF_REF1
0.15
V
0.5
Vcc - .85 V
pF
150
µA
µA
50
IIH
Input High Current (Pull-UP)
IIL
Input Low Current (Pull-UP)
Rpullup
Internal Pull-UP Resistance
VOH
Output High Voltage
VOL
Output Low Voltage
VP-P
Peak to Peak Output Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
Vcc + 0.3 V
2
-0.3
V
4
pF
150
µA
µA
µA
-150
Vcc - 1.4
Vcc - 1.0 V
Vcc - 2.0
Vcc - 1.7 V
1
0.4
0.85
V
2.4
VCC
V
IOH= 1mA
GND
0.4
V
IOL= 1mA
LOL
Networking & Communications
VCC = 3.456V
VIN = 0 V
kΩ
50
Table 10: DC Characteristics
8 of 10
●
µA
5
FOUT0, nFOUT0,
FOUT1, nFOUT1
VCC = VIN =
3.456V
kΩ
50
Note 1: Single-ended measurement. See Figure 6, Output Rise and Fall Time, on pg. 9.
M2020/21 Datasheet Rev 1.0
0.8
-5
NBW
VIN =
0 to 3.456V
kΩ
See Figure 4
REF_SEL, FIN_SEL1, FIN_SEL0,
MR_SEL1, MR_SEL0, P_SEL2,
P_SEL1, P_SEL0
µA
µA
-150
REF_SEL, FIN_SEL1, FIN_SEL0,
MR_SEL1, MR_SEL0, P_SEL2,
P_SEL1, P_SEL0, NBW
VCC = VIN =
3.456V
kΩ
150
Rpulldown Internal Pull-down Resistance
Integrated Circuit Systems, Inc.
4
-5
Rpulldown Internal Pull-down Resistance
nDIF_REF0, nDIF_REF1
mA
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VCSO BASED CLOCK PLL
Product Data Sheet
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz,
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
PLL Loop
Constants 1
Min
Typ
Max
Unit Conditions
FIN
Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
10
700
MHz
FOUT
Output Frequency
FOUT0, nFOUT0, FOUT1, nFOUT1
15
700
MHz
APR
VCSO Absolute
Pull-Range
Commercial
KVCO
VCO Gain
RIN
Internal Loop Resistor
±120
±50
Industrial
Wide Bandwidth
Narrow Bandwidth
BWVCSO VCSO Bandwidth
Φn
Phase Noise
and Jitter
Single Side Band
Phase Noise
@622.08MHz
1kHz Offset
700
kHz
-73
-103
-126
Fin=19.44 or
38.88 MHz
Mfin=32 or 16,
M=1, R=1
0.5
55
40
50
60
200
450
500
ps
20% to 80%
200
450
500
ps
20% to 80%
Output Duty Cycle 2
P = 4, 8, or 32
45
P=1
50kHz to 80MHz
FOUT0, nFOUT0, FOUT1, nFOUT1
kΩ
50
odc
Output Fall Time 2 for
2100
0.25
12kHz to 20MHz
tF
kΩ
0.5
Jitter (rms)
@622.08MHz
FOUT0, nFOUT0, FOUT1, nFOUT1
100
0.25
100kHz Offset
J(t)
tR
800
ppm
ppm
kHz/V
dBc/Hz
dBc/Hz
dBc/Hz
ps
ps
%
%
10kHz Offset
Output Rise Time 2 for
±200
±150
Table 11: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 7, Example Values for Loop Filter External Components, on pg. 7.
Note 2: See Parameter Measurement Information on pg. 9.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
80%
FOUT
80%
VP-P
Clock Output
tPW
(Output Pulse Width)
20%
tF
20%
tR
tPERIOD
odc =
tPW
tPERIOD
Figure 7: Output Duty Cycle
Figure 6: Output Rise and Fall Time
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Product Data Sheet
VCSO BASED CLOCK PLL
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the M2020/21 product web page at
www.icst.com/products/summary/m2020-2021.htm
for recommended PCB footprint, solder mask,
furnace profile, and related information.
Figure 8: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
Part Numbering Scheme
Part Number:
Standard VCSO Output Frequencies (MHz)*
622.0800
669.3120
625.0000
669.3266
Frequency Input Divider Option
0 = Mfin Divider selections of: 32, 8, 4, or 1
1 = Mfin Divider selections of: 16, 8, 4, or 1
Output type
1 = LVPECL
(For CML or LVDS clock output, consult factory)
627.3296
670.8386
644.5313
672.1600
666.5143
690.5692
Hitless Switching / Phase Build-out Options
1 = none
2 = Hitless Switching
3 = Hitless Switching with Phase Build-out
Temperature
“ - ” = 0 to +70 oC (commercial)
I = - 40 to +85 oC (industrial)
VCSO Frequency (MHz)
See Table 12, right. Consult ICS for other frequencies.
669.1281
669.3120
M202x- yz - xxx.xxxx
Figure 9: Part Numbering Scheme
Table 12: Standard VCSO Output Frequencies
Note *: Fout can equal Fvcso divided by: 1, 4, 8, or 32
Consult ICS for the availability of other VCSO frequencies.
Example Part Numbers
VCSO Frequency (MHz) Temperature
622.08
625.00
commercial
industrial
commercial
industrial
Order Part Number
M2020 - 11 - 622.0800 or M2021- 11 - 622.0800
M2020 - 11I 622.0800 or M2021- 11I 622.0800
M2020 - 11 - 625.0000 or M2021 - 11 - 625.0000
M2020 - 11I 625.0000 or M2021- 11I 625.0000
Table 13: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M2020/21 Datasheet Rev 1.0
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