Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 LP3995 Micropower 150-mA CMOS Voltage Regulator With Active Shutdown 1 Features 3 Description • • • • • • • • • • • • • • • The LP3995 linear regulator is designed to meet the requirements of portable battery-powered applications, providing an accurate output voltage with low noise and low quiescent current. Ideally suited for powering RF and analog devices, this device can also be used to meet more general circuit needs in which a fast turnoff is essential. 1 Input Range: 2.5 V to 6 V Accurate Output Voltage: ±75 mV / 2% Typical Dropout with 150 mA Load: 60 mV Virtually Zero Quiescent Current When Disabled Low Output Voltage Noise Stable With a 1-µF Output Capacitor Output Current: 150 mA Fast Turnon: 30 µs (Typical) Fast Turnoff: 175 µs (Typical) Stable With Ceramic Capacitor Logic Controlled Enable Fast Turnon Active Disable for Fast Turnoff Thermal-Overload and Short-Circuit Protection −40 to +125°C Junction Temperature Range for Operation For battery-powered applications the low dropout and low ground current provided by the device allows the lifetime of the battery to be maximized. The Enable(/Disable) control function allows the system to further extend the battery lifetime by reducing the power consumption to virtually zero. This function also incorporates an active discharge circuit on the output for faster device shutdown. Where the fast turnoff is not required the LP3999 linear regulator is recommended. The LP3995 also features internal protection against short-circuit currents and overtemperature conditions. The LP3995 is designed to be stable with small 1-µF ceramic capacitors. The small outline of the LP3995 DSBGA package with the required ceramic capacitors can realize a system application within minimal board area. Performance is specified for a −40°C to +125°C temperature range. 2 Applications • • • • • GSM Portable Phones CDMA Cellular Handsets Wideband CDMA Cellular Handsets Bluetooth Devices Portable Information Appliances The LP3995 is available in fixed output voltages from 1.5 V to 3.3 V, in DSBGA or WSON packages. For other package options or output-voltage options, contact your local TI sales office. Device Information(1) PART NUMBER LP3995 PACKAGE BODY SIZE DSBGA (5) 1.502 mm × 1.045 mm (MAX) WSON (6) 3.29 mm × 2.92 mm (NOM) (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit 1 Input IN (C3) 1 µF OUT CIN 6 (C1) 1 µF LP3995 COUT Load Enable 3 (A1) BYPASS EN 4 (A3) GND (B2) 2 10 nF CBP 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. 7 Parameter Measurement Information ................ 10 8 Detailed Description ............................................ 11 7.1 Input Test Signals ................................................... 10 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 11 8.4 Device Functional Modes........................................ 12 9 Application and Implementation ........................ 13 9.1 Application Information............................................ 13 9.2 Typical Application ................................................. 13 10 Power Supply Recommendations ..................... 17 11 Layout................................................................... 17 11.1 11.2 11.3 11.4 Layout Guidelines ................................................. Layout Examples................................................... DSBGA Mounting.................................................. DSBGA Light Sensitivity ....................................... 17 17 18 18 12 Device and Documentation Support ................. 19 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 13 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2013) to Revision F Page • Added Device Information and Pin Configuration and Functions sections, ESD Ratings table, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections ................................................. 1 • Changed Thermal Values, ..................................................................................................................................................... 1 • Deleted Lead Temp from Abs Max table (in POA); delete Heatsinking sections re: specific packages (outdated info) ....... 4 Changes from Revision D (March 2013) to Revision E • 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 18 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 LP3995 www.ti.com SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions YZR Package 5-Pin DSBGA Top View BYPASS A3 A1 EN B2 GND IN C3 IN C3 C1 OUT C1 OUT BYPASS A3 B2 GND A1 EN NGD Package 6-Pin WSON Top View IN 1 Device Code GND 2 EN 3 6 OUT OUT 6 5 N/C N/C 5 4 BYPASS 1 IN 2 GND BYPASS 4 PAD GND 3 EN PAD GND Pin Functions PIN NAME TYPE DESCRIPTION WSON DSBGA BYPASS 4 A3 — EN 3 A1 Input GND 2 B2 Ground Common ground The exposed thermal pad on the bottom of the WSON package should be connected to a copper thermal pad on the PCB under the package. The use of thermal vias to remove heat from the package into the PCB is recommended. Connect the exposed thermal pad to ground potential or leave floating. Do not connect the thermal pad to any potential other than the same ground potential seen at device pin 2. For additional information on using TI's non pull-back WSON package, see TI Application Note AN- 1187 Leadless Leadframe Package (LLP) (SNOA401). Thermal Pad — Ground IN 1 C3 Input N/C 5 — — OUT 6 C1 Output GND Bypass capacitor connection. Connect a 0.01-µF capacitor for noise reduction. Enable input; Disables the regulator when ≤ 0.4 V. Enables the regulator when ≥ 0.9 V. Voltage supply input No internal connection. This pin can be connected to GND, or left open. Voltage output. Connect this output to the load circuit. Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 3 LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT Input voltage, VIN –0.3 6.5 V Output voltage –0.3 (VIN + 0.3 V) to 6.5 V Enable input voltage –0.3 6.5 V 150 °C Junction temperature Continuous power dissipation (4) Internally limited −65 Storage temperature, Tstg (1) (2) (3) (4) 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office / Distributors for availability and specifications. In applications where high power dissipation and/or poor thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(MAX)) is dependant on the maximum operating junction temperature (TJ(MAX-OP)), the maximum power dissipation (PD(MAX)), and the junction-to-ambient thermal resistance in the application (RθJA). This relationship is given by: TA(MAX) = TJ(MAX-OP) − (PD(MAX) × RθJA). 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±2000 Machine model V ±200 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Input voltage, VIN NOM MAX UNIT 2.5 6 V 0 6 V Junction temperature −40 125 °C Ambient temperature (1) −40 85 °C Enable input voltage (1) 4 In applications where high power dissipation and/or poor thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(MAX)) is dependant on the maximum operating junction temperature (TJ(MAX-OP)), the maximum power dissipation (PD(MAX)), and the junction-to-ambient thermal resistance in the application (RθJA). This relationship is given by: TA(MAX) = TJ(MAX-OP) − (PD(MAX) × RθJA). Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 LP3995 www.ti.com SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 6.4 Thermal Information LP3995 THERMAL METRIC (1) RθJA (2) Junction-to-ambient thermal resistance, High-K RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB RθJC(bot) (1) (2) (3) YZR (DSBGA) NGD (WSON) 5 PINS 6 PINS UNIT 181.2 68.5 (3) °C/W 0.8 71.8 °C/W 107.9 35.2 °C/W 0.5 1.4 °C/W Junction-to-board characterization parameter 107.9 35.0 °C/W Junction-to-case (bottom) thermal resistance N/A 8.1 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. The PCB for the NGD (WSON) package RθJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5. 6.5 Electrical Characteristics Unless otherwise noted, VEN = 1.5 V, VIN = VOUT + 1 V, CIN = 1 µF, IOUT = 1 mA, COUT = 1 µF, CBYPASS = 0.01 µF. Typical (TYP) values and limits apply for TJ = 25°C; minimum (MIN) and maximum (MAX) apply over the full temperature range for operation, −40 to +125°C, unless otherwise specified in the Test Conditions. (1) (2) PARAMETER VIN TEST CONDITIONS Input voltage MIN TYP MAX UNIT 2.5 6 V IOUT = 1 mA, TJ = 25°C –50 50 IOUT = 1 mA –75 75 Line regulation error VIN = (VOUT(NOM)+1 V) to 6V, IOUT = 1 mA –3.5 3.5 µV/mA Load regulation error, DSBGA IOUT = 1 mA to 150 mA 10 75 µV/mA Load regulation error, WSON IOUT = 1 mA to 150 mA 70 125 µV/mA ƒ = 1 kHz, IOUT = 1 mA 55 ƒ = 10 kHz, IOUT = 1 mA 53 DEVICE OUTPUT: 1.5 ≤ VOUT < 1.8V Output voltage tolerance ΔVOUT PSRR Power supply rejection ratio (3) mV dB DEVICE OUTPUT: 1.8 V ≤ VOUT < 2.5 V IOUT = 1 mA, TJ = 25°C –50 50 IOUT = 1 mA –75 75 Line regulation error, DSBGA VIN = (VOUT(NOM)+1 V) to 6 V, IOUT = 1 mA –2.5 2.5 mV/V Line regulation error, WSON VIN = (VOUT(NOM)+1 V) to 6 V IOUT = 1 mA –3.5 3.5 mV/V Load regulation error, DSBGA IOUT = 1 mA to 150 mA 10 75 µV/mA Load regulation error, WSON IOUT = 1 mA to 150 mA 80 125 µV/mA ƒ = 1 kHz, IOUT = 1 mA 55 ƒ = 10 kHz, IOUT = 1 mA 50 Output voltage tolerance ΔVOUT PSRR (1) (2) (3) Power supply rejection ratio (3) mV dB All limits are ensured. All electrical characteristics having room-temperature limits are tested during production at TJ = 25°C or correlated using Statistical Quality Control methods. Operation over the temperature specification is specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. VOUT(NOM) is the stated output voltage option for the device. This electrical specification is ensured by design. Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 5 LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, VEN = 1.5 V, VIN = VOUT + 1 V, CIN = 1 µF, IOUT = 1 mA, COUT = 1 µF, CBYPASS = 0.01 µF. Typical (TYP) values and limits apply for TJ = 25°C; minimum (MIN) and maximum (MAX) apply over the full temperature range for operation, −40 to +125°C, unless otherwise specified in the Test Conditions. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DEVICE OUTPUT: 2.5 V ≤ VOUT ≤ 3.3 V Output voltage tolerance ΔVOUT –2 2 IOUT = 1 mA –3 3 –0.1 0.1 % of VOUT(NOM) Line regulation error VIN = (VOUT(NOM)+1 V) to 6 V IOUT = 1 mA Load regulation error, DSBGA IOUT = 1 mA to 150 mA 0.0004 0.002 %/mA Load regulation error, WSON IOUT = 1 mA to 150 mA 0.002 0.005 %/mA IOUT = 1 mA 0.4 2 IOUT = 150 mA 60 100 ƒ = 1 kHz, IOUT = 1 mA 60 ƒ = 10 kHz, IOUT = 1 mA 50 Dropout voltage Power supply rejection ratio (3) PSRR IOUT = 1 mA, TJ = 25°C %/V mV dB FULL VOUT RANGE ILOAD See (3) (4) Load current 0 VEN = 1.5 V, IOUT = 0 mA IQ Quiescent current VEN = 1.5 V, IOUT = 150 mA ISC Short-circuit current limit VEN = 0.4 V EN Output noise voltage TSHUTDOWN Thermal shutdown BW = 10 Hz to 100 kHz, VIN = 4.2 V, IOUT = 1 mA (3) Temperature µA 85 150 140 200 0.003 1.5 µA 450 mA 25 µVRMS 160 Hysteresis °C 20 ENABLE CONTROL CHARACTERISTICS IEN Maximum input current at EN input VIL Low input threshold VIH High input threshold (4) VEN = 0 V and VIN = 6 V 0.001 µA 0.4 V 0.9 V The device maintains a stable, regulated output voltage without load. 6.6 Timing Requirements MIN tON Turnon time to 95% level tOFF Turnoff time to 5% level (1) (2) (3) 6 (1) (2) (1) (3) NOM MAX UNIT 30 µs 175 µs This electrical specification is ensured by design. Time from VEN = 0.9 V to VOUT = 95% (VOUT(NOM)). Time from VEN = 0.4 V to VOUT = 5% (VOUT(NOM)). Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 LP3995 www.ti.com SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 6.7 Typical Characteristics Unless otherwise specified, CIN = COUT = 1 µF ceramic, VIN = VOUT + 1 V, TA = 25°C, EN pin is tied to VIN. VOUT = 1.8 V Figure 1. Output Voltage Change vs Temperature Figure 2. Ground Current vs Load Current VOUT = 2.8 V Figure 3. Ground Current vs Load Current Figure 4. Ground Current vs VIN at 25°C Figure 5. Ground Current vs VIN at 125°C Figure 6. Dropout vs Load Current Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 7 LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF ceramic, VIN = VOUT + 1 V, TA = 25°C, EN pin is tied to VIN. VOUT = 1.8 V Figure 7. Short-Circuit Current Figure 8. Ripple Rejection VOUT = 2.8 V VOUT = 2.8 V Figure 10. Enable Start-Up Time Figure 9. Ripple Rejection VOUT = 2.8 V VOUT = 1.8 V Figure 11. Enable Start-Up Time 8 Figure 12. Enable Start-Up Time Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 LP3995 www.ti.com SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) Unless otherwise specified, CIN = COUT = 1 µF ceramic, VIN = VOUT + 1 V, TA = 25°C, EN pin is tied to VIN. VOUT = 1.8 V VOUT = 2.8 V Figure 13. Enable Start-Up Time Figure 14. Turnoff Time VOUT = 1.8 V Figure 15. Turnoff Time Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 9 LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 www.ti.com 7 Parameter Measurement Information 7.1 Input Test Signals 30 us 30 us | 600 mV VIN = VOUT(NOM) + 1V 600 us 4.6 ms Figure 16. Line Transient Response Input Test Signal 50 mV VIN = VOUT(NOM) + 1V Figure 17. PSRR Input Test Signal 10 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 LP3995 www.ti.com SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 8 Detailed Description 8.1 Overview The LP3995 device is a CMOS voltage regulator with a low input operating voltage tolerance. Key protection circuits, including thermal-overload and short-circuit protection, are integrated in the device. Using the EN pin, the device may be controlled to provide a shutdown state, in which negligible supply current is drawn. The LP3995 is designed to be stable with space-saving ceramic capacitors. 8.2 Functional Block Diagram OUT IN VREF EN BYPASS Fast turnon and turnoff + - R1 Overcurrent Thermal Prot. R2 GND 8.3 Feature Description 8.3.1 Enable (EN) The EN pin is used to control the ON or OFF status of the LP3995. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. 8.3.2 Fast Turnoff When the EN pin voltage is lower than the VIL threshold, the output is disabled, and the pull-down circuitry is activated to discharge the output capacitance. 8.3.3 Low Output Noise The BYPASS pin is an external connection into the LP3995 band-gap circuitry allows the addition of an external capacitor to reduce output noise . A fast-charge circuit is controlled by the enable circuitry to reduce start-up delays. The capacitor on the BYPASS pin also prevents overshoot on the output during startup. 8.3.4 Output Capacitor The LP3995 requires at least a 1-µF low ESR ceramic capacitor at the OUT pin. 8.3.5 Thermal Overload Protection (TSD) Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry automatically enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating. The thermal shutdown circuitry of the LP3995 has been designed to protect against temporary thermal overload conditions. The thermal shutdown circuitry is not intended to replace proper heat-sinking. Continuously running the LP3995 device into thermal shutdown may degrade device reliability. Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 11 LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 www.ti.com 8.4 Device Functional Modes 8.4.1 Enable Operation The LP3995 may be switched ON or OFF by a logic input at the EN pin, VEN. A high voltage at this pin turns the device on. When the EN pin is low, the regulator output is off and the device typically consumes 3 nA. If the application does not require the shutdown feature, the EN pin should be tied to VIN to keep the regulator output permanently on. To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in Electrical Characteristics under VIL and VIH. 12 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 LP3995 www.ti.com SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LP3995 can provide 150-mA output current with 2.5-V to 6-V input. It is stable with a 1-μF ceramic output capacitor. An optional external bypass capacitor reduces the output noise without slowing down the load transient response. Typical output noise is 25 μVRMS at frequencies from 10 Hz to 100 kHz. Typical power supply rejection is 60 dB at 1 kHz. 9.2 Typical Application 1 Input IN (C3) OUT CIN 1 µF 6 (C1) 1 µF LP3995 COUT Load 3 Enable (A1) BYPASS EN 4 (A3) GND (B2) 2 10 nF CBP Figure 18. LP3995 Typical Application 9.2.1 Design Requirements For typical CMOS voltage regulator applications, use the parameters listed in Table 1. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Minimum input voltage 2.5 V Minimum output voltage 1.8 V Output current 150 mA 9.2.2 Detailed Design Procedure 9.2.2.1 External Capacitors In common with most regulators, the LP3995 requires external capacitors to ensure stable operation. The LP3995 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. 9.2.2.2 Input Capacitor An input capacitor is required for stability. It is recommended that a 1-µF capacitor be connected between the LP3995 IN pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 13 LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 www.ti.com NOTE Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the equivalent series resistance (ESR) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains ≅ 1 µF over the entire operating temperature range. 9.2.2.3 Output Capacitor The LP3995 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types Z5U, Y5V or X7R) in the 1-µF to 10-µF range, and with ESR between 5 mΩ to 500 mΩ, is suitable in the LP3995 application circuit. For this device the output capacitor should be connected between the OUT pin and ground. It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 mΩ to 500 mΩ for stability. Table 2. Recommended Output Capacitor PARAMETER COUT (1) Output Capacitor TEST CONDITIONS Capacitance (1) ESR MIN TYP 0.7 1 5 MAX Units 500 mΩ µF The capacitor tolerance should be ±30% or better over the temperature range. The recommended capacitor type is X7R however, dependant on the application X5R, Y5V, and Z5U can also be used. 9.2.2.4 No-Load Stability The LP3995 remains stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. 9.2.2.5 Capacitor Characteristics The LP3995 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 1 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LP3995. The temperature performance of ceramic capacitors varies by type. Most large value ceramic capacitors (≥ 2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25°C to +85°C. A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1-µF to 4.7-µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. 14 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 LP3995 www.ti.com SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 9.2.2.6 Noise Bypass Capacitor A bypass capacitor should be connected between the BYPASS pin and ground to significantly reduce the noise at the regulator output. This device pin connects directly to a high impedance node within the bandgap reference circuitry. Any significant loading on this node causes a change on the regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy. The use of a 0.01-µF bypass capacitor is strongly recommended to prevent overshoot on the output during startup. The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High quality ceramic capacitors with NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current. Unlike many other LDOs, the addition of a noise reduction capacitor does not effect the transient response of the device. 9.2.2.7 Fast Turnoff and Turnon The controlled switch-off feature of the device provides a fast turn off by discharging the output capacitor via an internal FET device. This discharge is current limited by the RDSon of this switch. Fast turnon is ensured by control circuitry within the reference block allowing a very fast ramp of the output voltage to reach the target voltage. 9.2.2.8 Power Dissipation The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. Equation 1 restates the equation given in note 5 of Absolute Maximum Ratings: TA(MAX) = TJ(MAX-OP) − (PD(MAX) × RθJA) (1) The allowable power dissipation for the device in a given package can be calculated: PD = TJ(MAX) – TA / RθJA (2) With an RθJA = 255°C/W, the device in the DSBGA package returns a value of 392 mW with a maximum junction temperature of 125°C. With an RθJA = 88°C/W, the device in the WSON package returns a value of 1.136 mW with a maximum junction temperature of 125°C. The actual power dissipation across the device can be represented by Equation 3: PD = (VIN − VOUT) × IOUT (3) This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. Equation 2 and Equation 3 should be used to determine the optimum operating conditions for the device in the application. This thermal resistance (RθJA) is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-spreading area and is to be used only as a relative measure of package thermal performance. For a welldesigned thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heatsink. 9.2.2.9 Estimating Junction Temperature The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are used in accordance with Equation 4 or Equation 5. Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 15 LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 www.ti.com TJ(MAX) = TTOP + (ΨJT × PD(MAX)) where • • PD(MAX) is explained in Equation 2 TTOP is the temperature measured at the center-top of the device package. TJ(MAX) = TBOARD + (ΨJB × PD(MAX)) (4) where • • PD(MAX) is explained in Equation 2. TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the package edge. (5) For more information about the thermal characteristics ΨJT and ΨJB, see TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953); for more information about measuring TTOP and TBOARD, see the TI Application Report Using New Thermal Metrics (SBVA025); and for more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017). Aforementioned application notes are available at www.ti.com. 9.2.3 Application Curves VOUT = 2.8 V VOUT = 2.8 V Figure 19. Line Transient Response Figure 20. Load Transient Response VOUT = 1.8 V Figure 21. Load Transient Response 16 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 LP3995 www.ti.com SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 10 Power Supply Recommendations The LP3995 is designed to operate from an input voltage supply range from 2.5 V to 6 V. 11 Layout 11.1 Layout Guidelines The dynamic performance of the LP3995 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP3995. Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP3995, and as close as is practical to the package. The ground connections for CIN and COUT should be back to the LP3995 ground pin using as wide, and as short, of a copper trace as is practical. Connections using long trace lengths, narrow trace widths, and/or connections through vias should be avoided. These add parasitic inductances and resistance that result in inferior performance especially during transient conditions. 11.2 Layout Examples EN BYPASS A3 A1 B2 COUT C1 GND C3 CIN IN OUT Figure 22. LP3995 DSBGA Layout IN 1 6 CIN OUT COUT GND 2 5 GND EN 3 4 BYPASS Thermal Vias Figure 23. LP3995 WSON Layout Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 17 LP3995 SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 www.ti.com 11.3 DSBGA Mounting The DSBGA package requires specific mounting techniques that are detailed in TI's AN-1112 Application Report (SNVA009). Referring to the section Surface Mount Assembly Considerations, it should be noted that the pad style which must be used with the 5-pin package is NSMD (non-solder mask defined) type. For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device. 11.4 DSBGA Light Sensitivity Exposing the DSBGA device to direct sunlight may cause mis-operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device. The wavelengths that have the most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has little effect on performance. Tests carried out on a DSBGA test board showed a negligible effect on the regulated output voltage when brought within 1 cm of a fluorescent lamp. A deviation of less than 0.1% from nominal output voltage was observed. 18 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 LP3995 www.ti.com SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For additional information, see the following: • TI Application Note DSBGA Wafer Level Chip Scale Package (SNVA009). • TI Application Note Leadless Leadframe Package (LLP) (SNOA401). • TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953). • TI Application Report Using New Thermal Metrics (SBVA025). • TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017). 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated Product Folder Links: LP3995 19 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3995ILD-1.5/NOPB ACTIVE WSON NGD 6 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L020B LP3995ILD-1.8/NOPB ACTIVE WSON NGD 6 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L022B LP3995ILD-2.8/NOPB ACTIVE WSON NGD 6 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L026B LP3995ILD-3.0/NOPB ACTIVE WSON NGD 6 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L030B LP3995ILDX-2.8/NOPB ACTIVE WSON NGD 6 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L026B LP3995ITL-1.5/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITL-1.8/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITL-1.9/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITL-2.5/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITL-2.8/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITL-3.0/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITLX-1.5/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITLX-1.6/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITLX-1.8/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITLX-1.9/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITLX-2.1/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITLX-2.5/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 8-Oct-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3995ITLX-2.7/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 9 LP3995ITLX-2.8/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITLX-2.85/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 LP3995ITLX-3.0/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 9 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3995ILD-1.5/NOPB WSON NGD 6 1000 178.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP3995ILD-1.8/NOPB WSON NGD 6 1000 178.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP3995ILD-2.8/NOPB WSON NGD 6 1000 178.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP3995ILD-3.0/NOPB WSON NGD 6 1000 178.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP3995ILDX-2.8/NOPB WSON NGD 6 4500 330.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP3995ITL-1.5/NOPB DSBGA YZR 5 250 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITL-1.8/NOPB DSBGA YZR 5 250 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITL-1.9/NOPB DSBGA YZR 5 250 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITL-2.5/NOPB DSBGA YZR 5 250 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITL-2.8/NOPB DSBGA YZR 5 250 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITL-3.0/NOPB DSBGA YZR 5 250 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITLX-1.5/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITLX-1.6/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITLX-1.8/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITLX-1.9/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITLX-2.1/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITLX-2.5/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITLX-2.7/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3995ITLX-2.8/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITLX-2.85/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 LP3995ITLX-3.0/NOPB DSBGA YZR 5 3000 178.0 8.4 1.09 1.55 0.76 4.0 8.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3995ILD-1.5/NOPB WSON NGD 6 1000 213.0 191.0 55.0 LP3995ILD-1.8/NOPB WSON NGD 6 1000 213.0 191.0 55.0 LP3995ILD-2.8/NOPB WSON NGD 6 1000 213.0 191.0 55.0 LP3995ILD-3.0/NOPB WSON NGD 6 1000 213.0 191.0 55.0 LP3995ILDX-2.8/NOPB WSON NGD 6 4500 367.0 367.0 35.0 LP3995ITL-1.5/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3995ITL-1.8/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3995ITL-1.9/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3995ITL-2.5/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3995ITL-2.8/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3995ITL-3.0/NOPB DSBGA YZR 5 250 210.0 185.0 35.0 LP3995ITLX-1.5/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3995ITLX-1.6/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3995ITLX-1.8/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3995ITLX-1.9/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3995ITLX-2.1/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3995ITLX-2.5/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3995ITLX-2.7/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3995ITLX-2.8/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3995ITLX-2.85/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 LP3995ITLX-3.0/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0 Pack Materials-Page 3 MECHANICAL DATA NGD0006A www.ti.com MECHANICAL DATA YZR0005xxx D 0.600±0.075 E TLA05XXX (Rev C) D: Max = 1.502 mm, Min =1.441 mm E: Max = 1.045 mm, Min =0.984 mm 4215043/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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