PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853016 is a low skew, high performance 1-to-2 Differential-to-3.3V, 5V LVPECL/ HiPerClockS™ ECL Fanout Buffer and a member of the HiPerClockS™ family of High Perfor mance Clock Solutions from ICS. The ICS853016 is characterized to operate from either a 3.3V or a 5V power supply. Guaranteed duty cycle skew characteristic makes the ICS853016 ideal for those clock distribution applications demanding well defined performance and repeatability. • (1) Differential 3.3V, 5V LVPECL / ECL output pair and (1) Single-ended 3.3V, 5V LVPECL / ECL output ICS • (1) Differential D, nD input pair • D, nD pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: >3GHz (typical) • Translates any single ended input signal to 3.3V to 5V LVPECL levels with resistor bias on nD input • Duty cycle skew: 10ps (typical) • Propagation delay: 400ps (typical) • LVPECL mode operating voltage supply range: VCC = 3.0V to 5.5V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -5.5V to -3.0V • -40°C to 85°C ambient operating temperature • Pin compatible with MC100EP16VCD and MC100EP16VCDT BLOCK DIAGRAM PIN ASSIGNMENT nQ D VBB/nD nEN VCC nQ 1 2 3 4 8 7 6 5 Vcc QHG nQHG VEE ICS853016 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View QHG D VBB/nD ICS853016 nQHG 8-Lead TSSOP, 118mil 3mm x 3mm x 0.95mm package body G Package Top View OE VBB LEN Q LATCH nEN D VEE The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853016AM www.icst.com/products/hiperclocks.html REV. A NOVEMBER 30, 2004 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 nQ Output 2 D Input Single-ended clock output. LVPECL interface levels. 3 VBB/nD Input 4 nEN Input 5 VEE Power 6, 7 nQHG, QHG Output Differential clock outputs. LVPECL interface levels. 8 VCC Power Positive supply pin. Pulldown Non-inver ting differential clock input. LVPECL interface levels. Reference voltage output/Inver ting differential clock input. LVPECL interface levels. Pulldown Enable input. Default LOW when left open. LVCMOS/LVTTL interface levels. Negative supply pin. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor 853016AM Test Conditions Minimum Typical 75 www.icst.com/products/hiperclocks.html 2 Maximum Units KΩ REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 6V (LVPECL mode, VEE = 0) Negative Supply Voltage, VEE -6V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those Outputs, IO Continuous Current Surge Current 50mA 100mA listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi- VBB Sink/Source, IBB ± 0.5mA mum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) (Junction-to-Ambient) for 8 Lead SOIC Package Thermal Impedance, θJA 101.7°C/W (0 m/s) (Junction-to-Ambient) for 8 Lead TSSOP TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 5.5V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage IE E Power Supply Current Test Conditions Minimum Typical Maximum 3.0 3.3 5.5 Units V 30 mA TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol Parameter VOH Output High Voltage; NOTE 1 Min -40°C Typ Max 2.175 2.275 2.38 1.545 Min 25°C Typ Max 2.225 2.295 2.37 1.52 Min 85°C Typ Max 2.295 2.33 2.365 V 1.535 Units VOL Output Low Voltage; NOTE 1 1.405 1.68 1.425 1.615 1.44 1.63 V VIH Input High Voltage (Single-Ended) 2.075 2.36 2.075 2.36 2.075 2.36 V VIL Input Low Voltage (Single-Ended) 1.43 1.765 1.43 1.765 1.43 1.765 V VBB Output Voltage Reference; NOTE 2 1.86 1.98 1.86 1.98 1.86 1.98 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input High Current D 150 1200 150 1200 150 1200 mV 3.3 1.2 3.3 1.2 3.3 V 150 µA VCMR IIH 800 1.2 800 150 -10 -10 IIL Input Low Current D Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for D is VCC + 0.3V. 853016AM www.icst.com/products/hiperclocks.html 3 150 -10 800 µA REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 5.0V; VEE = 0V Symbol Parameter Min -40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max Units VOH Output High Voltage; NOTE 1 3.875 3.975 4.08 3.925 3.995 4.07 3.995 4.03 4.065 V VOL Output Low Voltage; NOTE 1 3.105 3.245 3.38 3.125 3.22 3.315 3.14 3.235 3.33 V VIH Input High Voltage (Single-Ended) 3.775 4.06 3.775 4.06 3.775 4.06 V VIL Input Low Voltage (Single-Ended) 3.13 3.465 3.13 3.465 3.13 3.465 V VBB Output Voltage Reference; NOTE 2 3.56 3.68 3.56 3.68 3.56 3.68 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input High Current D 150 1200 150 1200 150 1200 mV 5 1.2 5 1. 2 5 V 150 µA VCMR IIH 800 1.2 800 150 800 150 -10 -10 IIL Input Low Current D Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for D is VCC + 0.3V. -10 µA TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V Symbol Parameter VOH -40°C 25°C 85°C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VIH Input High Voltage(Single-Ended) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V VIL Input Low Voltage(Single-Ended) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V VBB Output Voltage Reference; NOTE 2 -1.44 -1.32 -1.44 -1.32 -1.44 VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input High Current D 150 1200 150 1200 150 0 VEE+1.2V 0 VEE+1.2V VCMR IIH 800 VEE+1.2V 800 150 -10 -10 IIL Input Low Current D Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for D is VCC + 0.3V. 853016AM www.icst.com/products/hiperclocks.html 4 150 -10 800 -1.32 V 1200 mV 0 V 150 µA µA REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V Parameter fMAX Output Frequency tPLH tPHL tsk(odc) tR/tF Propagation Delay; NOTE 1 OR VCC = 3.0V TO 5.5V; VEE = 0V -40°C Symbol ICS853016 Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Units TBD >3 TBD GHz (Differential) nQ TBD 35 0 TBD ps (Differential) QHG, nQHG TBD 400 TBD ps (Single-Ended) nQ TBD 400 TBD ps (Single-Ended) QHG, nQHG TBD 450 TBD ps TBD 10 TBD ps TBD 30 0 TBD ps TBD 150 TBD ps Duty Cycle Skew; NOTE 2, 3 Output Rise/ nQ Fall Time 20% to 80% QHG, nQHG All parameters are measured at f ≤ 1.7GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured for only differential operation from the cross point of the inputs to the cross point of the outputs. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 853016AM www.icst.com/products/hiperclocks.html 5 REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx VCC SCOPE nQHG LVPECL V Cross Points PP V CMR QHG nQx VEE V EE -3.5V to -1.0V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nD D 80% 80% VSW I N G Clock Outputs 20% 20% tR nQ tF nQHG QHG tpLH OUTPUT RISE/FALL TIME PROPAGATION DELAY Part 1 nQHG QHG Part 2 nQHG QHG t sk(odc) DUTY CYCLE SKEW 853016AM www.icst.com/products/hiperclocks.html 6 REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS Figure 1 shows an example of the input that can be wired to accept single ended LVPECL levels. VCC C1 0.1u CLK_IN D VBB/nD FIGURE 1. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT 853016AM www.icst.com/products/hiperclocks.html 7 REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER TERMINATION FOR 3.3V LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω FIN 50Ω Zo = 50Ω VCC - 2V 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION TERMINATION FOR 5V LVPECL OUTPUT This section shows examples of 5V LVPECL output termination. Figure 3A shows standard termination for 5V LVPECL. The termination requires matched load of 50Ω resistors pull down to VCC - 2V = 3V at the receiver. Figure 3B shows Thevenin equivalence of Figure 3A. In actual application where the 3V DC power supply is not available, this approached is normally used. 5V 5V 5V 5V R3 84 PECL PECL Zo = 50 Ohm R4 84 Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - R1 50 - PECL R1 125 R2 50 PECL R2 125 3V FIGURE 3A. STANDARD 5V PECL OUTPUT TERMINATION 853016AM FIGURE 3B. 5V PECL OUTPUT TERMINATION EXAMPLE www.icst.com/products/hiperclocks.html 8 REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853016. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853016 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.5V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 30mA = 165mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW Total Power_MAX (3.8V, with all outputs switching) = 165mW + 61.88mW = 226.88mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.227W * 103.3°C/W = 108.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5A. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 5B. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 853016AM 0 1 2 101.7°C/W 90.5°C/W 89.8°C/W www.icst.com/products/hiperclocks.html 9 REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V Figure 4. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX -V Pd_H = [(V – (V CCO_MAX OH_MAX CC_MAX – 0.935V ) = 0.935V For logic low, VOUT = V (V =V OL_MAX =V CC_MAX – 1.67V ) = 1.67V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V -V CC _MAX L OH_MAX )= [(2V - 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.67V)/50Ω] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 853016AM www.icst.com/products/hiperclocks.html 10 REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS853016 is: 163 853016AM www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 7A. PACKAGE DIMENSIONS SYMBOL TABLE 7B. PACKAGE DIMENSIONS Millimeters MINIMUN N SYMBOL MAXIMUM Millimeters Minimum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e ICS853016 A 1.27 BASIC Maximum 8 -- 1.10 A1 0 0.15 A2 0.79 0.97 b 0.22 0.38 c 0.08 0.23 D 3.00 BASIC E 4.90 BASIC E1 3.00 BASIC H 5.80 6.20 e 0.65 BASIC h 0.25 0.50 e1 L 0.40 1.27 L 0.40 0.80 α 0° 8° α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-012 1.95 BASIC Reference Document: JEDEC Publication 95, MO-187 853016AM www.icst.com/products/hiperclocks.html 12 REV. A NOVEMBER 30, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853016 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS853016AM 853016A 8 lead SOIC 96 per tube -40°C to 85°C ICS853016AMT 853016A 8 lead SOIC on Tape and Reel 2500 -40°C to 85°C ICS853016AG 016A 8 lead TSSOP 100 per tube -40°C to 85°C ICS853016AGT 016A 8 lead TSSOP on Tape and Reel 2500 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853016AM www.icst.com/products/hiperclocks.html 13 REV. A NOVEMBER 30, 2004