Microchip MCP6234 20 î¼a, 300 khz rail-to-rail op amp Datasheet

MCP6231/2/4
20 µA, 300 kHz Rail-to-Rail Op Amp
Features
Description
•
•
•
•
•
•
The Microchip Technology Inc. MCP6231/2/4 operational amplifiers (op amps) provide wide bandwidth for
the quiescent current. The MCP6231/2/4 family has a
300 kHz Gain Bandwidth Product (GBWP) and 65°
(typ.) phase margin. This family operates from a single
supply voltage as low as 1.8V, while drawing 20 µA
(typ.) quiescent current. In addition, the MCP6231/2/4
family supports rail-to-rail input and output swing, with
a common mode input voltage range of VDD + 300 mV
to VSS – 300 mV. These op amps are designed in one
of Microchip’s advanced CMOS processes.
Gain Bandwidth Product: 300 kHz (typ.)
Supply Current: IQ = 20 µA (typ.)
Supply Voltage: 1.8V to 5.5V
Rail-to-Rail Input/Output
Extended Temperature Range: -40°C to +125°C
Available in 5-Pin SC-70 and SOT-23 packages
Applications
•
•
•
•
•
•
Automotive
Portable Equipment
Transimpedance amplifiers
Analog Filters
Notebooks and PDAs
Battery-Powered Systems
Package Types
MCP6231
MCP6231
PDIP, SOIC, MSOP
SOT-23-5
5 VDD
VOUT 1
VSS 2
• SPICE Macro Models (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
+
Available Tools
–
VIN+ 3
4 VIN–
NC 1
–
7 VDD
VIN+ 3
+
6 VOUT
VSS 4
SOT-23-5
RG1
VINA 2
–
4 VIN–
VIN+ 3
VIN1
MCP6231
+
RZ
VOUT
5 VINB+
SC-70-5, SOT-23-5
PDIP, SOIC, TSSOP
5 VDD
VIN+ 1
VSS 2
–
VOUTA 1
14 VOUTD
VINA– 2
- + + - 13 VIND–
4 VOUT VINA+ 3
12 VIND+
VDD 4
VINB+ 5
© 2005 Microchip Technology Inc.
6 VINB_
+ -
MCP6234
VIN– 3
Summing Amplifier Circuit
7 VOUTB
- +
MCP6231U
+
–
RX
VINA+ 3
8 VDD
VSS 4
RF
VDD
VOUTA 1
_
+
VIN2
RY
PDIP, SOIC, MSOP
5 VSS
VOUT 1
VDD 2
5 NC
MCP6232
MCP6231R
Typical Application
RG2
8 NC
VIN– 2
11 VSS
VINB– 6
10 VINC+
- + +- 9 V –
INC
VOUTB 7
8 VOUTC
DS21881C-page 1
MCP6231/2/4
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
All Inputs and Outputs ................. VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.................................... –65°C to +150°C
Junction Temperature (TJ)........................................... +150°C
ESD Protection On All Pins (HBM;MM) ............... ≥ 4 kV; 300V
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,
VCM = VDD/2, RL = 100 kΩ to VDD/2 and VOUT ≈ VDD/2.
Sym
Min
Typ
Max
Input Offset Voltage
VOS
-5.0
—
+5.0
mV
VCM = VSS
Extended Temperature
VOS
-7.0
—
+7.0
mV
TA = -40°C to +125°C,
VCM = VSS (Note)
Input Offset Drift with Temperature ΔVOS/ΔTA
—
±3.0
—
Power Supply Rejection Ratio
PSRR
—
83
—
dB
Input Bias Current:
IB
—
±1.0
—
pA
At Temperature
IB
—
20
—
pA
TA = +85°C
At Temperature
IB
—
1100
—
pA
TA = +125°C
Parameters
Units Conditions
Input Offset
µV/°C TA= -40°C to +125°C,
VCM = VSS
VCM = VSS
Input Bias Current and Impedance
Input Offset Current
IOS
—
±1.0
—
pA
Common Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||3
—
Ω||pF
Common Mode Input Range
VCMR
VSS – 0.3
—
VDD + 0.3
V
Common Mode Rejection Ratio
CMRR
61
75
—
dB
VCM = -0.3V to 5.3V,
VDD = 5V
AOL
90
110
—
dB
VOUT = 0.3V to VDD – 0.3V,
VCM = VSS
—
VDD – 35
mV
RL =10 kΩ, 0.5V Output
Overdrive
Common Mode
Open-Loop Gain
DC Open-Loop Gain (large signal)
Output
Maximum Output Voltage Swing
Output Short-Circuit Current
VOL, VOH VSS + 35
ISC
—
±6
—
mA
VDD = 1.8V
ISC
—
±23
—
mA
VDD = 5.5V
VDD
1.8
—
5.5
V
IQ
10
20
30
µA
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note:
IO = 0, VCM = VDD – 0.5V
The SC-70 package is only tested at +25°C.
DS21881C-page 2
© 2005 Microchip Technology Inc.
MCP6231/2/4
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
GBWP
—
300
—
kHz
Phase Margin
PM
—
65
—
°
Slew Rate
SR
—
0.15
—
V/µs
Input Noise Voltage
Eni
—
6.0
—
µVP-P
Input Noise Voltage Density
eni
—
52
—
nV/√Hz
f = 1 kHz
Input Noise Current Density
ini
—
0.6
—
fA/√Hz
f = 1 kHz
AC Response
Gain Bandwidth Product
G = +1
Noise
f = 0.1 Hz to 10 Hz
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Extended Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5L-SC70
θJA
—
331
—
°C/W
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Conditions
Temperature Ranges
Note
Thermal Package Resistances
Note:
The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
© 2005 Microchip Technology Inc.
DS21881C-page 3
MCP6231/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
90
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
CMRR, PSRR (dB)
630 Samples
VCM = VSS
85
PSRR (VCM = VSS)
80
75
CMRR (VCM = -0.3V to +5.3V,
VDD = 5.0V)
-50
-25
0
25
50
75
Ambient Temperature (°C)
Input Offset Voltage (mV)
FIGURE 2-4:
Temperature.
100
120
40
30
1.E+01
1.E+02
10
1.E+03
100
1.E+04
1k
100k
Frequency (Hz)
PSRR, CMRR vs.
-150
0
-180
30%
25%
20%
15%
10%
5%
0%
Input Bias Current (pA)
FIGURE 2-3:
DS21881C-page 4
Input Bias Current at +85°C.
Open-Loop Gain, Phase vs.
632 Samples
VCM = VDD/2
TA = +125°C
0.0
Percentage of Occurrences
42
36
30
24
18
12
-120
20
FIGURE 2-5:
Frequency.
630 Samples
VCM = VDD/2
TA = +85°C
6
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
0
Percentage of Occurrences
FIGURE 2-2:
Frequency.
40
-20
-210
0.1 1.E+
1 1.E+
10 1.E+
100 1.E+
1k 1.E+
10k 100k
1M 1.E+
10M
1.E+ 1.E+
1.E01 00 01 Frequency
02 03 (Hz)
04 05 06 07
1.E+05
10k
-90
Phase
0.6
20
-60
60
0.4
50
-30
2.0
PSRR+
0
1.8
60
80
1.6
CMRR
0.2
70
Gain
1.0
80
RL = 10 kΩ
VCM = VDD/2
100
0.8
PSRR-
Open-Loop Gain (dB)
PSRR, CMRR (dB)
90
125
CMRR, PSRR vs. Ambient
1.4
Input Offset Voltage.
1.2
FIGURE 2-1:
100
Open-Loop Phase (°)
5
4
3
2
1
0
-1
-2
-3
-4
70
-5
Percentage of Occurrences
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
Input Bias Current (nA)
FIGURE 2-6:
Input Bias Current at +125°C.
© 2005 Microchip Technology Inc.
MCP6231/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-7:
vs. Frequency.
Input Noise Voltage Density
FIGURE 2-10:
Input Offset Voltage (µV)
Input Offset Voltage (µV)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
450
350
250
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
150
0
-50
-100
-150
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-200
© 2005 Microchip Technology Inc.
12
10
8
6
VDD = 5.5V
-150
-200
VDD = 1.8V
-250
-300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Short-Circuit Current
(mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
50
4
-100
FIGURE 2-11:
Output Voltage.
VDD = 5.5 V
100
2
0
-50
Output Voltage (V)
FIGURE 2-8:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 1.8V.
150
0
VCM = VSS
50
Common Mode Input Voltage (V)
200
-2
Input Offset Voltage Drift.
100
VDD = 1.8V
-4
Input Offset Voltage Drift (µV/°C)
550
Input Offset Voltage (µV)
-6
-12
10
0.1 1.E+0
1
10 1.E+0
100 1.E+0
1k
10k 1.E+0
100k
1.E-01
1.E+0
1.E+0
0
1
2 (Hz)
3
4
5
Frequency
628 Samples
VCM = VSS
TA = -40°C to +125°C
-8
100
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-10
Percentage of Occurrences
Input Noise Voltage Density
(nV/—Hz)
1,000
30
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
Input Offset Voltage vs.
+ISC
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-ISC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-12:
Output Short-Circuit Current
vs. Ambient Temperature.
DS21881C-page 5
MCP6231/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
VDD = 5.5V
0.25
Falling Edge
0.20
0.15
0.10
Rising Edge
VDD = 1.8V
0.05
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-13:
Temperature.
125
Time (2 µs/div)
Slew Rate vs. Ambient
FIGURE 2-16:
Pulse Response.
1,000
VDD = 5.0V
G = +1 V/V
4.5
100
VDD – VOH
VOL – VSS
10
1
10µ
1.E-02
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
100µ
1m
1.E-01
1.E+00
Output Current Magnitude (A)
10m
1.E+01
0.0
Time (20 µs/div)
FIGURE 2-14:
Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-17:
Pulse Response.
30
Quiescent Current
per Amplifier (µA)
10
Max. Output Voltage Swing
(VP-P)
Small-Signal, Non-Inverting
5.0
Output Voltage (V)
Output Voltage Headroom
(mV)
G = +1 V/V
RL = 10 kΩ
Output Voltage (10 mV/div)
Slew Rate (V/µs)
0.30
VDD = 5.5V
1
VDD = 1.8V
20
15
10
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
10k
100k
1.E+04
1.E+05
Frequency (Hz)
1M
1.E+06
FIGURE 2-15:
Maximum Output Voltage
Swing vs. Frequency.
DS21881C-page 6
VCM = 0.9VDD
25
5
0.1
1k
1.E+03
Large-Signal, Non-Inverting
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-18:
Quiescent Current vs.
Power Supply Voltage.
© 2005 Microchip Technology Inc.
MCP6231/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6231
(PDIP, SOIC, MSOP)
MCP6231
(SOT-23-5)
MCP6231R
(SOT-23-5)
MCP6231U
(SOT-23-5)
Symbol
6
1
1
4
VOUT
Analog Output
2
4
4
3
VIN–
Inverting Input
3
3
3
1
VIN+
Non-inverting Input
7
5
2
5
VDD
Positive Power Supply
4
2
5
2
VSS
Negative Power Supply
1, 5, 8
—
—
—
NC
No Internal Connection
TABLE 3-2:
3.1
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6232
MCP6234
Symbol
1
1
VOUTA
Analog Output (op amp A)
2
2
VINA–
Inverting Input (op amp A)
3
3
VINA+
8
4
VDD
5
5
VINB+
Non-inverting Input (op amp B)
6
6
VINB–
Inverting Input (op amp B)
7
7
VOUTB
Analog Output (op amp B)
—
8
VOUTC
Analog Output (op amp C)
Description
Non-inverting Input (op amp A)
Positive Power Supply
—
9
VINC–
Inverting Input (op amp C)
—
10
VINC+
Non-inverting Input (op amp C)
4
11
VSS
—
12
VIND+
Non-inverting Input (op amp D)
—
13
VIND–
Inverting Input (op amp D)
—
14
VOUTD
Analog Output (op amp D)
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Description
Analog Inputs
The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents.
© 2005 Microchip Technology Inc.
Negative Power Supply
3.3
Power Supply (VSS and VDD)
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts can
share a bulk capacitor (typically 1 µF to 100 µF) with
other nearby analog parts; it needs to be within 100 mm
of the VDD pin.
DS21881C-page 7
MCP6231/2/4
4.0
APPLICATION INFORMATION
–
The MCP6231/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-cost, low-power and
general-purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6231/2/4 ideal for battery-powered applications.
4.1
6.0
VOUT
5.0
VDD = 5.0V
G = +2 V/V
MCP623X
+
VIN
VOUT
( Maximum expected VIN ) – V DD
RIN ≥ ------------------------------------------------------------------------------2 mA
Rail-to-Rail Inputs
The MCP6231/2/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 4-1 shows the input voltage exceeding
the supply voltage without any phase reversal.
Input, Output Voltages (V)
RIN
V SS – ( Minimum expected V IN )
R IN ≥ ---------------------------------------------------------------------------2 mA
FIGURE 4-2:
Resistor (RIN).
4.2
Input Current-Limiting
Rail-to-Rail Output
2.0
The output voltage range of the MCP6231/2/4 op amps
is VDD – 35 mV (max.) and VSS + 35 mV (min.) when
RL = 10 kΩ is connected to VDD/2 and VDD = 5.5V.
Refer to Figure 2-14 for more information.
1.0
4.3
0.0
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, but all gains show the
same general behavior.
4.0
VIN
3.0
-1.0
Time (1 ms/div)
FIGURE 4-1:
Phase Reversal.
The MCP6231/2/4 Show No
The input stage of the MCP6231/2/4 op amps use two
differential input stages in parallel. One operates at low
common mode input voltage (VCM) and the other at
high VCM. With this topology, the device operates with
VCM up to 300 mV above VDD and 300 mV below VSS.
The input offset voltage is measured at
VCM = VSS – 300 mV and VDD + 300 mV to ensure
proper operation.
Input voltages that exceed the input voltage range
(VSS – 0.3V to VDD + 0.3V at 25°C) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-2.
Capacitive Loads
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no
capacitive load.
–
VIN
MCP623X
+
RISO
VOUT
CL
FIGURE 4-3:
Output resistor, RISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
signal gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., –1 V/V gives GN = +2 V/V).
DS21881C-page 8
© 2005 Microchip Technology Inc.
MCP6231/2/4
4.6
Recommended RISO (:)
10,000
10k
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6231/2/4 family’s bias current at 25°C (1 pA, typ.).
1k
1,000
GN = 1 V/V
GN = 2 V/V
GN t 4 V/V
100
100
10p
10
100p
1n
10n
100
1000
10000
Normalized Load Capacitance; CL/GN (F)
FIGURE 4-4:
Recommended RISO Values
for Capacitive Loads.
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
VIN–
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6231/2/4 SPICE macro
model are very helpful. Modify RISO’s value until the
response is reasonable.
4.4
PCB Surface Leakage
VIN+
VSS
Supply Bypass
With this op amp, the power supply pin (VDD for
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good highfrequency performance. It can use a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other nearby analog parts.
4.5
Guard Ring
FIGURE 4-6:
for Inverting Gain.
1.
Unused Op Amps
An unused op amp in a quad package (MCP6234)
should be configured as shown in Figure 4-5. Both
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage
and minimizes the supply current draw of the unused
op amp. Circuit B minimizes the number of
components, but may draw a little more supply current
for the unused op amp.
¼ MCP6234 (A)
¼ MCP6234 (B)
2.
Example Guard Ring Layout
Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
Inverting Gain and Transimpedance Amplifiers
(convert current to voltage, such as photo
detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
VDD
VDD
FIGURE 4-5:
VDD
Unused Op Amps.
© 2005 Microchip Technology Inc.
DS21881C-page 9
MCP6231/2/4
4.7
Application Circuits
4.7.1
MATCHING THE IMPEDANCE AT
THE INPUTS
To minimize the effect of input bias current in an amplifier circuit (this is important for very high sourceimpedance applications, such as pH meters and
transimpedance amplifiers), the impedances at the
inverting and non-inverting inputs need to be
matched. This is done by choosing the circuit resistor
values so that the total resistance at each input is the
same. Figure 4-7 shows a summing amplifier circuit.
RG2
VIN2
RG1
VIN1
RF
VDD
R VIN + = R IN –
4.7.2
COMPENSATING FOR THE
PARASITIC CAPACITANCE
In analog circuit design, the PCB parasitic capacitance
can compromise the circuit behavior; Figure 4-8 shows
a typical scenario. If the input of an amplifier sees
parasitic capacitance of several picofarad (CPARA,
which includes the common mode capacitance of 6 pF,
typ.), and large RF and RG, the frequency response of
the circuit will include a zero. This parasitic zero
introduces gain-peaking and can cause circuit
instability.
–
RX
MCP623X
VOUT
+
RY
To minimize output offset voltage and increase circuit
accuracy, the resistor values need to meet the
conditions:
VAC
+
MCP623X
–
RZ
RG
RF
CPARA
CF
VOUT
VDC
FIGURE 4-7:
Summing Amplifier Circuit.
To match the inputs, set all voltage sources to ground
and calculate the total resistance at the input nodes. In
this summing amplifier circuit, the resistance at the
inverting input is calculated by setting VIN1, VIN2 and
VOUT to ground. In this case, RG1, RG2 and RF are in
parallel. The total resistance at the inverting input is:
1
R IN – = --------------------------------------------1
1
1
⎛ --------+ --------- + ------⎞
⎝ R G1 RG2 RF⎠
Where:
RVIN– = total resistance at the inverting input
At the non-inverting input, VDD is the only voltage
source. When VDD is set to ground, both Rx and Ry are
in parallel. The total resistance at the non-inverting
input is:
RG
C F = CPARA • ------RF
FIGURE 4-8:
Effect of Parasitic
Capacitance at the Input.
One solution is to use smaller resistor values to push
the zero to a higher frequency. Another solution is to
compensate by introducing a pole at the point at which
the zero occurs. This can be done by adding CF in
parallel with the feedback resistor (RF). CF needs to be
selected so that the ratio CPARA:CF is equal to the ratio
of RF:RG.
1
R VIN + = ------------------------- + R Z
1-⎞
1
⎛ ------ + ----⎝ RX RY⎠
Where:
RVIN+ = total resistance at the inverting
input
DS21881C-page 10
© 2005 Microchip Technology Inc.
MCP6231/2/4
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6231/2/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6231/2/4 op
amps is available on our web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the macro
model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab software is an innovative tool that
simplifies analog active-filter (using op amps) design.
Available at no cost from our web site at
www.microchip.com, the FilterLab design tool provides
full schematic diagrams of the filter circuit with
component values. It also outputs the filter circuit in
SPICE format, which can be used with the macro
model to simulate actual filter performance.
© 2005 Microchip Technology Inc.
DS21881C-page 11
MCP6231/2/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SC-70 (MCP6231U Only)
XXN (Front)
YWW (Back)
OR
Example:
AS2 (Front)
546 (Back)
XXNN
Example:
5-Lead SOT-23
4
5
Device
XXNN
1
2
3
Code
MCP6231
BJNN
MCP6231R
BKNN
MCP6231U
BLNN
Note:
Applies to 5-Lead SOT-23.
4
5
BJ25
1
2
3
Example:
8-Lead MSOP
XXXXXX
6232E
YWWNNN
546256
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
XXXXXXXX
XXXXYYWW
NNN
Example:
MCP6232E
e3
SN^^0546
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
MCP6232
e3
E/P^^256
0546
8-Lead SOIC (150 mil)
DS21881C-page 12
AS25
OR
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2005 Microchip Technology Inc.
MCP6231/2/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6234)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
14-Lead SOIC (150 mil) (MCP6234)
MCP6234
e3
E/P^^
0546256
Example:
MCP6234
e3
E/SL^^
0546256
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP6234)
Example:
XXXXXXXX
YYWW
6234E
0546
NNN
256
© 2005 Microchip Technology Inc.
DS21881C-page 13
MCP6231/2/4
5-Lead Small Outline Transistor Package (SC-70)
E
E1
D
p
B
n
1
Q1
A2
c
A
A1
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Top of Molded Pkg to Lead Shoulder
Lead Thickness
Lead Width
A
A2
A1
E
E1
D
L
Q1
c
B
MIN
.031
.031
.000
.071
.045
.071
.004
.004
.004
.006
INCHES
NOM
5
.026 (BSC)
MAX
.043
.039
.004
.094
.053
.087
.012
.016
.007
.012
MILLIMETERS*
NOM
5
0.65 (BSC)
0.80
0.80
0.00
1.80
1.15
1.80
0.10
0.10
0.10
0.15
MIN
MAX
1.10
1.00
0.10
2.40
1.35
2.20
0.30
0.40
0.18
0.30
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
JEITA (EIAJ) Standard: SC-70
Drawing No. C04-061
DS21881C-page 14
© 2005 Microchip Technology Inc.
MCP6231/2/4
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
E
E1
p
B
p1
n
D
1
α
c
A
L
β
Units
Dimension Limits
n
p
MIN
φ
A2
A1
INCHES*
NOM
5
.038
.075
.046
.043
.003
.110
.064
.116
.018
5
.006
.017
5
5
MAX
MIN
MILLIMETERS
NOM
5
0.95
1.90
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
0.15
0.43
5
5
Number of Pins
Pitch
p1
Outside lead pitch (basic)
Overall Height
A
.035
.057
0.90
Molded Package Thickness
A2
.035
.051
0.90
Standoff
A1
.000
.006
0.00
Overall Width
E
.102
.118
2.60
Molded Package Width
E1
.059
.069
1.50
Overall Length
D
.110
.122
2.80
Foot Length
L
.014
.022
0.35
φ
Foot Angle
0
10
0
c
Lead Thickness
.004
.008
0.09
Lead Width
B
.014
.020
0.35
α
Mold Draft Angle Top
0
10
0
β
Mold Draft Angle Bottom
0
10
0
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
MAX
1.45
1.30
0.15
3.00
1.75
3.10
0.55
10
0.20
0.50
10
10
EIAJ Equivalent: SC-74A
Drawing No. C04-091
© 2005 Microchip Technology Inc.
DS21881C-page 15
MCP6231/2/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
n
p
MIN
INCHES
NOM
8
.026 BSC
.033
.193 TYP.
.118 BSC
.118 BSC
.024
.037 REF
.006
.012
-
MAX
MILLIMETERS*
NOM
8
0.65 BSC
0.75
0.85
0.00
4.90 BSC
3.00 BSC
3.00 BSC
0.40
0.60
0.95 REF
0°
0.08
0.22
5°
5°
-
MIN
Number of Pins
Pitch
A
.043
Overall Height
A2
.030
.037
Molded Package Thickness
.000
.006
A1
Standoff
E
Overall Width
E1
Molded Package Width
D
Overall Length
L
.016
.031
Foot Length
Footprint (Reference)
F
φ
Foot Angle
0°
8°
c
Lead Thickness
.003
.009
.009
.016
Lead Width
B
α
Mold Draft Angle Top
5°
15°
β
5°
15°
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
15°
15°
JEDEC Equivalent: MO-187
Drawing No. C04-111
DS21881C-page 16
© 2005 Microchip Technology Inc.
MCP6231/2/4
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
§
A
A2
A1
E
E1
D
L
c
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2005 Microchip Technology Inc.
DS21881C-page 17
MCP6231/2/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21881C-page 18
© 2005 Microchip Technology Inc.
MCP6231/2/4
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
.240
.250
.260
E1
Overall Length
D
.740
.750
.760
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
§
eB
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
© 2005 Microchip Technology Inc.
MAX
4.32
3.68
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
15
DS21881C-page 19
MCP6231/2/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.150
.337
.010
.016
0
.008
.014
0
0
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.347
.020
.050
8
.010
.020
15
15
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
DS21881C-page 20
© 2005 Microchip Technology Inc.
MCP6231/2/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B1
α
β
MIN
.033
.002
.246
.169
.193
.020
0
.004
.007
0
0
INCHES
NOM
14
.026
.035
.004
.251
.173
.197
.024
4
.006
.010
5
5
A2
MAX
.043
.037
.006
.256
.177
.201
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
14
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
4.90
5.00
5.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
© 2005 Microchip Technology Inc.
DS21881C-page 21
MCP6231/2/4
NOTES:
DS21881C-page 22
© 2005 Microchip Technology Inc.
MCP6231/2/4
APPENDIX A:
REVISION HISTORY
Revision C (March 2005)
The following is the list of modifications:
1.
2.
3.
4.
5.
Added the MCP6234 quad op amp.
Corrected plots in Section 2.0 “Typical Performance Curves”.
Added Section 3.0 “Pin Descriptions”.
Added new SC-70 package markings. Added
PDIP-14, SOIC-14, and TSSOP-14 packages
and corrected package marking information
(Section 6.0 “Packaging Information”).
Added Appendix A: “Revision History”.
Revision B (August 2004)
Revision A (March 2004)
• Original Release of this Document.
© 2005 Microchip Technology Inc.
DS21881C-page 23
MCP6231/2/4
NOTES:
DS21881C-page 24
© 2005 Microchip Technology Inc.
MCP6231/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
Device
Tape and Reel
and/or
Alternate Pinout
Device:
-X
/XX
Temperature Package
Range
MCP6231:
MCP6231T:
MCP6231RT:
MCP6231UT:
MCP6232:
MCP6232T:
MCP6234:
MCP6234T:
Single Op Amp (MSOP, PDIP, SOIC)
Single Op Amp (Tape and Reel)
(MSOP, SOIC, SOT-23)
Single Op Amp (Tape and Reel)
(SOT-23)
Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(MSOP, SOIC)
Quad Op Amp
Quad Op Amp (Tape and Reel)
(TSSOP, SOIC)
Temperature Range:
E
= -40°C to +125°C
Package:
LT
MS
P
OT
=
=
=
=
Plastic Package (SC-70), 5-lead (MCP6231U only)
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6231, MCP6231R, MCP6231U)
SN = Plastic SOIC (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP (4.4 mil Body), 14-lead
© 2005 Microchip Technology Inc.
Examples:
a)
b)
c)
d)
e)
f)
MCP6231-E/SN:
Extended Temp.,
8LD SOIC package.
MCP6231-E/MS:
Extended Temp.,
8LD MSOP package.
MCP6231-E/P:
Extended Temp.,
8LD PDIP package.
MCP6231RT-E/OT: Tape and Reel,
Extended Temp.,
5LD SOT-23 package
MCP6231UT-E/OT: Tape and Reel,
Extended Temp.,
5LD SOT-23 package.
MCP6231UT-E/LT: Tape and Reel,
Extended Temp.,
5LD SC-70 package.
a)
MCP6232-E/SN:
b)
MCP6232-E/MS:
c)
MCP6232-E/P:
d)
MCP6232T-E/SN:
a)
MCP6234-E/P:
b)
MCP6234-E/SL:
c)
MCP6234-E/ST:
d)
MCP6234T-E/SL:
e)
MCP6234T-E/ST:
Extended Temp.,
8LD SOIC package.
Extended Temp.,
8LD MSOP package.
Extended Temp.,
8LD PDIP package.
Tape and Reel,
Extended Temp.,
8LD SOIC package.
Extended Temp.,
14LD PDIP package.
Extended Temp.,
14LD SOIC package.
Extended Temp.,
14LD TSSOP
package.
Tape and Reel,
Extended Temp.,
14LD SOIC package.
Tape and Reel,
Extended Temp.,
14LD TSSOP
package.
DS21881C-page 25
MCP6231/2/4
NOTES:
DS21881C-page 26
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance and WiperLock are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21881C-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
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Technical Support:
http://support.microchip.com
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03/01/05
DS21881C-page 28
© 2005 Microchip Technology Inc.