Cirrus CRD42L51 Low power, stereo codec with headphone amp Datasheet

CS42L51
Low Power, Stereo CODEC with Headphone Amp
DIGITAL to ANALOG FEATURES
ANALOG to DIGITAL FEATURES
98 dB Dynamic Range (A-wtd)
98 dB Dynamic Range (A-wtd)
-86 dB THD+N

-88 dB THD+N
Analog Gain Controls
– +32 dB or +16 dB MIC Pre-Amplifiers
Headphone Amplifier - GND Centered
–
–
–
–
–
On-Chip Charge Pump Provides -VA_HP
No DC-Blocking Capacitor Required
46 mW Power Into Stereo 16 Ω @ 1.8 V
88 mW Power Into Stereo 16 Ω @ 2.5 V
-75 dB THD+N
–
+20 dB Digital Boost
Programmable Automatic Level Control (ALC)
Digital Signal Processing Engine
–
–
–
–

Analog Programmable Gain Amplifier
(PGA)
Bass & Treble Tone Control, De-Emphasis
PCM + ADC Mix w/Independent Vol Control
Master Digital Volume Control
Soft Ramp & Zero Cross Transitions
–
Noise Gate for Noise Suppression
–
Programmable Threshold and
Attack/Release Rates
Independent Channel Control
Digital Volume Control
Beep Generator
– Tone Selections Across Two Octaves
High-Pass Filter Disable for DC Measurements
–
Separate Volume Control
Dual MIC Inputs
–
Programmable On & Off Time Intervals
–
Programmable, Low Noise MIC Bias Levels
–
Continuous, Periodic or One-Shot Beep
Selections
–
Differential MIC Mix for Common Mode
Noise Rejection
Stereo 3:1 Analog Input MUX
Very Low 64 Fs Oversampling Clock Reduces
Programmable Peak-Detect and Limiter
Power Consumption
Pop and Click Suppression
1.8 V to 3.3 V
1.8 V to 2.5 V
1.8 V to 2.5 V
MUX
Serial Audio
Input
Serial Audio
Output
Switched
Capacitor DAC
and Filter
Headphone
Amp - GND
Centered
Left HP Out
Switched
Capacitor DAC
and Filter
Headphone
Amp - GND
Centered
Right HP Out
Charge
Pump
ALC
Volume
Controls
High Pass
Filters
Multibit
Oversampling
ADC
MUX
Stereo Input 1
Stereo Input 2
PGA
MUX
Multibit
Oversampling
ADC
Register
Configuration
http://www.cirrus.com
Multibit
∆Σ Modulator
MUX
PCM Serial Interface
Reset
Level Translator
Hardware
Mode or I2C &
SPI Software
Mode
Control Data
Beep
Generator
Digital
Signal
Processing
Engine
1.8 V to 2.5 V
MUX
ALC
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
PGA
+32 dB
Stereo Input 3 /
Mic Input 1 & 2
+32 dB
MIC
Bias
JULY '06
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CS42L51
SYSTEM FEATURES
GENERAL DESCRIPTION
24-bit Converters
The CS42L51 is a highly integrated, 24-bit, 96 kHz, low
power stereo CODEC. Based on multi-bit, delta-sigma
modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. Both the ADC and DAC offer
many features suitable for low power, portable system
applications.
4 kHz to 96 kHz Sample Rate
Multi-bit Delta Sigma Architecture
Low Power Operation
–
Stereo Playback: 12.93 mW @ 1.8 V
–
Stereo Record and Playback: 20.18 mW @
1.8 V
Variable Power Supplies
–
1.8 V to 2.5 V Digital & Analog
–
1.8 V to 3.3 V Interface Logic
Power Down Management
–
ADC, DAC, CODEC, MIC Pre-Amplifier,
PGA
Software Mode (I²C® & SPI™ Control)
Hardware Mode (Stand-Alone Control)
Digital Routing/Mixes:
–
Analog Out = ADC + Digital In
–
Digital Out = ADC + Digital In
–
Internal Digital Loopback
–
Mono Mixes
Flexible Clocking Options
–
Master or Slave Operation
–
High-Impedance Digital Output Option (for
easy MUXing between CODEC and Other
Data Sources)
–
Quarter-Speed Mode - (i.e. Allows 8 kHz Fs
while maintaining a flat noise floor up to
16 kHz)
APPLICATIONS
HDD & Flash-Based Portable Audio Players
MD Players/Recorders
PDAs
Personal Media Players
Portable Game Consoles
Digital Voice Recorders
Digital Camcorders
The ADC input path allows independent channel control
of a number of features. An input multiplexer selects between line-level or microphone level inputs for each
channel. The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low
noise MIC bias voltage supply. A PGA is available for
line or microphone inputs and provides analog gain with
soft ramp and zero cross transitions. The ADC also features a digital volume attenuator with soft ramp
transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels
appropriately.
The DAC output path includes a digital signal processing engine. Tone Control provides bass and treble
adjustment of four selectable corner frequencies. The
Mixer allows independent volume control for both the
ADC mix and the PCM mix, as well as a master digital
volume control for the analog output. All volume level
changes may be configured to occur on soft ramp and
zero cross transitions. The DAC also includes de-emphasis, limiting functions and a beep generator
delivering tones selectable across a range of two full
octaves.
The stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump
provides a negative supply. This allows a ground-centered analog output with a wide signal swing and
eliminates external DC-blocking capacitors.
In addition to its many features, the CS42L51 operates
from a low-voltage analog and digital core, making this
CODEC ideal for portable systems that require extremely low power consumption in a minimal amount of
space.
The CS42L51 is available in a 32-pin QFN package in
both Commercial (-10 to +70° C) and Automotive
grades (-40 to +85° C). The CDB42L51 Customer Demonstration board is also available for device evaluation
and implementation suggestions. Please see “Ordering
Information” on page 85 for complete details.
Digital Cameras
Smart Phones
2
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CS42L51
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 7
1.1 Digital I/O Pin Characteristics ........................................................................................................... 9
2. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 10
3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 12
SPECIFIED OPERATING CONDITIONS ............................................................................................. 12
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 12
ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) .......................................................... 13
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) .......................................................... 14
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 15
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 16
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ...................................................... 17
LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................................. 18
HEADPHONE OUTPUT POWER CHARACTERISTICS ...................................................................... 19
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 20
SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 20
SWITCHING SPECIFICATIONS - I²C® CONTROL PORT .................................................................. 22
SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT ............................................................ 23
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 24
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 24
POWER CONSUMPTION .................................................................................................................... 25
4. APPLICATIONS ................................................................................................................................... 26
4.1 Overview ......................................................................................................................................... 26
4.1.1 Architecture ........................................................................................................................... 26
4.1.2 Line & MIC Inputs .................................................................................................................. 26
4.1.3 Line & Headphone Outputs ................................................................................................... 26
4.1.4 Signal Processing Engine ..................................................................................................... 26
4.1.5 Beep Generator ..................................................................................................................... 26
4.1.6 Device Control (Hardware or Software Mode) ...................................................................... 26
4.1.7 Power Management .............................................................................................................. 26
4.2 Hardware Mode .............................................................................................................................. 27
4.3 Analog Inputs ................................................................................................................................. 28
4.3.1 Digital Code, Offset & DC Measurement ............................................................................... 28
4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 29
4.3.3 Digital Routing ....................................................................................................................... 29
4.3.4 Differential Inputs .................................................................................................................. 29
4.3.4.1 External Passive Components ................................................................................... 29
4.3.5 Analog Input Multiplexer ........................................................................................................ 31
4.3.6 MIC & PGA Gain ................................................................................................................... 31
4.3.7 Automatic Level Control (ALC) .............................................................................................. 32
4.3.8 Noise Gate ............................................................................................................................ 33
4.4 Analog Outputs ............................................................................................................................... 34
4.4.1 De-Emphasis Filter ................................................................................................................ 34
4.4.2 Volume Controls .................................................................................................................... 35
4.4.3 Mono Channel Mixer ............................................................................................................. 35
4.4.4 Beep Generator ..................................................................................................................... 35
4.4.5 Tone Control .......................................................................................................................... 36
4.4.6 Limiter .................................................................................................................................... 36
4.4.7 Line-Level Outputs and Filtering ........................................................................................... 37
4.4.8 On-Chip Charge Pump .......................................................................................................... 38
4.5 Serial Port Clocking ........................................................................................................................ 38
4.5.1 Slave ..................................................................................................................................... 39
4.5.2 Master ................................................................................................................................... 39
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4.5.3 High-Impedance Digital Output ............................................................................................. 40
4.5.4 Quarter- and Half-Speed Mode ............................................................................................. 40
4.6 Digital Interface Formats ................................................................................................................ 40
4.7 Initialization ..................................................................................................................................... 41
4.8 Recommended Power-Up Sequence ............................................................................................. 41
4.9 Recommended Power-Down Sequence ........................................................................................ 42
4.10 Software Mode ............................................................................................................................. 43
4.10.1 SPI Control .......................................................................................................................... 43
4.10.2 I²C Control ........................................................................................................................... 43
4.10.3 Memory Address Pointer (MAP) .......................................................................................... 45
4.10.3.1 Map Increment (INCR) ............................................................................................. 45
5. REGISTER QUICK REFERENCE ........................................................................................................ 46
6. REGISTER DESCRIPTION .................................................................................................................. 49
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 49
6.2 Power Control 1 (Address 02h) ...................................................................................................... 49
6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 50
6.4 Interface Control (Address 04h) ..................................................................................................... 52
6.5 MIC Control (Address 05h) ............................................................................................................. 53
6.6 ADC Control (Address 06h) ............................................................................................................ 54
6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 56
6.8 DAC Output Control (Address 08h) ................................................................................................ 57
6.9 DAC Control (Address 09h) ............................................................................................................ 58
6.10 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ............... 59
6.11 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 60
6.12 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 61
6.13 PCMX Mixer Volume Control:
PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 62
6.14 Beep Frequency & Timing Configuration (Address 12h) .............................................................. 62
6.15 Beep Off Time & Volume (Address 13h) ...................................................................................... 63
6.16 Beep Configuration & Tone Configuration (Address 14h) ............................................................ 64
6.17 Tone Control (Address 15h) ......................................................................................................... 65
6.18 AOUTx Volume Control:
AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 66
6.19 PCM Channel Mixer (Address 18h) .............................................................................................. 67
6.20 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 67
6.21 Limiter Release Rate Register (Address 1Ah) .............................................................................. 69
6.22 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 70
6.23 ALC Enable & Attack Rate (Address 1Ch) ................................................................................... 70
6.24 ALC Release Rate (Address 1Dh) ................................................................................................ 71
6.25 ALC Threshold (Address 1Eh) ...................................................................................................... 71
6.26 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 72
6.27 Status (Address 20h) (Read Only) ............................................................................................... 73
6.28 Charge Pump Frequency (Address 21h) ...................................................................................... 74
7. ANALOG PERFORMANCE PLOTS .................................................................................................... 75
7.1 Headphone THD+N versus Output Power Plots ............................................................................ 75
7.2 Headphone Amplifier Efficiency ...................................................................................................... 77
7.3 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 78
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 79
8.1 Auto Detect Enabled ....................................................................................................................... 79
8.2 Auto Detect Disabled ...................................................................................................................... 80
9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 81
9.1 Power Supply, Grounding ............................................................................................................... 81
9.2 QFN Thermal Pad .......................................................................................................................... 81
10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 82
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CS42L51
11. PARAMETER DEFINITIONS .............................................................................................................. 83
12. PACKAGE DIMENSIONS ................................................................................................................. 84
THERMAL CHARACTERISTICS ........................................................................................................ 84
13. ORDERING INFORMATION ............................................................................................................. 85
14. REFERENCES .................................................................................................................................... 85
15. REVISION HISTORY ......................................................................................................................... 86
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ........................................................................... 10
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 11
Figure 3.Headphone Output Test Load ..................................................................................................... 19
Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 21
Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 21
Figure 6.Control Port Timing - I²C ............................................................................................................. 22
Figure 7.Control Port Timing - SPI Format ................................................................................................ 23
Figure 8.Analog Input Architecture ............................................................................................................ 28
Figure 9.MIC Input Mix w/Common Mode Rejection ................................................................................. 30
Figure 10.Differential Input ........................................................................................................................ 30
Figure 11.ALC ........................................................................................................................................... 32
Figure 12.Noise Gate Attenuation ............................................................................................................. 33
Figure 13.Output Architecture ................................................................................................................... 34
Figure 14.De-Emphasis Curve .................................................................................................................. 35
Figure 15.Beep Configuration Options ...................................................................................................... 36
Figure 16.Peak Detect & Limiter ............................................................................................................... 37
Figure 17.Master Mode Timing ................................................................................................................. 39
Figure 18.Tri-State Serial Port .................................................................................................................. 40
Figure 19.I²S Format ................................................................................................................................. 40
Figure 20.Left-Justified Format ................................................................................................................. 41
Figure 21.Right-Justified Format (DAC only) ............................................................................................ 41
Figure 22.Initialization Flowchart ............................................................................................................... 42
Figure 23.Control Port Timing in SPI Mode .............................................................................................. 43
Figure 24.Control Port Timing, I²C Write ................................................................................................... 44
Figure 25.Control Port Timing, I²C Read ................................................................................................... 44
Figure 26.AIN & PGA Selection ................................................................................................................ 56
Figure 27.THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) .................................................... 75
Figure 28.THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) .................................................... 75
Figure 29.THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) .................................................... 76
Figure 30.THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) .................................................... 76
Figure 31.Power Dissipation vs. Output Power into Stereo 16 Ω ......................................................................77
Figure 32.Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) .......................................... 77
Figure 33.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 78
Figure 34.ADC Passband Ripple .............................................................................................................. 82
Figure 35.ADC Stopband Rejection .......................................................................................................... 82
Figure 36.ADC Transition Band ................................................................................................................ 82
Figure 37.ADC Transition Band Detail ...................................................................................................... 82
Figure 38.DAC Passband Ripple .............................................................................................................. 82
Figure 39.DAC Stopband .......................................................................................................................... 82
Figure 40.DAC Transition Band ................................................................................................................ 82
Figure 41.DAC Transition Band (Detail) .................................................................................................... 82
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CS42L51
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 9
Table 2. Hardware Mode Feature Summary ............................................................................................. 27
Table 3. MCLK/LRCK Ratios .................................................................................................................... 39
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CS42L51
Pin Name
#
SDIN
SCLK
MCLK
SDOUT (M/S)
DGND
VD
VL
RESET
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
32
31
30
29
28
27
26
25
LRCK
1
24
AIN1B
SDA/CDIN (MCLKDIV2)
2
23
AIN1A
SCL/CCLK (I²S/LJ)
3
22
AFILTB
ADO/CS (DEM)
4
21
AFILTA
VA_HP
5
20
AIN2B/BIAS
FLYP
6
19
AIN2A
GND_HP
7
18
MICIN2/BIAS/AIN3B
FLYN
8
17
MICIN1/AIN3A
9
10
11
12
13
14
15
16
VSS_HP
AOUTB
AOUTA
VA
AGND
DAC_FILT+
VQ
ADC_FILT+
CS42L51
Pin Description
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
LRCK
1
SDA/CDIN
(MCLKDIV2)
2
SCL/CCLK
(I²S/LJ)
3
AD0/CS
(DEM)
4
VA_HP
5
Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.
FLYP
6
Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.
GND_HP
7
Analog Ground (Input) - Ground reference for the internal headphone/charge pump section.
FLYN
8
Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.
VSS_HP
9
Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog headphone section.
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Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the
control port interface in SPI Mode.
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.
Serial Control Port Clock (Input) - Serial clock for the serial control port.
Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface formats for the ADC & DAC.
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS
is the chip-select signal for SPI format.
De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.
7
CS42L51
AOUTB
AOUTA
10
11
Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table
VA
12
Analog Power (Input) - Positive power for the internal analog section.
AGND
13
Analog Ground (Input) - Ground reference for the internal analog section.
DAC_FILT+
14
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
VQ
15
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
ADC_FILT+
16
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
MICIN1/
AIN3A
17
Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table.
MICIN2/
BIAS/AIN3B
18
Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics
specification table. This pin can also be configured as an output to provide a low noise bias supply for an
external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.
AIN2A
19
Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification
table.
AIN2B/BIAS
20
Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.
AFILTA
AFILTB
21
22
Filter Connection (Output) - Filter connection for the ADC inputs.
AIN1A
AIN1B
23
24
Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification
table.
RESET
25
Reset (Input) - The device enters a low power mode when this pin is driven low.
VL
26
Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and
host control port. Refer to the Recommended Operating Conditions for appropriate voltages.
VD
27
Digital Power (Input) - Positive power for the internal digital section.
DGND
28
Digital Ground (Input) - Ground reference for the internal digital section.
SDOUT
(M/S)
29
Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and
Slave Mode for the serial port.
MCLK
30
Master Clock (Input) - Clock source for the delta-sigma modulators.
SCLK
31
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
SDIN
32
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
Thermal Pad
8
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
-
Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 81.
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CS42L51
1.1
Digital I/O Pin Characteristics
The logic level for each input should not exceed the maximum ratings for the VL power supply.
Pin Name
SW/(HW)
I/O
Driver
Receiver
RESET
Input
-
1.8 V - 3.3 V
SCL/CCLK
(I²S/LJ)
Input
-
1.8 V - 3.3 V, with Hysteresis
SDA/CDIN
(MCLKDIV2)
Input/Output
1.8 V - 3.3 V, CMOS/Open Drain
1.8 V - 3.3 V, with Hysteresis
AD0/CS
(DEM)
Input
-
1.8 V - 3.3 V
MCLK
Input
-
1.8 V - 3.3 V
LRCK
Input/Output
1.8 V - 3.3 V, CMOS
1.8 V - 3.3 V
SCLK
Input/Output
1.8 V - 3.3 V, CMOS
1.8 V - 3.3 V
SDOUT
(M/S)
Input/Output
1.8 V - 3.3 V, CMOS
1.8 V - 3.3 V
SDIN
Input
-
1.8 V - 3.3 V
Table 1. I/O Power Rails
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CS42L51
2. TYPICAL CONNECTION DIAGRAMS
See Note 4
+1.8 V or +2.5 V
1 µF
0.1 µF
0.1 µF
VD
VA
0.1 µF
+1.8 V or +2.5 V
1 µF
Note 4:
Series resistance in the path of the power supplies must
be avoided. Any voltage drop on VA_HP will directly
impact the negative charge pump supply (VSS_HP) and
result in clipping on the audio output .
VA_HP
AOUTB
**
1.5 µF
1 µF
**
Headphone Out
Left & Right
FLYP
AOUTA
FLYN
0.022 µF
See Note 5
VSS_HP
1.5 µF
**
51.1 Ω
**
1 µF
GND_HP
470 Ω
* *Use low ESR ceramic capacitors.
C
Note 2 :
CS42L51
For best response to Fs/2 :
C
Rext + 470
C=
4πFs (Rext × 470 )
Speaker Driver
Note 5 :
Larger capacitors, such as 1.5 µF, improves the charge
pump performance (and subsequent THD+N) at the full
scale output power achieved with gain (G) settings
greater than default.
AIN1A
1800 pF
*
1800 pF
*
100 kΩ
100 kΩ
100 Ω
AIN2A
LRCK
SDIN
SDOUT
1800 pF
* 1 µF
1800 pF
*
AIN2B
BIAS1
RESET
Right Analog Input 1
MICIN1
AIN3A
SDA/CDIN
Left Analog Input 2
100 Ω
100 kΩ
100 kΩ
100 Ω
Right Analog Input 2
1 µF
SCL/CCLK
Microphone Input
100 kΩ
1 µF
AD0/CS
BIAS2
AIN3B/MICIN2
Microphone Bias
RL
0.1 µF
2k Ω
See Note 1
Left Analog Input 1
100 Ω
1 µF
SCLK
Digital Audio
Processor
1 µF
AIN1B
MCLK
+1.8 V, +2.5 V
or +3.3 V
Rext
470 Ω
This circuitry is intended for applications where the
CS42L51 connects directly to an unbalanced output of the
device. For internal routing applications please see the
DAC Analog Output Characteristics section for loading
limitations.
2k Ω
Rext
Line Level Out
Left & Right
See Note 2
See Note 3
Note 3: The value of R L is dictated
by the microphone cartridge.
VL
ADC_FILT+
0.1 µF
Note 1:
Resistors are required for I²C
control port operation
DAC_FILT+
1 µF
10 µF
AGND
*
AFILTA
AFILTB
VQ
DGND
*
150 pF
150 pF
1 µF
* Capacitors must be C0G or equivalent
Figure 1. Typical Connection Diagram (Software Mode)
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CS42L51
See Note 4
+1.8V or +2.5V
1 µF
0.1 µF
0.1 µF
VD
VA
+1.8V or +2.5V
1 µF
0.1 µF
Note 4:
Series resistance in the path of the power supplies (typically
used for added filtering) must be avoided. Any voltage drop
on VA_HP will directly impact the negative charge pump
supply (VSS_HP) and result in clipping on the audio output .
VA_HP
AOUTB
1 µF
AOUTA
FLYN
1 µF
Headphone Out
Left & Right
FLYP
**
0.022 µF
51.1 Ω
VSS_HP
**
GND_HP
470Ω
C
* *Use low ESR ceramic capacitors.
CS42L51
C
Rext
Line Level Out
Left & Right
See Note 2
Rext
470Ω
Speaker Driver
MCLK
SCLK
LRCK
AIN1A
SDIN
VL or DGND (1)
SDOUT/
M/S
Digital Audio
Processor
Left Analog Input 1
1800 pF * 1 µF 100 Ω
100 kΩ
1800 pF *
100 kΩ
100 Ω
AIN1B
Right Analog Input 1
1 µF
RESET
I²S/LJ
ADC_FILT+
MCLKDIV2
DAC_FILT+
DEM
1 µF
AGND
*
+1.8V, 2.5 V
or +3.3V
AFILTA
AFILTB
VQ
VL
0.1 µF
150 pF
1 µF
* Capacitors must be C0G or equivalent
DGND
(1) Pull-up to VL (47 kΩ for Master Mode.
Pull-down to DGND for Slave Mode.
*
150 pF
10 µF
Note 2 :
This circuitry is intended for applications where the CS 42L51 connects directly to an unbalanced output of the device . For
internal routing applications please see the DAC Analog Output Characteristics section for loading limitations .
For best response to Fs/2 :
C=
Rext + 470
4πFs (Rext × 470 )
Figure 2. Typical Connection Diagram (Hardware Mode)
DS679F1
11
CS42L51
3. CHARACTERISTIC AND SPECIFICATION TABLES
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and
TA = 25° C.)
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.)
Parameters
Symbol
Min
Nom
Max
Units
1.65
2.37
1.65
2.37
1.65
2.37
1.65
2.37
3.14
1.8
2.5
1.8
2.5
1.8
2.5
1.8
2.5
3.3
1.89
2.63
1.89
2.63
1.89
2.63
1.89
2.63
3.47
V
V
V
V
V
V
V
V
V
-10
-40
-
+70
+85
°C
°C
DC Power Supply (Note 1)
VA
Analog Core
VA_HP
Headphone Amplifier
Digital Core
VD
Serial/Control Port Interface
VL
Ambient Temperature
Commercial - CNZ
Automotive - DNZ
TA
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
Parameters
Min
Max
Units
-0.3
-0.3
-0.3
3.0
3.0
4.0
V
V
V
Iin
-
±10
mA
Analog Input Voltage
VIN
AGND-0.7
VA+0.7
V
Digital Input Voltage
(Note 3)
VIND
-0.3
VL+ 0.4
V
Ambient Operating Temperature (power applied)
TA
-50
+115
°C
Storage Temperature
Tstg
-65
+150
°C
DC Power Supply
Symbol
Analog VA, VA_HP
VD
Digital
VL
Serial/Control Port Interface
Input Current
(Note 2)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes:
1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and
serial/control port interface supplies.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
12
DS679F1
CS42L51
ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive
input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
VA = 2.5 V (nominal)
Min
Typ
Max
Parameter (Note 5)
VA = 1.8 V (nominal)
Min
Typ
Max
Unit
Analog In to ADC (PGA bypassed)
Dynamic Range
A-weighted
unweighted
Total Harmonic Distortion + Noise
-1 dBFS
-20 dBFS
-60 dBFS
93
90
99
96
-
90
87
96
93
-
dB
dB
-
-86
-76
-36
-80
-
-
-84
-73
-33
-78
-
dB
dB
dB
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
A-weighted
unweighted
92
89
98
95
-
89
86
95
92
-
dB
dB
PGA Setting: +12 dB
A-weighted
unweighted
85
82
91
88
-
82
79
88
85
-
dB
dB
-1 dBFS
-60 dBFS
-
-88
-35
-81
-
-
-86
-32
-80
-
dB
dB
-1 dBFS
-
-85
-79
-
-83
-77
dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
PGA Setting: +12 dB
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
A-weighted
unweighted
-
86
83
-
-
83
80
-
dB
dB
-1 dBFS
-
-76
-
-
-74
-
dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
A-weighted
unweighted
-
78
74
-
-
75
71
-
dB
dB
-1 dBFS
-
-74
-
-
-71
-
dB
Interchannel Gain Mismatch
-
0.2
-
-
0.2
-
dB
Gain Drift
-
±100
-
-
±100
-
ppm/°C
-
352
-
-
352
-
LSB
-
90
-
-
90
-
dB
0.74•VA
0.75•VA
70
0.78•VA
0.794•VA
0.129•VA
0.022•VA
0.82•VA
0.83•VA
-
20
39
50
-
PGA Setting: 0 dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
Other Characteristics
DC Accuracy
Offset Error
SDOUT Code with HPF On
Input
Interchannel Isolation
DAC Isolation (Note 4)
Full-scale Input Voltage
Input Impedance (Note 6)
DS679F1
0.74•VA
ADC
PGA (0 dB) 0.75•VA
MIC (+16 dB)
MIC (+32 dB)
ADC
PGA
MIC
70
0.78•VA 0.82•VA
0.794•VA 0.83•VA
0.129•VA
0.022•VA
20
39
50
-
dB
Vpp
Vpp
Vpp
Vpp
kΩ
kΩ
kΩ
13
CS42L51
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input
filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
VA = 2.5 V (nominal)
Min
Typ
Max
Parameter (Note 5)
VA = 1.8 V (nominal)
Min
Typ
Max
Unit
Analog In to ADC
Dynamic Range
A-weighted
unweighted
Total Harmonic Distortion + Noise
-1 dBFS
-20 dBFS
-60 dBFS
91
78
99
96
-
88
85
96
93
-
dB
dB
-
-86
-76
-36
-78
-
-
-84
-73
-33
-76
-
dB
dB
dB
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
A-weighted
unweighted
90
87
98
95
-
87
84
95
92
-
dB
dB
PGA Setting: +12 dB
A-weighted
unweighted
83
80
91
88
-
80
77
88
85
-
dB
dB
-1 dBFS
-60 dBFS
-
-88
-35
-80
-
-
-86
-32
-78
-
dB
dB
-1 dBFS
-
-85
-77
-
-83
-75
dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
PGA Setting: +12 dB
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB
A-weighted
unweighted
-
86
83
-
-
83
80
-
dB
dB
-1 dBFS
-
-76
-
-
-74
-
dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
A-weighted
unweighted
-
78
74
-
-
75
71
-
dB
dB
-1 dBFS
-
-74
-
-
-71
-
dB
Interchannel Gain Mismatch
-
0.1
-
-
0.1
-
dB
Gain Drift
-
±100
-
-
±100
-
ppm/°C
-
352
-
-
352
-
LSB
-
90
-
-
90
-
dB
70
0.78•VA
0.794•VA
0.129•VA
0.022•VA
0.82•VA
0.83•VA
0.74•VA
0.75•VA
70
0.78•VA
0.794•VA
0.129•VA
0.022•VA
0.82•VA
0.83•VA
-
-
18
40
50
-
-
PGA Setting: 0 dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB
Other Characteristics
DC Accuracy
Offset Error
SDOUT Code with HPF On
Input
Interchannel Isolation
DAC Isolation (Note 4)
Full-scale Input Voltage
Input Impedance (Note 6)
ADC 0.74•VA
PGA (0 dB) 0.75•VA
MIC (+16 dB)
MIC (+32 dB)
18
ADC
40
PGA
50
MIC
dB
Vpp
Vpp
Vpp
Vpp
kΩ
kΩ
kΩ
4. Measured with DAC delivering full-scale output power into 16 Ω.
14
DS679F1
CS42L51
5. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table.
6. Measured between AINxx and AGND.
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 7)
Min
Typ
Max
Unit
0
-
0.4948
Fs
-0.09
-
0.17
dB
Stopband
0.6
-
-
Fs
Stopband Attenuation
33
-
-
dB
-
7.6/Fs
-
s
Passband (Frequency Response)
Passband Ripple
Total Group Delay
to -0.1 dB corner
High-Pass Filter Characteristics (48 kHz Fs)
Frequency Response
-3.0 dB
-0.13 dB
-
3.7
24.2
-
Hz
Hz
Phase Deviation
@ 20 Hz
-
10
-
Deg
-
-
0.17
dB
-
5/Fs
0
s
Passband Ripple
Filter Settling Time
10
7. Response is clock-dependent and will scale with Fs. Note that the response plots (Figure 33 to Figure 41)
have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF parameters are for Fs = 48 kHz.
DS679F1
15
CS42L51
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement
bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output
(see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.)
VA = 1.8V (nominal)
VA = 2.5V (nominal)
Min
Typ
Max Min
Typ
Max
Parameter (Note 8)
Unit
RL = 10 kΩ
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
A-weighted
unweighted
16-Bit
92
89
-
98
95
96
93
-
89
86
-
95
92
93
90
-
dB
dB
dB
dB
-
-86
-75
-35
-86
-73
-33
-78
-
-
-88
-72
-32
-88
-70
-30
-82
-
dB
dB
dB
dB
dB
dB
92
89
-
98
95
96
93
-
89
86
-
95
92
93
90
-
dB
dB
dB
dB
-
-75
-75
-35
-75
-73
-33
-69
-
-
-75
-72
-32
-75
-70
-30
-69
-
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
16-Bit
RL = 16 Ω
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
A-weighted
unweighted
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
16-Bit
Other Characteristics for RL = 16 Ω or 10 kΩ
Output Parameters
(Note 9)
Modulation Index (MI)
Analog Gain Multiplier (G)
Full-scale Output Voltage (2•G•MI•VA) (Note 9)
Full-scale Output Power (Note 9)
Interchannel Isolation (1 kHz)
16 Ω
10 kΩ
0.6787
0.6787
0.6047
0.6047
Refer to Table “Line Output Voltage Characteristics” on
page 18
Refer to Table “Headphone Output Power Characteristics”
on page 19
80
80
95
93
-
Interchannel Gain Mismatch
-
0.1
0.25
-
0.1
0.25
Gain Drift
-
±100
-
-
±100
-
Vpp
mW
dB
dB
dB
ppm/°
C
AC-Load Resistance (RL)
(Note 10)
16
-
-
16
-
-
Ω
Load Capacitance (CL)
(Note 10)
-
-
150
-
-
150
pF
16
DS679F1
CS42L51
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement
bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 kΩ, CL = 10 pF for the
line output (see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output.
HP_GAIN[2:0] = 011.)
VA = 2.5V (nominal)
Min
Typ
Max
Parameter (Note 8)
VA = 1.8V (nominal)
Min
Typ
Max
Unit
RL = 10 kΩ
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
A-weighted
unweighted
16-Bit
90
87
-
98
95
96
93
-
87
84
-
95
92
93
90
-
dB
dB
dB
dB
-
-86
-75
-35
-86
-73
-33
-73
-
-
-88
-72
-32
-88
-70
-30
-80
-
dB
dB
dB
dB
dB
dB
90
87
-
98
95
96
93
-
87
84
-
95
92
93
90
-
dB
dB
dB
dB
-
-75
-75
-35
-75
-73
-33
-67
-
-
-75
-72
-32
-75
-70
-30
-67
-
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
16-Bit
RL = 16 Ω
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
A-weighted
unweighted
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
16-Bit
Other Characteristics for RL = 16 Ω or 10 kΩ
Output Parameters
(Note 9)
Modulation Index (MI)
Analog Gain Multiplier (G)
Full-scale Output Voltage (2•G•MI•VA) (Note 9)
Full-scale Output Power (Note 9)
Interchannel Isolation (1 kHz)
16 Ω
10 kΩ
0.6787
0.6787
0.6047
0.6047
Refer to Table “Line Output Voltage Characteristics” on
page 18
Refer to Table “Headphone Output Power Characteristics”
on page 19
80
80
95
93
-
Interchannel Gain Mismatch
-
0.1
0.25
-
0.1
0.25
Gain Drift
-
±100
-
-
±100
-
Vpp
mW
dB
dB
dB
ppm/°
C
AC-Load Resistance (RL)
(Note 10)
16
-
-
16
-
-
Ω
Load Capacitance (CL)
(Note 10)
-
-
150
-
-
150
pF
DS679F1
17
CS42L51
LINE OUTPUT VOLTAGE CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF (see Figure 3).
Parameter
VA = 2.5V (nominal)
Min
Typ
Max
VA = 1.8V (nominal)
Min
Typ
Max
1.95
-
2.15
-
1.41
-
-
-
Unit
AOUTx Voltage Into RL = 10 kΩ
HP_GAIN[2:0]
Analog
Gain (G)
000
0.3959
001
0.4571
010
0.5111
011 (default)
0.6047
100
0.7099
101
0.8399
110
1.0000
111
1.1430
18
VA_HP
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
-
1.34
1.34
1.55
1.55
1.73
1.73
2.05
2.05
2.41
2.41
2.85
2.85
3.39
3.39
(See (Note 11)
3.88
-
0.97
0.97
1.12
1.12
1.25
1.25
1.48
1.48
1.73
1.73
2.05
2.05
2.44
2.44
2.79
2.79
1.55
-
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
DS679F1
CS42L51
HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 Ω, CL = 10 pF (see Figure 3).
VA = 1.8V (nominal)
Min
Typ
Max
VA = 2.5V (nominal)
Min
Typ
Max
Parameter
Unit
AOUTx Power Into RL = 16 Ω
HP_GAIN[2:0]
Analog
Gain (G)
000
0.3959
001
0.4571
010
0.5111
011 (default)
0.6047
100
0.7099
101
0.8399
110
1.0000
111
1.1430
VA_HP
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
-
14
14
19
19
23
23
(Note 11)
32
(Note 11)
44
-
-
-
-
(Note 9, 11)
7
7
10
10
12
12
17
17
23
23
(Note 9)
32
-
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
8. One-half LSB of triangular PDF dither is added to data.
9. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog
Gain (HP_GAIN[2:0])” on page 57. High gain settings at certain VA and VA_HP supply levels may
cause clipping when the audio signal approaches full-scale, maximum power output, as shown in
Figures 27 - 30 on page 76.
10. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable.
11. VA_HP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power.
AOUTx
51 Ω
0.022 µF
C
L
R
L
AGND
Figure 3. Headphone Output Test Load
DS679F1
19
CS42L51
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 12)
Frequency Response 10 Hz to 20 kHz
Passband
to -0.05 dB corner
to -3 dB corner
StopBand
StopBand Attenuation (Note 13)
Group Delay
De-emphasis Error
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Min
Typ
Max
Unit
-0.01
-
+0.08
dB
0
0
-
0.4780
0.4996
Fs
Fs
0.5465
-
-
Fs
50
-
-
dB
-
10.4/Fs
-
s
-
-
+1.5/+0
+0.05/-0.25
-0.2/-0.4
dB
dB
dB
Notes:
12. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 38 to Figure 41
on page 82) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
13. Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.)
Parameters
RESET pin Low Pulse Width
Symbol
(Note 14)
MCLK Frequency
MCLK Duty Cycle
(Note 15)
Min
Max
Units
1
-
ms
1.024
38.4
MHz
45
55
%
4
8
4
50
12.5
25
50
100
kHz
kHz
kHz
kHz
45
55
%
-
64•Fs
Hz
45
55
%
Slave Mode
Input Sample Rate (LRCK)
Quarter-Speed Mode
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
Fs
Fs
Fs
Fs
LRCK Duty Cycle
SCLK Frequency
1/tP
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
ts(LK-SK)
40
-
ns
LRCK Edge to SDOUT MSB Output Delay
td(MSB)
-
52
ns
SDOUT Setup Time Before SCLK Rising Edge
ts(SDO-SK)
20
-
ns
SDOUT Hold Time After SCLK Rising Edge
th(SK-SDO)
30
-
ns
SDIN Setup Time Before SCLK Rising Edge
ts(SD-SK)
20
-
ns
th
20
-
ns
SDIN Hold Time After SCLK Rising Edge
20
DS679F1
CS42L51
Parameters
Symbol
Min
Fs
-
Max
Units
Master Mode (Note 17)
Output Sample Rate (LRCK)
All Speed Modes
(Note 17)
MCLK
----------------128
Hz
45
55
%
-
64•Fs
Hz
45
55
%
td(MSB)
-
52
ns
SDOUT Setup Time Before SCLK Rising Edge
ts(SDO-SK)
20
-
ns
SDOUT Hold Time After SCLK Rising Edge
th(SK-SDO)
30
-
ns
SDIN Setup Time Before SCLK Rising Edge
ts(SD-SK)
20
-
ns
th
20
-
ns
LRCK Duty Cycle
1/tP
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDIN Hold Time After SCLK Rising Edge
14. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are
settled.
15. See “Example System Clock Frequencies” on page 79 for typical MCLK frequencies.
16. See
17. “Master” on page 39
18. “MCLK” refers to the external master clock applied.
//
LRCK
ts(LK-SK)
//
tP
//
SCLK
//
td(MSB)
SDOUT
ts(SD-SK)
SDIN
th(SK-SDO)
//
MSB
//
th
//
MSB
//
ts(SDO-SK)
MSB-1
MSB-1
Figure 4. Serial Audio Interface Slave Mode Timing
//
LRCK
//
tP
//
SCLK
//
td(MSB)
SDOUT
ts(SD-SK)
SDIN
th(SK-SDO)
//
MSB
//
th
//
MSB
//
ts(SDO-SK)
MSB-1
MSB-1
Figure 5. Serial Audio Interface Master Mode Timing
DS679F1
21
CS42L51
SWITCHING SPECIFICATIONS - I²C® CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RESET Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL and SDA
trc
-
1
µs
Fall Time SCL and SDA
tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
3450
ns
SDA Hold Time from SCL Falling
(Note 19)
SDA Setup time to SCL Rising
19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
Repeated
Start
Start
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
low
t
hdd
t sud
t sust
tr
Figure 6. Control Port Timing - I²C
22
DS679F1
CS42L51
SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
0
6.0
MHz
RESET Rising Edge to CS Falling
tsrs
20
-
ns
CS Falling to CCLK Edge
tcss
20
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 20)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 21)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 21)
tf2
-
100
ns
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For fsck <1 MHz.
RST
tsrs
CS
tcsh
tcss
tsch
tscl
tr2
CCLK
tf2
tdsu
tdh
CDIN
Figure 7. Control Port Timing - SPI Format
DS679F1
23
CS42L51
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
Parameters
Min
Typ
Max
Units
Nominal Voltage
Output Impedance
DC Current Source/Sink (Note 22)
-
0.5•VA
23
-
10
V
kΩ
µA
DAC_FILT+ Nominal Voltage
ADC_FILT+ Nominal Voltage
-
VA
VA
-
V
V
-
-0.8•(VA_HP)
10
V
µA
0.8•VA
0.7•VA
0.6•VA
0.5•VA
50
1
-
V
V
V
V
mA
dB
60
-
dB
VQ Characteristics
VSS_HP Characteristics
Nominal Voltage
DC Current Source
MIC BIAS Characteristics
DC Current Source
Power Supply Rejection Ratio (PSRR)
1 kHz
-
Power Supply Rejection Ratio (PSRR) (Note 23)
1 kHz
-
Nominal Voltage
MICBIAS_LVL[1:0] = 00
MICBIAS_LVL[1:0] = 01
MICBIAS_LVL[1:0] = 10
MICBIAS_LVL[1:0] = 11
22. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage
through electrolytic de-coupling capacitors.
23. Valid with the recommended capacitor values on DAC_FILT+, ADC_FILT+ and VQ. Increasing the capacitance will also increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 24)
Input Leakage Current
Symbol
Min
Max
Units
Iin
-
±10
µA
-
10
pF
Input Capacitance
1.8 V - 3.3 V Logic
High-Level Output Voltage (IOH = -100 µA)
VOH
VL - 0.2
-
V
Low-Level Output Voltage (IOL = 100 µA)
VOL
-
0.2
V
High-Level Input Voltage
VIH
0.68•VL
-
V
Low-Level Input Voltage
VIL
-
0.32•VL
V
24. See “Digital I/O Pin Characteristics” on page 9 for serial and control port power rails.
24
DS679F1
CS42L51
POWER CONSUMPTION
See (Note 25)
PDN_DACB
PDN_DACA
PDN_PGAB
PDN_PGAA
PDN_ADCB
PDN_ADCA
PDN
PDN_MICB
PDN_MICA
PDN_MICBIAS
Power Ctl. Registers
02h
03h
Operation
Typical Current (mA)
iVA_HP
iVA
iVD
iVL
(Note 28)
V
Total
Power
(mWrms)
1
x x x x x x x x x x 1.8
2.5
0
0
0
0
0
Off (Note 26)
0
0
0
0
0
2
Standby (Note 27)
x x x x x x 1 x x x 1.8
2.5
0
0.01
0.02
0
0.05
0
0.01
0.03
0
0.10
3
Mono Record
ADC 1 1 1 1 1 0 0 1 1 1 1.8
2.5
PGA to ADC 1 1 1 0 1 0 0 1 1 1 1.8
0
1.85
2.03
0.03
7.05
0
2.07
3.05
0.05
12.94
0
2.35
2.03
0.03
7.95
2.5
0
2.58
3.08
0.05
14.29
MIC to PGA to ADC 1 1 1 0 1 0 0 1 0 0 1.8
(with Bias)
2.5
MIC to PGA to ADC 1 1 1 0 1 0 0 1 0 1 1.8
(no Bias)
2.5
0
3.67
2.05
0.03
10.36
0
3.95
3.09
0.05
17.71
0
3.27
2.03
0.03
9.61
0
3.52
3.08
0.05
16.62
ADC 1 1 1 1 0 0 0 1 1 1 1.8
2.5
PGA to ADC 1 1 0 0 0 0 0 1 1 1 1.8
0
2.69
2.12
0.03
8.72
0
2.93
3.18
0.04
15.40
0
3.65
2.12
0.03
10.45
2.5
0
3.91
3.17
0.04
17.84
MIC to PGA to ADC 1 1 0 0 0 0 0 0 0 1 1.8
(no Bias)
2.5
0
5.48
2.11
0.03
13.73
0
5.76
3.17
0.04
22.45
1 0 1 1 1 1 0 1 1 1 1.8
2.5
1.66
1.40
2.35
0.01
9.74
2.03
1.71
3.48
0.02
18.08
4
5
Stereo Record
Mono Playback
6
Stereo Playback
0 0 1 1 1 1 0 1 1 1 1.8
2.5
2.77
2.05
2.35
0.01
12.93
3.21
2.50
3.49
0.02
23.02
7
Mono Record & Playback
PGA in (no MIC) to Mono Out
1 0 1 0 1 0 0 1 1 1 1.8
2.5
1.66
3.63
2.73
0.03
14.49
2.03
4.16
4.08
0.05
25.79
8
Phone Monitor
MIC (w/bias) in to Mono Out
1 0 1 0 1 0 0 1 0 0 1.8
2.5
1.66
4.95
2.75
0.03
16.90
2.03
5.52
4.08
0.05
29.20
9
Stereo Record & Playback
PGA in (no MIC) to Stereo Out
0 0 0 0 0 0 0 1 1 1 1.8
2.5
2.77
5.59
2.82
0.03
20.18
3.21
6.28
4.19
0.04
34.30
25. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =
48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and master/slave operation.
26. RESET pin 25 held LO, all clocks and data lines are held LO.
27. RESET pin 25 held HI, all clocks and data lines are held HI.
28. VL current will slightly increase in master mode.
DS679F1
25
CS42L51
4. APPLICATIONS
4.1
4.1.1
Overview
Architecture
The CS42L51 is a highly integrated, low power, 24-bit audio CODEC comprised of stereo analog-to-digital
converters (ADC), and stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma
techniques. The DAC operates at an oversampling ratio of 128Fs and the ADC operates at 64Fs, where
Fs is equal to the system sample rate. The different clock rates maximize power savings while maintaining
high performance. The CODEC operates in one of four sample rate speed modes: Quarter, Half, Single
and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input
Master Clock (MCLK).
4.1.2
Line & MIC Inputs
The analog input portion of the CODEC allows selection from and configuration of multiple combinations
of stereo and microphone (MIC) sources. Six line inputs with configuration for two MIC inputs (or one MIC
input with common mode rejection), two MIC bias outputs and independent channel control (including a
high-pass filter disable function) are available. A Programmable Gain Amplifier (PGA), MIC boost, and Automatic Level Control (ALC), with noise gate settings, provide analog gain and adjustment. Digital volume
controls, including gain, boost, attenuation and inversion are also available.
4.1.3
Line & Headphone Outputs
The analog output portion of the D/A includes a headphone amplifier capable of driving headphone and
line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale output swing centered around ground. This eliminates the need for large DC-Blocking capacitors and allows
the amplifier to deliver more power to headphone loads at lower supply voltages. Eight gain settings for
the headphone amplifier are available.
4.1.4
Signal Processing Engine
A signal processing engine is available to process serial input D/A data before output to the DAC. The
D/A data has independent volume controls and mixing functions such as mono mixes and left/right channel swaps. A Tone Control provides bass and treble at four selectable corner frequencies. An automatic
level control provides limiting capabilities at programmable attack and release rates, maximum thresholds
and soft ramping. A 15/50 µs de-emphasis filter is also available at a 44.1 kHz sample rate.
4.1.5
Beep Generator
A beep may be generated internally at select frequencies across approximately two octave major scales
and configured to occur continuously, periodically or at single time intervals controlled by the user. Volume
may be controlled independently.
4.1.6
Device Control (Hardware or Software Mode)
In Software Mode, all functions and features may be controlled via a two-wire I²C or three-wire SPI control
port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins.
4.1.7
Power Management
Two Software Mode control registers provide independent power-down control of the ADC, DAC, PGA,
MIC pre-amp and MIC bias, allowing operation in select applications with minimal power consumption.
26
DS679F1
CS42L51
4.2
Hardware Mode
A limited feature-set is available when the CODEC powers up in Hardware Mode (see “Recommended Power-Up Sequence” on page 41) and may be controlled via stand-alone control pins. Table 2 shows a list of
functions/features, the default configuration and the associated stand-alone control available.
Hardware Mode Feature/Function Summary
Feature/Function
Default Configuration
Stand-Alone Control
Note
Powered Up
Powered Up
Powered Up
Powered Up
Powered Down
Powered Down
-
-
Enabled
-
-
Auto-Detect Speed Mode
Single-Speed Mode
-
-
MCLK Divide
(Selectable)
“MCLKDIV2” pin 2
Serial Port Master / Slave Selection
(Selectable)
“M/S” pin 29
(Selectable)
“I²S/LJ” pin 3
Disabled
Disabled
Disabled
Disabled
0 dB
0 dB
Disabled
Disabled
-
-
-
-
-
-
-
-
Power Control
CODEC
PGAx
ADCx
DACx
MIC Bias
MICx Pre-amplifier
Auto-Detect
Speed Mode
Serial Port Slave
Serial Port Master
Interface Control
ADC
DAC
ADC Volume & Gain
Digital Boost
Soft Ramp
Zero Cross
Invert
PGAx
Attenuator
ALC
Noise Gate
ADCx High-Pass Filter
ADCx High-Pass Filter Freeze
Line/MIC Input Select
DAC Volume & Gain
HP Gain
AOUTx Volume
Invert
Soft Ramp
Zero Cross
DAC De-Emphasis
Signal Processing Engine (SPE)
Mix
Beep
Tone Control
Peak Detect and Limiter
Data Selection
Channel Mix
Charge Pump Frequency
ADC
DAC
Enabled
Continuous DC Subtraction
AIN1A to PGAA
AIN1B to PGAB
G = 0.6047
0 dB
Disabled
Enabled
Disabled
see Section
4.5 on page 38
see Section
4.5 on page 38
see Section
4.6 on page 40
see Section
(Selectable)
“DEM” pin 4
Disabled
Disabled
Disabled
Disabled
-
-
Data Input (PCM) to DAC
-
-
ADCA = L; ADCB = R
PCMA = L; PCMB = R
-
-
(64xFs)/7
-
-
on page 34
Table 2. Hardware Mode Feature Summary
DS679F1
27
CS42L51
4.3
Analog Inputs
AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level signals, allowing various gain and signal adjustments for each channel.
ADCA_MUTE
ADCA_DBOOST
+20dB
Digital
Boost
MUX
MUX
ADCA_ATT[7:0]
0/-96dB
1dB steps
PDN_ADCA
Multibit
Oversampling
ADC
Attenuator
ADCA_HPF FREEZE
ADCA_HPF ENABLE
INV_ADCA
SOFTA
PCM Serial Interface
MICMIX
DIGMIX
Σ
Noise Gate
NG_ALL
NG_EN
THRESH[3:0]
NGDELAY[1:0]
MICA_BOOST
MICBIAS
PDN_MICBIAS
ALC_ENB
ALCB_SRDIS
ALCB_ZCDIS
MICBIAS_SEL
PDN_ADCB
SOFTB
+20dB
Digital
Boost
ADCB_HPF FREEZE
ADCB_HPF ENABLE
AIN3A/ MICIN1
+16/
32 dB
PDN_PGAA
PDN_MICA
ALC
MUX
AIN1A
AIN2A
MUX
MICBIAS_LVL[1:0]
ADCB_DBOOST
MUX
PGA
AINA_MUX[1:0]
ALCA_SRDIS
ALCA_ZCDIS
ALC_ENA
ALC_ARATE[5:0]
ALC_RRATE[5:0]
MAX[2:0]
MIN[2:0]
PGAA_VOL[5:0]
ADC_SNGVOL
SOFTA
ZCROSSA
+12/-3dB
0.5dB steps
Attenuator
Multibit
Oversampling
ADC
PGAB_VOL[5:0]
ADC_SNGVOL
SOFTB
ZCROSSB
+12/-3dB
0.5dB steps
PGA
PDN_PGAB
ADCB_MUTE
AIN1B
AIN2B/MICBIAS
MUX
AIN3B/ MICIN2/
MICBIAS
+16/
32 dB
INV_ADCB
ADCB_ATT[7:0]
0/-96dB
1dB steps
AINB_MUX[1:0]
MICB_BOOST
PDN_MICB
TO SIGNAL PROCESSING
ENGINE (SPE)
FROM SIGNAL
PROCESSING ENGINE
(SPE)
Figure 8. Analog Input Architecture
4.3.1
Digital Code, Offset & DC Measurement
The ADC output data is in two’s complement binary format. For inputs above positive full scale or below
negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow
bit to be set to a ‘1’.
Given the two’s complement format, low-level signals may cause the MSB of the serial data to periodically
toggle between ‘1’ and ‘0’, possibly introducing noise into the system as the bit switches back and forth.
To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal
just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note
that this offset is not removed (refer to “Analog Input Characteristics (Commercial - CNZ)” on page 13
and/or “Analog Input Characteristics (Automotive - DNZ)” on page 14 for the specified offset level).
The CODEC may be used to measure DC voltages by disabling the high-pass filter for the designated
channel. DC levels are measured relative to VQ and will be decoded as positive two’s complement binary
numbers above VQ and negative two’s complement binary numbers below VQ.
Software
Controls:
28
“Status (Address 20h) (Read Only)” on page 73, “ADC Control (Address 06h)” on page 54.
DS679F1
CS42L51
4.3.2
High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the high-pass filter is “frozen” during normal operation, the current value of the DC offset for the
corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion
result. This feature makes it possible to perform a system DC offset calibration by:
1. Running the CODECwith the high-pass filter enabled and the DC offset not “frozen” until the filter
settles. See the Digital Filter Characteristics for filter settling time.
2. Freezing the DC offset.
The high-pass filters are controlled using the ADCx_HPFRZ and ADCx_HPFEN bits.
If a particular ADC channel is used to measure DC voltages, the high-pass filter may be disabled using
the ADCx_HPFEN bit.
Software
Controls:
4.3.3
“ADC Control (Address 06h)” on page 54.
Digital Routing
The digital output of the ADC may be internally routed to the signal processing engine (SPE) for playback
of analog input signals. Volume to the DAC may be controlled using the ADCMIX[6:0] bits. The serial input
data may also be routed to the ADC serial interface using the DIGMIX bit. This is useful for recording a
digital mix along with the analog input.
Software
Controls:
4.3.4
“ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)” on page 61, “Interface Control (Address 04h)” on page 52.
Differential Inputs
The stereo pair inputs act as a single differential input when the MICMIX bit is enabled. This provides common mode rejection of noise in digitally intense PCB’s where the microphone signal traverses long traces,
or across long microphone cables as illustrated in Figure 9.
Since the mixer provides a differential combination of the two signals, the potential input mix may exceed
the maximum full-scale input and result in clipping. The level out of the mixer, therefore, is automatically
attenuated 6 dB. Gain may be applied using either the analog PGA or MIC Pre-amp or the digital ADCMIX
volume control to re-adjust a small signal to desired levels.
The analog inputs may also be used as a differential input pair as illustrated in Figure 10. The two channels are differentially combined when the MICMIX bit is enabled.
4.3.4.1
External Passive Components
The microphone input is internally biased to VQ. Input signals must be AC coupled using external capacitors with values consistent with the desired high-pass filter design. The MICINx input resistance of 50 kΩ
may be combined with an external capacitor of 1 µF to achieve the cutoff frequency defined by the equation,
An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with
the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits.
DS679F1
29
CS42L51
1
fc = ----------------------------------------------- = 3.18 Hz
2π ( 50 kΩ ) ( 1 µF )
The MICBIAS series resistor must be selected based on the requirements of the particular microphone
used. The MICBIAS output pin is selected using the MICBIAS_SEL bit.
Software
Controls:
“Interface Control (Address 04h)” on page 52, “MIC Control (Address 05h)” on page 53.
MICBIAS
20
MICIN1
+
//
17
Σ
+
//
MICIN2
18
Figure 9. MIC Input Mix w/Common Mode Rejection
2.5 V
2.15 V
VA
AINxA
1.25 V
0.35 V
2.15 V
AINxB
1.25 V
0.35 V
Full-Scale Differential Input Level (MICMIX=1)
= (AINxA - AINxB) = 3.6 VPP = 1.27 VRMS
Figure 10. Differential Input
30
DS679F1
CS42L51
4.3.5
Analog Input Multiplexer
A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input
source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or bypassed around the PGA. To conserve power, the PGA’s may be powered down allowing the user to select
from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC preamp, however, the PGA must be powered up.
Analog input channel B may also be used as an output for the MIC bias voltage. The MICBIAS_SEL bit
routes the bias voltage to either of two pins. The multiplexer must then select from the remainder of the
two input channels.
The ADC, PGA and MIC pre-amplifier each has an associated input resistance. When selecting between
these paths, the input resistance to the CODEC will change accordingly. Refer to the input resistance
characteristics in the Characteristic and Specification Tables for the input resistance of each path.
Software
Controls:
4.3.6
“Power Control 1 (Address 02h)” on page 49, “MIC Control (Address 05h)” on page 53 “ADCx
Input Select, Invert & Mute (Address 07h)” on page 56.
MIC & PGA Gain
The MIC-level input passes through a +16 dB or +32 dB analog gain stage prior to the input multiplexer,
allowing it to be used for microphone level signals without the need for any external gain. The PGA must
be powered up when using the MIC pre-amp.
The PGA stage provides an additional +12 dB to -3 dB of analog gain in 0.5 dB steps.
Software
Controls:
DS679F1
“Power Control 1 (Address 02h)” on page 49, “ADCx Input Select, Invert & Mute (Address 07h)” on
page 56, “ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)” on
page 59, “MIC Control (Address 05h)” on page 53.
31
CS42L51
4.3.7
Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak
levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases
the digital attenuation levels at a programmable attack rate and maintains the resulting level below the
maximum threshold.
When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first
and the PGA gain is then increased at a programmable release rate and maintains the resulting level
above the minimum threshold.
Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC
soft ramp and zero cross dependency may be independently enabled/disabled.
Recommended settings: Best level control may be realized with the fastest attack and slowest release
setting with soft ramp enabled in the control registers. Note: 1.) The maximum realized gain must be set
in the PGAx_VOL register. The ALC will only apply the gain set in the PGAx_VOL. 2.) The ALC maintains
the output signal between the MIN and MAX thresholds. As the input signal level changes, the level-controlled output may not always be the same but will always fall within the thresholds.
“ALC Enable & Attack Rate (Address 1Ch)” on page 70, “ALC Release Rate (Address 1Dh)” on
page 71, “ALC Threshold (Address 1Eh)” on page 71, “ALCX & PGAX Control: ALCA, PGAA
(Address 0Ah) & ALCB, PGAB (Address 0Bh)” on page 59.
Software
Controls:
Input
MAX[2:0]
MIN[2:0]
below full scale
below full scale
ALC
ADCx_ATT[7:0] and
PGAx_VOL[4:0] volume
controls should NOT be
adjusted manually when
ALCx is enabled.
PGA Gain and/or
Attenuator
Output
(after ALC)
MAX[2:0]
MIN[2:0]
below full scale
below full scale
RRATE[5:0]
ARATE[5:0]
Figure 11. ALC
32
DS679F1
CS42L51
4.3.8
Noise Gate
The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents
the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before
the noise gate attacks the signal.
Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC pre-amplifier. For example: If both +32 dB pre-amplification and +12 dB programmable gain is applied, the maximum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale.
Ramp-down time to the maximum setting is affected by the SOFTx bit.
Recommended settings: For best results, enable soft ramp for the digital attenuator. When the analog inputs are configured for differential signals (see “Differential Inputs” on page 29), enable the NG_ALL bit
to trigger the noise gate only when both inputs fall below the threshold.
Software
Controls:
“Noise Gate Configuration & Misc. (Address 1Fh)” on page 72, “ADC Control (Address 06h)” on
page 54.
Output
(dB)
N
=1
EN
G
N
G
=0
EN
-96
Maximum Attenuation*
-52 dB
-64 dB
-80 dB
-40
Input (dB)
THRESH[2:0]
Figure 12. Noise Gate Attenuation
DS679F1
33
CS42L51
4.4
Analog Outputs
AOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing options
are available, including digital mixes with the ADC signal and an internal Beep Generator. The desired path
to the DAC must be selected using the DATA_SEL[1:0] bits.
Software
Controls:
“DAC Control (Address 09h)” on page 58.
ARATE[7:0]
RRATE[7:0]
MAX[2:0]
MIN[2:0]
LIM_SRDIS
LIM_ZCDIS
LIMIT_EN
SIGNAL PROCESSING ENGINE (SPE)
OUTA_VOL[7:0]
OUTB_VOL[7:0]
+12dB/-102dB
0.5dB steps
PCM Serial Interface
Chnl Vol.
Settings
DEEMPH
MUTE_PCMMIXA
MUTE_PCMMIXB
PCMMIXA_VOL[6:0]
PCMMIXB_VOL[6:0]
PCMA[1:0]
PCMB[1:0]
+12dB/-51.5dB
0.5dB steps
Demph
Limiter
VOL
TC_EN
Σ
Channel
Swap
VOL
DAC_SZC[1:0]
DACA_MUTE
DACB_MUTE
INV_DACA
INV_DACB
DAC_SNGVOL
AMUTE
BPVOL[4:0]
0dB/-50dB
2.0dB steps
Peak
Detect
Bass/
Treble/
Control
DATA_SEL[1:0]
01
PDN_DACA
PDN_DACB
Switched
Capacitor DAC
and Filter
HP_GAIN[2:0]
Headphone
Amp - GND
Centered
Left/Right
HP Out
00
BASS_CF[1:0]
TREB_CF[1:0]
Charge
Pump
BASS[3:0]
TREB[3:0]
+12.0dB/-10.5dB
1.5dB steps
CHRG_FREQ[3:0]
VOL
OFFTIME[2:0]
ONTIME[3:0]
FREQ[3:0]
REPEAT
BEEP
Beep
Generator
Figure 13. Output Architecture
4.4.1
De-Emphasis Filter
The CODEC includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 14. The de-emphasis feature is included to accommodate audio recordings
that utilize 50/15 µs pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode.
Software
Controls:
“DAC Control (Address 09h)” on page 58.
Pin
Hardware
Control:
34
Setting
“DEM” pin 4. LO
HI
Selection
No De-Emphasis
De-Emphasis Applied
DS679F1
CS42L51
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 14. De-Emphasis Curve
4.4.2
Volume Controls
Three digital volume control functions are implemented, offering independent control over the ADC and
PCM signal paths into the mixer as well as a combined control over the mixed signals. All volume controls
are programmable to ramp in increments of 0.125 dB at a rate controlled by the DAC soft ramp/zero cross
settings.
All signal paths may also be independently muted via mute control bits. When enabled, each bit attenuates the signal to its maximum value. When the mute bit is disabled, the signal returns to the attenuation
level set in the respective volume control register. The attenuation is ramped up and down at the rate
specified by the DAC_SZC[1:0] bits.
Software
Controls:
4.4.3
“ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)” on page 61, “PCMX
Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h)” on page 62, “AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)” on page 66, “DAC Output Control
(Address 08h)” on page 57.
Mono Channel Mixer
A channel mixer may be used to create a mix of the left and right channels for either the PCM or ADC
signals. This mix allows the user to produce a MONO signal from a stereo source. The mixer may also be
used to implement a left/right channel swap.
Software
Controls:
4.4.4
“PCM Channel Mixer (Address 18h)” on page 67.
Beep Generator
The Beep Generator generates audio frequencies across approximately two octave major scales. It offers
three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen on and eight off
times are available.
Note: The Beep is generated before the limiter and may affect desired limiting performance. If the limiter
function is used, it may be required to set the Beep volume sufficiently below the threshold to prevent the
peak detect from triggering. Since the master volume control, AOUTx_VOL[7:0], will affect the Beep volume, DAC volume may alternatively be controlled using the PCMMIXx_VOL[6:0] bits.
Software
Controls:
DS679F1
“Beep Frequency & Timing Configuration (Address 12h)” on page 62, “Beep Off Time & Volume
(Address 13h)” on page 63, “Beep Configuration & Tone Configuration (Address 14h)” on page 64
35
CS42L51
REPEAT = '1'
BEEP = '1'
CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains
on until REPEAT is cleared.
REPEAT = '1'
BEEP = '0'
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)
and volume (BPVOL) for the duration of ONTIME and turns off for
the duration of OFFTIME. On and off cycles are repeated until
REPEAT is cleared.
REPEAT = '0'
BEEP = '1'
SINGLE-BEEP: Beep turns on at a
configurable frequency (FREQ) and
volume (BPVOL) for the duration of
ONTIME. BEEP must be cleared
and set for additional beeps.
...
BPVOL[4:0]
FREQ[3:0]
ONTIME[3:0]
OFFTIME[2:0]
Figure 15. Beep Configuration Options
4.4.5
Tone Control
Shelving filters are used to implement bass and treble (boost and cut) with four selectable corner frequencies. Boosting will affect peak detect and limiting when levels exceed the maximum threshold settings.
Software
Controls:
4.4.6
“Tone Control (Address 15h)” on page 65.
Limiter
When enabled, the limiter monitors the digital input signal before the DAC modulator, detects when levels
exceed the maximum threshold settings and lowers the AOUT volume at a programmable attack rate below the maximum threshold. When the input signal level falls below the maximum threshold, the AOUT
volume returns to its original level set in the Volume Control register at a programmable release rate. Attack and release rates are affected by the DAC soft ramp/zero cross settings and sample rate, Fs. Limiter
soft ramp and zero cross dependency may be independently enabled/disabled.
Recommended settings: Best limiting performance may be realized with the fastest attack and slowest
release setting with soft ramp enabled in the control registers. The “cushion” bits allow the user to set a
threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the limiter attacks and releases.
Note:
1. When the Limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted
manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits.
2. The Limiter maintains the output signal between the CUSH and MAX thresholds. As the digital input
signal level changes, the level-controlled output may not always be the same but will always fall within
the thresholds.
Software
Controls:
36
“Limiter Release Rate Register (Address 1Ah)” on page 69, “Limiter Attack Rate Register (Address
1Bh)” on page 70, “DAC Control (Address 09h)” on page 58
DS679F1
CS42L51
Input
MAX[2:0]
Limiter
AOUTx_VOL[7:0] volume
control should NOT be
adjusted manually when
Limiter is enabled.
ATTACK/RELEASE SOUND
CUSHION
Volume
Output
(after Limiter)
CUSH[2:0]
MAX[2:0]
ARATE[5:0]
RRATE[5:0]
Figure 16. Peak Detect & Limiter
4.4.7
Line-Level Outputs and Filtering
The CODEC contains on-chip buffer amplifiers capable of producing line level single-ended outputs on
AOUTA and AOUTB. These amplifiers are ground centered and do not have any DC offset. A load stabilizer circuit, shown in the “Typical Connection Diagram (Software Mode)” on page 10 and the “Typical
Connection Diagram (Hardware Mode)” on page 11, is required on the analog outputs. This allows the
DAC amplifiers to drive line or headphone outputs.
Also shown in the Typical Connection diagrams is the recommended passive output filter to support higher impedances such as those found on the inputs to operational amplifiers. “Rext”, shown in the typical
connection diagrams, is the input impedance of the receiving device.
The invert and digital gain controls may be used to provide phase and/or amplitude compensation for an
external filter.
The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using
an off-chip low pass filter.
Software
Controls:
DS679F1
“DAC Output Control (Address 08h)” on page 57, “AOUTx Volume Control: AOUTA (Address 16h)
& AOUTB (Address 17h)” on page 66.
37
CS42L51
4.4.8
On-Chip Charge Pump
An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual
rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large,
DC-blocking capacitors. Added benefits include greater pop suppression and improved low frequency
(bass) response. Note: Series resistance in the path of the power supplies must be avoided. Any voltage
drop on the VA_HP supply will directly impact the derived negative voltage on the charge pump supply,
VSS_HP, and may result in clipping.
The FLYN and FLYP pins connect to internal switches that charges and discharges the external capacitor
attached, at a default switching frequency. This frequency may be adjusted in the control port registers.
Increasing the charge-pumping capacitor will slightly decease the pumping frequency. The capacitor connected to VSS_HP acts as a charge reservoir for the negative supply as well as a filter for the ripple induced by the charge pump. Increasing this capacitor will decrease the ripple on VSS_HP. Refer to the
typical connection diagrams in Figure 1 on page 10 or Figure 2 on page 11 for the recommended capacitor
values for the charge pump circuitry.
Software
Controls:
4.5
“Charge Pump Frequency (Address 21h)” on page 74.
Serial Port Clocking
The CODEC serial audio interface port operates either as a slave or master. It accepts externally generated
clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in
master mode.
The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate,
Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked
into or out of the device.
The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone control
pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in
Slave Mode. The value on the SDOUT pin is latched immediately after powering up in Hardware Mode.
Software
Control:
“MIC Power Control & Speed Control (Address 03h)” on page 50, “DAC Control
(Address 09h)” on page 58.
Pin
Hardware
Control:
“SDOUT, M/S” pin 29
“MCLKDIV2” pin 2
38
Setting
Selection
47 kΩ Pull-down
Slave
47 kΩ Pull-up
Master
LO
No Divide
HI
MCLK is divided by 2 prior
to all internal circuitry.
DS679F1
CS42L51
4.5.1
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the CODEC is automatically determined based
on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will
then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 standalone control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
Auto-Detect
QSM
HSM
SSM
DSM
Disabled
(Software
Mode only)
512, 768, 1024, 1536,
2048, 3072
256, 384, 512, 768,
1024, 1536
128, 192, 256, 384,
512, 768
128, 192, 256, 384
512, 768, 1024*, 1536*
256, 384, 512*, 768*
128, 192, 256*, 384*
1024, 1536, 2048*,
3072*
*MCLKDIV2 must be enabled.
Enabled
Table 3. MCLK/LRCK Ratios
4.5.2
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the CODEC operates in single-speed only. In Software Mode, the CODEC operates
in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
÷1
0
÷2
1
÷ 128
Double
Speed
00
÷ 128
Single
Speed
01
÷ 256
Half
Speed
10
÷ 512
Quarter
Speed
11
MCLK
LRCK Output
(Equal to Fs)
SPEED[1:0]
MCLKDIV2
÷2
Double
Speed
00
÷2
Single
Speed
01
÷4
Half
Speed
10
÷8
Quarter
Speed
11
SCLK Output
Figure 17. Master Mode Timing
DS679F1
39
CS42L51
4.5.3
High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-impedance state, allowing another device to transmit serial port data without bus contention.
CS42L51
Transmitting Device #2
Transmitting Device #1
SDOUT
3ST_SP
SCLK/LRCK
Receiving Device
Figure 18. Tri-State Serial Port
4.5.4
Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale
with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of
this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to
SSM.
4.6
Digital Interface Formats
The serial port operates in standard I²S, Left-Justified or Right-Justified (DAC only) digital interface formats
with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the rising edge of
SCLK. Figures 19-21 illustrate the general structure of each format. Refer to “Switching Specifications - Serial Port” on page 20 for exact timing relationship between clocks and data.
Software
Control:
“Interface Control (Address 04h)” on page 52.
Pin
Hardware
Control:
LRCK
“I²S/LJ” pin 3
Setting
Selection
LO
Left-Justified Interface
HI
I²S Interface
L eft C h a n n e l
R ig ht C h a n n el
SCLK
SDIN
MSB
LSB
MSB
AOUTA / AINxA
LSB
MSB
AOUTB / AINxB
Figure 19. I²S Format
40
DS679F1
CS42L51
LRCK
L eft C h a n n e l
R ig ht C h a n n e l
SCLK
SDIN
MSB
LS B
MSB
LSB
MSB
AOUTB / AINxB
AOUTA / AINxA
Figure 20. Left-Justified Format
LRCK
L eft C h a n n el
R ig ht C h a n n el
SCLK
MSB
SDIN
M SB
LSB
AOUTA
LS B
AOUTB
Figure 21. Right-Justified Format (DAC only)
4.7
Initialization
The initialization and Power-Down sequence flowchart is shown in Figure 22 on page 42. The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference, multi-bit DAC and ADC and
switched-capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The control port is accessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in “Software Mode” on page 43. If a valid write sequence to the control port is not made within approximately
10 ms, the CODEC will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, DAC_FILT+ and
ADC_FILT+ will begin powering up to normal operation. The charge pump slowly powers up and charges
the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK
period to determine the MCLK/LRCK frequency ratio and normal operation begins.
4.8
Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.
3. For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “standby”.
4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Start MCLK to the appropriate frequency, as discussed in Section 4.5.
6. Set the PDN bit to ‘0’b.
7. Apply LRCK,SCLK and SDIN for normal operation to begin.
8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
DS679F1
41
CS42L51
4.9
Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the CODEC in standby,
1. Mute the DAC’s and ADC’s.
2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches a
fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary
to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.
3. Bring RESET low.
No Power
1. No audio signal
generated.
Off Mode (Power Applied)
1. No audio signal generated.
2. Control Port Registers reset
to default.
PDN bit = '1'b?
Standby Mode
1. No audio signal generated.
2. Control Port Registers retain
settings.
Yes
No
No
RESET = Low?
Valid
MCLK Applied?
Yes
No
20 ms delay
Control Port
Active
Charge Caps
1. VQ Charged to
quiescent voltage.
2. Filtx+ Charged.
No
Control Port Valid
Write Seq. within
10 ms?
Yes
ADC Initialization
2048 internal
MCLK cycle delay
DAC Initialization
Digital/Analog
Output Muted
Charge Pump
Powered Up
50 ms delay
Headphone Amp
Powered Down
Hardware Mode
Minimal feature
set support.
Power Off Transition
1. Audible pops.
Software Mode
Registers setup to
desired settings.
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
20 µs delay
20 µs delay (DAC
only)
Headphone Amp
Powered Up
Stand-By
Transition
1. Pops suppressed.
No
Reset Transition
1. Pops suppressed.
Valid
MCLK/LRCK
Ratio?
Yes
RESET = Low
ERROR: MCLK/LRCK ratio change
ERROR: Power removed
Normal Operation
Audio signal generated per control port or standalone settings.
PDN bit set to '1'b
(software mode only)
ERROR: MCLK removed
Analog Output Freeze
1. Aout bias = last audio sample.
2. DAC Modulators stop operation.
3. Audible pops.
Figure 22. Initialization Flowchart
42
DS679F1
CS42L51
4.10
Software Mode
The control port is used to access the registers allowing the CODEC to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates in two modes: SPI and I²C, with the CODEC acting as a slave device. Software
Mode is selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought
high. I²C Mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently selecting the desired AD0 bit address state.
4.10.1 SPI Control
In Software Mode, CS is the CS42L51 chip-select signal, CCLK is the control port bit clock (input into the
CS42L51 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked
in on the rising edge of CCLK. The CODEC will only support write operations. Read request will be ignored.
Figure 23 shows the operation of the control port in Software Mode. To write to a register, bring CS low.
The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write
indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP.
There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment
after each byte is read or written, allowing block reads or writes of successive registers.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CCLK
CHIP ADDRESS (WRITE)
CDIN
1
0
0
1
0
1
0
MAP BYTE
0
INCR
6
5
4
3
DATA +n
DATA
2
1
0
7
6
1
0
7
6
1
0
Figure 23. Control Port Timing in SPI Mode
4.10.2 I²C Control
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected
through a resistor to VL or DGND as desired. The state of the pin is sensed while the CS42L51 is being
reset.
The signal timings for a read and write cycle are shown in Figure 24 and Figure 25. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42L51
after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write).
The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS42L51, the chip
address field, which is the first byte sent to the CS42L51, should match 100101 followed by the setting of
the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read,
DS679F1
43
CS42L51
the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP
allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge
bit. The ACK bit is output from the CS42L51 after each input byte is read and is input to the CS42L51 from
the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
24 25 26 27 28
19
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
0
1
AD0
MAP BYTE
0
INCR
6
5
4
3
1
0
ACK
7
6
1
ACK
DATA +n
DATA +1
DATA
2
0
7
6
1
0
7
6
1
ACK
0
ACK
STOP
START
Figure 24. Control Port Timing, I²C Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
STOP
MAP BYTE
0 1 AD0 0
INCR
6
5
4
3
2
1
0
ACK
CHIP ADDRESS (READ)
1
0
0
1
0
ACK
START
DATA
1 AD0 1
START
7
ACK
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 25. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 25, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100101x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100101x1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
44
DS679F1
CS42L51
4.10.3 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
4.10.3.1 Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
DS679F1
45
CS42L51
5. REGISTER QUICK REFERENCE
Software mode register defaults are as shown. “Reserved” registers must maintain their default state.
Addr
01h
Function
ID
p 49
default
02h
Power Ctl. 1
p 49
default
03h
Speed Ctl. &
Power Ctl. 2
p 50
default
04h
Interface Ctl.
p 52
default
05h
MIC Control
& Misc.
p 53
default
06h
ADC Control
p 54
default
07h
ADC Input
Select
, Invert, Mute
7
6
5
4
3
2
1
0
Chip_ID4
Chip_ID3
Chip_ID2
Chip_ID1
Chip_ID0
Rev_ID2
Rev_ID1
Rev_ID0
1
1
0
1
1
0
0
1
PDN_ADCB
PDN_ADCA
PDN
Reserved
PDN_DACB PDN_DACA dPDN_PGAB PDN_PGAA
0
0
0
0
0
0
0
0
AUTO
SPEED1
SPEED0
3-ST_SP
PDN_MICB
PDN_MICA
PDN_
MICBIAS
MCLKDIV2
1
0
1
0
1
1
1
0
SDOUT->SDIN
M/S
DAC_DIF2
DAC_DIF1
DAC_DIF0
ADC_I²S/LJ
DIGMIX
MICMIX
0
0
0
0
0
0
0
0
ADC_SNGVOL
ADCB_
DBOOST
ADCA_
DBOOST
MICBIAS_
SEL
MICBIAS_
LVL1
MICBIAS_
LVL0
MICB_
BOOST
MICA_
BOOST
0
0
0
0
0
0
0
0
ADCB_HPF
EN
ADCB_HP
FRZ
ADCA_HPF
EN
ADCA_HP
FRZ
SOFTB
ZCROSSB
SOFTA
ZCROSSA
1
0
1
0
0
0
0
0
INV_ADCB
INV_ADCA
ADCB_
MUTE
ADCA_
MUTE
AINB_MUX1
AINB_MUX AINA_MUX1 AINA_MUX0
0
0
0
0
0
0
0
0
0
HP_GAIN2
HP_GAIN1
HP_GAIN0
DAC_SNG
VOL
INV_PCMB
INV_PCMA
DACB_
MUTE
DACA_
MUTE
0
1
1
0
0
0
0
0
DATA_SEL1
DATA_SEL0
FREEZE
Reserved
DEEMPH
AMUTE
DAC_SZC1
DAC_SZC0
0
0
0
0
0
1
1
0
ALCA_SR
DIS
ALCA_ZC
DIS
Reserved
PGAA
VOL4
PGAA
VOL3
PGAA
VOL2
PGAA
VOL1
PGAA
VOL0
0
0
0
0
0
0
0
0
ALCB_SR
DIS
ALCB_ZC
DIS
Reserved
PGAB
VOL4
PGAB
VOL3
PGAB
VOL2
PGAB
VOL1
PGAB
VOL0
p 59
default
0
0
0
0
0
0
0
0
0Ch ADCA Attenuator
ADCA_
ATT7
ADCA_
ATT6
ADCA_
ATT5
ADCA_
ATT4
ADCA_
ATT3
ADCA_
ATT2
ADCA_
ATT1
ADCA_
ATT0
p 60
default
0
0
0
0
0
0
0
0
0Dh ADCB Attenuator
ADCB_
ATT7
ADCB_
ATT6
ADCB_
ATT5
ADCB_
ATT4
ADCB_
ATT3
ADCB_
ATT2
ADCB_
ATT1
ADCB_
ATT0
p 56
default
08h
DAC Output
Control
p 57
default
09h
DAC Control
p 58
default
0Ah
ALCA SZC &
PGAA Volume
p 59
default
0Bh
46
ALCB SZC &
PGAB Volume
DS679F1
CS42L51
Addr
Function
p 60
default
0Eh
Vol. Control
ADCMIXA
p 61
default
0Fh
Vol. Control
ADCMIXB
p 61
default
10h
Vol. Control
PCMMIXA
p 62
default
11h
Vol. Control
PCMMIXB
p 62
default
12h
BEEP Freq. &
OnTime
p 62
default
13h
BEEP Off
Time & Vol.
p 63
default
14h
BEEP Control & Tone
Config
p 64
default
15h
Tone Control
p 65
default
16h
Vol. Control
AOUTA
p 66
default
17h
Vol. Control
AOUTB
p 66
default
18h
PCM & ADC
Channel
Mixer
p 67
default
19h
Limiter
Threshold &
SZC Disable
p 67
default
DS679F1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MUTE_ADC
MIXA
ADCMIXA
VOL6
ADCMIXA
VOL5
ADCMIXA
VOL4
ADCMIXA
VOL3
ADCMIXA
VOL2
ADCMIXA
VOL1
ADCMIXA
VOL0
1
0
0
0
0
0
0
0
MUTE_ADC
MIXB
ADCMIXB
VOL6
ADCMIXB
VOL5
ADCMIXB
VOL4
ADCMIXB
VOL3
ADCMIXB
VOL2
ADCMIXB
VOL1
ADCMIXB
VOL0
1
0
0
0
0
0
0
0
MUTE_PCM
MIXA
PCMMIXA
VOL6
PCMMIXA
VOL5
PCMMIXA
VOL4
PCMMIXA
VOL3
PCMMIXA
VOL2
PCMMIXA
VOL1
PCMMIXA
VOL0
1
0
0
0
0
0
0
0
MUTE_PCM
MIXB
PCMMIXB
VOL6
PCMMIXB
VOL5
PCMMIXB
VOL4
PCMMIXB
VOL3
PCMMIXB
VOL2
PCMMIXB
VOL1
PCMMIXB
VOL0
1
0
0
0
0
0
0
0
FREQ3
FREQ2
FREQ1
FREQ0
ONTIME3
ONTIME2
ONTIME1
ONTIME0
0
0
0
0
0
0
0
0
OFFTIME2
OFFTIME1
OFFTIME0
BPVOL4
BPVOL3
BPVOL2
BPVOL1
BPVOL0
0
0
0
0
0
0
0
0
REPEAT
BEEP
Reserved
TREB_CF1
TREB_CF0
BASS_CF1
BASS_CF0
TC_EN
0
0
0
0
0
0
0
0
TREB3
TREB2
TREB1
TREB0
BASS3
BASS2
BASS1
BASS0
1
0
0
0
1
0
0
0
AOUTA_
VOL7
AOUTA_
VOL6
AOUTA_
VOL5
AOUTA_
VOL4
AOUTA_
VOL3
AOUTA_
VOL2
AOUTA_
VOL1
AOUTA_
VOL0
0
0
0
0
0
0
0
0
AOUTB_
VOL7
AOUTB_
VOL6
AOUTB_
VOL5
AOUTB_
VOL4
AOUTB_
VOL3
AOUTB_
VOL2
AOUTB_
VOL1
AOUTB_
VOL0
0
0
0
0
0
0
0
0
PCMA1
PCMA0
PCMB1
PCMB0
ADCA1
ADCA0
ADCB1
ADCB0
0
0
0
0
0
0
0
0
MAX2
MAX1
MAX0
CUSH2
CUSH1
CUSH0
LIM_SRDIS
LIM_ZCDIS
0
0
0
0
0
0
0
0
47
CS42L51
Addr
Function
7
6
5
4
3
2
1
0
1Ah
Limiter Config & Release
Rate
LIMIT_EN
LIMIT_ALL
LIM_RRATE
5
LIM_RRATE
4
LIM_RRATE
3
LIM_RRATE
2
LIM_RRATE
1
LIM_RRATE
0
0
1
1
1
1
1
1
1
Reserved
Reserved
p 70
default
0
0
1Ch ALC Enable
& Attack Rate
ALC_ENB
ALC_ENA
p 70
default
0
0
1Dh ALC Release
Rate
Reserved
Reserved
p 71
default
0
0
1
1
1
1
1
1
MAX2
MAX1
MAX0
MIN2
MIN1
MIN0
Reserved
Reserved
0
0
0
0
0
0
0
0
NG_ALL
NG_EN
NG_BOOST
THRESH2
THRESH1
THRESH0
NGDELAY1
NGDELAY0
p 72
default
0
0
0
0
0
0
0
0
Status
Reserved
p 73
default
0
0
0
0
0
0
0
0
CHRG_
FREQ3
CHRG_
FREQ2
CHRG_
FREQ1
CHRG_
FREQ0
Reserved
Reserved
Reserved
Reserved
0
1
0
1
0
0
0
0
p 69
default
1Bh
1Eh
Limiter Attack
Rate
ALC Threshold
p 71
default
1Fh
20h
21h
Noise Gate
Config
Charge Pump
Frequency
p 74
default
48
LIM_ARATE5 LIM_ARATE4 LIM_ARATE3 LIM_ARATE2 LIM_ARATE1 LIM_ARATE0
0
0
0
0
0
0
ALC_ARATE AALC_RATE ALC_ARATE ALC_ARATE ALC_ARATE ALC_ARATE
5
4
3
2
1
0
0
0
0
0
0
0
ALC_RRATE ALC_RRATE ALC_RRATE ALC_RRATE ALC_RRATE ALC_RRATE
5
4
3
2
1
0
SP_CLKER SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL
R
DS679F1
CS42L51
6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description.
All “Reserved” registers must maintain their default state.
Note:
Certain functions are only available when the “Signal Processing Engine to DAC” option is selected using
the DATA_SEL[1:0] bits, as described in section “DAC Data Selection (DATA_SEL[1:0])” on page 58.
6.1
Chip I.D. and Revision Register (Address 01h) (Read Only)
7
Chip_ID4
6
Chip_ID3
5
Chip_ID2
4
Chip_ID1
3
Chip_ID0
2
Rev_ID2
1
Rev_ID1
0
Rev_ID0
Chip I.D. (Chip_ID[4:0])
Default: 11011
Function:
I.D. code for the CS42L51. Permanently set to 11011.
Chip Revision (Rev_ID[2:0])
Default: 001
Function:
CS42L51 revision level. Revision B is coded as 001. Revision A is coded as 000.
6.2
Power Control 1 (Address 02h)
7
Reserved
6
PDN_DACB
5
PDN_DACA
4
PDN_PGAB
3
PDN_PGAA
2
PDN_ADCB
1
PDN_ADCA
0
PDN
Notes:
1. To activate the power-down sequence for individual channels (A or B,) both channels must first be powered down either by enabling the PDN bit or by enabling the power-down bits for both channels. Enabling the power-down bit on an individual channel basis after the CODEC has fully powered up will
mute the selected channel without achieving any power savings.
Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the select channels, 3.) disable the PDN bit.
Power Down DAC X (PDN_DACX)
Default: 0
0 - Disable
1 - Enable
Function:
DAC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 above.
DS679F1
49
CS42L51
Power Down PGA X (PDN_PGAX)
Default: 0
0 - Disable
1 - Enable
Function:
PGA channel x will either enter a power-down or muted state when this bit is enabled. See Power Control
1 (Address 02h) on page 49 above.
This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to
“ADCX Input Select Bits (AINX_MUX[1:0])” on page 56 for the required settings.
Power Down ADC X (PDN_ADCX)
Default: 0
0 - Disable
1 - Enable
Function:
ADC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 on page
49.
Power Down (PDN)
Default: 0
0 - Disable
1 - Enable
Function:
The entire CODEC will enter a low-power state when this function is enabled. The contents of the control
port registers are retained in this mode.
6.3
MIC Power Control & Speed Control (Address 03h)
7
AUTO
6
SPEED1
5
SPEED0
4
3-ST_SP
3
PDN_MICB
2
PDN_MICA
1
PDN_MICBIAS
0
MCLKDIV2
Auto-Detect Speed Mode (AUTO)
Default: 1
0 - Disable
1 - Enable
Function:
Enables the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a slave.
When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 39. The
SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
50
DS679F1
CS42L51
Speed Mode (SPEED[1:0])
Default: 01
11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates
10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates
01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates
00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates
Function:
Sets the appropriate speed mode for the CODEC in Master or Slave Mode. QSM is optimized for 8 kHz sample rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled
(see Auto-Detect Speed Mode (AUTO) above).
Tri-State Serial Port Interface (3ST_SP)
Default: 0
0 - Disable
1 - Enable
Function:
When enabled and the device is configured as a master, all serial port outputs are place in a high impedance
state. If the serial port is configured as a slave, only the SDOUT pin will be placed in a high-impedance state.
The other signals will remain as inputs.
Power Down MIC X (PDN_MICX)
Default: 1
0 - Disable
1 - Enable
Function:
When enabled, the microphone pre-amplifier for channel x will be in a power-down state.
Power Down MIC BIAS (PDN_MICBIAS)
Default: 1
0 - Disable
1 - Enable
Function:
When enabled, the microphone bias circuit will be in a power-down state.
MCLK Divide By 2 (MCLKDIV2)
Default: 0
0 - Disabled
1 - Divide by 2
Function:
Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled
in Slave Mode.
DS679F1
51
CS42L51
6.4
Interface Control (Address 04h)
7
SDOUT->SDIN
6
M/S
5
DAC_DIF2
4
DAC_DIF1
3
DAC_DIF0
2
ADC_I²S/LJ
1
DIGMIX
0
MICMIX
SDOUT to SDIN Loopback (SDOUT->SDIN)
Default: 0
0 - Disabled; SDOUT internally disconnected from SDIN
1 - Enabled; SDOUT internally connected to SDIN
Function:
Internally loops the signal on the SDOUT pin to SDIN.
Master/Slave Mode (M/S)
Default: 0
0 - Slave
1 - Master
Function:
Selects either master or slave operation for the serial port.
DAC Digital Interface Format (DAC_DIF[2:0])
Default = 000
DAC_DIF[2:0]
000
001
010
011
100
101
110
100
Description
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 24-bit data
Right-Justified, 20-bit data
Right-Justified, 18-bit data
Right-Justified, 16-bit data
Reserved
Reserved
Figure
20 on page 41
19 on page 40
21 on page 41
21 on page 41
21 on page 41
21 on page 41
-
Function:
Selects the digital interface format used for the data in on SDIN. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are
detailed in the section “Digital Interface Formats” on page 40.
52
DS679F1
CS42L51
ADC I²S or Left-Justified (ADC_I²S/LJ)
Default: 0
0 - Left-Justified
1 - I²S
Function:
Selects either the I²S or Left-Justified digital interface format for the data on SDOUT. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and
the options are detailed in this section .
Digital Mix (DIGMIX)
Default: 0
DIGMIX
0
DATA_SEL[1:0]
xx
00
01
10
11
1
Mix Selected
No Mix: ADC to ADC serial port, SDOUT data.
No Mix: SDIN data to ADC serial port, SDOUT data.
Mix: ADC + SDIN data to ADC serial port, SDOUT data.
No Mix: ADC to ADC serial port, SDOUT data.
Reserved
Function:
Selects between the ADC or a digital mix of the ADC and DAC into the serial port to the SDOUT pin. This
mix function is affected by the data select bits DATA_SEL[1:0].
Microphone Mix (MICMIX)
Default: 0
0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT.
1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT.
Function:
Selects between the ADC stereo mix or a differential mix of analog inputs A and B.
6.5
MIC Control (Address 05h)
7
ADC_SNGVOL
6
5
4
3
2
ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL MICBIAS_LVL1 MICBIAS_LVL0
1
0
MICB_BOOST MICA_BOOST
ADC Single Volume Control (ADC_SNGVOL)
Default: 0
0 - Disabled
1 - Enabled
Function:
The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels as well as
the ALC A and B enable (ALC_ENx) are independently controlled by their respective control registers when
this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator
Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are
ignored. The ALC enable control for channel B is controlled by the ALC A enable when the ADC_SNGVOL
bit is enabled and the ALC_ENB control register is ignored.
DS679F1
53
CS42L51
ADCx 20 dB Digital Boost (ADCx_DBOOST)
Default: 0
0 - Disabled
1 - Enabled
Function:
Applies a 20 dB digital gain to the input signal on ADC channel x, regardless of the input path.
MIC Bias Select (MICBIAS_SEL)
Default: 0
0 - MICBIAS on AIN3B/MICIN2 pin
1 - MICBIAS on AIN2B pin
Function:
Determines the output pin for the internally generated MICBIAS signal. If set to ‘0’b, the MICBIAS is output
on the AIN3B/MICIN2 pin. If set to ‘1’b, the MICBIAS is output on the AIN2B pin.
MIC Bias Level (MICBIAS_LVL[1:0])
Default: 00
00 - 0.8 x VA
01 - 0.7 x VA
10 - 0.6 x VA
11 - 0.5 x VA
Function:
Determines the output voltage level of the MICBIAS output.
MIC X Preamplifier Boost (MICX_BOOST)
Default: 0
0 - +16 dB Gain
1 - +32 dB Gain
Function:
Determines the amount of gain applied to the microphone preamplifier for channel x.
6.6
ADC Control (Address 06h)
7
6
5
4
ADCB_HPFEN ADCB_HPFRZ ADCA_HPFEN ADCA_HPFRZ
3
SOFTB
2
ZCROSSB
1
SOFTA
0
ZCROSSA
ADCX High-Pass Filter Enable (ADCX_HPFEN)
Default: 1
0 - High-pass filter is disabled
1 - High-pass filter is enabled
Function:
When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to ‘0’, the high-pass filter
will be disabled. For DC measurements, this bit must be cleared to ‘0’. See “ADC Digital Filter Characteristics” on page 15.
54
DS679F1
CS42L51
ADCX High-Pass Filter Freeze (ADCX_HPFRZ)
Default: 0
0 - Continuous DC Subtraction
1 - Frozen DC Subtraction
Function:
The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the
decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current value of the DC
offset is frozen, and this DC offset will continue to be subtracted from the conversion result. For DC measurements, this bit must be set to ‘1’. See “ADC Digital Filter Characteristics” on page 15.
Soft Ramp CHX Control (SOFTX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Soft Ramp allows level changes to be implemented via an incremental ramp. ADCx_ATT[7:0] digital attenuation changes are ramped from the current level to the new level at a rate of 0.125 dB per LRCK period.
PGAx_VOL[4:0] gain changes are ramped in 0.5 dB steps every 16 LRCK periods.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the ZCROSSx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB
steps and be implemented on a signal zero crossing.
Zero Cross CHX Control (ZCROSSX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Zero Cross Enable dictates that signal level changes will occur on a signal zero crossing to minimize audible
artifacts. The requested level change will occur after a timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function
is independently monitored and implemented for each channel.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the SOFTx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps
and be implemented on a signal zero crossing.
The ADC Attenuator ADCx_ATT[7:0] is not affected by the ZCROSSx bit.
DS679F1
SOFTx
ZCROSSx
Analog PGA Volume
(PGAx_VOL[4:0])
Digital Attenuator (ADCx_ATT[7:0])
0
0
Volume changes immediately.
Volume changes immediately.
0
1
Volume changes at next zero cross time.
Volume changes immediately.
1
0
Volume changes in 0.5 dB steps.
Change volume in 0.125 dB steps.
1
1
Volume changes in 0.5 dB steps at every
signal zero-cross.
Change volume in 0.125 dB steps.
55
CS42L51
6.7
ADCx Input Select, Invert & Mute (Address 07h)
7
AINB_MUX1
6
AINB_MUX0
5
AINA_MUX1
4
AINA_MUX0
3
INV_ADCB
2
INV_ADCA
1
0
ADCB_MUTE ADCA_MUTE
ADCX Input Select Bits (AINX_MUX[1:0])
Default: 00
PDN_PGAx
AINx_MUX[1:0]
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
Selected Path to ADC
AIN1x-->PGAx
AIN2x-->PGAx
AIN3x/MICINx-->PGAx
AIN3x/MICINx-->Pre-Amp(+16/+32 dB Gain)-->PGAx
AIN1x
AIN2x
AIN3x/MICINx
Reserved
Function:
Selects the specified analog input signal into ADCx. The microphone pre-amplifier is only available when
PDN_PGAx is disabled. See Figure 26.
AIN1x
AIN2x
AIN3x
AIN1x
AIN2x
AIN3x / MICINx
MUX
MUX
ADC
PGA
+16/
32 dB
Decoder
AINx_MUX[1:0]
PDN_PGAx
Figure 26. AIN & PGA Selection
ADCX Invert Signal Polarity (INV_ADCX)
Default: 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will invert the signal polarity of the ADC x channel.
ADCX Channel Mute (ADCX_MUTE)
Default: 0
0 - Disabled
1 - Enabled
Function:
The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit
(SOFT).
56
DS679F1
CS42L51
6.8
DAC Output Control (Address 08h)
7
6
5
HP_GAIN2
HP_GAIN1
HP_GAIN0
4
DAC_
SNGVOL
3
2
INV_PCMB
INV_PCMA
1
0
DACB_MUTE DACA_MUTE
Headphone Analog Gain (HP_GAIN[2:0])
Default: 011
HP_GAIN[2:0]
Gain Setting
000
001
010
011
100
101
110
111
0.3959
0.4571
0.5111
0.6047
0.7099
0.8399
1.0000
1.1430
Function:
These bits select the gain multiplier for the headphone/line outputs. See “Line Output Voltage Characteristics” on page 18 and “Headphone Output Power Characteristics” on page 19.
DAC Single Volume Control (DAC_SNGVOL)
Default: 0
Function:
The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the AOUTA Volume Control register and the AOUTB Volume Control register is ignored.
PCMX Invert Signal Polarity (INV_PCMX)
Default: 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will invert the signal polarity of the PCM x channel.
DACX Channel Mute (DACX_MUTE)
Default: 0
0 - Disabled
1 - Enabled
Function:
The output of channel x DAC will mute when enabled. The muting function is affected by the DACx Soft and
Zero Cross bits (DACx_SZC[1:0]).
DS679F1
57
CS42L51
6.9
DAC Control (Address 09h)
7
DATA_SEL1
6
DATA_SEL0
5
FREEZE
4
Reserved
3
DEEMPH
2
AMUTE
1
DAC_SZC1
0
DAC_SZC0
DAC Data Selection (DATA_SEL[1:0])
Default: 00
00 - PCM Serial Port to DAC
01 - Signal Processing Engine to DAC
10 - ADC Serial Port to DAC
11 - Reserved
Function:
Selects the digital signal source for the DAC. Note: Certain functions are only available when the “Signal
Processing Engine to DAC” option is selected using these bits.
Freeze Controls (FREEZE)
Default: 0
Function:
This function will freeze the previous settings of, and allow modifications to be made to all control port registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then
disable the FREEZE bit.
DAC De-Emphasis Control (DEEMPH)
Default: 0
0 - No De-Emphasis
1 - De-Emphasis Enabled
Function:
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control.
Enables the digital filter to apply the standard 15µs/50µs digital de-emphasis filter response for a sample
rate of 44.1 kHz.
Analog Output Auto MUTE (AMUTE)
Default: 0
0 - Auto Mute Disabled
1 - Auto Mute Enabled
Function:
Enables (or disables) Automatic Mute of the analog outputs after 8192 “0” samples on each digital input
channel.
58
DS679F1
CS42L51
DAC Soft Ramp and Zero Cross Control (DAC_SZC[1:0])
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control
Immediate Change
When Immediate Change is selected all volume-level changes will take effect immediately in one step.
Zero Cross
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the
signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored.
Soft Ramp
Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented
by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4
left/right clock periods.
Soft Ramp on Zero Crossing
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if
the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored.
6.10
ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)
7
6
ALCX_SRDIS ALCX_ZCDIS
5
Reserved
4
PGAX_VOL4
3
PGAX_VOL3
2
PGAX_VOL2
1
PGAX_VOL1
0
PGAX_VOL0
ALCX Soft Ramp Disable (ALCX_SRDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be
dictated by the soft ramp setting. ALC volume-level changes will take effect in one step.
DS679F1
59
CS42L51
ALCX Zero Cross Disable (ALCX_ZCDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not
be dictated by the zero cross setting. ALC volume-level changes will take effect immediately in one step.
PGA X Gain Control (PGAX_VOL[4:0])
Default: 00000
Binary Code
Volume Setting
11000
···
01010
···
00000
11111
11110
···
11001
11010
+12 dB
···
+5 dB
···
0 dB
-0.5 dB
-1 dB
···
-3 dB
-3 dB
Function:
The PGAx Gain Control register allows independent setting of the signal levels in 0.5 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from +12 dB to -3 dB. Gain settings are
decoded as shown in the table above. The gain changes are implemented as dictated by the ALCX Soft &
Zero Cross bits (ALCX_SZC). Levels are decoded as described in the table above.
Note:
6.11
When the ALC is enabled, the PGA is automatically controlled and should not be adjusted manually.
ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh)
7
ADCx_ATT7
6
ADCx_ATT6
5
ADCx_ATT5
4
ADCx_ATT4
3
ADCx_ATT3
2
ADCx_ATT2
1
ADCx_ATT1
0
ADCx_ATT0
ADCX Attenuation Control (ADCX_ATT[7:0])
Default: 00h
60
Binary Code
Volume Setting
0111 1111
···
0000 0000
1111 1111
1111 1110
···
1010 0000
···
1000 0000
0 dB
···
0 dB
-1 dB
-2 dB
···
-96 dB
···
-96 dB
DS679F1
CS42L51
Function:
The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits
(SOFTx & ZCROSSx) from 0 to -96 dB. Levels are decoded in two’s complement, as shown in the table
above.
Note:
6.12
When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should
not be adjusted manually.
ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)
7
6
5
4
3
2
1
0
MUTE_ADCMIXx ADCMIXx_VOL6 ADCMIXx_VOL5 ADCMIXx_VOL4 ADCMIXx_VOL3 ADCMIXx_VOL2 ADCMIXx_VOL1 ADCMIXx_VOL0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
ADCX Mixer Channel Mute (MUTE_ADCMIXX)
Default: 1
0 - Disabled
1 - Enabled
Function:
The ADC channel X input to the output mixer will mute when enabled. The muting function is affected by
the DACX Soft and Zero Cross bits (DACX_SZC[1:0]).
ADCX Mixer Volume Control (ADCMIXX_VOL[6:0])
Default = 000 0000
Binary Code
Volume Setting
001 1000
···
000 0000
111 1111
111 1110
···
001 1001
+12.0 dB
···
0 dB
-0.5 dB
-1.0 dB
···
-51.5 dB
Function:
The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the
DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in
the table above.
DS679F1
61
CS42L51
6.13
PCMX Mixer Volume Control:
PCMA (Address 10h) & PCMB (Address 11h)
7
MUTE_
PCMMIXx
6
PCMMIXx_
VOL6
5
PCMMIXx_
VOL5
4
PCMMIXx_
VOL4
3
PCMMIXx_
VOL3
2
PCMMIXx_
VOL2
1
PCMMIXx_
VOL1
0
PCMMIXx_
VOL0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
PCMX Mixer Channel Mute (MUTE_PCMMIXX)
Default = 1
0 - Disabled
1 - Enabled
Function:
The PCM channel X input to the output mixer will mute when enabled. The muting function is affected by
the DACX Soft and Zero Cross bits (DACX_SZC[1:0]).
PCMX Mixer Volume Control (PCMMIXX_VOL[6:0])
Default: 000 0000
Binary Code
Volume Setting
001 1000
···
000 0000
111 1111
111 1110
···
001 1001
+12.0 dB
···
0 dB
-0.5 dB
-1.0 dB
···
-51.5 dB
Function:
The level of the PCMX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the
DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as described
in the table above.
6.14
Beep Frequency & Timing Configuration (Address 12h)
7
FREQ3
6
FREQ2
5
FREQ1
4
FREQ0
3
ONTIME3
2
ONTIME2
1
ONTIME1
0
ONTIME0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Beep Frequency (FREQ[3:0])
Default: 0000
FREQ[3:0]
0000
0001
0010
0011
0100
62
Frequency
Pitch
Fs = 12, 24, 48 or 96
kHz
260.87 Hz
521.74 Hz
585.37 Hz
666.67 Hz
705.88 Hz
C4
C5
D5
E5
F5
DS679F1
CS42L51
FREQ[3:0]
Frequency
Pitch
Fs = 12, 24, 48 or 96
kHz
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
774.19 Hz
888.89 Hz
1000.00 Hz
1043.48 Hz
1200.00 Hz
1333.33 Hz
1411.76 Hz
1600.00 Hz
1714.29 Hz
2000.00 Hz
2181.82 Hz
G5
A5
B5
C6
D6
E6
F6
G6
A6
B6
C7
Function:
The frequency of the beep signal can be adjusted from 260.87 Hz to 2181.82 Hz. Beep frequency will scale
directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 15 on
page 36 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits.
Beep On Time Duration (ONTIME[3:0])
Default: 0000
TIME[3:0]
On Time
Fs = 12, 24, 48 or 96 kHz
0000
···
1111
86 ms
···
5.2 s
Function:
The on-duration of the beep signal can be adjusted from approximately 86 ms to 5.2 s. The on-duration will
scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure
15 on page 36 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits.
6.15
Beep Off Time & Volume (Address 13h)
7
OFFTIME2
6
OFFTIME1
5
OFFTIME0
4
BPVOL4
3
BPVOL3
2
BPVOL2
1
BPVOL1
0
BPVOL0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Beep Off Time (OFFTIME[2:0])
Default: 000
DS679F1
OFFTIME[2:0]
Off Time
Fs = 12, 24, 48 or
96 kHz
000
001
010
011
100
101
1.23 s
2.58 s
3.90 s
5.20 s
6.60 s
8.05 s
63
CS42L51
OFFTIME[2:0]
Off Time
Fs = 12, 24, 48 or
96 kHz
110
111
9.35 s
10.80 s
Function:
The off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. The off-duration
will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to
Figure 15 on page 36 for single-, multiple- and continuous-beep configurations using the REPEAT and
BEEP bits.
Beep Volume (BPVOL[4:0])
Default: 00000
Binary Code
Volume Setting
00110
···
00000
11111
11110
···
00111
+12.0 dB
···
0 dB
-2 dB
-4 dB
···
-50 dB
Function:
The level of the beep into the output mixer can be adjusted in 2.0 dB increments from +12 dB to -50 dB.
Refer to Figure 15 on page 36 for single-, multiple- and continuous-beep configurations using the REPEAT
and BEEP bits. Levels are decoded as described in the table above.
6.16
Beep Configuration & Tone Configuration (Address 14h)
7
REPEAT
6
BEEP
5
Reserved
4
TREB_CF1
3
TREB_CF0
2
BASS_CF1
1
BASS_CF0
0
TC_EN
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Repeat Beep (REPEAT)
Default: 0
0 - Disabled
1 - Enabled
Function:
This bit is used in conjunction with the BEEP bit to mix a continuous or periodic beep with the analog output.
Refer to Figure 15 on page 36 for a description of each configuration option.
Beep (BEEP)
Default: 0
0 - Disabled
1 - Enabled
Function:
64
DS679F1
CS42L51
This bit is used in conjunction with the REPEAT bit to mix a continuous or periodic beep with the analog
output. Note: Re-engaging the beep before it has completed its initial cycle will cause the beep signal to
remain ON for the maximum ONTIME duration. Refer to Figure 15 on page 36 for a description of each configuration option.
Treble Corner Frequency (TREB_CF[1:0])
Default: 00
00 - 5 kHz
01 - 7 kHz
10 - 10 kHz
11 - 15 kHz
Function:
The treble corner frequency is user selectable as shown above.
Bass Corner Frequency (BASS_CF[1:0])
Default: 00
00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - 250 Hz
Function:
The bass corner frequency is user-selectable as shown above.
Tone Control Enable (TC_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass and Treble tone control features are active when this bit is enabled.
6.17
Tone Control (Address 15h)
7
TREB3
6
TREB2
5
TREB1
4
TREB0
3
BASS3
2
BASS2
1
BASS1
0
BASS0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Treble Gain Level (TREB[3:0])
Default: 1000 dB (No Treble Gain)
DS679F1
Binary Code
Gain Setting
0000
···
0111
1000
1001
···
1111
+12.0 dB
···
+1.5 dB
0 dB
-1.5 dB
···
-10.5 dB
65
CS42L51
Function:
The level of the shelving treble gain filter is set by Treble Gain Level. The level can be adjusted in 1.5 dB
increments from +12.0 to -10.5 dB.
Bass Gain Level (BASS[3:0])
Default: 1000 dB (No Bass Gain)
Binary Code
Gain Setting
0000
···
0111
1000
1001
···
1111
+12.0 dB
···
+1.5 dB
0 dB
-1.5 dB
···
-10.5 dB
Function:
The level of the shelving bass gain filter is set by Bass Gain Level. The level can be adjusted in 1.5 dB increments from +10.5 to -10.5 dB.
6.18
AOUTx Volume Control:
AOUTA (Address 16h) & AOUTB (Address 17h)
7
6
5
4
3
2
1
0
AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
AOUTX Volume Control (AOUTX_VOL[7:0])
Default = 00h
Binary Code
Volume Setting
0001 1000
···
0000 0000
1111 1111
1111 1110
···
0011 0100
···
0001 1001
+12.0 dB
···
0 dB
-0.5 dB
-1.0 dB
···
-102 dB
···
-102 dB
Function:
The analog output levels can be adjusted in 0.5 dB increments from +12 to -102 dB as dictated by the DAC
Soft and Zero Cross bits (DACX_SZC[1:0]). Levels are decoded in unsigned binary as described in the table
above.
Note:
66
When the limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be achieved using the PCMMIXx_VOL[6:0] bits.
DS679F1
CS42L51
6.19
PCM Channel Mixer (Address 18h)
7
PCMA1
6
PCMA0
5
PCMB1
4
PCMB0
3
ADCA1
2
ADCA0
1
ADCB1
0
ADCB0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Channel Mixer (PCMx[1:0] & ADCx[1:0])
Default: 00
AOUTA PCMB[1:0] and/or AOUTB
ADCB[1:0]
PCMA[1:0]
and/or
ADCA[1:0]
00
L
01
00
L+R
-----------2
10
11
R
01
10
11
R
L+R
-----------2
L
Function:
Implements mono mixes of the left and right channels as well as a left/right channel swap.
6.20
Limiter Threshold SZC Disable (Address 19h)
7
MAX2
6
MAX1
5
MAX0
4
CUSH2
3
CUSH1
2
CUSH0
1
LIM_SRDIS
0
LIM_ZCDIS
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Maximum Threshold (MAX[2:0])
Default: 000
MAX[2:0] Threshold
Setting
(dB)
000
0
001
-3
010
-6
011
-9
101
-12
101
-18
110
-24
111
-30
Function:
Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack rate.
Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an
attack.
DS679F1
67
CS42L51
Cushion Threshold (CUSH[2:0])
Default: 000
CUSH[2:0] Threshold
Setting
(dB)
000
0
001
-3
010
-6
011
-9
101
-12
101
-18
110
-24
111
-30
Function:
Sets a cushion level below full scale. This setting is usually set slightly below the maximum (MAX[2:0])
threshold. The Limiter uses this cushion as a hysteresis point for the input signal as it maintains the signal
below the maximum as well as below the cushion setting. This provides a more natural sound as the limiter
attacks and releases.
Limiter Soft Ramp Disable (LIM_SRDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated
by the soft ramp setting. Note: This bit is ignored when the zero-cross function is enabled (i.e. when
DAC_SZC[1:0] = ‘01’b or ‘11’b.)
Limiter Zero Cross Disable (LIM_ZCDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated
by the zero-cross setting.
68
DS679F1
CS42L51
6.21
Limiter Release Rate Register (Address 1Ah)
7
LIMIT_EN
6
LIMIT_ALL
5
RRATE5
4
RRATE4
3
RRATE3
2
RRATE2
1
RRATE1
0
RRATE0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Peak Detect and Limiter Enable (LIMIT_EN)
Default: 0
0 - Disabled
1 - Enabled
Function:
Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting
is performed by digital attenuation. Note: When the limiter is enabled, the AOUT Volume is automatically
controlled and should not be adjusted manually. Alternative volume control may be realized using the
PCMMIXx_VOL[6:0] bits.
Peak Signal Limit All Channels (LIMIT_ALL)
Default: 1
0 - Individual Channel
1 - Both channel A & B
Function:
When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the specific channel indicating clipping. The other channels will not be affected.
When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both
channels in response to any single channel indicating clipping.
Limiter RELEASE Rate (RRATE[5:0])
Default: 111111
Binary Code
Release Time
000000
···
111111
Fastest Release
···
Slowest Release
Function:
Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in
the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting.
The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
DS679F1
69
CS42L51
6.22
Limiter Attack Rate Register (Address 1Bh)
7
Reserved
6
Reserved
5
ARATE5
4
ARATE4
3
ARATE3
2
ARATE2
1
ARATE1
0
ARATE0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Limiter Attack Rate (ARATE[5:0])
Default: 000000
Binary Code
Attack Time
000000
···
111111
Fastest Attack
···
Slowest Attack
Function:
Sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the
limiter threshold register.
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
6.23
ALC Enable & Attack Rate (Address 1Ch)
7
ALC_ENB
6
ALC_ENA
5
4
3
2
1
0
ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0
ALC Enable (ALC_ENX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Enables automatic level control for ADC channel x.
Note:
When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should
not be adjusted manually.
ALC Attack Rate (ARATE[5:0])
Default: 000000
Binary Code
Attack Time
000000
···
111111
Fastest Attack
···
Slowest Attack
Function:
Sets the rate at which the ALC attenuates the analog input from levels above the maximum setting in the
ALC threshold register.
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the SOFTx
& ZCROSSx bit settings unless the disable bit for each function is enabled.
70
DS679F1
CS42L51
6.24
ALC Release Rate (Address 1Dh)
7
Reserved
6
Reserved
5
4
3
2
1
0
ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0
ALC Release Rate (RRATE[5:0])
Default: 111111
Binary Code
Release Time
000000
···
111111
Fastest Release
···
Slowest Release
Function:
Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting
in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting.
The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and the SOFTx
& ZCROSS bit settings unless the disable bit for each function is enabled.
6.25
ALC Threshold (Address 1Eh)
7
MAX2
6
MAX1
5
MAX0
4
MIN2
3
MIN1
2
MIN0
1
Reserved
0
Reserved
Maximum Threshold (MAX[2:0])
Default: 000
MAX[2:0]
Threshold
Setting
(dB)
000
0
001
-3
010
-6
011
-9
100
-12
101
-18
110
-24
111
-30
Function:
Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack
rate.
Minimum Threshold (MIN[2:0])
Default: 000
MIN[2:0]
DS679F1
Threshold
Setting
(dB)
000
0
001
-3
010
-6
71
CS42L51
MIN[2:0]
Threshold
Setting
(dB)
011
-9
100
-12
101
-18
110
-24
111
-30
Function:
Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at a rate set
in the release rate register until levels again reach this minimum threshold. The ALC uses this minimum as
a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the
minimum setting. This provides a more natural sound as the ALC attacks and releases.
6.26
Noise Gate Configuration & Misc. (Address 1Fh)
7
NG_ALL
6
NG_EN
5
NG_BOOST
4
THRESH2
3
THRESH1
2
THRESH0
1
NGDELAY1
0
NGDELAY0
Noise Gate Channel Gang (NG_ALL)
Default: 0
0 - Disabled
1 - Enabled
Function:
Gangs the noise gate function for channel A and B. When enabled, both channels must fall below the threshold setting for the noise gate attenuation to take effect.
Noise Gate Enable (NG_EN)
Default: 0
0 - Disabled
1 - Enabled
Function:
Enables the noise gate. Maximum attenuation is relative to all gain settings applied.
Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])
Default: 000
72
THRESH[2:0]
Minimum Setting
(NG_BOOST = ‘0’b)
Minimum Setting
(NG_BOOST = ‘1’b)
000
001
010
011
100
101
110
111
-64 dB
-67 dB
-70 dB
-73 dB
-76 dB
-82 dB
Reserved
Reserved
-34 dB
-37 dB
-40 dB
-43 dB
-46 dB
-52 dB
-58 dB
-64 dB
DS679F1
CS42L51
Function:
Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96
dB. NG_BOOST = ‘1’b adds 30 dB to the threshold settings.
Noise Gate Delay Timing (NGDELAY[1:0])
Default: 00
00 - 50 ms
01 - 100 ms
10 - 150 ms
11 - 200 ms
Function:
Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx &
ZCROSS bit settings unless the disable bit for each function is enabled.
6.27
Status (Address 20h) (Read Only)
7
Reserved
6
SP_CLKERR
5
SPEA_OVFL
4
SPEB_OVFL
3
2
PCMA_OVFL PCMB_OVFL
1
ADCA_OVFL
0
ADCB_OVFL
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A ”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: 0
Function:
Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” on page 38 for valid clock ratios.
Note:
On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
Signal Processing Engine Overflow (SPEX_OVFL)
Default: 0
Function:
Indicates a digital overflow condition within the data path after the signal processing engine.
PCMX Overflow (PCMX_OVFL)
Default: 0
Function:
Indicates a digital overflow condition within the data path of the PCM mix.
ADC Overflow (ADCX_OVFL)
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS42L51 ADC signal path of each of the
associated ADC’s.
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CS42L51
6.28
Charge Pump Frequency (Address 21h)
7
6
5
4
CHRG_FREQ CHRG_FREQ CHRG_FREQ CHRG_FREQ
3
2
1
0
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Charge Pump Frequency (CHRG_FREQ[3:0])
Default: 0101
N
CHRG_FREQ[3:0]
0
...
15
0000
...
1111
Frequency
64xFs
----------------N+2
Function:
Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs,
should the switching frequency interfere with other system frequencies such as those in the AM radio band.
Note:
74
Distortion performance may be affected.
DS679F1
CS42L51
7. ANALOG PERFORMANCE PLOTS
7.1
Headphone THD+N versus Output Power Plots
Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48 kHz. Plots were taken from the CDB42L51 using an Audio Precision analyzer.
-10
G = 0.6047
-15
VA_HP = VA = 1.8 V
G = 0.7099
-20
G = 0.8399
-25
-30
G = 1.0000
-35
G = 1.1430
-40
Legend
-45
d
B
r
A
-50
NOTE: Graph shows the output power per channel (i.e.
Output Power = 23 mW into
single 16 Ω and 46 mW into
stereo 16 Ω with THD+N = 75 dB).
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
0
10m
20m
30m
40m
50m
60m
70m
80m
W
Figure 27. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load)
-10
-15
G = 0.6047
VA_HP = VA = 2.5 V
G = 0.7099
-20
-25
G = 0.8399
-30
G = 1.0000
-35
G = 1.1430
-40
Legend
-45
d
B
r
A
NOTE: Graph shows the output power per channel (i.e.
Output Power = 44 mW into
single 16 Ω and 88 mW into
stereo 16 Ω with THD+N = 75 dB).
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
0
10m
20m
30m
40m
50m
60m
70m
80m
W
Figure 28. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load)
DS679F1
75
CS42L51
G = 0.6047
VA_HP = VA = 1.8
G = 0.7099
-20
-30
G = 0.8399
-35
G = 1.0000
-40
G = 1.1430
-45
Legend
-50
NOTE: Graph shows the output power per channel (i.e.
Output Power = 22 mW into
single 32 Ω and 44 mW into
stereo 32 Ω with THD+N = 75 dB).
-55
d
B
r
-60
A
-65
-70
-75
-80
-85
-90
-95
-100
0
6m
12m
18m
24m
30m
36m
42m
48m
54m
60m
W
Figure 29. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load)
G = 0.6047
-20
VA_HP = VA = 2.5 V
-25
G = 0.7099
-30
G = 0.8399
-35
G = 1.0000
-40
G = 1.1430
-45
Legend
-50
-55
d
B
r
NOTE: Graph shows the output power per channel (i.e.
Output Power = 42 mW into
single 32 Ω and 84 mW into
stereo 32 Ω with THD+N = 75 dB).
-60
A
-65
-70
-75
-80
-85
-90
-95
-100
0
5m
10m
15m
20m
25m
30m
35m
40m
45m
50m
55m
60m
W
Figure 30. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load)
76
DS679F1
CS42L51
7.2
Headphone Amplifier Efficiency
The architecture of the headphone amplifier is that of typical class AB amplifiers. Test conditions (unless
otherwise specified): Input test signal is a 997 Hz sine wave; Power Consumption Mode 6 - Stereo Playback
w/16 Ω load. HP_GAIN = 1.1430. Best efficiency is realized when the amplifier outputs maximum power.
VA_HP = VA = 1.8 V
Figure 31. Power Dissipation vs. Output Power into Stereo 16 Ω
VA_HP = VA = 1.8 V
Figure 32. Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail)
DS679F1
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CS42L51
7.3
ADC_FILT+ Capacitor Effects on THD+N
The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion +
noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N
at low frequencies. Figure 33 shows the THD+N versus frequency for the ADC analog input. Plots were taken from the CDB42L51 using an Audio Precision analyzer.
-60
1 µF
-64
-68
10 µF
-72
22 µF
Legend –
Capacitor Value on ADC_FILT+
-76
d
B
F
S
-80
-84
-88
-92
-96
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 33. ADC THD+N vs. Frequency w/Capacitor Effects
78
DS679F1
CS42L51
8. EXAMPLE SYSTEM CLOCK FREQUENCIES
8.1
Auto Detect Enabled
Sample Rate
LRCK (kHz)
1024x
MCLK (MHz)
1536x
2048x*
8
11.025
12
3072x*
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
24.5760
33.8688
36.8640
Sample Rate
LRCK (kHz)
512x
MCLK (MHz)
768x
1024x*
16
22.05
24
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
16.3840
22.5792
24.5760
Sample Rate
LRCK (kHz)
MCLK (MHz)
384x
512x*
256x
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
Sample Rate
LRCK (kHz)
128x
192x
64
88.2
96
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
MCLK (MHz)
256x*
16.3840
22.5792
24.5760
1536x*
24.5760
33.8688
36.8640
768x*
24.5760
33.8688
36.8640
384x*
24.5760
33.8688
36.8640
*The”MCLKDIV2” pin 4 must be set HI.
DS679F1
79
CS42L51
8.2
80
Auto Detect Disabled
Sample Rate
LRCK (kHz)
512x
8
11.025
12
6.1440
768x
MCLK (MHz)
1024x
1536x
2048x
3072x
6.1440
8.4672
9.2160
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Sample Rate
LRCK (kHz)
256x
384x
512x
16
22.05
24
6.1440
6.1440
8.4672
9.2160
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
MCLK (MHz)
768x
12.2880
16.9344
18.4320
Sample Rate
LRCK (kHz)
256x
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
Sample Rate
LRCK (kHz)
128x
192x
64
88.2
96
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
1024x
1536x
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
MCLK (MHz)
384x
512x
16.3840
22.5792
24.5760
MCLK (MHz)
256x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
384x
24.5760
33.8688
36.8640
DS679F1
CS42L51
9. PCB LAYOUT CONSIDERATIONS
9.1
Power Supply, Grounding
As with any high-resolution converter, the CS42L51 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 1 on page 10 shows the recommended
power arrangements, with VA and VA_HP connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via
a ferrite bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS42L51 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS42L51 to minimize inductance effects. All signals, especially clocks, should be
kept away from the DAC_FILT+/ADC_FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The DAC_FILT+/ADC_FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from DAC_FILT+/ADC_FILT+ and AGND. The CDB42L51 evaluation
board demonstrates the optimum layout and power supply arrangements.
9.2
QFN Thermal Pad
The CS42L51 is available in a compact QFN package. The under side of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS42L51 evaluation board demonstrates the optimum thermal pad and via configuration.
DS679F1
81
CS42L51
10.ADC & DAC DIGITAL FILTERS
82
Figure 34. ADC Passband Ripple
Figure 35. ADC Stopband Rejection
Figure 36. ADC Transition Band
Figure 37. ADC Transition Band Detail
Figure 38. DAC Passband Ripple
Figure 39. DAC Stopband
Figure 40. DAC Transition Band
Figure 41. DAC Transition Band (Detail)
DS679F1
CS42L51
11.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
DS679F1
83
CS42L51
12.PACKAGE DIMENSIONS
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
e
b
D
Pin #1 Corner
Pin #1 Corner
E2
E
A1
L
D2
A
Top View
DIM
MIN
A
A1
b
D
D2
E
E2
e
L
-0.0000
0.0071
0.1280
0.1280
0.0118
Bottom View
Side View
INCHES
NOM
--0.0091
0.1969 BSC
0.1299
0.1969 BSC
0.1299
0.0197 BSC
0.0157
MAX
MIN
0.0394
0.0020
0.0110
-0.00
0.18
0.1319
3.25
0.1319
3.25
0.0197
0.30
MILLIMETERS
NOM
--0.23
5.00 BSC
3.30
5.00 BSC
3.30
0.50 BSC
0.40
NOTE
MAX
1.00
0.05
0.28
3.35
3.35
0.50
1
1
1,2
1
1
1
1
1
1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance
84
2 Layer Board
4 Layer Board
Symbol
Min
Typ
Max
Units
θJA
-
52
38
-
°C/Watt
DS679F1
CS42L51
13.ORDERING INFORMATION
Product
CS42L51
CDB42L51
CRD42L51
Description
Low-Power Stereo
CODEC w/HP Amp for
Portable Apps
CS42L51 Evaluation
Board
CS42L51 Reference
Design
Package Pb-Free
Grade
Temp Range
Commercial -10 to +70° C
32L-QFN
Yes
Automotive
-40 to +85° C
Container
Order #
Rail
CS42L51-CNZ
Tape & Reel CS42L51-CNZR
Rail
CS42L51-DNZ
Tape & Reel CS42L51-DNZR
-
No
-
-
-
CDB42L51
-
No
-
-
-
CRD42L51
14.REFERENCES
1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,
Version 6.0, February 1998.
2. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter
Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the
Audio Engineering Society, September 1997.
3. Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention
of the Audio Engineering Society, November 1988.
4. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and
on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989.
5. Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society,
October 1989.
6. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven
Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.
7. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
8. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000.
http://www.semiconductors.philips.com
DS679F1
85
CS42L51
15.REVISION HISTORY
Revision
86
Changes
A1
Initial Release
A2
Renamed pin 14, FILT1+, to DAC_FILT+ and pin 16, FILT2+, to ADC_FILT+.
Added 1.5 µF capacitor recommendation to figure “Typical Connection Diagram (Software Mode)” on page 10.
Removed the 0.1µF capacitors from pins DAC_FILT+, ADC_FILT+ and VQ on the figures “Typical Connection
Diagram (Software Mode)” on page 10 and “Typical Connection Diagram (Hardware Mode)” on page 11.
Added DAC Isolation specification to “Analog Input Characteristics (Commercial - CNZ)” on page 13 and “Analog
Input Characteristics (Automotive - DNZ)” on page 14.
Corrected specification table “Headphone Output Power Characteristics” on page 19.
Removed td timing specification from table in section “Switching Specifications - Serial Port” on page 20.
Added ts(SDO-SK) and th(SK-SDO) timing specification to table in section “Switching Specifications - Serial Port” on
page 20.
Adjusted timing specifications ts(SD-SK) from 0 ns to 20 ns and th from 50 ns to 20 ns in table in section “Switching
Specifications - Serial Port” on page 20.
Added MIC Bias PSRR specification to “DC Electrical Characteristics” on page 24.
Adjusted specification table “Power Consumption” on page 25.
Removed QSM clock ratios 128, 192, 256, 384 and HSM ratios 128, 192 from Table 3 on page 39.
Modified Digital Mix description in section “Digital Mix (DIGMIX)” on page 53.
Corrected DAC Zero Cross timeout period in section “Zero Cross” on page 59.
Adjusted BEEP off time settings in section “Beep Off Time (OFFTIME[2:0])” on page 63.
Modified BEEP description in section “Beep (BEEP)” on page 64.
Adjusted the minimum settings for the “Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])” on
page 72.
Swapped bits PCMA_OVFL w/PCMB_OVFL and ADCA_OVFL w/ADCB_OVFL in register “Status (Address 20h)
(Read Only)” on page 73.
Corrected Charge Pump Frequency setting in section “Charge Pump Frequency (CHRG_FREQ[3:0])” on
page 74.
Added sections “Headphone THD+N versus Output Power Plots” on page 75 and “ADC_FILT+ Capacitor Effects
on THD+N” on page 78.
DS679F1
CS42L51
Revision
Changes
PP1
Adjusted the minimum voltage specification in “Specified Operating Conditions” section on page 12.
Adjusted Ambient Operating Temp. specification in “Absolute Maximum Ratings” section on page 12.
Adjusted maximum “Analog In to PGA to ADC” THD+N performance specification in “Analog Input Characteristics (Commercial - CNZ)” on page 13.
Added Offset Error specification to “Analog Input Characteristics (Commercial - CNZ)” on page 13 and “Analog
Input Characteristics (Automotive - DNZ)” on page 14.
Corrected Interchannel Gain Mismatch specification in “Analog Input Characteristics (Commercial - CNZ)” on
page 13 and “Analog Input Characteristics (Automotive - DNZ)” on page 14.
Adjusted ADC full scale input voltage specification in “Analog Input Characteristics (Commercial - CNZ)” on
page 13 and “Analog Input Characteristics (Automotive - DNZ)” on page 14.
Corrected Group Delay characteristic in table in section “ADC Digital Filter Characteristics” on page 15.
Adjusted maximum “RL = 10kΩ” THD+N performance specification in “Analog Output Characteristics (Commercial - CNZ)” on page 16 and “Analog Output Characteristics (Automotive - DNZ)” on page 17.
Corrected Group Delay characteristic in table in section “Combined DAC Interpolation & on-Chip Analog FIlter
Response” on page 20.
Adjusted timing specifications td(MSB) from 40 ns to 52 ns and ts(SDO-SK) from 30 ns to 20 ns in table in section
“Switching Specifications - Serial Port” on page 20.
Adjusted I²C timing specification tack from 1000 ns to 3450 ns in table in section “” on page 21.
Adjusted High-Level Input Voltage specifications VIH from 0.65VL to 0.68VL and VIL from 0.35VL to 0.32VL in
table in section “Digital Interface Specifications & Characteristics” on page 24.
Adjusted the +20 dB Digital Boost block before the ALC feedback path in Figure 8 on page 28.
Modified ALC Recommended Settings in section “Automatic Level Control (ALC)” on page 32.
Modified step 2 of the “Recommended Power-Down Sequence” on page 42.
Corrected default values for ALC and Limiter Release Rates shown in “Register Quick Reference” on page 46.
Corrected default value for the DAC_SZC bits and Added AMUTE bit and description in “DAC Control (Address
09h)” on page 58.
Added section “Headphone Amplifier Efficiency” on page 77.
Corrected ADC Filter Response shown in Figures 34, 35, 36, and 37 on page 82.
Corrected ADC_SNGVOL description in “MIC Control (Address 05h)” on page 53.
F1
DS679F1
Final Release
87
CS42L51
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
88
DS679F1

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