LTC3875 Dual, 2-Phase, Synchronous Controller with Low Value DCR Sensing and Temperature Compensation DESCRIPTION FEATURES n n n n n n n n n n n n n n n n n Low Value DCR Current Sensing Programmable DCR Temperature Compensation ±0.5% 0.6V Output Voltage Accuracy Dual True Remote Sensing Differential Amplifiers Optional Fast Transient Operation Phase-Lockable Fixed Frequency 250kHz to 720kHz Dual, 180° Phased Controllers Reduce Required Input Capacitance and Power Supply Induced Noise Dual N-Channel MOSFET Synchronous Drive Wide VIN Range: 4.5V to 38V Operation Output Voltage Range with Low DCR: 0.6V to 3.5V, without Low DCR: 0.6V to 5V Adjustable Soft-Start Current Ramping or Tracking Foldback Output Current Limiting Clock Input and Output for Up to 12-Phase Operation Short-Circuit Soft Recovery Output Overvoltage Protection Power Good Output Voltage Monitor 40-Lead QFN Packages APPLICATIONS n n n Servers and Instruments Telecom Systems DC Power Distribution Systems The LTC®3875 is a dual output current mode synchronous step-down DC/DC controller that drives all N-channel synchronous power MOSFET stages. It employs a unique architecture which enhances the signal-to-noise ratio of the current sense signal, allowing the use of very low DC resistance power inductors to maximize the efficiency in high current applications. This feature also reduces the switching jitter commonly found in low DCR applications. The LTC3875 features two high speed remote sense differential amplifiers, programmable current sense limits from 10mV to 30mV and DCR temperature compensation to limit the maximum output current precisely over temperature. A unique thermal balancing function adjusts per phase current in order to minimize the thermal stress for multichip single output applications. The LTC3875 also features a precise 0.6V reference with guaranteed accuracy of ±0.5% that provides an accurate output voltage from 0.6V to 3.5V. A 4.5V to 38V input voltage range allows it to support a wide variety of bus voltages. The LTC3875 is available in a low profile 40-lead 6mm × 6mm (0.5mm pitch) and 40-lead 5mm × 5mm (0.4mm pitch) QFN packages. L, LT, LTC, LTM, Linear Technology, the Linear logo OPTI-LOOP, Burst Mode and PolyPhase are registered trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. TYPICAL APPLICATION High Efficiency Dual Phase 1.2V/60A Step-Down Converter (OPTIONAL) THERMAL SENSOR VOUT + 470µF 2.5V ×2 SP VIN INTVCC PHASMD CLKOUT PGOOD RUN1,2 IFAST ILIM ENTMPB MODE/PLLIN TG2 TG1 BOOST1 (OPTIONAL) 100 THERMAL SENSOR SW1 LTC3875 SW2 EXTVCC BG2 BG1 TAVG PGND TRSET1 TRSET2 SNSA1+ SNSA2+ SNS1– SNS2– SNSD1+ SNSD2+ TCOMP1 TCOMP2 VOSNS1+ FREQ VOSNS1– VOSNS2+ – ITH1 V VOUT 1.2V 60A OSNS2 TK/SS1 TK/SS2 ITH2 1500pF 122k 15k 20k + 470µF 2.5V ×2 SP 3875 TA01a For more information www.linear.com/LTC3875 12 10 90 8 85 6 80 75 20k 14 12VIN 1.8VO ~400kHz CCM 95 0.3µH (0.32mΩ DCR) BOOST2 0.1µF Efficiency and Power Loss vs Load Current 70 0 10 4 0.32mΩ 1.5mΩ 2 0.32mΩ PLOSS 1.5mΩ PLOSS 0 20 30 40 50 60 LOAD CURRENT (A) POWER LOSS (W) 0.3µH (0.32mΩ DCR) VIN 22µF 6V TO 14V 16V ×4 EFFICIENCY (%) INTVCC 4.7µF 3875 TA01b 3875fb 1 LTC3875 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (VIN).......................... 40V to –0.3V Topside Driver Voltages (BOOST1, BOOST2).................................... 46V to –0.3V Switch Voltage (SW1, SW2)........................... 40V to –5V INTVCC, RUN(s), PGOOD, EXTVCC (BOOST-SW1), (BOOST2-SW2).................... 6V to –0.3V SNSA+(s), SNSD+(s), SNS– (s) Voltages................................... INTVCC to –0.3V MODE/PLLIN, ILIM, FREQ, IFAST, ENTMPB VOSNS(s)+, VOSNS(s)– Voltages................ INTVCC to –0.3V ITH1, ITH2, PHASMD, TRSET1, TRSET2, TCOMP1, TCOMP2, TAVG Voltages........ INTVCC to –0.3V INTVCC Peak Output Current.................................100mA Operating Junction Temperature Range (Notes 2, 3)............................................. –40°C to 125°C Storage Temperature Range................... –65°C to 125°C PIN CONFIGURATION 40 39 38 37 36 35 34 33 32 31 CLKOUT PHASMD MODE/PLLIN RUN1 ILIM TRSET1 TCOMP1/ITEMP1 SNSD1+ 40 39 38 37 36 35 34 33 32 31 TK/SS1 1 30 SW1 TK/SS1 1 30 SW1 VOSNS1+ 2 29 TG1 VOSNS1+ 2 29 TG1 VOSNS1– 3 28 BOOST1 VOSNS1– 3 28 BOOST1 25 INTVCC VOSNS2+ 6 24 EXTVCC VOSNS2– 7 TK/SS2 8 23 BG2 TK/SS2 8 SNSA2+ 9 22 BOOST2 SNSA2+ 9 21 TG2 23 BG2 22 BOOST2 SNS2– 10 21 TG2 SW2 PGOOD ENTMPB IFAST SNSD2+ 11 12 13 14 15 16 17 18 19 20 SW2 PGOOD ENTMPB IFAST RUN2 FREQ TRSET2 TAVG TCOMP2/ITEMP2 25 INTVCC 24 EXTVCC 11 12 13 14 15 16 17 18 19 20 SNSD2+ 26 VIN 41 SGND/PGND RUN2 SNS2– 10 27 BG1 FREQ VOSNS2– 7 26 VIN ITH2 5 TRSET2 41 SGND/PGND VOSNS2+ 6 ITH1 4 TAVG ITH2 5 27 BG1 TCOMP2/ITEMP2 ITH1 4 2 SNS1– SNSA1+ CLKOUT PHASMD TOP VIEW MODE/PLLIN RUN1 ILIM TRSET1 TCOMP1/ITEMP1 SNSD1+ SNS1– SNSA1+ TOP VIEW UJ PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN UH PACKAGE 40-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 33°C/W, θJC = 2.0°C/W EXPOSED PAD (PIN 41) IS SGND/PGND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 44°C/W, θJC = 7.3°C/W EXPOSED PAD (PIN 41) IS SGND/PGND, MUST BE SOLDERED TO PCB 3875fb For more information www.linear.com/LTC3875 LTC3875 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3875EUH#PBF LTC3875EUH#TRPBF 3875 40-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C LTC3875IUH#PBF LTC3875IUH#TRPBF 3875 40-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C LTC3875EUJ#PBF LTC3875EUJ#TRPBF LTC3875 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LTC3875IUJ#PBF LTC3875IUJ#TRPBF LTC3875 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN1,2 = 5V unless otherwise noted. SYMBOL PARAMETER Main Control Loops Input Voltage Range VIN Output Voltage Range VOUT VOSNS1,2+ IOSNS1,2+ VREFLNREG VLOADREG Regulated VOUT Feedback Voltage Including Diffamp Error Feedback Current Reference Voltage Line Regulation Output Voltage Load Regulation Transconductance Amplifier gm gm1,2 Thermal Functions Thermal Sensor Current ITCOMP1,2 Internal Thermal Shutdown TSHDN Internal TS Hysteresis THYS Fast Transient Functions Fast Transient Program Current IFAST Current Sensing Functions AC Sense Pins Bias Current ISENSE(AC) DC Sense Pins Bias Current ISENSE(DC) Total Sense Gain to Current Comp AVT(SNS) CONDITIONS SNSD+ Pin to VOUT SNSD+ Pin to GND (Note 4); ITH1,2 Voltage = 1.2V, –40°C to 85°C (Note 4); ITH1,2 Voltage = 1.2V,–40°C to 125°C (Note 4) VIN = 4.5V to 38V (Note 4) (Note 4) Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ∆ITH Voltage = 1.2V to 1.6V ITH1,2 = 1.2V; Sink/Source 5µA (Note 4) MIN MAX 4.5 38 0.6 3.5 0.6 5 0.597 0.600 0.603 l 0.5965 0.600 0.6045 –30 –100 0.002 0.005 l l UNITS V V V V V nA %/V 0.01 –0.01 2.2 0.1 –0.1 29 30 160 10 31 µA °C °C 9 10 11 µA ±0.5 ±30 5 ±2 ±50 µA nA V/V l l (Note 8) (Note 8) Each Channel; VSNSA+(S) = 3.3V Each Channel; VSNSD+(S) = 3.3V TYP % % mmho 3875fb For more information www.linear.com/LTC3875 3 LTC3875 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN1,2 = 5V unless otherwise noted. SYMBOL VSENSE(MAX)(DC) PARAMETER CONDITIONS Maximum Current Sense Threshold 0°C to 85°C with SNSD+ Pin to VOUT VSNS–(s) = 1.2V, ILIM = 0V VSNS–(s) = 1.2V, ILIM = 1/4 INTVCC VSNS–(s) = 1.2V, ILIM = 1/2 INTVCC VSNS–(s) = 1.2V, ILIM = 3/4 INTVCC VSNS–(s) = 1.2V, ILIM = INTVCC –40°C to 125°C VSNS–(s) = 1.2V, ILIM = 0V VSNS–(s) = 1.2V, ILIM = 1/4 INTVCC VSNS–(s) = 1.2V, ILIM = 1/2 INTVCC VSNS–(s) = 1.2V, ILIM = 3/4 INTVCC VSNS–(s) = 1.2V, ILIM = INTVCC VSENSE(MAX)(NODE) Maximum Current Sense Threshold VSNS–(s) = 1.2V, ILIM = 0V with SNSD+ Pin to GND VSNS–(s) = 1.2V, ILIM = 1/4 INTVCC VSNS–(s) = 1.2V, ILIM = 1/2 INTVCC VSNS–(s) = 1.2V, ILIM = 3/4 INTVCC VSNS–(s) = 1.2V, ILIM = INTVCC Channel-to-Channel Current ILIM = Float, ENTMPB = Float IMISMATCH Mismatch (Thermal Balance Disabled) Input DC Supply Current (Note 5) IQ Normal Mode VIN = 15V (without EXTVCC Enabled) Shutdown VRUN1,2 = 0V UVLO Undervoltage Lockout VINTVCC Ramping Down UVLO Hyst UVLO Hysteresis Feedback Overvoltage Lockout Measured at VOSNS1,2+ VOVL Soft-Start Charge Current VTK/SS1,2 = 0V ITK/SS1,2 RUN Pin On Threshold VRUN1, VRUN2 Rising VRUN1,2 RUN Pin On Hysteresis VRUN1,2HYS Driver Functions TG Transition Time (Note 6) Rise Time CLOAD = 3300pF TG1,2 tr Fall Time TG1,2 tf CLOAD = 3300pF BG Transition Time (Note 6) Rise Time CLOAD = 3300pF BG1,2 tr Fall Time BG1,2 tf CLOAD = 3300pF Top Gate Off to Bottom Gate On CLOAD = 3300pF Each Driver TG/BG t1D Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On CLOAD = 3300pF Each Driver BG/TG t2D Delay Synchronous Switch-On Delay Time Minimum On-Time (Note 7) tON(MIN) 4 l l l l l l l l l l MIN TYP MAX UNITS 9 14 19 23.5 28.5 10 15 20 25 30 11 16 21 26.5 31.5 mV mV mV mV mV 8.5 13.5 17.5 22 26.5 45 70 95 117.5 142.5 10 15 20 25 30 50 75 100 125 150 11.5 16.5 22.5 28 33.5 55 80 105 132.5 157.5 5 mV mV mV mV mV mV mV mV mV mV % 7 40 3.7 0.5 0.645 1.25 1.22 80 10 60 4.0 mA µA V V V µA V mV 3.5 l l l 0.625 1.0 1.1 0.665 1.5 1.35 25 25 ns ns 25 25 30 ns ns ns 30 ns 90 ns 3875fb For more information www.linear.com/LTC3875 LTC3875 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN1,2 = 5V unless otherwise noted. SYMBOL PARAMETER INTVCC Linear Regulator Internal VCC Voltage VINTVCC INTVCC Load Regulation VLDO INT EXTVCC Switchover Voltage VEXTVCC EXTVCC Voltage Drop VLDO EXT EXTVCC Hysteresis VLDOHYS Oscillator and Phase-Locked Loop Nominal Frequency fNOM Lowest Frequency fLOW Highest Frequency fHIGH MODE/PLLIN Input Resistance RMODE/PLLIN Frequency Setting Current IFREQ CLKOUT Phase (Relative to Controller 1) CLK High CLK Low VPGL IPGOOD VPG On-Chip Driver TG RUP TG RDOWN BG RUP BG RDOWN CONDITIONS MIN TYP MAX 6V < VIN < 38V ICC = 0mA to 20mA EXTVCC Ramping Positive ICC = 20mA, VEXTVCC = 5.5V 5.3 5.5 0.5 4.7 50 200 5.7 2.0 VFREQ = 1.2V VFREQ = 0V VFREQ ≥ 2.4V 4.5 450 220 650 9.5 PHASMD = GND PHASMD = FLOAT PHASMD = INTVCC VINTVCC = 5.5V Clock Output High Voltage Clock Output Low Voltage PGOOD Voltage Low IPGOOD = 2mA PGOOD Leakage Current VPGOOD = 5.5V PGOOD Trip Level, Either Controller VOSNS+ with Respect to Set Output Voltage VOSNS+ Ramping Negative VOSNS+ Ramping Positive TG Pull-Up RDS(ON) TG Pull-Down RDS(ON) BG Pull-Up RDS(ON) BG Pull-Down RDS(ON) l TG High TG Low BG High BG Low Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3875 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3875E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3875I is guaranteed over the full –40° to 125° operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. 4.5 UNITS V % V mV mV 100 500 250 720 250 10 60 90 120 5.5 550 270 790 10.5 0.1 0.2 0.3 ±2 kHz kHz kHz kΩ µA Deg Deg Deg V V V µA –7.5 7.5 % % 2.6 1.5 2.4 1.1 Ω Ω Ω Ω Note 3: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the formula: TJ = TA + (PD • θJA°C/W) where θJA = 44°C/W for the 5mm × 5mm QFN and θJA = 33°C/W for the 6mm × 6mm QFN. Note 4: The LTC3875 is tested in a feedback loop that servos VITH1,2 to a specified voltage and measures the resultant VOSNS1,2+. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 8: Guaranteed by design. 3875fb For more information www.linear.com/LTC3875 5 LTC3875 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Output Current and Mode (Figure 16 Application Circuit) 100 90 80 100 Burst Mode OPERATION 80 EFFICIENCY (%) 60 CCM 50 PULSE-SKIPPING 40 30 20 70 Burst Mode OPERATION 60 IL1, IL2 10A/DIV CCM 50 PULSESKIPPING 40 30 VOUT 100mV/DIV AC-COUPLED 20 VIN = 12V VOUT = 1.5V 10 0 0.01 ILOAD 40A/DIV 5A TO 30A 90 70 EFFICIENCY (%) Load Step (Figure 16 Application Circuit) (Burst Mode Operation) Efficiency vs Output Current and Mode (Figure 16 Application Circuit) 0.1 1 10 LOAD CURRENT (A) 0 0.01 100 0.1 1 10 LOAD CURRENT (A) 3875 G01 3875 G03 100 Load Step (Figure 16 Application Circuit) (Pulse-Skipping Mode) ILOAD 40A/DIV 5A TO 30A ILOAD 40A/DIV 5A TO 30A IL1, IL2 10A/DIV IL1, IL2 10A/DIV VOUT 100mV/DIV AC-COUPLED VOUT 100mV/DIV AC-COUPLED 10µs/DIV 10µs/DIV 3875 G02 Load Step (Figure 16 Application Circuit) (Forced Continuous Mode) VIN = 12V VOUT = 1.5V VIN = 12V VOUT = 1.5V VIN = 12V VOUT = 1V 10 VOUT 1V/DIV VOSNS+ 500mV/DIV TK/SS 500mV/DIV VIN = 12V VOUT = 1.5V 3875 G04 Prebiased Output at 1V 10µs/DIV VIN = 12V VOUT = 1.5V CCM: NO LOAD 3875 G05 Tracking Up and Down with External Ramp Coincident Tracking 2.5ms/DIV 3875 G06 Quiescent Current vs Temperature without EXTVCC 10.0 TK/SS1 TK/SS2 2V/DIV 9.5 9.0 SUPPLY CURRENT (mA) RUN 2V/DIV VOUT2 VOUT1 VOUT1 VOUT2 1V/DIV VOUT1 VOUT1 VOUT2 500mV/DIV VOUT2 VIN = 12V 2.5ms/DIV VOUT1 = 1.5V, RLOAD = 12Ω, CCM VOUT2 = 1V, RLOAD = 6Ω, CCM 3875 G07 VIN = 12V 10ms/DIV VOUT1 = 1V, 1Ω LOAD VOUT2 = 1.5V, 1.5Ω LOAD 3875 G08 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 3875 G09 6 3875fb For more information www.linear.com/LTC3875 LTC3875 TYPICAL PERFORMANCE CHARACTERISTICS Current Sense Threshold vs ITH Voltage 40 CURRENT SENSE THRESHOLD (mV) 6 INTVCC VOLTAGE (V) 5 4 3 2 1 0 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 35 ILIM = 0 ILIM = 1/4 INTVCC ILIM = 1/2 INTVCC ILIM = 3/4 INTVCC ILIM = INTVCC 35 30 25 20 15 10 5 0 –5 –10 40 Maximum Current Sense Threshold vs Common Mode Voltage CURRENT SENSE THRESHOLD (mV) INTVCC Line Regulation 0.5 0 3875 G10 1.30 ILIM = GND 10 5 0.1 0.4 0.3 0.5 0.2 FEEDBACK VOLTAGE (V) 0.6 1.25 1.20 1.15 1.10 4 ON 1.20 1.15 OFF 1.10 1.05 1.00 –50 1.00 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 0 50 100 TEMPERATURE (°C) Regulated Feedback Voltage vs Temperature 150 4320 G01 3875 G14 3875 G13 Oscillator Frequency vs Temperature 0.6045 900 0.6035 800 0.6025 700 0.6015 0.6005 0.5995 0.5985 VFREQ = 1.22V 500 400 VFREQ = GND 300 200 0.5965 100 10 30 50 70 90 110 130 TEMPERATURE (°C) VFREQ = INTVCC 600 0.5975 0.5955 –50 –30 –10 1 2 3 VSENSE COMMON MODE VOLTAGE (V) 1.25 1.05 0 0 1.30 FREQUENCY (kHz) 0 5 Shutdown (RUN) Threshold vs Temperature RUN PIN THRESHLD (V) ILIM = 3/4 INTVCC TK/SS CURRENT (µA) 1.35 ILIM = 1/4 INTVCC 15 FEEDBACK VOLTAGE (V) MAXIMUM CURRENT SENSE THRESHOLD (mV) ILIM = INTVCC ILIM = 1/2 INTVCC ILIM = GND 10 3875 G12 1.40 20 ILIM = 1/4 INTVCC 15 TK/SS Pull-Up Current vs Temperature 35 25 ILIM = 1/2 INTVCC 20 3875 G11 Maximum Current Sense Threshold vs Feedback Voltage (Current Foldback) 30 ILIM = 3/4 INTVCC 25 0 2 1 1.5 ITH VOLTAGE (V) ILIM = INTVCC 30 0 –50 3875 G16 0 50 100 TEMPERATURE (°C) 150 3875 G17 3875fb For more information www.linear.com/LTC3875 7 LTC3875 TYPICAL PERFORMANCE CHARACTERISTICS OSCILLATOR FREQUENCY (kHz) RISING 4.2 4.0 FALLING 3.8 3.6 3.4 45 VFREQ = INTVCC 800 4.6 UVLO THRESHOLD (V) 50 900 4.8 4.4 Shutdown Current vs Input Voltage 700 600 SHUTDOWN CURRENT (µA) 5.0 Oscillator Frequency vs Input Voltage Undervoltage Lockout Threshold (INTVCC) vs Temperature VFREQ = 1.22V 500 400 VFREQ = GND 300 200 100 3.2 3.0 –50 0 50 100 TEMPERATURE (°C) 0 150 25 20 15 10 0 10 20 40 30 0 0 INPUT VOLTAGE (V) 45 7 QUIESCENT CURRENT (mA) 8 35 30 25 20 15 20 25 30 INPUT VOLTAGE (V) 4 VOUT LOW RIPPLE FIGURE 20 10mV/DIV AC-COUPLED 3 2 10 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 0 40 VOUT TYPICAL FRONT PAGE 10mV/DIV AC-COUPLED 5 1 35 Very Low Output Voltage Ripple 6 15 3875 G21 10 3875 G20 Quiescent Current vs Input Voltage without EXTVCC 50 40 5 3875 G19 Shutdown Current vs Temperature SHUTDOWN CURRENT (µA) 30 5 3875 G18 8 40 35 VIN = 12V VOUT = 2.5V 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 2µs/DIV 3875 G23 40 3875 G22 3875fb For more information www.linear.com/LTC3875 LTC3875 PIN FUNCTIONS TK/SS1, TK/SS2 (Pin 1, Pin 8): Output Voltage Tracking and Soft-Start Inputs. When one channel is configured to be the master, a capacitor to ground at this pin sets the ramp rate for the master channel’s output voltage. When the channel is configured to be the slave, the feedback voltage of the master channel is reproduced by a resistor divider and applied to this pin. Internal soft-start currents of 1.25µA charge these pins. VOSNS1+, VOSNS2+ (Pin 2, Pin 6): Positive Inputs of Remote Sensing Differential Amplifiers. These pins receive the remotely sensed feedback voltage from external resistive divider across the output. The differential amplifier outputs are connected directly to the error amplifiers’ inputs internally inside the IC. VOSNS1–, VOSNS2– (Pin 3, Pin 7): Negative Inputs of Remote Sensing Differential Amplifiers. Connect these pins to the negative terminal of the output capacitors when remote sensing is desired. Connect these pins to local signal ground if remote sensing is not used. ITH1, ITH2 (Pin 4, Pin 5): Current Control Threshold and Error Amplifier Compensation Points. The current comparators’ tripping thresholds increase with these control voltages. TAVG (Pin 13): Average Temperature Summing Point. Connect a resistor to ground to sum all currents together for multi-channels or multi-IC operations when temperature balancing function is enabled. The value of the resistor should be the TRSET resistor value divided by the number of channels in the system. Float this pin if thermal balancing is not used. FREQ (Pin 15): There is a precision 10µA current flowing out of this pin. A resistor to ground sets a voltage which in turn programs the frequency. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. IFAST (Pin 17): Programmable Pin for Fast Transient Operation for Channel 2 Only. A resistor to ground programs the threshold of the output load transient excursion. Float this pin to disable this function. See the Applications Information section for more details. ENTMPB (Pin 18): Enable Pin for Temperature Balancing Function. Ground this pin to enable the temperature balancing function. Float this pin for normal operation. PGOOD (Pin 19): Power Good Indicator Output. Open-drain logic that is pulled to ground when either channel’s output exceeds ±7.5% regulation window, after the internal 20µs power bad mask timer expires. EXTVCC (Pin 24): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies the IC power, bypassing the internal low dropout regulator, whenever EXTVCC is higher than 4.7V. Do not exceed 6V on this pin and make sure that EXTVCC < VIN at all times. INTVCC (Pin 25): Internal 5.5V Regulator Output. The control circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. VIN (Pin 26): Main Input Supply. Decouple this pin to PGND with a capacitor (0.1µF to 1µF). BG1, BG2 (Pin 27, Pin 23): Bottom Gate Driver Outputs. These pins drive the gates of the bottom N-channel MOSFETs between INTVCC and PGND. BOOST1, BOOST2 (Pin 28, Pin 22): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC. TG1, TG2 (Pin 29, Pin 21): Top Gate Driver Outputs. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch node voltage. SW1, SW2 (Pin 30, Pin 20): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. CLKOUT (Pin 31): Clock Output Pin. Clock output with phase changeable by PHASMD to enable usage of multiple LTC3875s in multiphase systems signal swing is from INTVCC to ground. 3875fb For more information www.linear.com/LTC3875 9 LTC3875 PIN FUNCTIONS PHASMD (Pin 32): Phase Programmable Pin. This pin can be tied to SGND, INTVCC or left floating. It determines the relative phases between the internal controllers as well as the phasing of the CLKOUT signal. See Table 1 in the Operation section for details. MODE/PLLIN (Pin 33): Forced Continuous Mode, Burst Mode or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force the IC into continuous mode of operation. Connect to INTVCC to enable pulse-skipping mode of operation. Leave the pin floating to enable Burst Mode operation. A clock on the pin will force the IC into continuous mode of operation and synchronize the internal oscillator with the clock on this pin. The PLL compensation network is integrated into the IC. RUN1, RUN2 (Pin 34, Pin 16): Run Control Inputs. A voltage above 1.22V on either pin turns on the IC. However, forcing both pins below 1.14V causes the IC to shut down. There is a 1.0µA pull-up current for both pins. Once the RUN pin rises above 1.22V, an additional 4.5µA pull-up current is added to the pin. ILIM (Pin 35): Current Comparators’ Sense Voltage Range Input. A resistor divider sets the maximum current sense threshold to five different levels for the current comparators. TRSET1, TRSET2 (Pin 36, Pin 14): Input of the Temperature Balancing Circuitries. Connect these pins through resistors to ground to convert the TCOMP pin voltages to currents. These currents are then mirrored to pin TAVG and are added together for all channels. Float this pin if thermal balancing is not used. 10 TCOMP1/ITEMP1, TCOMP2/ITEMP2 (Pin 37, Pin 12): Input of the Temperature Balancing Circuitries. Connect these pins to external NTC resistors or temperature sensing ICs placed near inductors. These pins are used to sense temperature of each channel and balance the temperature of the whole system accordingly. When thermal balancing function is disabled, these pins can be programmed to compensate the temperature coefficient of the DCR. Connect to an NTC (negative tempco) resistor placed near the output inductor to compensate for its DCR change over temperature. Floating this pin disables the DCR temperature compensation function. SNSD1+, SNSD2+ (Pin 38, Pin 11): DC Current Sense Comparator Inputs. The (+) input to the DC current comparator is normally connected to a DC current sensing network. Ground these pins to disable the novel DCR sensing and enable normal DCR sensing with five times current limit. SNS1–, SNS2– (Pin 39, Pin 10): AC and DC Current Sense Comparator Inputs. The (–) inputs to the current comparators are connected to the output. SNSA1+, SNSA2+ (Pin 40, Pin 9): AC Current Sense Comparator Inputs. The (+) input to the AC current comparator is normally connected to a DCR sensing network. When combined with the SNSD+ pin, the DCR sensing network can be skewed to increase the AC ripple voltage by a factor of 5. SGND/PGND (Exposed Pad Pin 41): Signal/Power Ground Pin. Connect this pin closely to the sources of the bottom N-channel MOSFETs, the (–) terminal of CVCC and the (–) terminal of CIN. All small-signal components and compensation components should connect to this ground. 3875fb For more information www.linear.com/LTC3875 LTC3875 BLOCK DIAGRAM MODE/PLLIN (Functional diagram shows one channel only) PHASMD TCOMP/ITEMP EXTVCC TEMPSNS – 4.7V FREQ 0.6V MODE/SYNC DETECT + F VIN + 5.5V REG + – INTVCC F PLL-SYNC VIN CIN BOOST BURST EN CLKOUT S R Q IFAST (CHANNEL 2 ONLY) + TG FCNT OSC ICMP + – M1 SW ON VOUT SNSA+ SWITCH LOGIC AND ANTISHOOTTHROUGH – 5k IREV CB DB SNS– + BG RUN M2 OV PGND R2 COUT R1 SGND CVCC ILIM PGOOD SLOPE COMPENSATION + INTVCC UVLO 0.555V UV – 1 50k ITHB SNSD+ + ACTIVE CLAMP AMP SLEEP OV – + – – + + 0.5V – EA SS RUN 0.66V 20k + 20k DIFFAMP 1.25µA + VIN + – 0.6V REF SNS– – + + VOSNS+ – – 1.22V 20k VFB 0.55V – V 20k OSNS 1µA/5.5µA ITH RC CC1 30µA TCOMP/ITEMP RUN TK/SS CSS MIRROR + AMP ENTMPB *n EQUALS THE NUMBER OF CHANNELS IN PARALLEL – TAVG + TRSET RTCOMP RTCOMP n* gm – 3875 BD REPEAT FOR MULTICHIP OPERATIONS 3875fb For more information www.linear.com/LTC3875 11 LTC3875 OPERATION Main Control Loop The LTC3875 is a constant frequency, current mode stepdown controller with two channels operating 180° or 240° out of phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier EA. The remote sense amplifier (DIFFAMP) converts the sensed differential voltage across the output feedback resistor divider to an internal voltage (VFB) referred to SGND. The VFB signal is then compared to the internal 0.6V reference voltage by the EA. When the load current increases, it causes a slight decrease in VFB relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, IREV, or the beginning of the next cycle. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open or tied to a voltage less than 4.5V, an internal 5.5V linear regulator supplies INTVCC power from VIN. If EXTVCC is taken above 4.7V, the 5.5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. When using EXTVCC, the VIN voltage has to be higher than EXTVCC voltage at all time and has to come before EXTVCC is applied. Otherwise, EXTVCC current will flow back to VIN through the internal switch’s body diode and potentially damage the device. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source. Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage, VIN, decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period plus 100ns 12 every third cycle to allow CB to recharge. However, it is recommended that a load be present or the IC operates at low frequency during the drop-out transition to ensure that CB is recharged. Shutdown and Start-Up (RUN1, RUN2 and TK/SS1, TK/SS2 Pins) The two channels of the LTC3875 can be independently shut down using the RUN1 and RUN2 pins. Pulling either of these pins below 1.14V shuts down the main control loop for that channel. Pulling both pins low disables both channels and most internal circuits, including the INTVCC regulator. Releasing either RUN pin allows an internal 1µA current to pull up the pin and enable the controller. Alternatively, the RUN pins may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on these pins. The start-up of each channel’s output voltage, VOUT, is controlled by the voltage on its TK/SS pin. When the voltage on the TK/SS pin is less than the 0.6V internal reference, the LTC3875 regulates the VFB voltage to the TK/SS pin voltage instead of the 0.6V reference. This allows the TK/SS pin to be used to program the soft-start period by connecting an external capacitor from the TK/SS pin to SGND. An internal 1.25µA pull-up current charges this capacitor, creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly from 0V to 0.6V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively the TK/SS pin can be used to cause the start-up of VOUT to “track” that of another supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the corresponding RUN pin is pulled low to disable a controller, or when INTVCC drops below its undervoltage lockout threshold of 3.7V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, both controllers are disabled and the external MOSFETs are held off. Internal Soft-Start By default, the start-up of the output voltage is normally controlled by an internal soft-start ramp. The internal soft-start ramp represents one of the noninverting inputs For more information www.linear.com/LTC3875 3875fb LTC3875 OPERATION to the error amplifier. The VFB signal is regulated to the lower of the error amplifier’s three noninverting inputs (the internal soft-start ramp, the TK/SS pin or the internal 600mV reference). As the ramp voltage rises from 0V to 0.6V, over approximately 600µs, the output voltage rises smoothly from its pre-biased value to its final set value. Certain applications can require the start-up of the converter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. In order to prevent the output from discharging under these conditions, the top and bottom MOSFETs are disabled until soft-start is greater than VFB. Light Load Current Operation (Burst Mode Operation, Pulse-Skipping, or Continuous Conduction) The LTC3875 can be enabled to enter high efficiency Burst Mode operation, constant frequency pulse-skipping mode, or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to a DC voltage below 0.6V (e.g., SGND). To select pulse-skipping mode of operation, tie the MODE/PLLIN pin to INTVCC. To select Burst Mode operation, float the MODE/PLLIN pin. When a controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.5V, the internal sleep signal goes high (enabling sleep mode) and both external MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IREV) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE/PLLIN pin is connected to INTVCC, the LTC3875 operates in PWM pulse-skipping mode at light loads. At very light loads, the current comparator, ICMP, may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Multichip Operations (PHASMD and CLKOUT Pins) The PHASMD pin determines the relative phases between the internal channels as well as the CLKOUT signal as shown in Table 1. The phases tabulated are relative to zero phase being defined as the rising edge of the clock of phase 1. Table 1 PHASMD GND FLOAT INTVCC Phase 1 0° 0° 0° Phase 2 180° 180° 240° CLKOUT 60° 90° 120° The CLKOUT signal can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or separate outputs. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A 2-stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s). 3875fb For more information www.linear.com/LTC3875 13 LTC3875 OPERATION Single Output Multiphase Operation translated to its output, relative to SGND. Care should be taken to route the VOSNS+ and VOSNS– PCB traces parallel to each other all the way to the remote sensing points on the board. In addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. Ideally, the VOSNS+ and VOSNS– traces should be shielded by a low impedance ground plane to maintain signal integrity. The LTC3875 can be used for single output multiphase converters by making these connections • Tie all of the ITH pins together; • Tie all of the VOSNS+ pins together; • Tie all of the TK/SS pins together; • Tie all of the RUN pins together. Current Sensing with Very Low Inductor DCR Examples of single output multiphase converters are shown in the Typical Applications section. For low output voltage, high current applications, it’s common to use low winding resistance (DCR) inductors to minimize the winding conduction loss and maximize the supply efficiency. Inductor DCR current sensing is also used to eliminate the current sensing resistor and its conduction loss. Unfortunately, with a very low inductor DCR value, 1mΩ or less, the AC current sensing signal ripple can be less than 10mVP-P. This makes the current loop sensitive to PCB switching noise and causes switching jitter. Sensing the Output Voltage The LTC3875 includes two low offset, high input impedance, unity gain, high bandwidth differential amplifier for applications that require true remote sensing. Differentially sensing the load greatly improves regulation in high current, low voltage applications, where board interconnection losses can be a significant portion of the total error budget. The LTC3875 differential amplifier’s positive terminal VOSNS+ senses the divided output through a resistor divider and its negative terminal VOSNS– senses the remote ground of the load. The differential amplifier output is connected to the negative terminal of the internal error amplifier inside the controller. Therefore, its differential output signal (VFB) is not accessible from outside the IC. In a typical application where differential sensing is desired, connect the VOSNS+ pin to the center tap of the feedback divider across the output load, and the VOSNS– pin to the load ground. When differential sensing is not used, the VOSNS– pin can be connected to local ground. See Figure 1. The LTC3875 employs a unique and proprietary current sensing architecture to enhance its signal-to-noise ratio in these situations. This enables it to operate with a small sense signal of a very low value inductor DCR, 1mΩ or less. The result is improved power efficiency, and reduced jitter due to switching noise which could corrupt the signal. The LTC3875 can sense a DCR value as low as 0.2mΩ with careful PCB layout. The LTC3875 uses two positive sense pins, SNSD+ and SNSA+ to acquire signals. It processes them internally to provide the response as with a DCR sense signal that has a 14dB (5×) signal-to-noise ratio improvement without affecting output voltage feedback loop. In the meantime, the current limit threshold is still a function of the inductor peak current times its DCR value and its accuracy is also improved five times and can be accurately set from 10mV to 30mV in a 5mV steps with the ILIM pin VOUT 10Ω COUT2 FEEDBACK DIVIDER The LTC3875 differential amplifier has a typical output slew rate of 2V/µs. The amplifier is configured for unity gain, meaning that the difference between VOSNS+ and VOSNS– is RD1 COUT1 10Ω RD2 CFF VOSNS+ VOSNS – LTC3875 + DIFFAMP – 0.6V INTSS – + + + EA ITH TK/SS 3875 F01 Figure 1. Differential Amplifier Connection 14 For more information www.linear.com/LTC3875 3875fb LTC3875 OPERATION The thermal balancing can be enabled by setting the ENTMPB pin to ground. Each channel has a TCOMP/ITEMP pin which sources a 30µA precision current. By connecting a linearized NTC network or a temperature sensing IC placed near the hot spot of the converter from this pin to SGND, the temperature of each channel can be sensed. The sensed voltage from each channel is converted to a current, which is programmable with resistor, RTCOMP, at the TRSET pin. The current from each channel is then summed together at the TAVG pin. The resistor value at the TAVG is RTCOMP/n, where n is the number of phases. The voltage at TAVG is then a representation of the average temperature of the whole system. By comparing the phase temperature and average temperature, an internal transconductance amplifier then adjusts the phase current accordingly to match the phase temperature to the average temperature of the system. (see Figure 4b for inductor DCR sensing connections). The filter time constant, R1 • C1, of the SNSD+ should match the L/DCR of the output inductor, while the filter at SNSA+ should have a bandwidth of five times larger than that of SNSD+, i.e, R2 • C2 equals one-fifth of R1 • C1. Thermal Balancing For Multiphase Operation When LTC3875 is used as a single output multiphase converter, the temperature of the whole system can be balanced by enabling the thermal balancing function. This prevents hot spots due to imperfection of current matching and component mismatch. Therefore, it improves the overall reliability of the power supply system. Refer to Figure 2 for the following discussion of thermal balancing for the LTC3875. 30µA TCOMP1 THERMAL SENSOR OR NTC MIRROR 1:1 + – TRSET1 RTCOMP CHANNEL 1 ADJUST CHANNEL CURRENT gm AMP + TAVG – RAVG 30µA TCOMP2 THERMAL SENSOR OR NTC MIRROR 1:1 + – REPEAT FOR MULTICHIP OPERATIONS TRSET2 RTCOMP CHANNEL 2 ADJUST CHANNEL CURRENT gm AMP + – 3875 F02 Figure 2. Thermal Balancing Technique for Multichip Operations 3875fb For more information www.linear.com/LTC3875 15 LTC3875 OPERATION Inductor DCR Sensing Temperature Compensation Inductor DCR current sensing provides a lossless method of sensing the instantaneous current. Therefore, it can provide higher efficiency for applications of high output currents. However the DCR of a copper inductor typically has a positive temperature coefficient. As the temperature of the inductor rises, its DCR value increases. The current limit of the controller is therefore reduced. LTC3875 offers a method to counter this inaccuracy by allowing the user to place an NTC temperature sensing resistor near the inductor. The ENTMPB pin has to be floating to enable the inductor DCR sensing temperature compensation function. The TCOMP/ITEMP pin, when left floating, is at a voltage around 5.5V and DCR temperature compensation is also disabled. A constant 30µA precision current flows out the TCOMP/ITEMP pin. By connecting a linearized NTC resistor network from the TCOMP/ITEMP pin to SGND, the maximum current sense threshold can be varied over temperature according the following equation: VSENSEMAX(ADJ) = VSENSE(MAX) • 2.2 – VITEMP 1.5 where: VSENSEMAX(ADJ) is the maximum adjusted current sense threshold. VSENSE(MAX) is the maximum current sense threshold specified in the electrical characteristics table. It is typically 10mV, 15mV, 20mV, 25mV or 30mV depending on the setting ILIM pins. VITEMP is the voltage of the TCOMP/ ITEMP pin. The valid voltage range for DCR temperature compensation on the TCOMP/ITEMP pin is between 0.7V to SGND with 0.7V or above being no DCR temperature correction. An NTC resistor has a negative temperature coefficient, meaning that its value decreases as temperature rises. The VITEMP voltage, therefore, decreases as temperature increases and in turn VSENSEMAX(ADJ) will increase to compensate the DCR temperature coefficient. The NTC resistor, however, is nonlinear, but the user can linearize its value by building a resistor network with regular 16 resistors. Consult the NTC manufacturer’s data sheets for detailed information. Another use for the TCOMP/ITEMP pins, in addition to NTC compensated DCR sensing, is adjusting VSENSE(MAX) to values between the nominal values of 10mV,15mV, 20mV, 25mV and 30mV for a more precise current limit setting. This is done by applying a voltage less than 0.7V to the TCOMP/ITEMP pin. VSENSE(MAX) will be varied per the above equation. The current limit can be adjusted using this method either with a sense resistor or DCR sensing. The ENTMPB pin also needs to be floating to use this function. For more information see the NTC Compensated DCR Sensing paragraph in the Applications Information section. Frequency Selection and Phase-Locked Loop (FREQ and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3875’s controllers can be selected using the FREQ pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ pin can be used to program the controller’s operating frequency from 250kHz to 720kHz. There is a precision 10µA current flowing out of the FREQ pin, so the user can program the controller’s switching frequency with a single resistor to SGND. A curve is provided later in the application section showing the relationship between the voltage on the FREQ pin and switching frequency. A phase-locked loop (PLL) is integrated on the LTC3875 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The controller is operating in forced continuous mode when it is synchronized. The PLL loop filter network is also integrated inside the LTC3875. The phase-locked loop is capable of locking any frequency within the range of 250kHz to 720kHz. The frequency setting resistor should always be present to set the controller’s initial switching frequency before locking to the external clock to minimize the transient. 3875fb For more information www.linear.com/LTC3875 LTC3875 OPERATION Power Good (PGOOD Pin) When both VOSNS+ pins’ voltages are not within ±7.5% of the 0.6V reference voltage, the PGOOD pin is pulled low. The PGOOD pin is also pulled low when the RUN pins are below 1.14V or when the LTC3875 is in the soft-start, UVLO or tracking phase. The PGOOD pin will flag power good immediately when both the VOSNS+ pins are within the ±7.5% of the reference window. However, there is an internal 20µs power bad mask when VOSNS+ voltages go out of the ±7.5% window. The PGOOD pin is allowed to be pulled up by an external resistor to sources of up to 6V. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The plots in Figure 3 show the improvement with and without the transient improvement circuit for a typical 12V (VIN) to 1.5V (VOUT ) high current application. The circuit with fast transient shows a near 30% improvement for the worst case transient steps. For this application, IFAST pin voltage is programmed to be around 0.62V and the circuit is not very sensitive to this programmed voltage. During the double frequency operation, care has to be taken not to violate the minimum on-time requirement of the LTC3875. The fast transient mode is only enabled in forced continuous mode for channel 2 and is disabled automatically during start-up, or when output is out of regulation window. In order to properly take advantage of the fast transient circuit, the following equation needs to be satisfied: VSENSE(MAX) 0.7 – VIFAST 0.9375 VOUT • + 1– 30mV 25k fOSC VIN • 5k ≥ 5 • ∆IL •DCR Fast Transient Operation The LTC3875 also has a transient improvement function implemented on channel 2. In normal operation, IFAST pin is floated. This will disable the transient improvement circuit. To enable the transient improvement function, connect a resistor from IFAST pin to ground. The voltage difference between 0.7V and IFAST pin voltage programs the window of sensitivity of when a transient condition is detected. During the load step-up, a comparator monitoring the ripple voltage will compare with the scaled version of the programmed window voltage and trip. This indicates that a load step is detected. The LTC3875 will immediately turn on the top gate and also double the switching frequency for about 20 cycles. where, VSENSE(MAX) is the maximum sense threshold voltage VIFAST is the programmed voltage on the IFAST pin fOSC is the programmed switching frequency VOUT is the converter’s output voltage VIN is the converter’s input voltage ΔIL is the inductor ripple current DCR is the winding resistance of the inductor As a rule of thumb, the value of the left side of the equation should be 20% larger than the value of the right side of the equation. 3875fb For more information www.linear.com/LTC3875 17 LTC3875 OPERATION Fast Transient Disabled VO 50mV/DIV Fast Transient Enabled 67.5mV 95mV SW NODE 10V/DIV IO 10A/DIV 0A TO 15A 0A TO 15A 3875 F03 Figure 3. Worst-Case Transient Comparison Between Normal Mode Operation and Fast Transient Mode of Operation for 12V/1.5V Application with 15A Load Step APPLICATIONS INFORMATION The Typical Application on the first page of this data sheet is a basic LTC3875 application circuit configured as a dual phase single output power supply. The LTC3875 has an optional thermal balancing function that balances the thermal stress between phases, thus increasing the reliability of the whole system. In addition, the LTC3875 is designed and optimized for use with a very low value DCR inductor by utilizing a novel approach to reduce the noise sensitivity of the sensing signal by a factor of 14dB. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, as the DCR value drops below 1mΩ, the signal-to-noise ratio is low and current sensing is difficult. The LTC3875 uses an LTC proprietary technique to solve this issue with minimum additional external components. In general, external component selection is driven by the load requirement, and begins with the DCR and inductor value. Next, power MOSFETs are selected. Finally, input and output capacitors are selected. Current Limit Programming The ILIM pin is a 5-level logic input which sets the maximum current limit of the controller. The input impedance of the ILIM pin is 250kΩ. When ILIM is grounded, floated, or tied to INTVCC, the typical value for the maximum current sense threshold will be 10mV, 20mV, or 30mV, respectively. Setting ILIM to one-fourth INTVCC and three-fourths INTVCC 18 provides maximum current sense thresholds of 15mV or 25mV. The user should select the proper ILIM level based on the inductor DCR value and targeted current limit level. SNSD+, SNSA+ and SNS– Pins The SNSA+ and SNS– pins are the direct inputs to the current comparators, while the SNSD+ pin is the input of an internal DC amplifier. The operating input voltage range of 0V to 3.5V is for SNSA+, SNSD+ and SNS– in a typical application. All the positive sense pins that are connected to the current comparator or the DC amplifier are high impedance with input bias currents of less than 1µA, but there is a resistance of about 300k from the SNS– pin to ground. The SNS– pin should be connected directly to VOUT. The SNSD+ pin connects to the filter that has a R1 • C1 time constant equals L/DCR of the inductor. The SNSA+ pin is connected to the second filter, R2 • C2, with the time constant equals (R1 • C1)/5. Care must be taken not to float these pins. Filter components, especially capacitors, must be placed close to the LTC3875, and the sense lines should run close together to a Kelvin connection underneath the current sense element (Figure 4a). Because the LTC3875 is designed to be used with a very low DCR value to sense inductor current, without proper care, the parasitic resistance, capacitance and inductance will degrade the current sense signal integrity, making the programmed current limit unpredictable. As shown in Figure 4b, resistors R1 and R2 are placed close to the 3875fb For more information www.linear.com/LTC3875 LTC3875 APPLICATIONS INFORMATION TO SENSE FILTER, NEXT TO THE CONTROLLER 3875 F04a COUT INDUCTOR Figure 4a. Sense Lines Placement with Inductor DCR VIN INTVCC VIN BOOST INDUCTOR LTC3875 RITEMP TCOMP/ITEMP TG DCR VOUT BG PGND RS 22.6k R1 R2 + SNSD SNS– RNTC 100k L SW RP 90.9k SNSA+ C1 C2 SGND PLACE C1, C2 NEXT TO IC PLACE R1, R2 NEXT TO INDUCTOR R1C1 = 5 • R2C2 3875 F04b Figure 4b. Inductor DCR Current Sensing output inductor and capacitors C1 and C2 are close to the IC pins to prevent noise coupling to the sense signal. For applications where the inductor DCR is large, the LTC3875 could also be used like any typical current mode controller with conventional DCR sensing by disabling the SNSD+ pin, shorting it to ground. An RSENSE resistor or a DCR sensing RC filter can be used to sense the output inductor signal and connects to the SNSA+ pin. If the RC filter is used, its time constant, R • C, equals L/DCR of the output inductor. In these applications, the current limit, VSENSE(MAX), will be five times the value of VSENSE(MAX) with DC loop enabled, and the operating voltage range of SNSA+ and SNS– is from 0V to 5V. An output voltage of 5V can be generated. Low Inductor DCR Sensing and Current Limit Estimation The LTC3875 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor DCR in the sub milliohm range (Figure 4b). The DCR is the inductor DC winding resistance, which is often less than 1mΩ for high current inductors. In high current and low output voltage applications, conduction loss of a high DCR inductor or a sense resistor will cause a significant reduction in power efficiency. For a specific output requirement and inductor, choose the current limit sensing level that provides proper margin for maximum load current, and uses the relationship of the sense pin filters to output inductor characteristics as depicted below. VSENSE(MAX) ∆I IMAX + L 2 L/DCR = R1•C1= 5 •R2 •C2 DCR = where: VSENSE(MAX) is the maximum sense voltage for a given ILIM threshold. IMAX is the maximum load current. ∆IL is the inductor ripple current. L/DCR is the output inductor characteristics. 3875fb For more information www.linear.com/LTC3875 19 LTC3875 APPLICATIONS INFORMATION R1 • C1 is the filter time constant of the SNSD+ pin. R2 • C2 is the filter time constant of the SNSA+ pin. For example, for a 12VIN, 1.2V/30A step-down buck converter running at 400kHz frequency, a 0.15µH, 0.4mΩ inductor is chosen. This inductor provides 15A peak-topeak ripple current, which is 50% of the 30A full load current. At full load, the inductor peak current is 30A + 15A/2 = 37.5A. IL(PK) • DCR = 37.5A • 0.4mΩ = 15mV. In this case, choose the 20mV ILIM setting which is the closest but higher than 15mV to provide margin for current limit. Select the two R/C sensing network: Filter on SNSD+ pin: R1 • C1 = L/DCR, Filter on SNSA+ pin: R2 • C2 = (L/DCR)/5. In this case, the ripple sense signal across SNSA+ and SNS– pins is ∆ILP-P • DCR • 5 = 15A • 0.4mΩ • 5 = 30mV. This signal should be more than 15mV for good signal-tonoise ratio. In this case, it is certainly sufficient. The peak inductor current at current limit is: ILIM(PK) = 20mV/DCR = 20mV/0.4mΩ = 50A. The average inductor current, which is also the output current, at current limit is : ILIM(AVG) = ILIM(PK) – ∆ILP-P/2 = 50A – 15A/2 = 42.5A. To ensure that the load current will be delivered over the full operating temperature range, the temperature coefficient of DCR resistance, approximately 0.4%/°C, should be taken into account. The LTC3875 features a DCR temperature compensation circuit that uses an NTC temperature sensing resistor for this purpose. See the Inductor DCR Sensing Temperature Compensation section for details. Typically, C1 and C2 are selected in the range of 0.047µF to 0.47µF. If C1 and C2 are chosen to be 100nF, and an inductor of 150nH with 0.4mΩ DCR is selected, R1 and R2 will be 4.64k and 931Ω respectively. The bias current at SNSD+ and SNSA+ is about 30nA and 500nA respectively, and it causes some small error to the sense signal. 20 There will be some power loss in R1 and R2 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: PLOSS (R) = ( VIN(MAX) – VOUT ) • VOUT R Ensure that R1 and R2 have a power rating higher than this value. However, DCR sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. To maintain a good signal-to-noise ratio for the current sense signal, using ∆VSENSE of 15mV between SNSA+ and SNS– pins or an equivalent 3mV ripple on the current sense signal. The actual ripple voltage across SNSA+ and SNS– pins will be determined by the following equation: ∆VSENSE = VOUT VIN – VOUT • VIN R2•C2 • fOSC Inductor DCR Sensing Temperature Compensation with NTC Thermistor For DCR sensing applications, the temperature coefficient of the inductor winding resistance should be taken into account when the accuracy of the current limit is critical over a wide range of temperature. The main element used in inductors is copper; that has a positive tempco of approximately 4000ppm/°C. The LTC3875 provides a feature to correct for this variation through the use of the TCOMP/ITEMP pin. There is a 30µA precision current source flowing out of the TCOMP/ITEMP pin. A thermistor with a NTC (negative temperature coefficient) resistance can be used in a network, RITEMP (Figure 4b) connected to maintain the current limit threshold constant over a wide operating temperature. The TCOMP/ITEMP voltage range that activates the correction is from 0.7V or less. If this pin is floating, its voltage will be at INTVCC potential, about 5.5V. When the TCOMP/ITEMP voltage is higher than 0.7V, the temperature compensation is inactive. Floating the ENTMPB pin enables the temperature compensation function. The following guidelines will help to choose components for temperature correction. The initial compensation is for 25°C ambient temperature: 3875fb For more information www.linear.com/LTC3875 LTC3875 APPLICATIONS INFORMATION 2. Calculate the TCOMP/ITEMP pin resistance and the maximum inductor temperature which is typically 100°C. Use the following equations: VITEMP100C = (100°C – 25°C) • 0.4 IMAX •DCR (Max)• 100 0.7 – 1.5 VSENSE(MAX) = 0.25V Since VSENSE(MAX) = IMAX • DCR (Max): RITEMP100C = VITEMP100C = 8.33k 30µA where: RITEMP100C = TCOMP/ITEMP pin resistance at 100°C. VITEMP100C = TCOMP/ITEMP pin voltage at 100°C. VSENSE(MAX) = Maximum current sense threshold at room temperature. IMAX = Maximum inductor peak current. DCR (Max) = Maximum DCR value. Calculate the values for the NTC network’s parallel and series resistors, RP and RS. A simple method is to graph the following RS versus RP equations with RS on the y-axis and RP on the x-axis. RS = RITEMP25C – RNTC25C||RP RS = RITEMP100C – RNTC100C||RP Next, find the value of RP that satisfies both equations which will be the point where the curves intersect. Once RP is known, solve for RS. The resistance of the NTC thermistor can be obtained from the vendor’s data sheet either in the form of graphs, tabulated data, or formulas. The approximate value for the NTC thermistor for a given temperature can be calculated from the following equation: 1 1 R = RO • exp B • – T + 273 TO + 273 where: R = Resistance at temperature T, which is in degrees C. RO = Resistance at temperature TO, typically 25°C. B = B-constant of the thermistor. Figure 5 shows a typical resistance curve for a 100k thermistor and the TCOMP/ITEMP pin network over temperature. Starting values for the NTC compensation network are: • NTC RO = 100k • RS = 3.92k • RP = 24.3k But, the final values should be calculated using the above equations and checked at 25°C and 100°C. After determining the components for the temperature compensation network, check the results by plotting IMAX versus inductor temperature using the following equations: IDC(MAX) = VSENSEMAX(ADJ) – ( ∆VSENSE 2 ) 0.4 DCR(MAX) at 25°C • 1+ TL(MAX) – 25°C • 100 where: 10000 1000 RESISTANCE (kΩ) 1. Set the TCOMP/ITEMP pin resistance to 23.33k at 25°C. With 30µA flowing out of the TCOMP/ITEMP pin, the voltage on the TCOMP/ITEMP pin will be 0.7V at room temperature. Current limit correction will occur for inductor temperatures greater than 25°C. THERMISTOR RESISTANCE RO = 100k, TO = 25°C B = 4334 for 25°C/100°C 100 10 RITMP RS = 20kΩ RP = 43.2kΩ 100k NTC 1 –40 –20 0 20 40 60 80 100 120 INDUCTOR TEMPERATURE (°C) 3875 F05 Figure 5. Resistance Versus Temperature for ITEMP Pin Network and the 100k NTC 3875fb For more information www.linear.com/LTC3875 21 LTC3875 APPLICATIONS INFORMATION VSENSEMAX(ADJ) = VSENSE(MAX) • 2.2 – VITEMP 1.5 VITEMP = 30µA • (RS + RP||RNTC) CONNECT TO ITEMP1 NETWORK VOUT1 VOUT2 L1 L2 SW1 SW2 CONNECT TO ITEMP2 NETWORK RNTC2 RNTC1 IDC(MAX) = Maximum average inductor current. GND TC is the inductor temperature. GND 3875 F07a The resulting current limit should be greater than or equal to IMAX for inductor temperatures between 25°C and 100°C. (7a) Dual Output Dual Phase DCR Sensing Application VOUT Typical values for the NTC compensation network are: • NTC RO = 100k, B-constant = 3000 to 4000 • RS ≈ 3.92k • RP ≈ 24.3k Generating the IMAX versus inductor temperature curve plot first using the above values as a starting point, and then adjusting the RS and RP values as necessary, is another approach. Figure 6 shows a curve of IMAX versus inductor temperature. For PolyPhase® applications, tie the TCOMP/ ITEMP pins together and calculate for an TCOMP/ITEMP pin current of 30µA • #phases. For the most accurate temperature detection, place the thermistors next to the inductors as shown in Figure 7. Take care to keep the TCOMP/ITEMP pins away from the switch nodes. Slope Compensation and Inductor Peak Current 70 L1 RNTC SW1 L2 SW2 3875 F07b (7b) Single Output Dual Phase DCR Sensing Application Figure 7. Thermistor Locations. Place Thermistor Next to Inductor(s) for Accurate Sensing of the Inductor Temperature, but Keep the ITEMP Pins away from the Switch Nodes and Gate Traces Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3875 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Inductor Value Calculation IMAX (A) 60 50 NOMINAL IMAX Given the desired input and output voltages, the inductor value and operating frequency, fOSC, directly determine the inductor’s peak-to-peak ripple current: CORRECTED IMAX RS = 3.92k RP = 24.3k 40 NTC THERMISTOR: RO = 100k UNCORRECTED TO = 25°C IMAX B = 4334 30 –40 –20 0 20 40 60 80 100 120 INDUCTOR TEMPERATURE (°C) 3875 F06 Figure 6. Worst-Case IMAX vs Inductor Temperature Curve with and without NTC Temperature Compensation 22 IRIPPLE = VOUT VIN – VOUT VIN fOSC •L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. 3875fb For more information www.linear.com/LTC3875 LTC3875 APPLICATIONS INFORMATION A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L≥ VIN – VOUT VOUT • fOSC •IRIPPLE VIN Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode (Optional) Selection At least two external power MOSFETs need to be selected: One N-channel MOSFET for the top (main) switch and one or more N-channel MOSFET(s) for the bottom (synchronous) switch. The number, type and on-resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than one-third of the input voltage. In applications where VIN >> VOUT , the top MOSFETs’ onresistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low on-resistance with significantly reduced input capacitance for the main switch application in switching regulators. The peak-to-peak MOSFET gate drive levels are set by the internal regulator voltage, VINTVCC, requiring the use of logic-level threshold MOSFETs in most applications. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the on-resistance, RDS(ON), input capacitance, input voltage and maximum output current. MOSFET input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (Figure 8). The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain voltage, but can be adjusted for different VDS voltages by multiplying the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturer’s data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: VIN VGS MILLER EFFECT a V b QIN CMILLER = (QB – QA)/VDS + VGS – +V DS – 3875 F08 Figure 8. Gate Charge Characteristic 3875fb For more information www.linear.com/LTC3875 23 LTC3875 APPLICATIONS INFORMATION Main Switch Duty Cycle = VOUT VIN V –V Synchronous Switch Duty Cycle = IN OUT VIN The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: PMAIN = VOUT 2 IMAX ) (1+ δ )RDS(ON) + ( VIN ( VIN )2 IMAX (RDR ) (CMILLER ) • 2 1 1 + V •f V – V MILLER MILLER INTVCC V –V 2 PSYNC = IN OUT (IMAX ) (1+ δ )RDS(ON) VIN where δ is the temperature dependency of RDS(ON), RDR is the effective top driver resistance (approximately 2Ω at VGS = VMILLER), VIN is the drain potential and the change in drain potential in the particular application. VMILLER is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 20V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + δ ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. 24 An optional Schottky diode across the synchronous MOSFET conducts during the dead time between the conduction of the two large power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse-recovery period which could cost as much as several percent in efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition loss due to their larger junction capacitance. Soft-Start and Tracking The LTC3875 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. When one particular channel is configured to soft-start by itself, a capacitor should be connected to its TK/SS pin. This channel is in the shutdown state if its RUN pin voltage is below 1.14V. Its TK/SS pin is actively pulled to ground in this shutdown state. Once the RUN pin voltage is above 1.22V, the channel powers up. A soft-start current of 1.25µA then starts to charge its soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. Current fold-back is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is defined to be the voltage range from 0V to 0.6V on the TK/SS pin. The total soft-start time can be calculated as: tSOFTSTART = 0.6 • CSS 1.25µA Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse-skipping mode up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.56V, it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.56V. The output ripple is minimized during the 60mV forced continuous mode window ensuring a clean PGOOD signal. When the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by 3875fb For more information www.linear.com/LTC3875 LTC3875 APPLICATIONS INFORMATION a resistor divider and applied to the TK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the LTC3875 is forced into continuous mode of operation as soon as VFB is below the undervoltage threshold of 0.55V regardless of the setting on the MODE/PLLIN pin. However, the LTC3875 should always be set in forced continuous mode tracking down when there is no load. After TK/SS drops below 0.1V, its channel will operate in discontinuous mode. The LTC3875 allows the user to program how its output ramps up and down by means of the TK/SS pins. Through these pins, the output can be set up to either coincidentally or ratiometrically track another supply’s output, as shown in Figure 9. In the following discussions, VOUT1 refers to the LTC3875’s output 1 as a master channel and VOUT2 refers to the LTC3875’s output 2 as a slave channel. In practice, though, either phase can be used as the master. To implement the coincident tracking in Figure 9a, connect an additional resistive divider to VOUT1 and connect its midpoint to the TK/SS pin of the slave channel. The ratio of this divider should be the same as that of the slave channel’s feedback divider shown in Figure 10a. In this tracking mode, VOUT1 must be set higher than VOUT2. To implement the ratiometric tracking in Figure 10b, the ratio of the VOUT2 divider should be exactly the same as the master channel’s feedback divider shown in Figure 9b. By selecting different resistors, the LTC3875 can achieve different modes of tracking including the two in Figure 9. So which mode should be programmed? While either mode in Figure 9 satisfies most practical applications, some trade-offs exist. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. When the master channel’s output experiences dynamic excursion (under load transient, for example), VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 VOUT2 TIME TIME (9a) Coincident Tracking 3875 F09 (9b) Ratiometric Tracking Figure 9. Two Different Modes of Output Voltage Tracking VOUT1 TO TK/SS2 PIN VOUT2 R3 R1 R4 R2 TO TO + VOSNS1+ VOSNS2 PIN PIN R3 R4 VOUT1 TO TK/SS2 PIN VOUT2 R1 R2 TO TO VOSNS2+ VOSNS1+ PIN PIN R3 R4 3875 F10 (10a) Coincident Tracking Setup (10b) Ratiometric Tracking Setup Figure 10. Setup for Coincident and Ratiometric Tracking 3875fb For more information www.linear.com/LTC3875 25 LTC3875 APPLICATIONS INFORMATION the slave channel output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. Pre-Biased Output Start-Up There may be situations that require the power supply to start up with a pre-bias on the output capacitors. In this case, it is desirable to start up without discharging that output pre-bias. The LTC3875 can safely power up into a pre-biased output without discharging it. The LTC3875 accomplishes this by disabling both TG and BG until the TK/SS pin voltage and the internal soft-start voltage are above the VOSNS+ pin voltage. When VOSNS+ is higher than TK/SS or the internal soft-start voltage, the error amp output is low. The control loop would like to turn BG on, which would discharge the output. Disabling BG and TG prevents the pre-biased output voltage from being discharged. When TK/SS and the internal soft-start both cross 500mV or VOSNS+, whichever is lower, TG and BG are enabled. If the pre-bias is higher than the OV threshold, the bottom gate is turned on immediately to pull the output back into the regulation window. INTVCC Regulators and EXTVCC The LTC3875 features a PMOS LDO that supplies power to INTVCC from the VIN supply. INTVCC powers the gate drivers and much of the LTC3875’s internal circuitry. The linear regulator regulates the voltage at the INTVCC pin to 5.5V when VIN is greater than 6V. EXTVCC connects to INTVCC through a P-channel MOSFET and can supply the needed power when its voltage is higher than 4.7V. Each of these can supply a peak current of 100mA and must be bypassed to ground with a minimum of a 4.7µF ceramic capacitor or a low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maxi- 26 mum junction temperature rating for the LTC3875 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the 5.5V linear regulator or EXTVCC. When the voltage on the EXTVCC pin is less than 4.7V, the linear regulator is enabled. Power dissipation for the IC in this case is highest and is equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, the LTC3875 INTVCC current is limited to less than 44mA from a 38V supply in the UJ package and not using the EXTVCC supply: TJ = 70°C + (44mA)(38V)(33°C/W) = 125°C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (MODE/PLLIN = SGND) at maximum VIN. When the voltage applied to EXTVCC rises above 4.7V, the INTVCC linear regulator is turned off and the EXTVCC is connected to the INTVCC. The EXTVCC remains on as long as the voltage applied to EXTVCC remains above 4.5V. Using the EXTVCC allows the MOSFET driver and control power to be derived from one of the LTC3875’s switching regulator outputs during normal operation and from the INTVCC when the output is out of regulation (e.g., start-up, short-circuit). If more current is required through the EXTVCC than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply more than 6V to the EXTVCC pin and make sure that EXTVCC < VIN. Significant efficiency and thermal gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Tying the EXTVCC pin to a 5V supply reduces the junction temperature in the previous example from 125°C to: TJ = 70°C + (44mA)(5V)(33°C/W) = 77°C However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from the output. 3875fb For more information www.linear.com/LTC3875 LTC3875 APPLICATIONS INFORMATION The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5.5V regulator resulting in an efficiency penalty at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If a 5V external supply is available, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. For applications where the main input power is below 5V, tie the VIN and INTVCC pins together and tie the combined pins to the 5V input with a 1Ω or 2.2Ω resistor as shown in Figure 11 to minimize the voltage drop caused by the gate charge current. This will override the INTVCC linear regulator and will prevent INTVCC from dropping too low due to the dropout voltage. Make sure the INTVCC voltage is at or exceeds the RDS(ON) test voltage for the MOSFET which is typically 4.5V for logic level devices. VIN LTC3875 INTVCC RVIN 1Ω CINTVCC 4.7µF + 5V CIN 3875 F11 Figure 11. Setup for a 5V Input MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC – VDB where VDB is the diode forward voltage drop. The value of the boost capacitor, CB, needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Undervoltage Lockout The LTC3875 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTVCC is below 3.7V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 500mV of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pins have a precision turn-on reference of 1.22V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 4.5µA of current flows out of the RUN pin once the RUN pin voltage passes 1.22V. One can program the hysteresis of the run comparator by adjusting the values of the resistive divider. For accurate VIN undervoltage detection, VIN needs to be higher than 4.5V. CIN and COUT Selection Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitor, CB, connected to the BOOST pin supplies the gate drive voltages for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate source of the The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used 3875fb For more information www.linear.com/LTC3875 27 LTC3875 APPLICATIONS INFORMATION in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ 1/2 IMAX ( VOUT ) ( VIN – VOUT ) VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3875, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of the LTC3875 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the top MOSFETs 28 should be placed within 1cm of each other and share a common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1µF to 1µF) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3875, is also suggested. A 2.2Ω to 10Ω resistor placed between CIN and the VIN pin provides further isolation between the two channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is approximated by: 1 ∆VOUT ≈IRIPPLE ESR+ 8fCOUT where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. Setting Output Voltage The LTC3875 output voltages are each set by an external feedback resistive divider carefully placed across the output, as shown in Figure 1. The regulated output voltage is determined by: R VOUT = 0.6V • 1+ D1 RD2 To improve the frequency response, a feed-forward capacitor, CFF, may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Fault Conditions: Current Limit and Current Foldback The LTC3875 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. Foldback current limiting is disabled during the soft-start or tracking up. Under short-circuit conditions 3875fb For more information www.linear.com/LTC3875 LTC3875 APPLICATIONS INFORMATION with very low duty cycles, the LTC3875 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The shortcircuit ripple current is determined by the minimum on-time, tON(MIN), of the LTC3875 (≈90ns), the input voltage and inductor value: ∆IL(SC) = tON(MIN) • VIN L The resulting short-circuit current is: ISC = 1/ 3VSENSE(MAX) RSENSE 1 – ∆IL(SC) 2 Overcurrent Fault Recovery When the output of the power supply is loaded beyond its preset current limit, the regulated output voltage will collapse depending on the load. The output may be shorted to ground through a very low impedance path or it may be a resistive short, in which case the output will collapse partially, until the load current equals the preset current limit. The controller will continue to source current into the short. The amount of current sourced depends on the ILIM pin setting and the VFB voltage as shown in the Current Foldback graph in the Typical Performance Characteristics section. Upon removal of the short, the output soft starts using the internal soft-start, thus reducing output overshoot. In the absence of this feature, the output capacitors would have been charged at current limit, and in applications with minimal output capacitance this may have resulted in output overshoot. Current limit foldback is not disabled during an overcurrent recovery. The load must step below the folded back current limit threshold in order to restart from a hard short. Thermal Protection Excessive ambient temperatures, loads and inadequate airflow or heat sinking can subject the chip, inductor, FETs etc. to high temperatures. This thermal stress reduces component life and if severe enough, can result in immediate catastrophic failure (Note 1). To protect the power supply from undue thermal stress, the LTC3875 has a fixed chip temperature-based thermal shutdown. The internal thermal shutdown is set for approximately 160°C with 10°C of hysteresis. When the chip reaches 160°C, both TG and BG are disabled until the chip cools down below 150°C. Phase-Locked Loop and Frequency Synchronization The LTC3875 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. The turn-on of controller 2’s top MOSFET is thus 180° out-of-phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. There is a precision 10µA of current flowing out of FREQ pin. This allows the user to use a single resistor to SGND to set the switching frequency when no external clock is applied to the MODE/PLLIN pin. The internal switch between FREQ pin and the integrated PLL filter network is on, allowing the filter network to be precharged to the same voltage potential as the FREQ pin. The relationship between the voltage on the FREQ pin and the operating frequency is shown in Figure 12 and specified in the Electrical Characteristic table. If an external clock is detected on the MODE/PLLIN pin, the internal switch mentioned above will turn off and isolate the influence of FREQ pin. Note that the LTC3875 can only be synchronized to an external clock whose frequency is within range of the LTC3875’s internal VCO. This is guaranteed to be between 250kHz and 720kHz. A simplified block diagram is shown in Figure 13. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the filter network. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the filter network. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to For more information www.linear.com/LTC3875 3875fb 29 LTC3875 APPLICATIONS INFORMATION cycle applications may approach this minimum on-time limit and care should be taken to ensure that: 900 800 FREQUENCY (kHz) 700 tON(MIN) < 600 500 400 300 200 100 0 0 0.5 2 1.5 1 FREQ PIN VOLTAGE (V) 2.5 3875 F12 Figure 12. Relationship Between Oscillator Frequency and Voltage at the FREQ Pin 2.4V 5V RSET 10µA FREQ EXTERNAL OSCILLATOR MODE/ PLLIN DIGITAL SYNC PHASE/ FREQUENCY DETECTOR VCO VOUT ( VIN • f ) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3875 is approximately 90ns, with reasonably good PCB layout, minimum 30% inductor current ripple and at least 2mV ripple on the current sense signal or equivalent 10mV between SNSA+ and SNS– pins. The minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak sense voltage decreases the minimum on-time gradually increases to 110ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Efficiency Considerations 3875 F13 Figure 13. Phase-Locked Loop Block Diagram the phase difference. The voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. Typically, the external clock (on MODE/PLLIN pin) input high threshold is 1.6V, while the input low threshold is 1V. It is not recommended to apply the external clock when IC is in shutdown. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the LTC3875 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty 30 The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3875 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. VIN current typically results in a small (<0.1%) loss. 3875fb For more information www.linear.com/LTC3875 LTC3875 APPLICATIONS INFORMATION 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. The LTC3875 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. Supplying INTVCC power through EXTVCC from an output-derived source will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 2.5mA of VIN current. This reduces the midcurrent loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Typical Application circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor (if used). In continuous mode, the average output current flows through L, but is “chopped” between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L to obtain I2R losses. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. Transition losses apply only to the topside MOSFET(s), and become significant only when operating at high input voltages (typically 15V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f Other “hidden” losses such as copper trace and internal battery resistances can account for an additional efficiency degradation in portable systems. It is very important to include these “system” level losses during the design Checking Transient Response 3875fb For more information www.linear.com/LTC3875 31 LTC3875 APPLICATIONS INFORMATION a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load-step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. 2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The VFB and ITH traces should be as short as possible. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. 4. Do the (+) plates of CIN connect to the drain of the topside MOSFET as closely as possible? This capacitor provides the pulsed current to the MOSFET. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 14. Figure 15 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout: 1. Are the top N-channel MOSFETs M1 and M3 located within 1cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 32 3. Are the SNSD+, SNSA+ and SNS– printed circuit traces routed together with minimum PC trace spacing? The filter capacitors between SNSD+, SNSA+ and SNS– should be as close as possible to the pins of the IC. Connect the SNSD+ and SNSA+ pins to the filter resistors as illustrated in Figure 4. 5. Keep the switching nodes, SW, BOOST and TG away from sensitive small-signal nodes (SNSD+, SNSA+, SNS–, VOSNS+, VOSNS–). Ideally the SW, BOOST and TG printed circuit traces should be routed away and separated from the IC and especially the quiet side of the IC. Separate the high dv/dt traces from sensitive small-signal nodes with ground traces or ground planes. 6. The INTVCC decoupling capacitor should be placed immediately adjacent to the IC between the INTVCC pin and PGND plane. A 1µF ceramic capacitor of the X7R or X5R type is small enough to fit very close to the IC to minimize the ill effects of the large current pulses drawn to drive the bottom MOSFETs. An additional 4.7µF to 10µF of ceramic, tantalum or other very low ESR capacitance is recommended in order to keep the internal IC supply quiet. 7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. 3875fb For more information www.linear.com/LTC3875 LTC3875 APPLICATIONS INFORMATION CLKOUT LTC3875 VOSNS1+ PGOOD PGOOD VPULL-UP PHASMD IFAST SNSA1 TG1 SNS1– SW1 L1 VOUT1 CB1 SNSD1+ M1 BOOST1 FREQ ILIM BG1 MODE/PLLIN RUN1 RIN 2.2Ω VIN 1µF EXTVCC SNS2– INTVCC SNSD2+ CINTVCC 4.7µF BG2 VOSNS2– VOSNS2+ VIN GND CIN COUT2 10µF ×2 CERAMIC M3 BOOST2 ITH2 COUT1 + SNSA2– 10µF ×2 CERAMIC CVIN 1µF PGND SGND D1 (OPT) + RUN2 M2 + VOSNS– + fIN RPU2 + ITH1 TK/SS1 M4 D2 (OPT) CB2 SW2 TG2 TK/SS2 VOUT2 L2 3875 F14 Figure 14. Recommended Printed Circuit Layout Diagram SW1 L1 D1 VOUT1 COUT1 RL1 VIN RIN CIN SW2 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. D2 L2 VOUT2 COUT2 RL2 3875 F15 Figure 15. Branch Current Waveforms For more information www.linear.com/LTC3875 3875fb 33 LTC3875 APPLICATIONS INFORMATION 8. Use a low impedance source such as a logic gate to drive the MODE/PLLIN pin and keep the lead as short as possible. 9. The 47pF to 330pF ceramic capacitor between the ITH pin and signal ground should be placed as close as possible to the IC. Figure 15 illustrates all branch currents in a switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. High electric and magnetic fields will radiate from these loops just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the noise generated by a switching regulator. The ground terminations of the synchronous MOSFET and Schottky diode should return to the bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. External OPTI-LOOP® compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure. PC Board Layout Debugging Start with one controller at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold— typically 10% of the maximum designed current level in Burst Mode® operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a sub-harmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is 34 not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. Design Example As a design example for a single output dual phase high current regulator, assume VIN = 12V(nominal), VIN = 20V (maximum), VOUT = 1.5V, IMAX1,2 = 30A, and f = 400kHz (see Figure 16). The regulated output voltages are determined by: R VOUT = 0.6 • 1+ B RA Shorting the VOSNS1+ pins and VOSNS2+ pins together. Using 20k, 1% resistor from VOSNS+ node to remote ground, the top feedback resistor is (to the nearest 1% standard value) 30.1k. 3875fb For more information www.linear.com/LTC3875 LTC3875 APPLICATIONS INFORMATION INTVCC 60k 20k 4.7µF THERMAL SENSOR INTVCC PHASMD CLKOUT PGOOD RUN1,2 IFAST ILIM ENTMPB MODE/PLLIN TG2 TG1 LTC3875 CB1 0.1µF L1 0.33µH (0.32mΩ DCR) R2 931Ω VIN D1 CMDSH-3 M1 BSC050NE2LS BOOST1 R1 4.64k M2 BSC010NE2LSI RTRSET1 10k 220nF 220nF VOUT + COUT3 470µF ×2 COUT4 100µF ×2 RTAVG 5k SW1 EXTVCC BG1 TAVG TRSET1 SNSA1+ SNS1– VIN 270µF 4.5V TO 20V 50V 10µF ×4 INTVCC D2 CMDSH-3 THERMAL SENSOR M3 BSC050NE2LS CB2 0.1µF L2 0.33µH (0.32mΩ DCR) BOOST2 SW2 M4 BSC010NE2LSI BG2 PGND TRSET2 SNSA2+ R1 4.64k R2 931Ω RTRSET2 10k SNS2– SNSD1+ TCOMP1 VOSNS1+ VOSNS1– ITH1 SNSD2+ TCOMP2 FREQ VOSNS2+ VOSNS2– ITH2 TK/SS1 TK/SS2 220nF 220nF RB 30.1k 1.5nF 100k 0.1µF 10k RA 20k COUT1 100µF ×2 + VOUT 1.5V 60A COUT2 470µF ×2 3875 F16 Figure 16. High Efficiency Dual Phase 400kHz, 1.5V/60A Step-Down Converter with Optional Thermal Balancing The frequency is set by biasing the FREQ pin to 1V (see Figure 12). The inductance values are based on a 35% maximum ripple current assumption (10.5A for each channel). The highest value of ripple current occurs at the maximum input voltage: L= VOUT VOUT 1– f • ∆IL(MAX) VIN(MAX) This design will require 0.33µH. The Würth 744301033, 0.32µH inductor is chosen. At the nominal input voltage (12V), the ripple current will be: ∆IL(NOM) = VOUT VOUT 1– f •L VIN(NOM) It will have 10A (33%) ripple. The peak inductor current will be the maximum DC value plus one-half the ripple current, or 35A. The minimum on-time occurs at the maximum VIN, and should not be less than 90ns: tON(MIN) = VOUT VIN(MAX) ( f ) = 1.5V = 187ns 20V ( 400kHz ) DCR sensing is used in this circuit. If C1 and C2 are chosen to be 220nF, based on the chosen 0.33µH inductor with 0.32mΩ DCR, R1 and R2 can be calculated as: L = 4.69k DCR •C1 L R2 = = 937Ω DCR •C2 • 5 R1= 3875fb For more information www.linear.com/LTC3875 35 LTC3875 APPLICATIONS INFORMATION Choose R1 = 4.64k and R2 = 931Ω. The maximum DCR of the inductor is 0.34mΩ. The VSENSE(MAX) is calculated as: VSENSE(MAX) = IPEAK • DCR (Max) = 12mV The current limit is chosen to be 15mV. If temperature variation is considered, please refer to Inductor DCR Sensing Temperature Compensation with NTC Thermistor. The power dissipation on the topside MOSFET can be easily estimated. Choosing an Infineon BSC050NE2LS MOSFET results in: RDS(ON) = 7.1mΩ (max), VMILLER = 2.8V, CMILLER ≅ 35pF. At maximum input voltage with TJ (estimated) = 75°C: PMAIN = 1.5V (30A )2 1+ (0.005)(75°C – 25°C) • 20V 30A (0.0071Ω) + (20V )2 (2Ω )(35pF ) • 2 1 1 + 5.5V – 2.8V 2.8V ( 400kHz ) = 599mW+122mW = 721mW For a 0.32mΩ DCR, a short-circuit to near ground will result in a folded back current of: ISC = 36 (1/ 3)15mV – 1 90ns (20V ) = 12.9A 0.0032Ω 2 0.33µH An Infineon BSC010NE2LS, RDS(ON) = 1.1mΩ, is chosen for the bottom FET. The resulting power loss is: PSYNC = 20V – 1.5V (30A )2 • 20V 1+ ( 0.005) • ( 75°C – 25°C) • 0.001Ω PSYNC = 1.14W CIN is chosen for an equivalent RMS current rating of at least 13.7A. COUT is chosen with an equivalent ESR of 4.5mΩ for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (∆IL) = 0.0045Ω • 10A = 45mVP-P Further reductions in output voltage ripple can be made by placing a 100µF ceramic capacitor across COUT. Thermal Balancing Converter Example If thermal balancing function is desired, connecting ENTMPB pin to ground enables the temperature balancing function, but disables the inductor DCR sensing temperature compensation function. For a 4-phase design select TRSET1,2,3,4 = 10k, then RTAVG = 2.5k. The resistance vs temperature slope of NTC connected to the TCOMP pin need to be modified according to the inductor current correction range. Please refer to temperature balancing with NTC thermistor example shown in Figure 17. 3875fb For more information www.linear.com/LTC3875 1% R19, 10k C11, 100pF VOSNS– VOSNS+ C12 1.5nF ITH R14 20k For more information www.linear.com/LTC3875 TAVG TRSET2 TRSET1 C16 220nF R13 V 13.3k FB C2 0.1µF TK/SS 38 37 36 TCOMP1 TRSET1 35 34 RUN R10 1k 33 INTVCC1 32 31 CLKOUT TAVG TRSET2 LTC3875 FREQ RUN2 IFAST ENTMPB R43, 2.49k R40, 10k R37, 10k 14 R32 100k 1% 15 THERMAL SENSOR THERMAL SENSOR TRSET2 16 RUN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C13 1µF INTVCC1 Q4 BSC010NE2LSI Q3 BSC050NE2LS C18 CMDSH-3 0.1µF INTVCC1 INTVCC1 C14 4.7µF 10V D2 VIN D1, CMDSH-3 R18, 2.2Ω C7 0.1µF Q1 BSC050NE2LS VIN CIN2 10µF 1210 R34 3.57k 1% CIN4 10µF 1210 L2 CIN5 10µF 1210 0.25µH DCR = 0.32mΩ 744301025 L1 R11 3.57k 1% R12 715Ω 1% 0.25µH DCR = 0.32mΩ R35 744301025 715Ω 1% VIN Q2 BSC010NE2LSI CIN3 10µF 1210 Figure 17a. 4-Phase 1.0V/120A Step-Down Converter with Thermal Balancing TCOMP2 TCOMP1 13 TAVG 12 TCOMP2 11 PGOOD SW2 TCOMP2 SGND/PGND SNSD2+ TG2 BOOST2 SNSA2+ SNS2– BG2 TK/SS2 INTVCC EXTVCC VOSNS2– VOSNS2+ VIN ITH2 BOOST1 VOSNS1– BG1 TG1 VOSNS1+ ITH1 SW1 TK/SS1 C19, 220nF 41 10 9 8 7 6 5 4 3 2 1 39 C4 220nF SNSA1+ SNS1– SNSD1+ TCOMP1 TRSET1 ILIM RUN1 MODE/PLLIN PHASMD CLKOUT 40 C3 220nF R9, 3.01k + + COUT3 100µF 6.3V 1210 ×2 + R20, 10Ω COUT1 100µF 6.3V 1210 ×2 R16, 10Ω VIN VIN J2 COUT4 330µF 2.5V 7343 ×2 VOSNS– COUT2 330µF 2.5V 7343 ×2 GND VOUT 1V/120A 3875 F17a VOUT J4 J3 GND VIN 4.5V TO 14V VOUT VOSNS+ CIN1 270µF 16V J1 LTC3875 TYPICAL APPLICATIONS 3875fb 37 38 C17, 100pF ITH VOSNS– For more information www.linear.com/LTC3875 TK/SS TRSET4 TRSET3 C24 220nF VFB 39 C9 220nF 38 37 36 TCOMP3 TRSET3 35 34 RUN 33 CLKOUT INTVCC2 32 31 TAVG TRSET2 FREQ RUN2 IFAST ENTMPB 12 R41, 10k R38, 10k 13 R33 100k 1% 15 THERMAL SENSOR 16 RUN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C15 1µF INTVCC2 INTVCC2 Q7 BSC010NE2LSI Q6 BSC050NE2LS C20 CMDSH-3 0.1µF INTVCC2 C23 4.7µF 10V D4 VIN D3, CMDSH-3 R21, 2.2Ω C8 0.1µF Q8 BSC050NE2LS VIN CIN7 10µF 1210 R39 3.57k 1% CIN9 10µF 1210 L3 L4 CIN8 10µF 1210 0.25µH DCR = 0.32mΩ 744301025 R23 3.57k 1% R15 715Ω 1% 0.25µH DCR = 0.32mΩ R36 744301025 715Ω 1% VIN Q5 BSC010NE2LSI CIN6 10µF 1210 Figure 17b. 4-Phase 1.0V/120A Step-Down Converter with Thermal Balancing TCOMP4 14 TRSET4 THERMAL SENSOR TAVG TCOMP3 TCOMP4 11 PGOOD SW2 TCOMP2 SNSD2+ SGND/PGND SNSA2+ TG2 BG2 BOOST2 TK/SS2 SNS2– EXTVCC VOSNS2– INTVCC VIN VOSNS2+ BG1 BOOST1 VOSNS1– ITH2 TG1 VOSNS1+ ITH1 SW1 TK/SS1 LTC3875 SNSA1+ SNS1– SNSD1+ TCOMP1 TRSET1 ILIM RUN1 MODE/PLLIN PHASMD CLKOUT C21, 220nF 41 10 9 8 7 6 5 4 3 2 1 40 C6 220nF R17, 3.01k R22 1k + COUT15 100µF 6.3V 1210 ×2 COUT9 100µF 6.3V 1210 ×2 + COUT13 330µF 2.5V 7343 ×2 COUT10 330µF 2.5V 7343 ×2 3875 F17b VOUT VOUT LTC3875 TYPICAL APPLICATIONS 3875fb 1% R19, 20k C11, 100pF VOSNS– VOSNS + C12 2.2nF ITH R14 20k For more information www.linear.com/LTC3875 TAVG TRSET2 TRSET1 C16 220nF R13 VFB 147k C2 0.1µF TK/SS 38 37 36 35 34 RUN 33 32 31 CLKOUT TAVG TRSET2 RUN2 IFAST ENTMPB BOOST1 VOSNS1– LTC3875 TG1 VOSNS1+ FREQ R43, 5k R40, 10k 14 R32 100k 1% 15 THERMAL SENSOR THERMAL SENSOR TRSET2 16 RUN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C13 1µF INTVCC1 Q4 BSC010NE2LSI Q3 BSC024NE2LS C18 CMDSH-3 0.1µF INTVCC1 INTVCC1 C14 4.7µF 10V D2 VIN D1, CMDSH-3 R18, 2.2Ω C7 0.1µF Q1 BSC024NE2LS VIN CIN3 10µF 1210 CIN2 10µF 1210 R35 3.48k 1% CIN4 10µF 1210 VIN Q2 BSC010NE2LSI Figure 18. 5.0V/50A 2-Phase Step-Down Converter with Remote Sensing TCOMP2 TCOMP1 13 TAVG 12 TCOMP2 11 PGOOD SW2 TCOMP2 SNSD2+ SGND/PGND SNSA2+ TG2 BG2 BOOST2 TK/SS2 SNS2– EXTVCC VOSNS2– INTVCC VIN ITH2 VOSNS2 BG1 ITH1 + SW1 TK/SS1 R37, 10k 41 10 9 8 7 6 5 4 3 2 1 39 TCOMP1 TRSET1 SNSA1+ SNS1– SNSD1+ TCOMP1 TRSET1 ILIM RUN1 MODE/PLLIN PHASMD CLKOUT 40 C3 220nF L1 1µH DCR = 1.3mΩ L2 CIN5 10µF 1210 1µH DCR = 1.3mΩ R12 3.48k 1% + + COUT7 100µF 6.3V 1210 ×2 + R20, 10Ω COUT3 100µF 6.3V 1210 ×2 R16, 10Ω VIN VIN J2 COUT5 330µF 6.3V 7343 ×2 VOSNS– COUT2 330µF 6.3V 7343 ×2 GND VOUT 5V/50A 3875 F18 VOUT J4 J3 GND VIN 11V TO 13V VOUT VOSNS+ CIN1 270µF 16V J1 LTC3875 TYPICAL APPLICATIONS 3875fb 39 40 1% R19, 10k C11, 100pF VOSNS – VOSNS+ C12 1.5nF ITH R14 20k C16 47nF R13 VFB 13.3k C2 0.1µF TK/SS + 38 37 36 TCOMP1 TRSET1 35 34 RUN INTVCC 33 32 31 CLKOUT TAVG TRSET2 FREQ RUN2 IFAST ENTMPB For more information www.linear.com/LTC3875 14 TRSET2 R32 100k 1% 15 16 RUN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C13 1µF C18 CMDSH-3 0.1µF C14 4.7µF 10V D2 VIN D1, CMDSH-3 R18, 2.2Ω C7 0.1µF INTVCC INTVCC INTVCC U103 VRA001-4COG 11 1 VOUT1 VIN1 12 7 VIN2 VOUT2 5 PWMH 15 4 PWML TEMPP 14 3 VGATE TEMPN 2 GND 6 10 GND CN 9 8 GND CP 13 GND R34 4.75k 1% R11 4.75k 1% U102 VRA001-4COG 11 1 VOUT1 VIN1 12 7 VIN2 VOUT2 5 PWMH 15 4 PWML TEMPP 14 3 VGATE TEMPN 2 GND 6 10 GND CN 9 8 GND CP 13 GND CIN3 10µF 1210 CIN2 10µF 1210 Figure 19. 1.0V/80A 2-Phase High Efficiency Step-Down Converter with AcBel Power Block 13 TAVG 12 TCOMP2 11 PGOOD SW2 TCOMP2 SNSD2+ SGND/PGND BOOST2 SNSA2+ TG2 BG2 TK/SS2 SNS2– EXTVCC INTVCC VOSNS2– VOSNS2 VIN LTC3875 BG1 ITH2 BOOST1 TG1 SW1 ITH1 + VOSNS1– VOSNS1 TK/SS1 C19, 47nF 41 10 9 8 7 6 5 4 3 2 1 39 C4 47nF SNSA1+ SNS1– SNSD1+ TCOMP1 TRSET1 ILIM RUN1 MODE/PLLIN PHASMD CLKOUT 40 C3 47nF VIN CIN4 10µF 1210 + + COUT3 100µF 6.3V 1210 ×2 CIN5 10µF 1210 3875 F19 VIN R20, 10Ω COUT1 100µF 6.3V 1210 ×2 R16, 10Ω VIN VIN J2 + GND COUT4 330µF 2.5V 7343 ×2 VOSNS– COUT2 330µF 2.5V 7343 ×2 GND VOUT J4 VOUT 1V/80A VIN 7V TO 14V VOUT J3 VOSNS+ CIN1 270µF 16V J1 LTC3875 TYPICAL APPLICATIONS 3875fb 1% R19 174k VO2SNS– R25 20k C17 68pF C12 220pF C9 10pF C11, 10pF VO2SNS+ R21 90.9k R15 174k 1% C8 220pF VO1SNS– VO1SNS+ C21 0.1µF R39 50Ω R14 20k R13 63.4k C16 470nF For more information www.linear.com/LTC3875 TRSET2 40 C3 470nF 39 C4 1nF 38 37 36 TCOMP1 TRSET1 35 34 R10 1k R9, 1k 33 INTVCC 32 31 + TAVG LTC3875 TRSET2 FREQ RUN2 IFAST ENTMPB 14 2µs/DIV R43, 5k TRSET2 3.1mV R32 100k 1% 15 17 19 VIN = 25V VOUT = 2.5V/2A THERMAL SENSOR 18 VO 10mV/DIV TCOMP1 3875 F20b 16 PGOOD 20 21 22 23 24 25 26 27 28 29 30 2µs/DIV VIN INTVCC 3.8mV INTVCC 3875 F20c L2 CIN5 10µF 1210 CIN2 10µF 1210 VIN R35 402Ω 1% 11µH DCR = 15.8mΩ VIN THERMAL SENSOR Q103 FDMS3610S C18 CMDSH-3 0.1µF INTVCC C14 4.7µF 10V D2 TCOMP2 C13 1µF R18, 2.2Ω CMDSH-3 D1 C7 0.1µF Q102 FDMS3610S Figure 20. Dual Output Ultralow Ripple 2.5V/2A, 3.3V/2A Step-Down Converter VO 5mV/DIV R40, 10k R37, 10k VIN = 12V VOUT = 2.5V/2A 12 TCOMP2 11 TAVG 13 TAVG TCOMP2 SNSD2+ TG2 SW2 SNSA2+ SGND/PGND BG2 BOOST2 TK/SS2 SNS2– EXTVCC VOSNS2– INTVCC VIN ITH2 VOSNS2+ BG1 BOOST1 TG1 SW1 ITH1 VOSNS1– VOSNS1 TK/SS1 SNSA1+ SNS1– SNSD1+ TCOMP1 TRSET1 ILIM RUN1 MODE/PLLIN PHASMD CLKOUT C19, 1nF 41 10 9 8 7 6 5 4 3 2 1 TRSET1 C15 68pF C2 0.1µF R38 50Ω R34 10Ω 1% RS2 0.006Ω RS1 0.006Ω R17 10Ω 1% + VO2SNS– COUT5 330µF 2.5V 7343 J2 GND VIN 12V TO 25V GND VOUT1 2.5V/2A J6 J5 3875 F20a GND VOUT2 3.3V/2A VO1SNS– COUT2 330µF 2.5V 7343 J4 J3 VO1SNS+ R20, 10Ω COUT1 100µF 6.3V 1210 + VOUT1 R16, 10Ω + J1 CIN1 270µF 16V VO2SNS+ VOUT2 R36, 10Ω COUT8 100µF 6.3V 1210 R24, 10Ω 11µH DCR = 15.8mΩ L1 R12 402Ω 1% VIN VIN LTC3875 TYPICAL APPLICATIONS 3875fb 41 42 VO2SNS– R25 20k R21 30.1k VO2SNS+ 1% R19 10k C11, 150pF R15 10k 1% C21 0.1µF C12 1.5nF C9 150pF C8, 1.5nF VO1SNS– VO1SNS+ C16 220nF R14 20k R13 13.3k 39 C4 220nF 38 37 36 TCOMP1 TRSET1 35 34 R10 1k 33 INTVCC 32 31 TAVG TRSET2 FREQ RUN2 IFAST ENTMPB TCOMP2 For more information www.linear.com/LTC3875 THERMAL SENSOR R32 100k 1% 15 16 17 18 19 PGOOD SW2 20 21 22 23 24 25 26 27 28 29 30 C13 1µF INTVCC C14 4.7µF 10V D2 VIN INTVCC Q1 BSC050NE2LS INTVCC Q2 BSC010NE2LSI Q4 BSC010NE2LSI C18 CMDSH-3 0.1µF Q3 BSC050NE2LS R18, 2.2Ω CMDSH-3 D1 C7 0.1µF R34 4.64Ω 1% L1 + R36, 10Ω COUT3 100µF 6.3V 1210 ×2 R24, 10Ω 0.25µH 744301025 DCR = 0.32mΩ R12 715 1% 3875 F21 CIN2 10µF 1210 R11 3.57k 1% CIN5 10µF 1210 R35 931Ω 1% 0.33µH 744301033 DCR = 0.32mΩ L2 VIN CIN3 10µF 1210 CIN4 10µF 1210 Figure 21. Dual Output 1V/30A, 1.5V/30A Step-Down Converter with Remote Sensing TCOMP2 TRSET2 THERMAL SENSOR TAVG 12 11 TCOMP1 13 TCOMP2 SNSD2+ SGND/PGND 14 BOOST2 SNSA2+ TG2 BG2 TK/SS2 SNS2– EXTVCC VOSNS2– INTVCC VIN VOSNS2+ ITH2 BOOST1 VOSNS1– BG1 TG1 VOSNS1+ ITH1 SW1 TK/SS1 LTC3875 SNSA1+ SNS1– SNSD1+ TCOMP1 TRSET1 ILIM RUN1 MODE/PLLIN PHASMD CLKOUT 40 C19, 220nF 41 10 9 8 7 6 5 4 3 2 1 C2 0.1µF C3 220nF R9, 3.01k + VO2SNS– COUT4 330µF 2.5V 7343 ×2 VOUT2 VO2SNS+ R20, 10Ω COUT1 100µF 6.3V 1210 ×2 + VOUT1 J1 GND J6 J5 GND VOUT2 1.5V/30A VO1SNS– COUT2 330µF 2.5V 7343 ×2 J4 J3 GND VOUT1 1V/30A VIN 4.5V TO 14V VO1SNS+ CIN1 270µF 16V J2 R16, 10Ω VIN VIN LTC3875 TYPICAL APPLICATIONS 3875fb LTC3875 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC3875#packaging for the most recent package drawings. UH Package 40-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1746 Rev B) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.50 ±0.05 3.60 REF (4 SIDES) 3.50 ±0.05 PACKAGE OUTLINE 0.20 ±0.05 0.40 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ±0.10 (4 SIDES) 0.75 ±0.05 R = 0.05 TYP R = 0.100 TYP 39 40 0.40 ±0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 3.60 REF (4-SIDES) 3.50 ±0.10 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 3.50 ±0.10 (UH40) QFN REV B 0415 0.200 REF 0.20 ± 0.05 0.00 – 0.05 NOTE: 1. DRAWING CONFIRMS TO JEDEC PACKAGE OUTLINE MO-220 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE 0.40 BSC BOTTOM VIEW—EXPOSED PAD 3875fb For more information www.linear.com/LTC3875 43 LTC3875 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC3875#packaging for the most recent package drawings. UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 ±0.05 6.50 ±0.05 5.10 ±0.05 4.42 ±0.05 4.50 ±0.05 (4 SIDES) 4.42 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 ±0.10 (4 SIDES) 0.75 ±0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 ±0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 4.50 REF (4-SIDES) 4.42 ±0.10 2 PIN 1 NOTCH R = 0.45 OR 0.35 × 45° CHAMFER 4.42 ±0.10 (UJ40) QFN REV Ø 0406 0.200 REF 0.25 ±0.05 0.00 – 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 44 0.50 BSC BOTTOM VIEW—EXPOSED PAD 3875fb For more information www.linear.com/LTC3875 LTC3875 REVISION HISTORY REV DATE DESCRIPTION A 4/15 Corrected typographical errors 1 to 30 Modifications to figures 28 to 35 Simplified schematics 36 to 44 B 11/15 PAGE NUMBER 1, 2, 3, 5, 43 Added UH Package Removed Temp Dot from ISENSE(AC) 3 3875fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more information www.linear.com/LTC3875 tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 45 LTC3875 TYPICAL APPLICATION High Efficiency Dual Phase 1V/60A Step-Down Converter INTVCC 4.7µF (OPTIONAL) BSC050NE2LS THERMAL SENSOR 0.1µF 0.25µH (0.32mΩ DCR) 715 3.57k BSC010NE2LSI 220nF 220nF VOUT + 470µF 2.5V ×2 SP VIN 22µF 6V TO 14V 16V ×4 VIN INTVCC PHASMD CLKOUT PGOOD RUN1,2 IFAST ILIM ENTMPB MODE/PLLIN TG2 TG1 BOOST1 (OPTIONAL) BSC050NE2LS 0.1µF BOOST2 SW1 LTC3875 SW2 EXTVCC BG2 BG1 TAVG PGND TRSET1 TRSET2 SNSA1+ SNSA2+ SNS1– SNS2– SNSD1+ SNSD2+ TCOMP1 TCOMP2 VOSNS1+ FREQ VOSNS1– VOSNS2+ – ITH1 V TK/SS1 TK/SS2 BSC010NE2LSI 0.25µH (0.32mΩ DCR) 3.57k 715 220nF 220nF VOUT 1.2V 60A 13.3k OSNS2 ITH2 0.1µF THERMAL SENSOR 1500pF 100k 10k 20k + 470µF 2.5V ×2 SP 3875 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3774 Dual, Multiphase Current Mode Synchronous Step-Down DC/DC Controller for Sub-Milliohm DCR Sensing Operates with DrMOS, Power Blocks or External Drives/MOSFETs, 4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V LTC3866 Single Output Current Mode Synchronous Controller with Sub-Milliohm DCR Sensing Synchronous Fixed Frequency 250kHz to 770kHz, 4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V LTC3855 Dual, Multiphase, Synchronous Step-Down DC/DC Controller with Differential Output Sensing and DCR Temperature Compensation PLL Fixed Frequency 250kHz to 770kHz, 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12V LTC3838/LTC3838-1/ LTC3838-2 Dual, Fast, Accurate Step-Down Controlled On-Time DC/DC Controller with Differential Output Sensing Synchronizable Fixed Frequency 200kHz to 2MHz, 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.5V LTC3890/LTC3890-1/ Dual, High VIN, Low IQ 2-Phase Synchronous Step-Down DC/DC LTC3890-2/LTC3890-3 Controller PLL Capable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA LTC3861/LTC3861-1 Dual, Multiphase, Synchronous Step-Down Voltage Mode DC/DC Controller with Diff Amp and Accurate Current Sharing Operates with DrMOS, Power Blocks or External Drivers/MOSFETs, 3V ≤ VIN ≤ 24V LTC3856 Single Output, Dual Channel Synchronous Step-Down DC/DC Controller Phase-Lockable Fixed 250kHz to 770kHz Frequency, with Differential Output Sensing and DCR Temperature Compensation 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5V LTC3869 Dual 2-Phase, Synchronous Step-Down DC/DC Controller Synchronous Fixed Frequency 250kHz to 780kHz, 4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 12.5V LTC3857/LTC3857-1 LTC3858/LTC3858-1 38V Low IQ, Dual Output 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle PLL Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA/170µA 46 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC3875 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3875 3875fb LT 1115 REV B • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013