204pin DDR3 SDRAM SODIMM
DDR3 SDRAM
Unbuffered SODIMM
Based on 2Gb M version
HMT451S6MMP(R)8C
** Contents are subject to change without prior notice.
Rev. 0.2 / Apr. 2009
1
HMT451S6MMP(R)8C
Revision History
Revision No.
History
Draft Date
0.1
Initial Release
Oct. 2008
0.2
IDD Update
Apr. 2009
Rev. 0.2 / Apr. 2009
Remark
2
HMT451S6MMP(R)8C
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Features
1.1.2 Ordering Information
1.2 Speed Grade & Key Parameters
1.3 Address Table
2. Pin Architecture
2.1 Pin Definition
2.2 Input/Output Functional Description
2.3 Pin Assignment
3. Functional Block Diagram
3.1 4GB, 512Mx64 Module(2Rank of x8)
4. Absolute Maximum Ratings
4.1 Absolute Maximum DC Ratings
4.2 Operating Temperature Range
5. AC & DC Operating Conditions
5.1 Recommended DC Operating Conditions
5.2 DC & AC Logic Input Levels
5.2.1 For Single-ended Signals
5.2.2 For Differential Signals
5.2.3 Differential Input Cross Point
5.3 Slew Rate Definition
5.3.1 For Ended Input Signals
5.3.2 For Differential Input Signals
5.4 DC & AC Output Buffer Levels
5.4.1 Single Ended DC & AC Output Levels
5.4.2 Differential DC & AC Output Levels
5.4.3 Single Ended Output Slew Rate
5.4.4 Differential Ended Output Slew Rate
5.5 Overshoot/Undershoot Specification
5.5.1 Address and Control Overshoot and Undershoot Specifications
5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
5.6 Input/Output Capacitance & AC Parametrics
5.7 IDD Specifications & Measurement Condtiions
6. Electrical Characteristics and AC Timing
6.1 Refresh Parameters by Device Density
6.2 DDR3 Standard speed bins and AC para
7. DIMM Outline Diagram
7.1 4GB, 512Mx64 Module(2Rank of x8)
Rev. 0.2 / Apr. 2009
3
HMT451S6MMP(R)8C
1. Description
This Hynix unbuffered Small Outline Dual In-Line Memory Module (SODIMM) series consists of 2Gb M version. DDR3
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered SODIMM
series based on 2Gb M ver. provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• VDD=VDDQ=1.5V
• VDDSPD=3.0V to 3.6V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with
CK transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
• BL switch on the fly
• 8 banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package: JEDEC standard 82ball
FBGA(x4/x8) with support balls
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Programmable additive latency 0, CL-1 and CL-2 supported
• Write Levelization supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• 8 bit pre-fetch
• Auto Self Refresh supported
1.1.2 Ordering Information
Density
Organization
# of
DRAMs
# of
ranks
Materials
HMT451S6MMP8C-S6/G7*
4GB
512Mx64
16
2
Lead free
HMT451S6MMR8C-S6/G7*
4GB
512Mx64
16
2
Halogen free
Part Name
*Information on temperature sensor can be found on the label:
T0 indicates that the DIMM has temperature sensor.
N0 indicates that the DIMM does not have temperature sensor.
Rev. 0.2 / Apr. 2009
4
HMT451S6MMP(R)8C
1.2 Speed Grade & Key Parameters
MT/S
DDR3-800
DDR3-1066
Grade
-S6
-G7
tCK (min)
2.5
1.875
ns
CAS Latency
6
7
tCK
tRCD (min)
15
13.125
ns
tRP (min)
15
13.125
ns
tRAS (min)
37.5
37.5
ns
tRC (min)
52.5
50.625
ns
CL-tRCD-tRP
6-6-6
7-7-7
tCK
Unit
1.3 Address Table
4GB
Organization
512M x 64
Refresh Method
8K/64ms
Row Address
A0-A14
Column Address
A0-A9
Bank Address
BA0-BA2
Page Size
1KB
# of Rank
2
# of Device
16
Rev. 0.2 / Apr. 2009
5
HMT451S6MMP(R)8C
2. Pin Architecture
2.1 Pin Definition
Pin Name
Description
Pin Name
Description
CK[1:0]
Clock Inputs, positive line
2
DQ[63:0]
Data Input/Output
64
CK[1:0]
Clock Inputs, negative line
2
DM[7:0]
Data Masks
8
CKE[1:0]
Clock Enables
2
DQS[7:0]
Data strobes
8
RAS
Row Address Strobe
1
DQS[7:0]
Data strobes complement
8
CAS
Column Address Strobe
1
RESET
Reset pin
1
WE
Write Enable
1
TEST
Logic Analyzer specific test pin (No
1
connect on SODIMM)
S[1:0]
Chip Selects
2
EVENT
Address Inputs
14
Address Input/Autoprecharge
A[9:0], A11,
A[15:13]
A10/AP
Temperature event pin
1
VDD
Core and I/O power
18
1
VSS
Ground
52
Input/Output Reference
2
SPD and Temp sensor power
1
A12/BC
Address Input/Burst Stop
1
VREFDQ
BA[2:0]
SDRAM Bank Address
3
VREFCA
On-die termination control
2
VDDSPD
ODT[1:0]
SCL
Serial Presence Detect (SPD) Clock
1
input
Vtt
Termination voltage
2
SDA
SPD Data Input/Output
1
NC
Reserved for future use
2
SPD address
2
SA[1:0]
Rev. 0.2 / Apr. 2009
Total
204
6
HMT451S6MMP(R)8C
2.2 Input/Output Functional Description
Symbol
Type
Polarity
Function
The system clock inputs. All address and command lines are sampled on the cross
CK0/CK0
CK1/CK1
Input
Cross point
point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock.
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when
CKE[1:0]
Input
Active High
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Enables the associated DDR3 SDRAM command decoder when low and disables the
S[1:0]
Input
Active Low
command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank
1 is selected by S1.
RAS, CAS, WE
Input
Active Low
BA[2:0]
Input
-
ODT[1:0]
Input
Active High
When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define the operation to be executed by the SDRAM.
Selects which DDR3 SDRAM internal bank of eight is activated.
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR3 SDRAM mode register.
During a Bank Activate command cycle, defines the row address when sampled at
the cross point of the rising edge of CK and falling edge of CK. During a Read or
Write command cycle, defines the column address when sampled at the cross point
of the rising edge of CK and falling edge of CK. In addition to the column address,
A[9:0], A10/AP,
A11, A12/BC,
A[15:13]
AP is used to invoke autoprecharge operation at the end of the burst read or write
Input
-
cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be
precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to
precharge. If AP is high, all banks will be precharged regardless of the state of BA0BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
A12(BC) is sampled during READ and WRITE commands to determine if burst chop
(on-thefly) will be performed (HIGH, no burst chop; LOW, burst chopped)
DQ[63:0]
In/Out
-
DM[7:0]
Input
Active High
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates
as a byte mask by allowing input data to be written if it is low but blocks the write
operation if it is high. In Read mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In
DQS[7:0],
DQS[7:0]
Write mode, the data strobe is sourced by the controller and is centered in the data
In/Out
Cross Point
window. In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent
at the leading edge of the data window. DQS signals are complements, and timing is
relative to the crosspoint of respective DQS and DQS.
Rev. 0.2 / Apr. 2009
7
HMT451S6MMP(R)8C
Symbol
Type
VDD,VDDSPD,
VSS,
Supply
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for
the module.
Supply
Reference voltage for SSTL15 inputs.
VREFDQ,
VREFCA
Polarity
Function
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and
SDA
In/Out
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA[1:0]
Input
Address pins used to select the Serial Presence Detect and Temp sensor base
address.
TEST
In/Out
EVENT
Wire OR
Out
Active Low
RESET
In
Active Low
Temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the
system planar to act as a pull up.
Rev. 0.2 / Apr. 2009
The TEST pin is reserved for bus analysis tools and is not connected on normal
memory modules (SO-DIMMs).
The EVENT pin is reserved for use to flag critical module temperature. A resistor
may be connected from EVENT bus line to VDDSPD on the system planar to act as a
pullup.
This signal resets the DDR3 SDRAM
8
HMT451S6MMP(R)8C
2.3 Pin Assignment
Pin
#
Front
Side
Pin
#
Back
Side
Pin
#
Front
Side
Pin
#
Back
Side
Pin
#
Front
Side
Pin
#
Back
Side
Pin
#
Front
Sid
Pin
#
Back
Side
1
VREFDQ
2
VSS
53
DQ19
54
VSS
105
VDD
106
VDD
157
DQ42
158
DQ46
3
VSS
4
DQ4
55
VSS
56
DQ28
107 A10/AP 108
BA1
159
DQ43
160
DQ47
5
DQ0
6
DQ5
57
DQ24
58
DQ29
109
BA0
110
RAS
161
VSS
162
VSS
7
DQ1
8
VSS
59
DQ25
60
VSS
111
VDD
112
VDD
163
DQ48
164
DQ52
9
VSS
10
DQS0
61
VSS
62
DQS3
113
WE
114
S0
165
DQ49
166
DQ53
11
DM0
12
DQS0
63
DM3
64
DQS3
115
CAS
116
ODT0
167
VSS
168
VSS
13
VSS
14
VSS
65
VSS
66
VSS
117
VDD
118
VDD
169
DQS6
170
DM6
15
DQ2
16
DQ6
67
DQ26
68
DQ30
119
A132
120
ODT1
171
DQS6
172
VSS
17
DQ3
18
DQ7
69
DQ27
70
DQ31
121
S1
122
NC
173
VSS
174
DQ54
19
VSS
20
VSS
71
VSS
72
VSS
123
VDD
124
VDD
175
DQ50
176
DQ55
21
DQ8
22
DQ12
73
CKE0
74
CKE1
125
TEST
126 VREFCA 177
DQ51
178
VSS
23
DQ9
24
DQ13
75
VDD
76
VDD
127
VSS
128
VSS
179
VSS
180
DQ60
25
VSS
26
VSS
77
NC
78
A152
129
DQ32
130
DQ36
181
DQ56
182
DQ61
27
DQS1
28
DM1
79
BA2
80
A142
131
DQ33
132
DQ37
183
DQ57
184
VSS
29
DQS1
30
RESET
81
VDD
82
VDD
133
VSS
134
VSS
185
VSS
186
DQS7
31
VSS
32
VSS
83 A12/BC
84
A11
135
DQS4
136
DM4
187
DM7
188
DQS7
33
DQ10
34
DQ14
85
A9
86
A7
137
DQS4
138
VSS
189
VSS
190
VSS
35
DQ11
36
DQ15
87
VDD
88
VDD
139
VSS
140
DQ38
191
DQ58
192
DQ62
37
VSS
38
VSS
89
A8
90
A6
141
DQ34
142
DQ39
193
DQ59
194
DQ63
39
DQ16
40
DQ20
91
A5
92
A4
143
DQ35
144
VSS
195
VSS
196
VSS
41
DQ17
42
DQ21
93
VDD
94
VDD
145
VSS
146
DQ44
197
SA0
198
EVENT
43
VSS
44
VSS
95
A3
96
A2
147
DQ40
148
DQ45
199 VDDSPD 200
SDA
45
DQS2
46
DM2
97
A1
98
A0
149
DQ41
150
VSS
201
SA1
202
SCL
47
DQS2
48
VSS
99
VDD
100
VDD
151
VSS
152
DQS5
203
VTT
204
VTT
49
VSS
50
DQ22
101
CK0
102
CK1
153
DM5
154
DQS5
51
DQ18
52
DQ23
103
CK0
104
CK1
155
VSS
156
VSS
NC = No Connect; RFU = Reserved Future Use
1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
Rev. 0.2 / Apr. 2009
9
HMT451S6MMP(R)8C
240ohm
+/-1%
(SPD)
A[O:N]/BA[O:N]
SPD/TS
VREFCA
VREFDQ
D0–D15
VDD
D0–D15
VSS
D0–D7, SPD, TS
CK0
D0–D3, D8-D11
CK1
D4–D7, D12-D15
CK0
D0–D3, D8-D11
D0–D15
CK1
CKE0
D4–D7, D12-D15
CKE1
D8–D15
D0–D7
S0
D0–D7
S1
D8–D15
D0–D7
ODT0
ODT1
V1
D8–D15
EVENT
Temp Sensor
RESET
D0-D15
D4,D12
V2
D5,D13
V3
D6,D14
V4
D7,D15
D0,D8
NOTES
V2
D1,D9
V3
D2,D10
V4
D3,D11
Vtt
V1
ODT0/ODT1
CK
CKE0/CKE1
CK
D7,D15
(Stacked)
WE
Vtt
VDDSPD
240ohm
+/-1%
A[O:N]/BA[O:N]
ZQ
ODT0/ODT1
CK
CKE0/CKE1
CK
WE
CAS
RAS
DQS
DQS
DM
DQ [0:7]
A[O:N]/BA[O:N]
ODT0/ODT1
CK
CKE0/CKE1
CK
CAS
WE
ZQ
240ohm
+/-1%
D6,D14
(Stacked)
CS0/CS1
DQS7
DQS7
DM7
DQ [56:63]
RAS
CS
DQS
DQS
DM
DQ [0:7]
CAS
ODT0/ODT1
CK
CKE0/CKE1
WE
CK
CAS
D3,D11
(Stacked)
DQS5
DQS5
DM5
DQ [40:47]
ZQ
240ohm
+/-1%
D5,D13
(Stacked)
RAS
240ohm
+/-1%
DQS
DQS
DM
DQ [0:7]
CS0/CS1
ZQ
ODT0/ODT1
CK
CKE0/CKE1
CK
WE
CAS
RAS
CS0/CS1
DQS
DQS
DM
DQ [0:7]
A[O:N]/BA[O:N]
240ohm
+/-1%
D2,D10
(Stacked)
DQS3
DQS3
DM3
DQ [24:31]
A[O:N]/BA[O:N]
ZQ
ODT0/ODT1
CK
CKE0/CKE1
CK
WE
CAS
DQS
DQS
DM
DQ [0:7]
CS0/CS1
DQS6
DQS6
DM6
DQ [48:55]
RAS
CS0/CS1
D1,D9
(Stacked)
RAS
DQS4
DQS4
DM4
DQ [32:39]
ZQ
240ohm
+/-1%
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
SDA
WP
Vtt
ODT0/ODT1
CK
CKE0/CKE1
SCL
A0
A1
A2
SCL
SA0
SA1
Vtt
DQS2
DQS2
DM2
DQ [16:23]
SDA
EVENT
D4,D12
(Stacked)
WE
SCL
A0 Temp Sensor
(with SPD)
A1
A2
EVENT
SCL
SA0
SA1
A[O:N]/BA[O:N]
CK1
CK1
ZQ
CK
DQS
DQS
DM
DQ [0:7]
CAS
DQS1
DQS1
DM1
DQ [8:15]
RAS
ODT0/ODT1
CK
CKE0/CKE1
CK
WE
RAS
CAS
D0,D8
(Stacked)
CS0/CS1
A[O:N]/BA[O:N]
240ohm
+/-1%
CS0/CS1
ZQ
ODT0/ODT1
CK0
CKE0/CKE1
WE
CK0
CAS
DQS
DQS
DM
DQ [0:7]
The SPD may be
integrated with the Temp Sensor or may be
a separate component
A[O:N]/BA[O:N]
DQS0
DQS0
DM0
DQ [0:7]
RAS
S0/S1
3.1 4GB, 512Mx64 Module(2Rank of x8)
Address and Control Lines
1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are
maintained as shown
Vtt
Rank 0
Rank 1
Vtt
VDD
Rev. 0.2 / Apr. 2009
VDD
10
HMT451S6MMP(R)8C
4. ABSOLUTE MAXIMUM RATINGS
4.1 Absolute Maximum DC Ratings
Symbol
Parameter
VDD
VDDQ
VIN, VOUT
TSTG
Rating
Units
Notes
Voltage on VDD pin relative to Vss
- 0.4 V ~ 1.975 V
V
,3
Voltage on VDDQ pin relative to Vss
- 0.4 V ~ 1.975 V
V
,3
Voltage on any pin relative to Vss
- 0.4 V ~ 1.975 V
V
-55 to +100 ℃
℃
Storage Temperature
,2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
4.2 DRAM Component Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Units
Notes
Normal Temperature Range
0 to 85
℃
,2
Extended Temperature Range
85 to 95
℃
1,3
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM.
For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating
conditions
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85°… and
95°… case temperature.
Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.
(This double refresh requirement may not apply for some devices.) It is also possible to specify a component
with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to supplier data sheet and/
or the DIMM SPD for option avail ability.
b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or
enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
Rev. 0.2 / Apr. 2009
11
HMT451S6MMP(R)8C
5. AC & DC Operating Conditions
5.1 Recommended DC Operating Conditions
Symbol
Parameter
VDD
VDDQ
Rating
Units
Notes
1.575
V
1,2
1.575
V
1,2
Min.
Typ.
Max.
Supply Voltage
1.425
1.500
Supply Voltage for Output
1.425
1.500
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
5.2 DC & AC Logic Input Levels
5.2.1 DC & AC Logic Input Levels for Single-Ended Signals
DDR3-800, DDR3-1066
Symbol
Parameter
Unit
Notes
-
V
1, 2
Vref - 0.100
V
1, 2
-
V
1, 2
Vref - 0.175
V
1, 2
Min
Max
Vref + 0.100
VIH(DC)
DC input logic high
VIL(DC)
DC input logic low
VIH(AC)
AC input logic high
VIL(AC)
AC input logic low
VRefDQ (DC)
Reference Voltage for
DQ, DM inputs
0.49 * VDD
0.51 * VDD
V
3, 4
VRefCA (DC)
Reference Voltage for
ADD, CMD inputs
0.49 * VDD
0.51 * VDD
V
3, 4
VTT
Termination voltage for
DQ, DQS outputs
VDDQ/2 - TBD
VDDQ/2 + TBD
V
Vref + 0.175
1. For DQ and DM, Vref = VrefDQ. For input only pins except RESET#, Vref = VrefCA.
2. The “t.b.d.” entries might change based on overshoot and undershoot specification.
3. The ac peak noise on VRef may not allow VRef to deviate from VRef (DC) by more than +/-1% VDD
(for reference: approx. +/- 15 mV).
For reference: approx. VDD/2 +/- 15 mV.
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure
5.2.1. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise).VRef(DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet
the min/max requirements in Table 1. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than
+/- 1% VDD.
Rev. 0.2 / Apr. 2009
12
HMT451S6MMP(R)8C
voltage
VDD
VRef(t)
VRef ac-noise
VRef(DC)max
VRef(DC)
VDD/2
VRef(DC)min
VSS
time
< Figure 5.2.1: Illustration of Vref (DC) tolerance and Vref AC-noise limits >
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on
VRef. "VRef " shall be understood as VRef (DC), as defined in Figure.
This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low
level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account
for VRef (DC) deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD)
are included in DRAM timings and their associated deratings.
5.2.2 DC & AC Logic Input Levels for Differential Signals
Symbol
Parameter
VIHdiff
Differential input logic high
VILdiff
Differential input logic low
DDR3-800, DDR3-1066
Unit
Notes
-
V
1
- 0.200
V
1
Min
Max
+ 0.200
Note1:
Refer to “Overshoot and Undershoot Specification section 6.5 on 26 page
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HMT451S6MMP(R)8C
5.2.3 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each
cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table The
differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the
midlevel between of VDD and VSS.
VDD
CK#, DQS#
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
< Figure 5.2.3: Vix Definition >
DDR3-800, DDR3-1066
Symbol
VIX
Parameter
Differential Input Cross Point
Voltage relative to VDD/2
Unit
Min
Max
- 150
+ 150
Notes
mV
< Table 5.2.3: Cross point voltage for differential input signals (CK, DQS) >
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HMT451S6MMP(R)8C
5.3 Slew Rate Definitions
5.3.1 For Single Ended Input Signals
- Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef
and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the
slew rate between the last crossing of VRef and the first crossing of VIL (AC) max.
- Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max and
the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate
between the last crossing of VIH (DC) min and the first crossing of VRef.
Measured
Description
Input slew rate for rising edge
Min
Max
Vref
VIH (AC) min
Input slew rate for falling edge
Vref
VIL (AC) max
Input slew rate for rising edge
VIL (DC) max
Vref
Input slew rate for falling edge
VIH (DC) min
Vref
Defined by
Applicable for
VIH (AC) min-Vref
Delta TRS
Vref-VIL (AC) max
Setup
(tIS, tDS)
Delta TFS
Vref-VIL (DC) max
Delta TFH
VIH (DC) min-Vref
Hold
(tIH, tDH)
Delta TRH
< Table 5.3.1: Single-Ended Input Slew Rate Definition >
Part A: Set up
Single Ended input Voltage(DQ,ADD, CMD)
Delta TRS
vIH(AC)min
vIH(DC)min
vRefDQ or
vRefCA
vIL(DC)max
vIL(AC)max
Delta TFS
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HMT451S6MMP(R)8C
P a rt B : H o ld
Single Ended input Voltage(DQ,ADD, CMD)
D e lta T R H
v IH (A C )m in
v IH (D C )m in
v R e fD Q o r
v R e fC A
v IL (D C )m a x
v IL (A C )m a x
D e lta T F H
< Figure 5.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals >
5.3.2 Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table
and Figure .
Description
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
Measured
Min
Max
VILdiffmax
VIHdiffmin
VIHdiffmin
VILdiffmax
Defined by
VIHdiffmin-VILdiffmax
DeltaTRdiff
VIHdiffmin-VILdiffmax
DeltaTFdiff
Note:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
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Differential Input Voltage (i.e. DQS-DQS; CK-CK)
HMT451S6MMP(R)8C
D e lta
T R d iff
vIH d iffm in
0
vILd iffm a x
D e lta
T F d iff
< Figure 5.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# >
5.4 DC & AC Output Buffer Levels
5.4.1 Single Ended DC & AC Output Levels
Below table shows the output levels used for measurements of single ended signals.
Symbol
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
Parameter
DC output high measurement level
(for IV curve linearity)
DC output mid measurement level
(for IV curve linearity)
DC output low measurement level
(for IV curve linearity)
AC output high measurement level
(for output SR)
DDR3-800, 1066
Unit
0.8 x VDDQ
V
0.5 x VDDQ
V
0.2 x VDDQ
V
VTT + 0.1 x VDDQ
V
Notes
1
AC output low measurement level
VTT - 0.1 x VDDQ
V
1
(for output SR)
1. The swing of ± 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing
with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2.
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HMT451S6MMP(R)8C
5.4.2 Differential DC & AC Output Levels
Below table shows the output levels used for measurements of differential signals.
Symbol
VOHdiff
(AC)
Parameter
AC differential output high
measurement level (for output SR)
DDR3-800, 1066
Unit
Notes
+ 0.2 x VDDQ
V
1
VOLdiff
(AC)
AC differential output low
- 0.2 x VDDQ
V
1
measurement level (for output SR)
1. The swing of °æ 0.2 x VDDQ is based on approximately 50% of the static differential output high
or low swing with a driver impedance of 40ߟ and an effective test load of 25ߟ to VTT = VDDQ/2 at each of
the differential output
5.4.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 5.4.3.
Description
Measured
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
Defined by
VOH(AC)-VOL(AC)
DeltaTRse
VOH(AC)-VOL(AC)
DeltaTFse
Note:
Output slew rate is verified by design and characterisation, and may not be subject to production test.
Single Ended Output Voltage(l.e.DQ)
D e lt a T R s e
vO H (A C )
V∏
vO L(A C )
D e lt a T F s e
< Figure 5.4.3: Single Ended Output Slew Rate Definition >
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HMT451S6MMP(R)8C
Parameter
Symbol
Single-ended Output Slew Rate
SRQse
DDR3-800
DDR3-1066
Min
Max
Min
Max
2.5
5
2.5
5
Units
V/ns
*** Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
For Ron = RZQ/7 setting
< Table 5.4.3: Output Slew Rate (single-ended) >
5.4.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in below Table and Figure 5.4.4
Description
Measured
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff (AC)
VOHdiff (AC)
Differential output slew rate for falling edge
VOHdiff (AC)
VOLdiff (AC)
VOHdiff (AC)-VOLdiff (AC)
DeltaTRdiff
VOHdiff (AC)-VOLdiff (AC)
DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test..
Differential Output Voltage(i.e. DQS-DQS)
D e lta
T R d iff
v O H d iff(A C )
O
v O L d iff(A C )
D e lta
T F d iff
< Figure 5.4.4: Differential Output Slew Rate Definition >
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HMT451S6MMP(R)8C
DDR3-800
Parameter
Differential Output Slew Rate
Symbol
SRQdiff
DDR3-1066
Min
Max
Min
Max
5
10
5
10
Units
V/ns
***Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
< Table 5.4.4: Differential Output Slew Rate >
5.5 Overshoot and Undershoot Specifications
5.5.1 Address and Control Overshoot and Undershoot Specifications
Description
Maximum peak amplitude allowed for
overshoot area (see Figure)
Maximum peak amplitude allowed for
undershoot area (see Figure)
Maximum overshoot area above VDD
(See Figure)
Maximum undershoot area below VSS
(See Figure)
Specification
DDR3-800
DDR3-1066
0.4V
0.4V
0.4V
0.4V
0.67 V-ns
0.5 V-ns
0.67 V-ns
0.5 V-ns
< Table 5.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins >
< Figure 5.5.1: Address and Control Overshoot and Undershoot Definition >
Maximum Amplitude
Overshoot Area
Volts
(V)
VDD
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
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HMT451S6MMP(R)8C
5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
Specification
Description
Maximum peak amplitude allowed for
overshoot area (see Figure)
Maximum peak amplitude allowed for
undershoot area (see Figure)
Maximum overshoot area above VDDQ
(See Figure)
Maximum undershoot area below VSSQ
(See Figure)
DDR3-800
DDR3-1066
0.4V
0.4V
0.4V
0.4V
0.25 V-ns
0.19 V-ns
0.25 V-ns
0.19 V-ns
< Table 5.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask >
M a x im u m A m p litu d e
O v e rsh o o t A re a
V o lts
(V )
VDDQ
VSSQ
U n d e rsh o o t A re a
M a x im u m A m p litu d e
T im e (n s)
C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n
< Figure 5.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition >
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HMT451S6MMP(R)8C
5.6 Pin Capacitance
Parameter
Symbol
Input/output capacitance
(DQ, DM, DQS, DQS#, TDQS,
TDQS#)
DDR3-800
DDR3-1066
Units Notes
Min
Max
Min
Max
CIO
TBD
TBD
TBD
TBD
pF
1,2,3
Input capacitance, CK and
CK#
CCK
TBD
TBD
TBD
TBD
pF
2,3,5
Input capacitance delta
CK and CK#
CDCK
TBD
TBD
TBD
TBD
pF
2,3,4
CI
TBD
TBD
TBD
TBD
pF
2,3,6
CDDQS
TBD
TBD
TBD
TBD
pF
2,3,12
CDI_CTRL
TBD
TBD
TBD
TBD
pF
2,3,7,8
Input capacitance delta
CDI_ADD_
(All ADD/CMD input-only pins)
CMD
TBD
TBD
TBD
TBD
pF
2,3,9,
10
Input/output capacitance delta
(DQ, DM, DQS, DQS#)
TBD
TBD
TBD
TBD
pF
2,3,11
Input capacitance
(All other input-only pins)
Input capacitance delta, DQS
and DQS#
Input capacitance delta
(All CTRL input-only pins)
CDIO
Notes:
1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic
characterization of TDQS/TDQS# should be close as much as possible, Cio & Cdio requirement is applied
(recommend deleting note or changing to “Although the DM, TDQS and TDQS# pins have different functions,
the loading matches DQ and DQS.”)
2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK#.
5. The minimum CCK will be equal to the minimum CI.
6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#.
7. CTRL pins defined as ODT, CS and CKE.
8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#))
9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#.
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#))
11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#))
12. Absolute value of CIO(DQS) - CIO(DQS#)
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HMT451S6MMP(R)8C
5.7 IDD Specifications (TCASE: 0 to 95oC)
4GB, 512M x 64 SO-DIMM: HMT451S6MMP8C
Symbol
DDR3 800
DDR3 1066
Unit
note
IDD0
IDD1
IDD2N
IDD2NT
IDD2QNT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD6TC
IDD7
1152
1376
mA
x8
1320
1536
mA
x8
848
1072
mA
x8
864
1104
mA
x8
1232
1264
mA
x8
208
208
mA
x8
400
528
mA
x8
832
1056
mA
x8
912
1152
mA
x8
512
672
mA
x8
1680
2096
mA
x8
920
1048
mA
x8
1456
1856
mA
x8
2488
2704
mA
x8
192
192
mA
x8
192
192
mA
x8
192
192
mA
x8
2560
2888
mA
x8
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HMT451S6MMP(R)8C
5.7 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the
setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the
DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of
the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to
support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application,
IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
”0” and “LOW” is defined as VIN <= VILAC(max).
•
”1” and “HIGH” is defined as VIN >= VIHAC(max).
•
“FLOATING” is defined as inputs are VREF - VDD/2.
•
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1 on Page 26.
•
Basic IDD and IDDQ Measurement Conditions are described in Table 2 on page 26.
•
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 on page 30 through Table 10 on
page 36.
•
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual
IDD or IDDQ measurement is started.
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
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HMT451S6MMP(R)8C
IDDQ (optional)
IDD
VDD
VDDQ
RESET
CK/CK
DDR3
SDRAM
CKE
CS
RAS, CAS, WE
A, BA
ODT
ZQ
VSS
DQS, DQS
DQ, DM,
TDQS, TDQS
RTT = 25 Ohm
VDDQ/2
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above]
Application specific
memory channel
environment
Channel
IO Power
Simulation
IDDQ
Test Load
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
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HMT451S6MMP(R)8C
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3-800
DDR3-1066
5-5-5
7-7-7
tCK
2.5
1.875
ns
CL
5
7
nCK
nRCD
5
7
nCK
nRC
20
27
nCK
nRAS
15
20
nCK
Symbol
Unit
5
7
nCK
x4/x8
16
20
nCK
x16
20
27
nCK
x4/x8
4
4
nCK
x16
4
6
nCK
nRFC -512Mb
36
48
nCK
nRFC-1 Gb
44
59
nCK
nRFC- 2 Gb
64
86
nCK
nRFC- 4 Gb
120
160
nCK
nRFC- 8 Gb
140
187
nCK
nRP
nFAW
nRRD
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High
IDD0
between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3 on
page 30; Data IO: FLOATING; DM: stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... (see Table 3 on page 30); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 3 on page 30
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS:
IDD1
High between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling
according to Table 4 on page 31; DM: stable at 0; Bank Activity: Cycling with on bank active at a time:
0,0,1,1,2,2,... (see Table 4 on page 31); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 4 page 31
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HMT451S6MMP(R)8C
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2N
Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING;
DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: stable at 0; Pattern Details: see Table 5 on page 32
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2NT Address, Bank Address Inputs: partially toggling according to Table 6 on page 32; Data IO: FLOATING;
DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: toggling according to Table 6 on page 32; Pattern Details: see Table 6 on page 32
IDDQ2NT Precharge Standby ODT IDDQ Current
(optional Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
)
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2P0
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power
Down Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2P1
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power
Down Mode: Fast Exitc)
Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
IDDQ4R Operating Burst Read IDDQ Current
(optional Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
)
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HMT451S6MMP(R)8C
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD3N
Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING;
DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: stable at 0; Pattern Details: see Table 5 on page 32
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between RD;
Command, Address, Bank Address Inputs: partially toggling according to Table 7 on page 33; Data IO:
IDD4R
seamless read data burst with different data between one burst and the next one according to Table 7 on
page 33; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks:
0,0,1,1,2,2,...(see Table 7 on page 33); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 7 on page 33
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between WR;
Command, Address, Bank Address Inputs: partially toggling according to Table 8 on page 34; Data IO:
IDD4W
seamless read data burst with different data between one burst and the next one according to Table 8 on
page 34; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,...(see Table 8 on page 34); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at HIGH; Pattern Details: see Table 8 on page 34
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between
IDD5B
REF; Command, Address, Bank Address Inputs: partially toggling according to Table 9 on page 35; Data
IO: FLOATING; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9 on page 35); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9 on
page 35
Rev. 0.2 / Apr. 2009
28
HMT451S6MMP(R)8C
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale);
IDD6
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
Self-Refresh Current: Extended Temperature Range (optional)f)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extend-
IDD6ET
ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS,
Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Extended
Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
FLOATING
Auto Self-Refresh Current (optional)f)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale);
IDD6TC
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Auto SelfRefresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1 on page 26; BL:
8a); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially tog-
IDD7
gling according to Table 10 on page 36; Data IO: read data burst with different data between one burst and
the next one according to Table 10 on page 36; DM: stable at 0; Bank Activity: two times interleaved
cycling through banks (0, 1,...7) with different addressing, wee Table 10 on page 36; Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10 on page 36
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported
by DDR3 SDRAM device
Rev. 0.2 / Apr. 2009
29
HMT451S6MMP(R)8C
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
0
-
0
F
0
-
0
-
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 3 - IDD0 Measurement-Loop Patterna)
3,4
...
nRAS
...
Static High
toggling
1*nRC+0
...
1*nRC+nRAS
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT
0
0
1
1
0
00
00
0
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
...
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
F
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.2 / Apr. 2009
30
HMT451S6MMP(R)8C
0
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE
CAS
RAS
CS
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
3,4
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
0
0000000
0
0
0
0
-
nRCD
...
nRAS
...
Static High
Datab)
0
...
toggling
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 4 - IDD1 Measurement-Loop Patterna)
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
00
0
0
F
0
-
1*nRC+1,2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
1*nRC+3,4
...
1*nRC+nRCD
...
1*nRC+nRAS
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
F
0
0011001
1
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
F
...
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
0
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.2 / Apr. 2009
31
HMT451S6MMP(R)8C
0
Static High
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE
CAS
RAS
CS
Datab)
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
D
1
1
1
1
0
0
0
0
0
F
0
-
3
toggling
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
1
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-17
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
0
0000000
0
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
Static High
toggling
3
D
1
1
1
1
0
0
0
1
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3
12-15
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4
16-19
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-17
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7
28-31
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
0
0
F
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.2 / Apr. 2009
32
HMT451S6MMP(R)8C
Static High
toggling
1
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
Command
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna)
Datab)
RD
0
1
0
1
0
0
00
0
0
0
0
000000
00
D
1
0
0
0
0
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
0
0
00
0
0
0
0
-
4
RD
0
1
0
1
0
0
00
0
0
F
0
001100
11
5
D
1
0
0
0
0
0
00
0
0
F
0
-
D,D
1
1
1
1
0
0
00
0
0
F
0
-
6,7
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.2 / Apr. 2009
33
HMT451S6MMP(R)8C
Static High
toggling
1
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
Command
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 8 - IDD4W Measurement-Loop Patterna)
Datab)
WR
0
1
0
0
1
0
00
0
0
0
0
000000
00
D
1
0
0
0
1
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
1
0
00
0
0
0
0
-
4
WR
0
1
0
0
1
0
00
0
0
F
0
001100
11
5
D
1
0
0
0
1
0
00
0
0
F
0
-
D,D
1
1
1
1
1
0
00
0
0
F
0
-
6,7
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.2 / Apr. 2009
34
HMT451S6MMP(R)8C
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE
CAS
RAS
CS
Command
Cycle
Number
Sub-Loop
CKE
Datab)
0
0
REF
0
0
0
1
0
0
0
0
0
0
0
-
1
1.2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
3,4
D, D
1
1
1
1
0
0
00
0
0
F
0
-
Static High
toggling
CK, CK
Table 9 - IDD5B Measurement-Loop Patterna)
2
5...8
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
33...nRFC-1
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.2 / Apr. 2009
35
HMT451S6MMP(R)8C
Table 10 - IDD7 Measurement-Loop Patterna)
0
1
2
3
4
Static High
toggling
5
6
7
8
9
10
11
12
13
14
15
16
17
18
14
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE
CAS
RAS
CS
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
Datab)
0
ACT
0
0
1
1
0
0
00
0
0
0
0
RDA 0
1
0
1
0
0
00
1
0
0
0 00000000
D
1
0
0
0
0
0
00
0
0
0
0
repeat above D Command until nRRD - 1
ACT
0
0
1
1
0
1
00
0
0
F
0
RDA 0
1
0
1
0
1
00
1
0
F
0 00110011
D
1
0
0
0
0
1
00
0
0
F
0
repeat above D Command until 2* nRRD - 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
F
0
4*nRRD
...
Assert and repeat above D Command until nFAW - 1, if necessary
nFAW
repeat Sub-Loop 0, but BA[2:0] = 4
nFAW+nRRD
repeat Sub-Loop 1, but BA[2:0] = 5
nFAW+2*nRRD
repeat Sub-Loop 0, but BA[2:0] = 6
nFAW+3*nRRD
repeat Sub-Loop 1, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
F
0
nFAW+4*nRRD
...
Assert and repeat above D Command until 2* nFAW - 1, if necessary
2*nFAW+0
ACT
0
0
1
1
0
0
00
0
0
F
0
2*nFAW+1
RDA 0
1
0
1
0
0
00
1
0
F
0 00110011
D
1
0
0
0
0
0
00
0
0
F
0
2&nFAW+2
Repeat above D Command until 2* nFAW + nRRD - 1
2*nFAW+nRRD
ACT
0
0
1
1
0
1
00
0
0
0
0
2*nFAW+nRRD+1 RDA 0
1
0
1
0
1
00
1
0
0
0 00000000
D
1
0
0
0
0
1
00
0
0
0
0
2&nFAW+nRRD+
2
Repeat above D Command until 2* nFAW + 2* nRRD - 1
2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3
D
1
0
0
0
0
0
00
0
0
0
0
2*nFAW+4*nRRD
Assert and repeat above D Command until 3* nFAW - 1, if necessary
3*nFAW
repeat Sub-Loop 10, but BA[2:0] = 4
3*nFAW+nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
0
00
0
0
0
0
3*nFAW+4*nRRD
Assert and repeat above D Command until 4* nFAW - 1, if necessary
1
2
...
nRRD
nRRD+1
nRRD+2
...
2*nRRD
3*nRRD
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.2 / Apr. 2009
36
HMT451S6MMP(R)8C
6. Electrical Characteristics and AC Timing
6.1 Refresh Parameters by Device Density
Parameter
Symbol
512Mb
1Gb
2Gb
4Gb
8Gb
Units
tRFC
90
110
160
300
350
ns
0 ×C < TCASE < 85 ×C
7.8
7.8
7.8
7.8
7.8
us
85 ×C < TCASE < 95 ×C
3.9
3.9
3.9
3.9
3.9
us
REF command to
ACT or REF
command time
Average periodic
refresh interval
tREFI
6.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC
for each corresponding bin
DDR3 800 Speed Bin
DDR3-800E
CL - nRCD - nRP
Unit
6-6-6
Symbol
min
max
Internal read command to first data
tAA
15
20
ns
ACT to internal read or write delay time
tRCD
15
—
ns
PRE command period
tRP
15
—
ns
ACT to ACT or REF command period
tRC
52.5
—
ns
ACT to PRE command period
tRAS
37.5
9 * tREFI
ns
Parameter
CL = 5
CWL = 5
tCK(AVG)
CL = 6
CWL = 5
tCK(AVG)
Reserved
2.5
3.3
ns
1)2)3)4)
ns
1)2)3)
Supported CL Settings
6
nCK
Supported CWL Settings
5
nCK
Rev. 0.2 / Apr. 2009
Notes
37
HMT451S6MMP(R)8C
DDR3 1066 Speed Bin
DDR3-1066F
CL - nRCD - nRP
7-7-7
Unit
Parameter
Symbol
min
max
Internal read command to
first data
tAA
13.125
20
ns
ACT to internal read or
write delay time
tRCD
13.125
—
ns
PRE command period
tRP
13.125
—
ns
ACT to ACT or REF
command period
tRC
50.625
—
ns
ACT to PRE command
period
tRAS
37.5
9 * tREFI
ns
CL = 5
CL = 6
CL = 7
CL = 8
Note
CWL = 5
tCK(AVG)
Reserved
ns
1)2)3)4)6)
CWL = 6
tCK(AVG)
Reserved
ns
4)
CWL = 5
tCK(AVG)
ns
1)2)3)6)
CWL = 6
tCK(AVG)
Reserved
ns
1)2)3)4)
CWL = 5
tCK(AVG)
Reserved
ns
4)
CWL = 6
tCK(AVG)
ns
1)2)3)4)
CWL = 5
tCK(AVG)
ns
4)
CWL = 6
tCK(AVG)
ns
1)2)3)
2.5
3.3
1.875
< 2.5
Reserved
1.875
< 2.5
Supported CL Settings
6, 7, 8
nCK
Supported CWL Settings
5, 6
nCK
Rev. 0.2 / Apr. 2009
38
HMT451S6MMP(R)8C
*Speed Bin Table Notes*
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Notes:
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection
of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the
DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC
standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns],
rounding up to the next ‘Supported CL’.
3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG) down to the
next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to
CLSELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory
feature. Refer to supplier’s data sheet and SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
Rev. 0.2 / Apr. 2009
39
HMT451S6MMP(R)8C
7. DIMM Outline Diagram
7.1 512Mx64 - HMT451S6MMP8C
Front View
Side
3.80mm max
67.60mm
2.0
30.0mm
4.00 ± 0.10
Detail-B
pin 1
20.0mm
Detail- A
6.00
SPD
1.00 ± 0.08 mm
pin 203
21.00
2.15
2 X φ 1.80 ± 0.10
39.00
1.65 ± 0.10
3.00
Back View
Detail of Contacts A
Detail of Contacts B
2.55
0.3 ± 0.15
4.00
2.55
0.20
0.45 ± 0.10
0.3~1.0
0.60
1.00 ± 0.05
3.00
Rev. 0.2 / Apr. 2009
40