Cypress CY7C1049D-10VXI 4-mbit (512 k ã 8) static ram ttl-compatible inputs and output Datasheet

CY7C1049D
4-Mbit (512 K × 8) Static RAM
Features
Functional Description[1]
■
Pin- and function-compatible with CY7C1049B
■
High speed
❐ tAA = 10 ns
■
Low active power
❐ ICC = 90 mA at 10 ns
■
Low CMOS Standby power
❐ ISB2 = 10 mA
The CY7C1049D is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and tri-state drivers. Writing to the
device is accomplished by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
■
2.0 V data retention
■
Automatic power-down when deselected
■
TTL-compatible inputs and outputs
■
Easy memory expansion with CE and OE features
■
Available in Pb-free 36-Pin (400-Mil) Molded SOJ package
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049D is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolutionary) pinout.
Logic Block Diagram
I/O0
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
I/O2
SENSE AMPS
ROW DECODER
I/O1
512K x 8
I/O3
I/O4
I/O5
COLUMN
DECODER
CE
I/O6
POWER
DOWN
I/O7
A 11
A 12
A 13
A14
A15
A16
A17
A18
WE
OE
Selection Guide
–10
Unit
Maximum access time
10
ns
Maximum operating current
90
mA
Maximum CMOS standby current
10
mA
Note
1. For guidelines on SRAM system design, refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05474 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 20, 2011
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CY7C1049D
Contents
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 3
Operating Range ............................................................... 3
Electrical Characteristics
Over the Operating Range ............................................... 3
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
AC Test Loads and Waveforms ....................................... 4
Switching Characteristics
Over the Operating Range ............................................... 5
Data Retention Characteristics
Over the Operating Range ............................................... 5
Data Retention Waveform ................................................ 6
Switching Waveforms ...................................................... 6
Document #: 38-05474 Rev. *E
Truth Table ........................................................................ 9
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Diagram ............................................................ 10
Acronyms ........................................................................ 10
Document Conventions ................................................. 10
Units of Measure ....................................................... 10
Document History Page ................................................. 11
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support ....................... 12
Products .................................................................... 12
PSoC Solutions ......................................................... 12
Page 2 of 12
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CY7C1049D
Pin Configuration
SOJ
Top View
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
DC Input Voltage[2] .............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage........................................... >2001 V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[2] ...–0.5 V to +6.0 V
Ambient
Temperature
VCC
–40°C to +85°C
4.5 V–5.5 V
Range
DC Voltage Applied to Outputs
in High Z State[2] .................................. –0.5 V to VCC + 0.5 V
Industrial
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
VIH[2]
VIL[2]
IIX
IOZ
ICC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Leakage Current
Output Leakage
Current
VCC Operating
Supply Current
–10
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
GND < VI < VCC
GND < VOUT < VCC,
Output Disabled
VCC = Max.,
f = fMAX = 1/tRC
100 MHz
83 MHz
66 MHz
40 MHz
ISB1
ISB2
Automatic CE Power-Down
Current —TTL Inputs
Automatic CE Power-Down
Current —CMOS Inputs
Document #: 38-05474 Rev. *E
Max. VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
Max. VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
Min.
2.4
–
2.0
–0.5
–1
–1
Max.
–
0.4
VCC + 0.5
0.8
+1
+1
Unit
V
V
V
V
μA
μA
–
–
–
–
–
–
–
–
–
90
mA
80
mA
70
mA
60
mA
20
mA
10
mA
–
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CY7C1049D
Capacitance[3]
Parameter
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz,
VCC = 5.0 V
8
pF
8
pF
Test Conditions
SOJ Package
Unit
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
57.91
°C/W
36.73
°C/W
Thermal Resistance[3]
Parameter
Description
ΘJA
Thermal resistance
(Junction to Ambient)[3]
ΘJC
Thermal resistance
(Junction to Case)[3]
AC Test Loads and Waveforms[4]
10-ns device
Z = 50Ω
ALL INPUT PULSES
OUTPUT
3.0 V
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5 V
90%
30 pF*
GND
90%
10%
10%
≤ 3 ns
(a)
≤ 3 ns
(b)
HIGH-Z CHARACTERISTICS
R1 481Ω
5V
OUTPUT
THÉVENIN EQUIVALENT
167Ω
1.73 V
OUTPUT
Equivalent to:
5 pF
R2
255Ω
INCLUDING
JIG AND
SCOPE
(c)
Notes
2. Minimum voltage is –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05474 Rev. *E
Page 4 of 12
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CY7C1049D
Switching Characteristics[5] Over the Operating Range
-10
Parameter
Description
Min.
Max.
Unit
–
μs
Read Cycle
tpower
VCC(typical) to the First Access[6]
100
tRC
Read Cycle Time
10
–
ns
tAA
Address to Data Valid
–
10
ns
tOHA
Data Hold from Address Change
3
–
ns
tACE
CE LOW to Data Valid
–
10
ns
tDOE
OE LOW to Data Valid
–
5
ns
0
–
ns
–
5
ns
3
–
ns
–
5
ns
Z[8]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to High Z[7, 8]
Z[8]
tLZCE
CE LOW to Low
tHZCE
CE HIGH to High Z[7, 8]
tPU
CE LOW to Power-Up
0
–
ns
tPD
CE HIGH to Power-Down
–
10
ns
tWC
Write Cycle Time
10
–
ns
tSCE
CE LOW to Write End
7
–
ns
Write Cycle[9, 10]
tAW
Address Set-Up to Write End
7
–
ns
tHA
Address Hold from Write End
0
–
ns
tSA
Address Set-Up to Write Start
0
–
ns
tPWE
WE Pulse Width
7
–
ns
tSD
Data Set-Up to Write End
6
–
ns
tHD
Data Hold from Write End
0
–
ns
tLZWE
WE HIGH to Low Z[8]
3
–
ns
tHZWE
WE LOW to High Z[7, 8]
–
5
ns
Data Retention Characteristics Over the Operating Range
Parameter
Conditions[12]
VCC for Data Retention
VDR
ICCDR
tCDR
Description
[3]
tR[11]
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
VCC = VDR = 2.0 V,
CE > VCC – 0.3 V
VIN > VCC – 0.3 V or VIN < 0.3 V
Min.
Max
Unit
2.0
–
V
–
10
mA
0
–
ns
tRC
–
ns
Notes
4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the
test load shown in Figure (c)
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05474 Rev. *E
Page 5 of 12
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CY7C1049D
Data Retention Waveform
DATA RETENTION MODE
4.5 V
VCC
VDR > 2 V
4.5 V
tR
tCDR
CE
Switching Waveforms
Figure 1. Read Cycle No. 1[13, 14]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes
11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 μs or stable at VCC(min.) > 50 μs
12. No input may exceed VCC + 0.5 V.
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for read cycle.
Document #: 38-05474 Rev. *E
Page 6 of 12
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CY7C1049D
Switching Waveforms(continued)
Figure 2. Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
Figure 3. Write Cycle No. 1 (CE Controlled)[16, 17]
tWC
ADDRESS
tSCE
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Notes
15. Address valid prior to or coincident with CE transition LOW.
16. Data I/O is high impedance if OE = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05474 Rev. *E
Page 7 of 12
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CY7C1049D
Switching Waveforms(continued)
Figure 4. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 18
tHZOE
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)[17]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 18
DATA VALID
tHZWE
Document #: 38-05474 Rev. *E
tHD
tLZWE
Page 8 of 12
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CY7C1049D
m bngggggggg
Truth Table
I/O0–I/O7
Mode
Power
CE
H
OE
X
WE
X
High-Z
Power-down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
Package
Diagram
Ordering Code
CY7C1049D-10VXI
51-85090
Package Type
36-Lead (400-Mil) Molded SOJ (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 7 C 1 04 9
D - 10
VX
I
Temperature Range:
I = Industrial
Package Type:
VX = 36-Lead Molded SOJ (Pb-free)
Speed: 10 ns
D = C9, 90 nm Technology
9 = Data width × 8-bits
04 = 4-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Please contact your local Cypress sales representative for availability of these parts.
Note
18. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05474 Rev. *E
Page 9 of 12
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CY7C1049D
Package Diagram
Figure 6. 36-Pin (400-Mil) Molded SOJ (51-85090)
51-85090 *E
Acronyms
Document Conventions
Acronym
Description
CE
chip enable
CMOS
Complementary metal oxide semiconductor
I/O
Input/output
OE
output enable
SRAM
Static random access memory
SOJ
Small Outline J-Lead
TSOP
Thin Small Outline Package
VFBGA
Very Fine-Pitch Ball Grid Array
Document #: 38-05474 Rev. *E
Units of Measure
Symbol
Unit of Measure
ns
nano seconds
V
Volts
µA
micro Amperes
mA
milli Amperes
mV
milli Volts
mW
milli Watts
MHz
Mega Hertz
pF
pico Farad
°C
degree Celcius
W
Watts
Page 10 of 12
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CY7C1049D
Document History Page
Document Title: CY7C1049D 4-Mbit (512K x 8) Static RAM
Document Number: 38-05474
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
201560
SWI
See ECN
Advance Datasheet for C9 IPP
*A
233729
RKF
See ECN
1.AC, DC parameters are modified as per EROS(Spec # 01-2165)
2.Pb-free offering in the ‘ordering information’
*B
351096
PCI
See ECN
Changed from Advance to Preliminary
Removed 17, 20 ns Speed bin
Added footnote # 4
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 67 and 54 mA to 75 and 70 mA for 12 and 15 ns
speed bins respectively
ICC (Ind’l): Changed from 80, 67 and 54 mA to 90, 85 and 80 mA for 10, 12 and
15 ns speed bins respectively
Added VIH(max) spec in Note# 2
Modified Note# 10 on tR
Changed tSCE from 8 to 7 ns for 10 ns speed bin
Changed reference voltage level for measurement of Hi-Z parameters from ±500
mV to ±200 mV
Added Truth Table on page# 6
Removed L-Version
Added 10 ns parts in the Ordering Information Table
Added Lead-Free Product Information
Shaded Ordering Information Table
*C
446328
NXR
See ECN
Converted from Preliminary to Final
Removed -12 and -15 speed bins
Removed Commercial Operating Range product information
Changed Maximum Rating for supply voltage from 7 V to 6 V
Updated Thermal Resistance table
Changed tHZWE from 6 ns to 5 ns
Updated footnote #7 on High-Z parameter measurement
Replaced Package Name column with Package Diagram in the Ordering Information table
*D
3109184
AJU
*E
3235742
PRAS
Document #: 38-05474 Rev. *E
12/13/2010 Added Ordering Code Definitions.
Updated Package Diagram.
04/20/2011 Updated template.
Added Acronyms and Units of measure.
Page 11 of 12
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CY7C1049D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05474 Rev. *E
Revised April 20, 2011
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