MOTOROLA MCM6708AJ12 64k x 4 bit static ram Datasheet

MOTOROLA
Order this document
by MCM6708A/D
SEMICONDUCTOR TECHNICAL DATA
MCM6708A
64K x 4 Bit Static RAM
The MCM6708A is a 262,144 bit static random access memory organized as
65,536 words of 4 bits, fabricated using high–performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
The MCM6708A is available in a 300 mil, 24 lead plastic surface–mount SOJ
package.
•
•
•
•
•
J PACKAGE
300 MIL SOJ
CASE 810A–02
Single 5 V ± 10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs are TTL Compatible
Three State Outputs
Fast Access Times:
MCM6708A–8 = 8 ns
MCM6708A–10 = 10 ns
MCM6708A–12 = 12 ns
PIN ASSIGNMENT
A0
1
24
A1
2
23
VCC
A15
A2
3
22
A14
A3
4
21
A13
A4
5
20
A12
A5
6
19
A11
A
A6
7
18
A10
A
A7
8
17
DQ0
A8
9
16
DQ1
A9
10
15
DQ2
E
11
14
DQ3
VSS
12
13
W
BLOCK DIAGRAM
A
A
MEMORY MATRIX
256 ROWS x 256 x 4
COLUMNS
ROW
DECODER
A
A
A
A
DQ0
•
•
•
•
•
•
COLUMN I/O
•
•
•
INPUT
DATA
CONTROL
COLUMN DECODER
DQ3
A
A
A
A
A
A
A
A
PIN NAMES
A0 – A15 . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ0 – DQ3 . . . . . . . Data Input/Output
VCC . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . No Connection
E
W
REV 5
5/95
 Motorola, Inc. 1995
MOTOROLA
FAST SRAM
MCM6708A
2–1
TRUTH TABLE (X = Don’t Care)
E
G
W
Mode
Output
Cycle
H
X
X
Not Selected
High–Z
—
L
H
H
Read
High–Z
—
L
L
H
Read
Dout
Read Cycle
L
X
L
Write
Din
Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
± 30
mA
Power Dissipation
PD
2.0
W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to + 70
°C
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Storage Temperature — Plastic
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
Parameter
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.2
—
VCC + 0.3*
V
—
0.8
V
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (E = VIH, Vout = 0 to VCC)
Input Low Voltage
VIL
– 0.5**
* VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
DC CHARACTERISTICS
Parameter
Ilkg(O)
—
± 1.0
µA
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
Output Low Voltage (IOL = 8.0 mA)
VOL
—
0.4
V
POWER SUPPLY CURRENTS
Parameter
Symbol
MCM6708A–8
MCM6708A–10
MCM6708A–12
Unit
Notes
AC Active Supply Current (Iout = 0 mA, VCC = max,
f = fmax)
ICCA
185
175
165
mA
1, 2, 3
AC Standby Current (E = VIH, VCC = max, f = fmax)
ISB1
120
110
105
mA
1, 2, 3
CMOS Standby Current (VCC = max, f = 0 MHz,
E ≥ VCC – 0.2 V, Vin ≤ VSS, or ≥ VCC – 0.2 V)
ISB2
50
50
50
mA
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
MCM6708A
2–2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Max
Unit
Address Input Capacitance
Cin
5
pF
Control Pin Input Capacitance (E, G, W)
Cin
5
pF
Input/Output Capacitance
CI/O
6
pF
Parameter
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLES 1 AND 2 (See Notes 1 and 2)
MCM6708A–8
Parameter
MCM6708A–10
MCM6708A–12
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
8
—
10
—
12
—
ns
3
Address Access Time
tAVQV
—
8
—
10
—
12
ns
Chip Enable Access Time
tELQV
—
8
—
10
—
12
ns
Output Hold from Address Change
tAXQX
3
—
3
—
3
—
ns
Chip Enable Low to Output Active
tELQX
1
—
1
—
1
—
ns
4, 5, 6
Chip Enable High to Output High–Z
tEHQZ
0
4.5
0
5
0
6
ns
4, 5, 6
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ max is less than tELQX min for a given device and from device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
AC TEST LOADS
TIMING LIMITS
+5 V
480 Ω
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
OUTPUT
255 Ω
5 pF
VL = 1.5 V
Figure 1A
MOTOROLA FAST SRAM
Figure 1B
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
MCM6708A
2–3
READ CYCLE 1 (See Note)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
DATA VALID
tAVQV
NOTE: Device is continuously selected (E = VIL, G = VIL).
READ CYCLE 2 (See Note)
tAVAV
A (ADDRESS)
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
DATA VALID
Q (DATA OUT)
tAVQV
NOTE: Addresses valid prior to or coincident with E going low.
MCM6708A
2–4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6708A–8
Parameter
MCM6708A–10
MCM6708A–12
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
8
—
10
—
12
—
ns
3
Address Setup Time
tAVWL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVWH
8
—
9
—
10
—
ns
Write Pulse Width
tWLWH,
tWLEH
8
—
9
—
10
—
ns
Data Valid to End of Write
tDVWH
4
—
5
—
6
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
0
4
0
5
0
6
ns
4, 5, 6
Write High to Output Active
tWHQX
3
—
3
—
3
—
ns
4, 5, 6
Write Recovery Time
tWHAX
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
tAVAV
A (ADDRESS)
tAVWH
tWHAX
E (CHIP ENABLE)
tWLWH
tWLEH
W (WRITE ENABLE)
tAVWL
tDVWH
DATA VALID
D (DATA IN)
tWLQZ
Q (DATA OUT)
MOTOROLA FAST SRAM
tWHDX
HIGH–Z
tWHQX
HIGH–Z
MCM6708A
2–5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6708A–8
Parameter
MCM6708A–10
MCM6708A–12
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
8
—
10
—
12
—
ns
3
Address Setup Time
tAVEL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVEH
8
—
9
—
10
—
ns
Chip Enable to End of Write
tELEH,
tELWH
7
—
8
—
9
—
ns
Data Valid to End of Write
tDVEH
4
—
5
—
6
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
ns
4, 5
Write Recovery Time
tEHAX
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
tAVAV
A (ADDRESS)
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
tEHAX
W (WRITE ENABLE)
tDVEH
DATA VALID
D (DATA IN)
tEHDX
Q (DATA OUT)
MCM6708A
2–6
HIGH–Z
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
J PACKAGE
300 MIL SOJ
CASE 810A–02
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
3. CONTROLLING DIMENSION: INCH.
4. DIMENSION R TO BE DETERMINED AT DATUM
-T-.
F
24
13
1
DETAIL Z
N
D 24 PL
0.18 (0.007)
12
T A
S
H BRK
-A-
0.18 (0.007)
P
-B-
L
G
M
M
M
E
0.10 (0.004)
K
DETAIL Z
-T-
SEATING
PLANE
R
0.25 (0.010)
S RAD
S
T B
S
C
S
T
B
S
DIM
A
B
C
D
E
F
G
H
K
L
M
N
P
R
S
INCHES
MIN
MAX
0.620 0.630
0.295 0.305
0.128 0.148
0.015 0.020
0.088 0.098
0.026 0.032
0.050 BSC
—
0.020
0.035 0.045
0.025 BSC
0_
5_
0.030 0.045
0.335 0.345
0.260 0.280
0.030 0.040
MILLIMETERS
MIN
MAX
15.75 16.00
7.50
7.74
3.26
3.75
0.39
0.50
2.24
2.48
0.67
0.81
1.27 BSC
—
0.50
0.89
1.14
0.64 BSC
0_
5_
0.76
1.14
8.51
8.76
6.61
7.11
0.77
1.01
M
MOTOROLA FAST SRAM
MCM6708A
2–7
ORDERING INFORMATION
(Order by Full Part Number)
MCM
6708A
X
XX
XX
Motorola Memory Prefix
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Part Number
Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns)
Package (J = 300 mil SOJ)
Full Part Numbers — MCM6708AJ8
MCM6708AJ10
MCM6708AJ12
MCM6708AJ8R2
MCM6708AJ10R2
MCM6708AJ12R2
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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MCM6708A
2–8
◊
*MCM6708A/D*
MCM6708A/D
MOTOROLA FAST
SRAM