E2U0020-28-81 This version: Aug. 1998 MSM7533H/7533V/7534 Previous version: Nov. 1996 ¡ Semiconductor MSM7533H/7533V/7534 ¡ Semiconductor 2ch Single Rail CODEC GENERAL DESCRIPTION The MSM7533 and MSM7534 are two-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices contain two-channel AD/DA converters in a single chip and achieve a reduced footprint and a reduced number of external components. The MSM7533 and MSM7534 are best suited for an analog interface to an echo canceller DSP used in digital telephone terminals, digital PABXs, and hands free terminals. FEATURES • Single power supply: +5 V • Power consumption Operating mode: 35 mW Typ. 74 mW Max. VDD = 5 V Power save mode: 7 mW Typ. 16 mW Max. VDD = 5 V Power down mode: 0.05 mW Typ. 0.3 mW Max. VDD = 5 V • ITU-T Companding law MSM7533H: m-law MSM7534: A-law MSM7533V: m/A-law pin selectable • Built-in PLL eliminates a master clock • The PCM interface can be switched between 2 channel serial/parallel • Transmission clock: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544/200 kHz (During 2 channel serial mode, the 64 and 96 kHz clocks are disabled) • Adjustable transmit gain • Built-in reference voltage supply • Analog output can directly drive a 600 W line transformer • Package options: 20-pin plastic skinny DIP (DIP20-P-300-2.54-S1) (Product name : MSM7533HRS) (Product name : MSM7533VRS) (Product name : MSM7534RS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7533HGS-K) (Product name : MSM7533VGS-K) (Product name : MSM7534GS-K) 1/18 ¡ Semiconductor MSM7533H/7533V/7534 BLOCK DIAGRAM AIN1 – + RC LPF 8th BPF – + RC LPF 8th BPF AD CONV. DOUT1 DOUT2 TCONT GSX1 AIN2 GSX2 AOUT1 AOUT2 SGC PLL AUTO ZERO – + BCLK RTIM 5th LPF S&H 5th LPF SG GEN S&H VR GEN RSYNC (ALAW) DA CONV. – + XSYNC RCONT PWD Logic CHPS DIN1 DIN2 PDN VDD AG DG 2/18 ¡ Semiconductor MSM7533H/7533V/7534 PIN CONFIGURATION (TOP VIEW) SGC 1 20 AIN2 AOUT2 2 19 GSX2 AOUT1 3 18 GSX1 PDN 4 17 AIN1 SGC 1 24 AIN2 AOUT2 2 23 GSX2 NC 3 22 GSX1 AOUT1 4 21 AIN1 PDN 5 CHPS 5 VDD 6 DG 7 16 (ALAW) * 15 AG 14 BCLK RSYNC 8 13 XSYNC DIN2 9 12 DOUT2 DIN1 10 11 DOUT1 CHPS 6 20 NC 19 (ALAW) * NC 7 18 AG VDD 8 17 NC DG 9 16 BCLK RSYNC 10 15 XSYNC DIN2 11 14 DOUT2 DIN1 12 13 DOUT1 NC : No connect pin 24-Pin Plastic SOP 20-Pin Plastic Skinny DIP * The ALAW pin is only applied to the MSM7533VRS/MSM7533VGS-K. 3/18 ¡ Semiconductor MSM7533H/7533V/7534 PIN AND FUNCTIONAL DESCRIPTIONS AIN1, AIN2, GSX1, GSX2 AIN1 and AIN2 are the transmit analog inputs for channels 1 and 2. GSX1 and GSX2 are the transmit level adjustments for channels 1 and 2. AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output of the op-amp and are used to adjust the level, as shown below. When not using AIN1 and AIN2, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving and power down mode, the GSX1 and GSX2 outputs are at AG voltage. R2 CH1 Analog Input C1 R1 C2 R3 AIN1 – + R4 CH2 Analog Input GSX1 GSX2 AIN2 – + CH1 Gain Gain = R2/R1 £ 10 R1: Variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) CH2 Gain Gain = R4/R3 £ 10 R3: Variable R4 > 20 kW C2 > 1/(2 ¥ 3.14 ¥ 30 ¥ R3) AOUT1, AOUT2 AOUT1 is the receive analog output for channel 1 and AOUT2 is used for channel 2. The output signal has an amplitude of 3.4 VPP above and below the signal ground voltage (SG). When the digital signal of +3 dBmO is input to DIN1 and DIN2, it can drive a load of 600 W or more. During power saving or power down mode, these outputs are at the voltage level of SG with a high impedance. 4/18 ¡ Semiconductor MSM7533H/7533V/7534 VDD Power supply for +5 V. A power supply for an analog circuit of the system which the device is applied should be used. A bypass capacitor of 0.1 mF to 1 mF with excellent high frequency characteristics and a capacitor of 10 mF to 20 mF should be connected between this pin and the AG pin if needed. DIN1 DIN1 is the PCM signal input for channel 1, when the parallel mode is selected. A serial PCM signal input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLK signal. The analog signal is output from the AOUT1 pin. The data rate of the PCM signal is equal to the frequency of BCLK signal. The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is not used and should be connected to GND (0 V). DIN2 DIN2 is the PCM signal input for channel 2, when the parallel mode is selected. A serial PCM signal input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLK signal. The analog signal is output from the AOUT2 pin. The data rate of the PCM signal is equal to the frequency of BCLK signal. The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is used for the 2ch multiplexed PCM signal input. BCLK Shift clock signal input for the DIN1, DIN2, DOUT1, and DOUT2 signals. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048, or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. 5/18 ¡ Semiconductor MSM7533H/7533V/7534 RSYNC Receive synchronizing signal input. The eight bits PCM data required are selected from serial PCM signals on the DIN1 and DIN2 pins by the receive synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK (generated from the same clock source as BCLK). The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristic of the receive section. However, if the frequency characteristic of the system used is not strictly specified, this device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics in this specifications are not guaranteed. XSYNC Transmit synchronizing signal input. The PCM output signal from the DOUT1 and DOUT2 pins is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristic of the transmit section. However, if the frequency characteristic of the system used is not strictly specified, this device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving state. 6/18 ¡ Semiconductor MSM7533H/7533V/7534 DOUT1 PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance sate during power saving or power down mode. When the serial mode is selected, this pin is for the output of serial multiplexed 2ch PCM signal. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7534(A-law) outputs the character signal, inverting the even bits. PCMIN/PCMOUT Input/Output Level MSM7533H (m-law) MSD MSM7534 (A-law) MSD +Full scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 +0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 –0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 –Full scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 DOUT2 PCM signal outputs for channel 2 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power saving or power down modes. When the serial mode is selected, this pin is left open. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7534(A-law) outputs the character signal, inverting the even bits. 7/18 ¡ Semiconductor MSM7533H/7533V/7534 CHPS Control signal input for the mode selection of PCM input and output. When this signal is at a logic "1" level, the PCM input and output are in the parallel mode. The PCM data of CH1 and CH2 is input to DIN1 and DIN2, and output from DOUT1 and DOUT2 with the same timing. When this signal is at a logic "0" level, the PCM input and output is in the serial mode. The PCM data of CH1 and CH2 is input to DIN2 and output from DOUT1 as time division multiplexed data. The parallel mode is conveniently applied to the digital interface to the echo canceller (MSM7520), and the serial mode is applied to the digital interface to PCM multiplexer's for PABXs. PDN Power down control signal. When PDN is at a logic "0" level, both transmit and receive circuits are in a power down state. AG Analog signal ground. DG Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Provides only for the MSM7533VRS/MSM7533VGS-K. The CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since this pin is internally pulled down. 8/18 ¡ Semiconductor MSM7533H/7533V/7534 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit VDD — 0 to 7 V Analog Input Voltage VAIN — –0.3 to VDD + 0.3 V Digital Input Voltage VDIN — –0.3 to VDD + 0.3 V Storage Temperature TSTG — –55 to +150 °C Power Supply Voltage RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Symbol VDD Condition Voltage must be fixed Ta — Min. Typ. Max. Unit 4.75 5.0 5.25 V –30 +25 +85 °C — — 3.4 VPP 2.2 — VDD V 0 — 0.8 V Analog Input Voltage VAIN Digital Input High Voltage VIH Digital Input Low Voltage VIL Clock Frequency FC Sync Pulse Frequency FS XSYNC, RSYNC 6.0 8.0 9.0 Clock Duty Ratio DC BCLK 40 50 60 % Digital Input Rise Time tIr XSYNC, RSYNC, BCLK, DIN1, — — 50 ns Digital Input Fall Time tIf DIN2, PDN, CHPS — — 50 ns tXS BCLKÆXSYNC, See Timing Diagram 100 — — ns tSX XSYNCÆBCLK, See Timing Diagram 100 — — ns tRS BCLKÆRSYNC, See Timing Diagram 100 — — ns tSR RSYNCÆBCLK, See Timing Diagram 100 — — ns Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Gain = 1 XSYNC, RSYNC, BCLK, DIN1, DIN2, PDN, CHPS BCLK = (eliminates 64, 96 kHz, when 2ch serial mode) 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, kHz 1536, 1544, 200 kHz Sync Pulse Width tWS XSYNC, RSYNC 1 BCLK — 100 ms DIN Set-up Time tDS DIN1, DIN2 100 — — ns DIN Hold Time Digital Output Load tDH DIN1, DIN2 100 — — ns RDL Pull-up resistor, DOUT1, DOUT2 0.5 — — kW CDL DOUT1, DOUT2 — Analog Input Allowable DC Offset Voff Allowable Jitter Width — — 100 pF Transmit gain stage, Gain = 1 VDD/2–100 — VDD/2+100 mV Transmit gain stage, Gain = 10 VDD/2–10 — VDD/2+10 mV — 500 ns XSYNC, RSYNC — 9/18 ¡ Semiconductor MSM7533H/7533V/7534 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Symbol IDD1 Condition Operating mode, No signal Min. Typ. Max. Unit — 7.0 14.0 mA — 1.3 3.0 mA Power-save mode, PDN = 1, Power Supply Current IDD2 XSYNC or BCLK OFF IDD3 Power-down mode, PDN = 0 — 0.01 0.05 mA Input High Voltage VIH — 2.2 — VDD V Input Low Voltage VIL — 0.0 — 0.8 V High Level Input Leakage Current IIH — — — 2.0 mA Low Level Input Leakage Current IIL — — — 0.5 mA Digital Output Low Voltage VOL 0.0 0.2 0.4 V Pull-up resistance > 500 W Digital Output Leakage Current IO — — — 10 mA Input Capacitance CIN — — 5 — pF Transmit Analog Interface Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Min. Typ. Max. Unit Input Resistance Symbol RINX AIN1, AIN2 Condition 10 — — MW Output Load Resistance RLGX GSX1, GSX2 20 — — kW Output Load Capacitance CLGX with respect to SG — — 30 pF Output Amplitude VOGX –1.7 — +1.7 V Offset Voltage VOSGX –20 — +20 mV Gain = 1 Receive Analog Interface Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Symbol Output Load Resistance RLAO Output Load Capacitance CLAO Output Amplitude VOAO Offset Voltage VOSAO Condition AOUT1, AOUT2 (each) with respect to SG AOUT1, AOUT2 AOUT1, AOUT2, RL = 0.6 kW, with respect to SG AOUT1, AOUT2 with respect to SG Min. Typ. Max. Unit 0.6 — — kW — — 50 pF –1.7 — +1.7 V –100 — +100 mV 10/18 ¡ Semiconductor MSM7533H/7533V/7534 AC Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Transmit Frequency Response Receive Frequency Response Loss T1 Freq. (Hz) 60 Loss T2 300 Loss T3 1020 Loss T4 2020 Loss T5 3000 Symbol Receive Gain Tracking Typ. Max. Unit 20 26 — dB –0.15 +0.07 +0.20 dB Reference 0 dB –0.15 –0.04 +0.20 dB –0.15 +0.06 +0.20 dB Loss T6 3400 0 0.4 0.80 dB 300 –0.15 –0.03 +0.20 dB Loss R2 1020 Loss R3 2020 Loss R4 Loss R5 Reference 0 dB –0.15 –0.02 +0.20 dB 3000 –0.15 +0.15 +0.20 dB 3400 0.0 0.45 0.80 dB SD T1 3 35 43 — SD T2 0 35 41 — 1020 –30 35 38 — SD T4 –40 29 31.5 — SD T5 –45 24 27 — SD R1 3 36 43 — SD R2 0 36 41 — SD R3 1020 *1 –30 36 40 — SD R4 –40 30 33.5 — SD R5 –45 25 30 — GT T1 3 –0.3 +0.01 +0.3 GT T3 *1 –10 GT T2 Transmit Gain Tracking Min. Loss R1 Transmit Signal to Distortion Ratio SD T3 Receive Signal to Distortion Ratio Level Condition (dBm0) –0.3 –0.09 +0.3 GT T4 –50 –0.5 –0.09 +0.5 GT T5 –55 –1.2 –0.1 +1.2 GT R1 3 –0.3 0 +0.3 GT R2 –10 1020 dB Reference –40 GT R3 1020 dB dB Reference –40 –0.3 +0.09 +0.3 GT R4 –50 –0.5 +0.2 +0.5 GT R5 –55 –1.2 +0.23 +1.2 dB *1 Psophometric filter is used 11/18 ¡ Semiconductor MSM7533H/7533V/7534 AC Characteristics (Continued) (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Idle Channel Noise Symbol Freq. (Hz) Nidle T — Nidle R — Level Condition (dBm0) AIN = SG — *1*2 — (Deviation of Temperature and Power) Typ. Max. –73.5 –70 –71.5 –68 — –78 –75 — Unit dBmOp AV T VDD = 5.0 V 0.821 0.850 0.880 AV R Ta = 25°C *4 0.821 0.850 0.880 –0.2 — +0.2 dB –0.2 — +0.2 dB — — 0.6 ms — 0.19 0.75 — 0.11 0.35 — 0.02 0.125 Absolute Level (Initial Difference) Absolute Level *1 *3 Min. AV Tt 1020 0 VDD = 5 V ± 5% Ta = –30 AV Rt to 85°C *4 Vrms A to A Absolute Delay Td 1020 0 BCLK = 64 kHz tgd T1 Transmit Group Delay Receive Group Delay 500 tgd T2 600 tgd T3 1000 *5 0 tgd T4 2600 — 0.05 0.125 tgd T5 2800 — 0.07 0.75 tgd R1 500 tgd R2 600 tgd R3 1000 tgd R4 2600 tgd R5 2800 *5 0 CR T Crosstalk Attenuation CR R CR CH *1 *2 *3 *4 *5 1020 0 — 0.00 0.75 — 0.00 0.35 — 0.00 0.125 — 0.09 0.125 — 0.12 0.75 TRANS Æ RECV 75 80 — RECV Æ TRANS 70 76 — CH to CH 73 78 — ms ms dB Psophometric filter is used Upper is specified for the m-law, lower for the A-law Input "0" code to PCMIN AVT is defined between GSX and DOUT and AVR between DIN and AOUT Minimum value of the group delay distortion 12/18 ¡ Semiconductor MSM7533H/7533V/7534 AC Characteristics (Continued) (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Freq. Level Condition (Hz) (dBm0) 0 to 4.6 kHz to DIS 0 4000 Hz 72 kHz Symbol S IMD 300 to 0 3400 fa = 470 –4 fd = 320 PSR T 0 to PSR R 50 kHz 50 mVPP 4.6 kHz to 100 kHz 2fa – fd *6 tSD Digital Output Delay Time tXD1 tXD2 CL = 100 pF + 1 LSTTL tXD3 Min. Typ. Max. Unit 30 32 — dB — –37.5 –35 dBmO — –52 –35 dBmO — 30 — dB 20 — 200 20 — 200 20 — 200 20 — 200 ns *6 The measurement under idle channel noise 13/18 , , ¡ Semiconductor MSM7533H/7533V/7534 TIMING DIAGRAM Transmit Timing BCLK 1 2 tXS XSYNC DOUT1 DOUT2 3 4 5 6 7 8 9 10 11 9 10 11 tSX tWS tXD1 tSD MSD D2 tXD2 D3 D4 D5 D6 tXD3 D8 D7 Transmit Side Receive Timing BCLK 1 tRS RSYNC DIN1 DIN2 2 3 4 5 6 7 8 tSR tWS tDS D2 MSD tDH D3 D4 D5 D6 D7 D8 Receive Side Figure. 1 Timing Diagram in the Parallel Mode (CHPS = 1) BCLK XSYNC DOUT1 MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 CH1 PCM Data D3 D4 D5 D6 D7 D8 D7 D8 CH2 PCM Data Transmit Side BCLK RSYNC DIN2 MSD D2 D3 D4 D5 D6 CH1 PCM Data D7 D8 MSD D2 D3 D4 D5 D6 CH2 PCM Data Receive Side Figure. 2 Timing Diagram in the Serial Mode (CHPS = 0) 14/18 ¡ Semiconductor MSM7533H/7533V/7534 APPLICATION CIRCUIT Example of Basic Connection (PCM Serial Mode Operation) +5 V MSM7533 AIN1 GSX1 CH1 Analog Input AOUT1 CH1 Analog Output DIN2 DIN1 AIN2 GSX2 CH2 Analog Input SGC AG DG 0.1 mF 0V 10 mF + +5 V 2CH Multiplex PCM (Open) Signal Output 0V CHPS VDD 2CH Multiplex PCM Signal Intput Bit Clock Input Sync Pulse Input BCLK XSYNC RSYNC PDN AOUT2 CH2 Analog Output 1 kW DOUT1 DOUT2 0V Power Down Control Input 1: Operation 0: Power Down 1 mF 0 to 20 W Example of Interface to the Echo Canceller MSM7520 MSM7533 SIN ROUT +5 V 10 kW +5 V AIN1 GSX1 AOUT1 PDN CHPS XSYNC RSYNC BCLK DIN1 DOUT1 AOUT2 GSX2 AIN2 VDD 0.1 mF 10 W + SGC 1 mF 10 mF AG DG 10 kW DOUT2 DIN2 SOUT RIN +5 V 0V +5 V MSM7520-001 RESET POWER DOWN +5 V 0V +5 V SIN ROUT SCK SYNC INT IRLD SYNCO SCKO RST PWDWN CKSEL VDD SOUT RIN NLP GC +5 V HCL ADP ATT VSS X1 X2 36 MHz CLK Input 0V 15/18 ¡ Semiconductor MSM7533H/7533V/7534 RECOMMENDATIONS FOR ACTUAL DESIGN • To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin each other as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup phenomenon when turning the power on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 16/18 ¡ Semiconductor MSM7533H/7533V/7534 PACKAGE DIMENSIONS (Unit : mm) DIP20-P-300-2.54-S1 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.49 TYP. 17/18 ¡ Semiconductor MSM7533H/7533V/7534 (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/18