IDT IDT70T3509MS133BPGI High-speed 2.5v 1024k x 36 synchronous dual-port static ram with 3.3v or 2.5v interface Datasheet

HIGH-SPEED 2.5V
1024K x 36
IDT70T3509M
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
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True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz)(max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Interrupt Flags
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth)
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 133MHz
– Fast 4.2ns clock to data out
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Includes JTAG functionality
Available in a 256-pin Ball Grid Array (BGA)
Common BGA footprint provides design flexibility over
seven density generations (512K to 36M-bit)
Green parts available, see ordering information
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Functional Block Diagram
FT/PIPEL
BE3L
BE3R
BE2L
BE2R
BE1L
BE1R
BE0L
BE0R
1/0
0a 1a
0b 1b
0c 1c
0d 1d
1d 0d
1c 0c
1b 0b
1a 0a
a
b
c
d
d
c
b
a
FT/PIPER
1/0
R/WL
R/WR
(2)
(2)
CE0L
CE1L
1
1
0
0
B B B B B B B B
W W WW W W W W
0 1 2 3 3 2 1 0
L L L L R R R R
1/0
OEL
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
1/0
OER
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
1d 0d 1c 0c 1b 0b 1a 0a
FT/PIPEL
CE0R
CE1R
,
0a 1a 0b 1b 0c 1c 0d 1d
FT/PIPER
0/1
0/1
a b cd
dcba
1024K x 36
MEMORY
ARRAY
I/O0L - I/O35L
Din_L
I/O0R - I/O 35R
Din_R
CLKR
CLKL
,
A19R
A19L
Counter/
Address
Reg.
A0L
REPEATL
ADSL
CNTEN L
Counter/
Address
Reg.
ADDR_R
ADDR_L
A 0R
REPEATR
ADSR
CNTENR
TDI
CE 0 L
CE0 R
CE1R
INTERRUPT
LOGIC
CE1L
R/ W L
JTAG
TDO
TCK
TMS
TRST
R/ WR
INTL
INTR
(1)
ZZL
ZZ
CONTROL
LOGIC
ZZR
(1)
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
2. See Truth Table I for Functionality.
5682 drw 01
AUGUST 2007
1
©2007 Integrated Device Technology, Inc.
DSC 5682/7
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Description:
The IDT70T3509M is a high-speed 1024K x 36 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times. With an input data register, the
IDT70T3509M has been optimized for applications having unidirectional
or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70T3509M can support an operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (VDD) is at 2.5V.
6.42
2
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Pin Configuration (1,2,3,4)
70T3509M BP
BP-256(5,7)
256-Pin BGA
Top View(6)
08/03/04
A1
NC
B1
I/O18L
C1
A2
TDI
B2
NC
C2
I/O18R I/O19L
D1
D2
A3
A19L
B3
TDO
C3
VSS
D3
A4
A 17L
B4
A 18L
C4
A16L
D4
A5
A6
A 14L
A11L
B5
B6
A15L
C5
A13L
D5
A12L
C6
A10L
D6
A7
A 8L
B7
A 9L
C7
A7L
D7
A9
A8
BE2L
CE1L
B9
B8
BE3L
BE1L
B10
B11
C10
C11
BE0L CLKL ADSL
D9
D8
A11
A12
OEL CNTENL A5L
CE0L R/WL REPEATL
C9
C8
A10
D10
D11
B12
A4L
C12
A6L
D12
A13
A2L
B13
A1L
C13
A3L
D13
A14
A0L
B14
VDD
C14
A15
A16
NC
NC
B16
B15
I/O17L
NC
C16
C15
OPTL I/O17R I/O16L
D14
D16
D15
I/O20R I/O19R I/O20L PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R
E1
E2
E3
E4
I/O21R I/O21L I/O22L VDDQL
F1
F2
F3
F4
E5
VDD
F5
I/O23L I/O22R I/O23R VDDQL VDD
G1
G2
G3
G4
I/O24R I/O24L I/O25L VDDQR
H1
H2
H3
H4
G5
VSS
H5
I/O26L I/O25R I/O26R VDDQR VSS
J1
J2
J3
J4
I/O27L I/O28R I/O27R VDDQL
K1
K2
K3
K4
I/O29R I/O29L I/O28L VDDQL
L1
L2
L3
L4
J5
ZZR
K5
VSS
L5
I/O30L I/O31R I/O30R VDDQR VDD
M1
M2
M3
M4
I/O32R I/O32L I/O31L VDDQR
N1
N2
N3
N4
M5
VDD
N5
E6
VDD
F6
E7
INTL
F7
NC
G6
VSS
H6
VSS
J6
VSS
K6
VSS
L6
NC
M6
VDD
N6
NC
G7
VSS
H7
VSS
J7
VSS
K7
VSS
L7
NC
M7
INTR
N7
E9
E8
VSS
VSS
F9
F8
VSS
VSS
G9
G8
VSS
H8
VSS
H9
VSS
J8
VSS
J9
VSS
K8
VSS
K9
VSS
L8
VSS
L9
VSS
M8
VSS
M9
VSS
N8
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
V SS
J10
VSS
K10
VSS
L10
V SS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
F12
P2
P3
I/O35R I/O34L TMS
R1
I/O35L
T1
NC
R2
NC
T2
TCK
R3
P4
A16R
R4
TRST A18R
T3
A19R
T4
A17R
P5
A13R
R5
A15R
T5
A14R
P6
A10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P8
P9
P10
P11
BE1R BE0R CLKR ADS R
R8
R9
R10
R11
G12
VSS
H12
VSS
J12
T9
BE2R CE1R
T10
T11
E16
E15
F13
F14
F15
F16
G13
G14
G15
G16
VDDQL I/O10L I/O11L I/O11R
H13
H14
VDDQL I/O9R
J13
J14
H16
H15
IO9L I/O10R
J15
J16
ZZL VDDQR I/O8R I/O7R
K12
VSS
L12
VDD
M12
VDD
N12
P12
A6R
R12
BE3R CE0R R/WR REPEATR A4R
T8
E14
VDD VDDQR I/O12R I/O13R I/O12L
I/O33L I/O34R I/O33R P IP E /FTR V DDQR VDDQR VDDQL VDDQL V DDQR VDDQR VDDQL VDDQL
P1
E13
VDD VDDQR I/O13L I/O14L I/O14R
T12
OER CNTENR A5R
K13
K14
K15
I/O8L
K16
VDDQR I/O6R I/O6L I/O7L
L13
L14
VDDQL I/O5L
M13
M14
VDDQL I/O3R
N13
VDD
P13
A3R
R13
A1R
T13
A2R
N14
I/O2L
P14
L15
L16
I/O4R I/O5R
M16
M15
I/O3L I/O4L
N16
N15
I/O1R I/O2R
P15
P16
I/O0L I/O0R
R14
OPTR
T14
A 0R
I/O1L
R16
R15
NC
T15
NC
,
T16
NC
NC
5682 drw 02d
NOTES:
,
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.76mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. BP-256 package thickness is 1.76mm nominal. This is thicker than the BC-256 package (1.40mm nominal) used for the lower density IDT dual-port products.
6.42
3
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (Input)(5)
R/WL
R/WR
Read/Write Enable (Input)
OEL
OER
Output Enable (Input)
A0L - A19L
A0R - A19R
Address (Input)
I/O0L - I/O35L
I/O0R - I/O35R
Data Input/Output
CLKL
CLKR
Clock (Input)
PL/FTL
PL/FTR
Pipeline/Flow-Through (Input)
ADSL
ADSR
Address Strobe Enable (Input)
CNTENL
CNTENR
Counter Enable (Input)
REPEATL
REPEATR
Counter Repeat(3) (Input)
BE0L - BE3L
BE0R - BE3R
Byte Enables (9-bit bytes) (Input)(5)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
OPTL
OPTR
Option for selecting VDDQX(1,2) (Input)
ZZL
ZZR
INTL
Sleep Mode pin(4) (Input)
VDD
Power (2.5V)(1) (Input)
VSS
Ground (0V) (Input)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz) (Input)
TMS
Test Mode Select (Input)
TRST
Reset (Initialize TAP Controller) (Input)
INTR
Interrupt Flag (Output)
5682 tbl 01
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPT X is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADS X.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundary scan not be operated during sleep mode.
5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
4
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
OE
CLK
CE0
CE 1
BE3
BE2
BE1
BE0
R/W
ZZ
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
X
↑
H
L
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
X
↑
L
L
X
X
X
X
X
X
Active
Active
Active
Active
Not Allowed
X
↑
H
H
X
X
X
X
X
X
Active
Active
Active
Active
Not Allowed
X
↑
L
H
H
H
H
H
X
L
High-Z
High-Z
High-Z
High-Z
All Bytes Deselected
X
↑
L
H
H
H
H
L
L
L
High-Z
High-Z
High-Z
DIN
Write to Byte 0 Only
X
↑
L
H
H
H
L
H
L
L
High-Z
High-Z
DIN
High-Z
Write to Byte 1 Only
X
↑
L
H
H
L
H
H
L
L
High-Z
DIN
High-Z
High-Z
Write to Byte 2 Only
X
↑
L
H
L
H
H
H
L
L
DIN
High-Z
High-Z
High-Z
Write to Byte 3 Only
X
↑
L
H
H
H
L
L
L
L
High-Z
High-Z
DIN
DIN
X
↑
L
H
L
L
H
H
L
L
DIN
DIN
High-Z
High-Z
X
↑
L
H
L
L
L
L
L
L
DIN
DIN
DIN
DIN
Write to All Bytes
L
↑
L
H
H
H
H
L
H
L
High-Z
High-Z
High-Z
DOUT
Read Byte 0 Only
L
↑
L
H
H
H
L
H
H
L
High-Z
High-Z
DOUT
High-Z
Read Byte 1 Only
L
↑
L
H
H
L
H
H
H
L
High-Z
DOUT
High-Z
High-Z
Read Byte 2 Only
L
↑
L
H
L
H
H
H
H
L
DOUT
High-Z
High-Z
High-Z
Read Byte 3 Only
L
↑
L
H
H
H
L
L
H
L
High-Z
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
L
↑
L
H
L
L
H
H
H
L
DOUT
DOUT
High-Z
High-Z
Read Upper 2 Bytes Only
MODE
Deselected–Power Down
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
L
↑
L
H
L
L
L
L
H
L
DOUT
DOUT
DOUT
DOUT
H
↑
X
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Outputs Disabled
X
X
X
X
X
X
X
X
X
H
High-Z
High-Z
High-Z
High-Z
Sleep Mode
Read All Bytes
5682 tbl 02
NOTES:
1. "H" = V IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = VIH.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II—Address Counter Control
Address
Previous
Internal
Address
Internal
Address
Used
CLK
An
X
An
↑
ADS
L(4)
CNTEN
REPEAT(6)
I/O(3)
X
H
DI/O (n)
(1,2)
MODE
External Address Used
X
An
An + 1
↑
H
L
H
DI/O(n+1)
Counter Enabled—Internal Address generation (7)
X
An + 1
An + 1
↑
H
H
H
DI/O(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
An
↑
X
(4)
X
X
X
(5)
DI/O(n)
L
Counter Set to last valid ADS load
5682 tbl 03
NOTES:
1. "H" = V IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE 0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
7. Address A 19 must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000H through 7FFFFH the value
of a A19 is 0, while for physical addresses 80000H through FFFFF H the value of A19 is 1. The user needs to keep track of the device counter and make sure that
A19 is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter operation and that A19 is in the appropriate
state when using the REPEAT function.
6.42
5
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
(1)
Ambient
Temperature
GND
VDD
0OC to +70OC
0V
2.5V + 100mV
-40OC to +85OC
0V
2.5V + 100mV
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
5682 tbl 04
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
2.4
2.5
2.6
V
VDDQ
I/O Supply Voltage (3)
2.4
2.5
2.6
V
VSS
Ground
0
0
0
V
VIH
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
1.7
____
VDDQ + 100mV(2)
V
VIH
Input High Voltage
JTAG
1.7
____
VDD + 100mV(2)
V
VIH
Input High Voltage ZZ, OPT, PIPE/FT
VDD - 0.2V
____
VDD + 100mV(2)
V
VIL
Input Low Voltage
-0.3(1)
____
0.7
V
VIL
Input Low Voltage ZZ, OPT, PIPE/FT
-0.3(1)
____
0.2
V
_
5682 tbl 05a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to Vss(0V), and V DDQX for that port must be supplied as indicated
above.
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol
VDD
VDDQ
Parameter
Core Supply Voltage
I/O Supply Voltage
(3)
Min.
Typ.
Max.
Unit
2.4
2.5
2.6
V
3.15
3.3
3.45
V
0
0
0
V
2.0
____
VDDQ + 150mV(2)
V
1.7
____
VDD + 100mV(2)
V
VDD - 0.2V
____
VDD + 100mV(2)
V
VSS
Ground
VIH
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
VIH
Input High Voltage
JTAG
VIH
Input High Voltage ZZ, OPT, PIPE/FT
VIL
Input Low Voltage
-0.3(1)
____
0.8
V
VIL
Input Low Voltage ZZ, OPT, PIPE/FT
-0.3(1)
____
0.2
V
_
5682 tbl 05b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = V DDQ + 1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin
for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated
above.
6.42
6
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Absolute Maximum Ratings (1)
Symbol
Rating
Com'l
& Ind
Unit
VTERM
(VDD)
VDD Terminal Voltage
with Respect to GND
-0.5 to 3.6
VTERM(2)
(VDDQ)
VDDQ Terminal Voltage
with Respect to GND
-0.3 to VDDQ + 0.3
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to VDDQ + 0.3
V
TBIAS(3)
Temperature Under Bias
-55 to +125
o
C
TSTG
Storage Temperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
IOUT(For VDDQ = 3.3V) DC Output Current
50
IOUT(For VDDQ = 2.5V) DC Output Current
40
V
mA
mA
5682 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) BGA ONLY
Symbol
Parameter
Input Capacitance
CIN
(2)
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
35
pF
VOUT = 0V
35
pF
5682 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T3509MS
Symbol
|ILI|
|ILI|
|ILO|
VOL (3.3V)
Parameter
Test Conditions
Input Leakage Current(1)
(1,2)
JTAG & ZZ Input Leakage Current
(1,3)
Output Leakage Current
Output Low Voltage
(1)
(1)
Min.
Max.
Unit
VDDQ = Max., VIN = 0V to VDDQ
___
20
µA
VDD = Max., V IN = 0V to VDD
___
60
µA
CE0 = VIH and CE1 = VIL, VOUT = 0V to VDDQ
___
20
µA
IOL = +4mA, VDDQ = Min.
___
0.4
V
V
V
VOH (3.3V)
Output High Voltage
IOH = -4mA, V DDQ = Min.
2.4
___
VOL (2.5V)
Output Low Voltage (1)
IOL = +2mA, VDDQ = Min.
___
0.4
VOH (2.5V)
Output High Voltage (1)
IOH = -2mA, V DDQ = Min.
2.0
___
V
5682 tbl 08
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
6.42
7
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (3) (VDD = 2.5V ± 100mV)
70T3509MS133
Com'l
& Ind
Symbol
IDD
ISB1(6)
ISB2(6)
ISB3
ISB4(6)
Izz
Parameter
Test Condition
Version
Typ. (4)
Max.
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM'L
S
800
1120
IND
S
800
1370
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
S
560
760
IND
S
560
940
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = V IH(5)
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
680
880
IND
S
680
1090
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CE0L = CE0R > VDD - 0.2V and
CE1L = CE1R < 0.2V,
VIN > V DDQ - 0.2V or VIN < 0.2V, f = 0(2)
COM'L
S
20
60
IND
S
20
80
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5)
VIN > V DDQ - 0.2V or VIN < 0.2V
Active Port, Outputs Disabled, f = fMAX(1)
COM'L
S
680
880
IND
S
680
1090
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR = VIH
f=fMAX(1)
COM'L
S
20
60
IND
S
20
80
Unit
mA
mA
mA
mA
mA
mA
5682 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 30mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH (enabled)
CEX = VIH means CE0X = VIH and CE1X = VIL (disabled)
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V (enabled - CMOS levels)
CEX > VDD - 0.2V means CE0X > VDD - 0.2V and CE1X < 0.2V (disabled - CMOS levels)
"X" represents "L" for left port or "R" for right port.
6. ISB1, I SB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
6.42
8
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
GND to 3.0V/GND to 2.4V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.4V
Input Rise/Fall Times
2ns
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Output Load
Figure 1
5682 tbl 10
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
5682 drw 03
Figure 1. AC Output Test load.
∆ tCD
(Typical, ns)
∆ Capacitance (pF) from AC Test Load
6.42
9
5682 drw 04
,
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
70T3509MS133
Com'l
& Ind
Symbol
Parameter
(1)
Min.
Max.
Unit
ns
tCYC1
Clock Cycle Time (Flow-Through)
25
____
tCYC2
Clock Cycle Time (Pipelined)(1)
7.5
____
ns
tCH1
Clock High Time (Flow-Through)(1)
10
____
ns
tCL1
Clock Low Time (Flow-Through)(1)
10
____
ns
tCH2
Clock High Time (Pipelined)(2)
3
____
ns
ns
(1)
tCL2
Clock Low Time (Pipelined)
3
____
tSA
Address Setup Time
1.8
____
ns
tHA
Address Hold Time
0.5
____
ns
tSC
Chip Enable Setup Time
1.8
____
ns
tHC
Chip Enable Hold Time
0.5
____
ns
ns
tSB
Byte Enable Setup Time
1.8
____
tHB
Byte Enable Hold Time
0.5
____
ns
tSW
R/W Setup Time
1.8
____
ns
tHW
R/W Hold Time
0.5
____
ns
tSD
Input Data Setup Time
1.8
____
ns
ns
tHD
Input Data Hold Time
0.5
____
tSAD
ADS Setup Time
1.8
____
ns
tHAD
ADS Hold Time
0.5
____
ns
tSCN
CNTEN Setup Time
1.8
____
ns
tHCN
CNTEN Hold Time
0.5
____
ns
tSRPT
REPEAT Setup Time
1.8
____
ns
tHRPT
REPEAT Hold Time
0.5
____
ns
tOE
Output Enable to Data Valid
____
4.6
ns
tOLZ(4)
Output Enable to Output Low-Z
1
____
ns
tOHZ(4)
Output Enable to Output High-Z
1
4.2
ns
tCD1
Clock to Data Valid (Flow-Through)(1)
____
15
ns
tCD2
Clock to Data Valid (Pipelined)(1)
____
4.2
ns
ns
tDC
Data Output Hold After Clock High
1
____
tCKHZ(4)
Clock High to Output High-Z
1
4.2
ns
tCKLZ(4)
Clock High to Output Low-Z
1
____
ns
tINS
Interrupt Flag Set Time
____
7
ns
tINR
Interrupt Flag Reset Time
____
7
ns
tCOLS
Collision Flag Set Time
____
4.2
ns
tCOLR
Collision Flag Reset Time
____
4.2
ns
tZZSC
Sleep Mode Set Cycles
2
____
cycles
tZZRC
Sleep Mode Recovery Cycles
3
____
cycles
6
____
Port-to-Port Delay
tCO
Clock-to-Clock Offset
ns
5682 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4. Guaranteed by design (not production tested).
6.42
10
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(1,2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tSB
tHB
BEn
R/W
tSW tHW
tSA
ADDRESS
(4)
tHA
An
An + 1
(1 Latency)
An + 2
An + 3
tDC
tCD2
DATAOUT
Qn
tCKLZ
OE
tHB
(5)
Qn + 1
Qn + 2
(5)
(1)
tOHZ
tOLZ
(1)
,
tOE
5682 drw 05
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE"X" = VIL)(1,2,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tSC
tHC
(3)
CE1
tSB
tHB
BEn
tSB
R/W
tHB
tSW tHW
tSA
ADDRESS
tHC
(4)
tHA
An
An + 1
tCD1
An + 2
tCKHZ
Qn
DATAOUT
Qn + 1
tCKLZ
OE
An + 3
tDC
tOHZ
Qn + 2
tOLZ
(5)
tDC
(1)
tOE
5682 drw 06
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
11
,
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
tSW
tHW
tSA
tHA
R/W"A
"
ADDRESS"A"
NO
MATCH
MATCH
tSD
DATAIN"A"
tHD
VALID
tCO(3)
CLK"B"
tCD2
R/W"B"
ADDRESS"B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
DATAOUT"B"
VALID
,
tDC
5682 drw 09
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2 ). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + t CYC2 + t CD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
tSW tHW
R/W "A"
tSA
ADDRESS "A"
"A"
NO
MATCH
MATCH
tSD
DATAIN
tHA
tHD
VALID
tCO
(3)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
,
5682 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + t CYC + tCD1 ). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + t CD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
12
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
BEn
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(1)
tCKHZ
tCKLZ
tCD2
Qn + 3
Qn
DATAOUT
(4)
READ
NOP
WRITE
READ
5682 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
,
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2)
tCH2
tCYC2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
BEn
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Dn + 2
tCD2
(1)
Qn
DATAOUT
An + 3
An + 4
An + 5
tHD
Dn + 3
tCKLZ
tCD2
Qn + 4
(4)
tOHZ
OE
READ
WRITE
READ
,
NOTES:
5682 drw 12
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
13
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
tCH1
tCYC1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
BEn
tSW tHW
R/W
tSW tHW
(3)
An
tSA tHA
ADDRESS
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(1)
tCD1
Qn
DATAOUT
tCD1
Qn + 1
tDC
tCKLZ
tCKHZ
(5)
NOP
READ
WRITE
tCD1
Qn + 3
tDC
READ
,
5682 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
BEn
tSW tHW
tSW tHW
R/W
(3)
An
tSA tHA
ADDRESS
An +1
DATAIN
(1)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
An + 4
tOE
tCD1
Qn
tCKLZ
tOHZ
An + 5
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
5682 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
14
,
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
A0 - A18
tHA
An
tSA
A19(3)
tSAD tHAD
ADS
tSAD tHAD
CNTEN
t SCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
,
Qn + 3
(3)
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5682 drw 15a
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCYC1
tCH1
tCL1
CLK
tSA
A0 - A18
tHA
An
tSA
A19(3)
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
tDC
READ
EXTERNAL
ADDRESS
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
,
(3)
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
5682 drw 16a
NOTES:
1. CE 0, OE, BEn = VIL; CE1, R/W, and REPEAT = V IH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
remains constant for subsequent clocks.
3. Address A19 must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000H through 7FFFFH the
value of a A19 is 0, while for physical addresses 80000H through FFFFFH the value of A19 is 1. The user needs to keep track of the device counter and make
sure that A19 is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter operation. As shown this
transition reflects An = 7FFFF H or FFFFFH.
6.42
15
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
A0 - A18
tHA
An
tSA
A19(7)
INTERNAL(3)
ADDRESS
An(5)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
tSCN tHCN
CNTEN
(5)
tSD tHD
Dn + 1
Dn
DATAIN
Dn + 1
Dn + 4
Dn + 3
Dn + 2
(7)
WRITE
EXTERNAL
ADDRESS
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5682 drw 17a
Timing Waveform of Counter Repeat(2,6)
tCYC2
CLK
tSA tHA
A0 - A18
An
tSA
A19(7)
INTERNAL(3)
ADDRESS
An+2
An+1
An
An+2
An
An+1
An+2
An+2
tSAD tHAD
ADS
tSW tHW
R/W
tSCN tHCN
CNTEN
REPEAT
(4)
tSRPT tHRPT
,
tSD tHD
DATAIN
D0
D3
D2
D1
tCD1
An
DATAOUT
An+1
An+2
An+2
(7)
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
WRITE TO
An+1
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
REPEAT
READ LAST
ADS
ADDRESS
An
,
ADVANCE
COUNTER
READ
An+1
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
NOTES:
5682 drw 18a
1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II. A19 must be in the appropriate state when using the REPEAT
function to guarantee the correct address location is loaded.
5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
7. Address A19 must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000H through 7FFFFH the
value of a A19 is 0, while for physical addresses 80000H through FFFFFH the value of A19 is 1. The user needs to keep track of the device counter and make
sure that A19 is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter operation. As shown this
transition reflects An = 7FFFFH or FFFFFH.
6.42
16
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Waveform of Interrupt Timing(2)
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL(3)
FFFFF
tSC
tHC
CEL(1)
tINS
INT R
tINR
CLKR
tSC
tHC
CER(1)
R/WR
ADDRESS
tSW
tHW
tSA
tHA
FFFFF
R(3)
5682 drw 19
NOTES:
1. CE 0 = VIL and CE1 = V IH.
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e. address needs to be qualified by one of the Address counter control signals.
Truth Table III - Interrupt Flag(1)
Left Port
CLKL
R/WL
(2)
CEL
(2)
Right Port
A19L-A0L
INT L
CLKR
R/WR
CER(2)
A19R-A0R
INTR
(2)
Function
↑
L
L
FFFFF
X
↑
X
X
X
L
Set Right INT R Flag
↑
X
X
X
X
↑
H
L
FFFFF
H
Reset Right INT R Flag
↑
X
X
X
L
↑
L
L
FFFFE
X
Set Left INTL Flag
↑
H
L
FFFFE
H
↑
X
X
X
X
Reset Left INTL Flag
5682 tbl 12
NOTES:
1. INT L and INTR must be initialized at power-up by Resetting the flags.
2. CE 0 = VIL and CE1 = V IH, R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. Address is for internal register, not the external bus, i.e. address needs to be qualified by one of the Address counter control signals.
6.42
17
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform - Entering Sleep Mode (1,2)
R/W
(3)
Timing Waveform - Exiting Sleep Mode
(1,2)
An
An+1
(5)
R/W
OE
(5)
Dn
DATAOUT
Dn+1
(4)
NOTES:
1. CE1 = V IH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = V IH).
4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = V IL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42
18
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Functional Description
Sleep Mode
The IDT70T3509M provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
The combination of a HIGH on CE0 and a LOW on CE1 for one clock
cycle will power down the internal circuitry to reduce static power
consumption. Multiple chip enables allow easier banking of multiple
IDT70T3509Ms for depth expansion configurations. Two cycles are
required with CE0 LOW and CE1 HIGH to re-activate the outputs.
The IDT70T3509M is equipped with an optional sleep or low power
mode on both ports. The sleep mode pin on both ports is asynchronous
and active high. During normal operation, the ZZ pin is pulled low. When
ZZ is pulled high, the port will enter sleep mode where it will meet lowest
possible power conditions. The sleep mode timing diagram shows the
modes of operation: Normal Operation, No Read/Write Allowed and Sleep
Mode.
For normal operation all inputs must meet setup and hold times prior
to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device
must be disabled via the chip enable pins. If a write or read operation occurs
during these periods, the memory array may be corrupted. Validity of data
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enable must be valid for one full cycle before a read will result in the output
of valid data.
During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (IZZ). All outputs will remain in
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.
Width Expansion
The IDT70T3509M can be used in applications requiring expanded
width. Through combining the control signals, the devices can be grouped
as necessary to accommodate applications needing 72-bits or wider.
6.42
19
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
JTAG Functionality and Configuration
The IDT70T3509M is composed of four independent memory arrays,
and thus cannot be treated as a single JTAG device in the scan chain.
The four arrays (A, B, C and D) each have identical characteristics and
commands but must be treated as separate entities in JTAG operations.
Please refer to Figure 2.
JTAG signaling must be provided serially to each array and utilize the
information provided in the Identification Register Definitions, Scan
Register Sizes, and System Interface Parameter tables. Specifically, all
serial commands must be issued to the IDT70T3509M in the following
sequence: Array D, Array C, Array B, Array A. Please reference
Application Note AN-411, "JTAG Testing of Multichip Modules" for specific
instructions on performing JTAG testing on the IDT70T3509M. AN-411
is available at www.idt.com.
IDT70T3509M
TDOB
Array B
Array C
TDIC
TDIB
TDOC
TDOA
TDID
Array A
Array D
TDI
TCK
TMS
TRST
5682 drw 24
Figure 2. JTAG Configuration for IDT70T3509M
6.42
20
TDO
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
,
Figure 5. Standard JTAG Timing
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics (1,2,3,4)
70T3509M
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
JTAG Clock Low
40
____
ns
JTAG Clock Rise Time
____
(1)
ns
(1)
tJCL
tJR
3
tJF
JTAG Clock Fall Time
____
3
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
JTAG Data Output
____
25
ns
ns
ns
tJCD
tJDC
JTAG Data Output Hold
0
____
tJS
JTAG Setup
15
____
tJH
JTAG Hold
15
____
ns
5682 tbl 15
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
21
5682 drw 25
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Identification Register Definitions
Instruction Field Array D
Value
Array D
Revision Number (31:28)
0x0
Instruction Field Array C
Value
Array C
Revision Number (63:60)
0x0
Instruction Field Array B
Revision Number (95:92)
Value
Array B
0x0
Value
Instruction Field Array A
Description
Array A
Revision Number (127:124)
0x0
Reserved for Version number
IDT Device ID (27:12)
0x333 IDT Device ID (59:44)
0x333 IDT Device ID (91:76)
0x333 IDT Device ID (123:108)
0x333 Defines IDT Part number
IDT JEDEC ID (11:1)
0x33 IDT JEDEC ID (43:33)
0x33
0x33
0x33
ID Register Indicator Bit (Bit 0)
1
ID Register Indicator Bit (Bit 32)
1
IDT JEDEC ID (75:65)
ID Register Indicator Bit (Bit 64)
1
IDT JEDEC ID (107:97)
ID Register Indicator Bit (Bit 96)
1
Allows unique identification of device vendor as IDT
Indicates the presence of an ID Register
5682 tbl 16
Scan Register Sizes
Bit Size
Array A
Bit Size
Array B
Bit Size
Array C
Bit Size
Array D
Bit Size
70T3509M
Instruction (IR)
4
4
4
4
16
Bypass (BYR)
1
1
1
1
4
32
32
32
32
128
Note (3)
Note (3)
Note (3)
Note (3)
Note (3)
Register Name
Identification (IDR)
Boundary Scan (BSR)
5682 tbl 17
System Interface Parameters
Instruction
Code
Description
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000000000000000
BYPASS
1111111111111111
IDCODE
0010001000100010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100010001000100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers except INTx to a High-Z state.
HIGHZ
CLAMP
0011001100110011
SAMPLE/PRELOAD
0001000100010001
RESERVED
PRIVATE
Places the bypass register (BYR) between TDI and TDO.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
0101010101010101, 0111011101110111, Several combinations are reserved. Do not use codes other than those
1000100010001000, 1001100110011001, identified above.
1010101010101010, 1011101110111011,
1100110011001100
0110011001100110,1110111011101110,
1101110111011101
For internal use only.
5682 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
22
IDT70T3509M
High-Speed 2.5V
1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Ordering Information
IDT XXXXX
Device
Type
A
999
A
Power
Speed
Package
A
A
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
BP(3)
256-pin BGA (BP-256)
133
Commercial and Industrial Speed in Megahertz
S
Standard Power
70T3509M
36Mbit (1024K x 36) 2.5V Synchronous Dual-Port RAM
5682 drw 26
NOTES:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
3. BP-256 package thickness is 1.76mm nominal. This is thicker than the BC-256 package (1.40mm nominal) used for the lower density IDT dual-port products.
Datasheet Document History:
11/09/04:
03/24/05:
06/14/05:
08/27/07:
Initial Public Release of Preliminary Datasheet
Page 1 Added I-temp offering to features
Page 6 Added I-temp information to the Recommended Operating Temperature and Supply Voltage table
Page 8 Added I-temp values to the DC Electrical Characteristics table
Page 10 Added I-temp to the heading of the AC Electrical Characteristics table
Page 23 Added I-temp to ordering information
Page 1 Added green availability to features
Page 1 - 23 Removed Preliminary status
Page 1 Added feature to highlight footprint compatibility
Page 3 & 23 Added a footnote to highlight package thickness of BP-256 vs. BC-256
Page 1 Functional Block Diagram changed to correct chip enable logic and added footnote 2 referencing Truth Table I
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800-345-7015 or 408-284-8200
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www.idt.com
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6.42
23
for Tech Support:
408-284-2794
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