ETC GLT41316-50P 64k x 16 cmos dynamic ram with fast page mode Datasheet

G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Features :
Description :
∗
∗
∗
∗
∗
The GLT41316 is a 65,536 x 16 bit highperformance CMOS dynamic random access
memory. The GLT41316 offers Fast Page
mode ,and has both BYTE WRITE and
WORD WRITE access cycles via two WE
pins. The GLT41316 has symmetric address
and accepts 256-cycle refresh in 4ms
interval.
All inputs are TTL compatible. Fast
Page Mode operation allows random access
up to 256x16 bits, within a page, with cycle
times as short as 18ns.
The GLT41316 is best suited for
graphics, and DSP applications requiring
high performance memories.
65,536 words by 16 bits organization.
Fast access time and cycle time.
Dual WE Input.
Low power dissipation.
Read-Modify-Write, RAS -Only Refresh,
CAS -Before- RAS Refresh, Hidden
Refresh and Test Mode Capability.
∗ 256 refresh cycles per 4ms.
∗ Available in 40-pin 400 mil SOJ,and 40/44
pin TSOP (II).
∗ Single 5.0V±10% Power Supply.
∗ All inputs and Outputs are TTL
compatible. ∗
Fast Page Mode operation.
HIGH PERFORMANCE
30
35
40
45
Max. RAS Access Time, (tRAC)
30 ns
35 ns
40 ns
45 ns
Max. Column Address Access Time, (tAA)
15 ns
18 ns
20 ns
22 ns
Min. Fast Page Mode Cycle Time, (tPC)
18 ns
21 ns
23 ns
25 ns
Min. Read/Write Cycle Time, (tRC)
65 ns
70 ns
75 ns
80 ns
Max. CAS Access Time (tCAC)
10 ns
11 ns
12 ns
12 ns
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-1-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Pin Configuration :
TSOP(Type II)
Top View
GLT41316
SOJ Top View
Pin Descriptions:
Name
A0 - A7
Function
RAS
Address Inputs
Row Address Strobe
CAS
Column Address Strobe
UW
Read / Upper Byte Write Enable
LW
Read / Lower Byte Write Enable
OE
DQ0 - DQ15
VCC
VSS
NC
Output Enable
Data Inputs / Outputs
+5V Power Supply
Ground
No Connection
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-2-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Absolute Maximum Ratings*
Capacitance*
TA=25°C, VCC=5V±10%, VSS=0V
Operating Temperature, TA (ambient)
.......................................-0°C to +70°C
Storage Temperature(plastic)....-55°C to +150°C
Voltage Relative to VSS...............-1.0V to + 7.0V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Symbol
Parameter
Max. Unit
CIN1
Address Input
5
pF
CIN2
RAS , CAS , UW , LW , OE
7
pF
COUT
Data Input/Output
7
pF
*Note: Operation above Absolute Maximum Ratings *Note: Capacitance is sampled and not 100% tested
can adversely affect device reliability.
Electrical Specifications
l
l
l
WE means UW and LW .
All voltages are referenced to GND.
After power up, wait more than 100µs and then, execute eight CAS -before- RAS or RAS -only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-3-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Truth Table: GLT41316
Function
ADDRESS
DQs
RAS
CAS
UW
LW
OE
Standby
H
H→X
X
X
X
Read: Word
L
L
H
H
L
ROW/COL Data Out
Write: Word(Early Write)
L
L
L
L
X
ROW/COL Data-In
Write: Lower Byte (Early)
L
L
H
L
X
Write: Upper Byte (Early)
L
L
L
H
X
Read Write
L
L
H→L
H→L
L→H
ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
ROW/COL Data-Out,Data-In
H
H
L
H
L
Note
s
High-Z
ROW/COL Data-Out
Fast-Page-
1st Cycle
L
H→L
Mode Read
2nd Cycle
L
H→L
Fast-Page-
1st Cycle
L
H→L
L
L
X
Mode Write
2nd Cycle
L
H→L
L
L
X
Fast-Page-
1st Cycle
L
H→L
H→L
H→L
L→H
2nd Cycle
L
H→L
H→L
H→L
L→H
Read
L→H→L
L
H
H
L
ROW/COL Data-Out
Write
L→H→L
L
L
L
L
X
ROW/COL Data-In
H
X
X
X
H→L
L
X
X
X
COL
Data-Out
ROW/COL Data-In
COL
Data-In
ROW/COL Data-Out,Data-In
1,2
1
1
2
2
1,2
Mode ReadWrite
Hidden
Refresh
RAS -Only Refresh
CBR Refresh
COL
ROW
Data-Out,Data-In
High-Z
High-Z
Notes:
1. These READ cycles are always WORD READ cycles .
2. These WRITE cycles may also be BYTE READ cycles (either UW or LW active).
3. EARLY WRITE only.
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-4-
1,2
1
2,3
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.
Sym.
Parameter
ILI
Input Leakage Current
(any input pin)
ILO
Output Leakage Current
(for High-Z State)
Operating Current,
Random READ/WRITE
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
Standby Current,(TTL)
Refresh Current,
RAS-Only
Operating Current,
EDO Page Mode
Refresh Current,
CAS Before RAS
Standby Current, (CMOS)
Test Conditions
Access
Time
0V ≤ VIN ≤ 5.5V
(All other pins not under
test=0V)
0V ≤ Vout ≤ 5.5V
Output is disabled (Hiz)
Min.
+10
µA
-10
+10
µA
180
170
160
150
RAS , CAS at VIH
other inputs ≥VSS
RAS cycling, CAS at
VIH
tRC = tRC (min.)
RAS at VIL, CAS ,
address cycling: tPC =
tPC(min.)
RAS , CAS ,
address cycling:
tRC = tRC (min.)
Max. Unit Notes
-10
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
tRC = tRC (min.)
Typ
4
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
180
170
160
150
180
170
160
150
RAS ≥VCC-0.2V,
CAS ≥VCC-0.2V,
mA
1,2
mA
mA
2
mA
1,2
mA
1
2
mA
+0.8
VCC+1
0.4
V
V
V
V
All other inputs ≥VSS
VIL
VIH
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
2.4
IOL = 4.2mA
IOH = -5mA
2.4
3
3
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of
one transition per address cycle in random Read/Write and Fast Page Mode.
3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not
to exceed 20ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-5-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
AC Characteristics (0° C ≤ TA ≤ 70° C, See note 1,2)
Test condition:VCC=5.0V±10%, VIH/VIL=2.4V/0.8V,VOH/VOL=2.4V/0.4V
Parameter
tRAC = 30 ns tRAC = 35 ns tRAC = 40 ns tRAC = 45 ns
Symbo MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Notes
l
Read/Write Cycle Time
Read Midify Write Cycle Time
tRC
tRWC
tRAC
65
80
-
30
70
99
-
35
75
105
-
40
80
110
-
45
ns
ns
ns
3,4
tCAC
-
10
-
11
-
12
-
12
ns
3,4
tAA
tCLZ
0
15
0
18
-
0
20
-
0
22
-
ns
ns
3,4
3
tOFF
3
8
3
8
3
8
3
8
ns
7
tT
tRP
3
25
50
-
3
25
50
-
3
25
50
-
3
25
50
-
ns
ns
2
tRAS
30
100k
35
100k
40
100K
45
tRSH
10
-
12
-
12
-
13
-
ns
tCSH
30
-
36
-
40
-
46
-
ns
tCAS
10
10000
12
10000
12
10000
13
tRCD
13
20
17
24
18
28
18
33
ns
4
tRAD
10
15
12
17
13
20
13
23
ns
4
tCRP
5
-
5
-
5
-
5
-
ns
8
tASR
tRAH
tASC
tCAH
tAR
0
7
0
6
26
-
0
7
0
6
30
-
0
8
0
6
34
-
0
8
0
6
39
-
ns
ns
ns
ns
ns
to RAS
Column Address Lead Time Referenced
tRAL
15
-
18
-
20
-
23
-
ns
to RAS
Read Command Setup Time
Read Command Hold Time Referenced
tRCS
tRRH
0
0
-
0
0
-
0
0
-
0
0
-
ns
ns
9
to RAS
Read Command Hold Time Referenced
tRCH
0
-
0
-
0
-
0
-
ns
9
tWCH
6
-
6
-
6
-
6
-
ns
10
tWCR
26
-
30
-
34
-
39
-
ns
5
tWP
6
-
6
-
6
-
6
-
ns
10
Access Time from RAS
Access Time from CAS
Access Time from Column Address
CAS to Output in Low-Z
Output Buffer Turn-off Delay from CAS
Transition Time(Rise and Fall)
RAS Precharge Time
RAS Pulse Width
RAS Hold Time
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time Referenced
100K ns
10000 ns
to CAS
WE Hold Time Referenced to CAS
Write Command Hold Time Referenced
to RAS
WE Pulse Width
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-6-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Parameter
WE Lead Time Referenced to RAS
WE Lead Time Referenced to CAS
Data-In Setup Time
Data-In Hold Time
Data Hold Time Referenced to RAS
WE Setup Time
RAS to WE Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
CAS Setup Time( CAS before RAS
Refresh)
CAS Hold Time( CAS before RAS
Refresh)
RAS to CAS Precharge Time
CAS Precharge Time(CBR Counter Test
Cycle)
tRAC = 30 ns tRAC = 35 ns tRAC = 40 ns tRAC = 45 ns
Symbo MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Notes
l
tRWL
10
-
11
-
12
-
12
-
ns
tCWL
10
-
11
-
12
-
12
-
ns
tDS
tDH
tDHR
0
7
27
-
0
7
31
-
0
8
36
-
0
8
41
-
ns
ns
ns
11
11
6
tWCS
0
-
0
-
0
-
0
-
ns
5
tRWD
47
-
58
-
63
-
68
-
ns
5
tCWD
24
-
29
-
30
-
30
-
ns
5
tAWD
29
-
36
-
38
-
40
-
ns
5
tCSR
5
-
5
-
5
-
5
-
ns
tCHR
10
-
10
-
10
-
10
-
ns
tRPC
5
-
5
-
5
-
5
-
ns
tCPT
20
-
20
-
20
-
20
-
ns
-
18
-
21
-
23
-
25
ns
18
48
-
21
60
-
23
63
-
25
65
-
ns
ns
5.5
-
6
-
7
-
7
-
ns
30
100k
35
100k
40
100K
45
100K
ns
25
-
25
-
25
-
30
-
ns
-
10
-
11
-
12
-
12
ns
8
-
8
-
8
-
8
-
ns
3
8
3
8
3
8
3
8
ns
tOEH
6
-
6
-
7
-
7
-
ns
tWHR
15
-
15
-
15
-
15
-
ns
tREF
-
4
-
4
-
4
-
4
ms
tCPA
Access Time from CAS Precharge
Fast Page mode Read/Write Cycle Time tPC
Fast Page mode Read Modify Write
tPRWC
Cycle Time
t
CAS Precharge Time(Fast Page mode) CP
tRASP
RAS Pulse Width(Fast Page mode)
tRHCP
RAS Hold Time from CAS Precharge
tOEA
Access Time from OE
tOED
OE to Delay Time
Output Buffer Turn-off Delay Time from tOEZ
3
7
OE
OE Hold Time
WE Hold Time(Hidden Refresh Cycle)
Refresh Time(256cycles)
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-7-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Notes
1. An initial pause of 100µs is required after power-up followed by any 8 RAS only Refresh or CAS
before RAS Refresh cycles to initialize the internal circuit.
2. VIH(min.) and VIL(min.) are reference levels for measuring timing of input signals. Transition times
are measured between VIH(min.) and VIL(max.), AC measurements assume tT = 3ns.
3. Measured with an equivalent to 2 TTL loads and 100pF.
4. For read cycles, the access time is defined as follows:
Input Conditions
tRAD ≤ tRAD(MAX.) and tRCD ≤ tRCD(MAX.)
tRAD(max.)< tRAD and tRCD ≤ tRCD(MAX.)
tRCD(max.)< tRCD
Access Time
tRAC(MAX.)
tAA(MAX.)
tCAC(MAX.)
tRAD(MAX.) and tRCD(MAX.) indicate the points which the access time changes and are not the limits of
operation.
5. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data
sheet
as electric characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and the data output
will remain high impedance for the duration of the cycle. If tCWD ≥ tCWD(min.),tRWD ≥ tRWD (min.) and
tAWD ≥ tAWD(min.), then the cycle is a read-modify-write cycle and the data output will contain the data
read from the selected address. If neither of the above conditions is satisfied, the condition of the
data
out is indeterminate.
6. tAR, tWCR, and tDHR are referenced to tRAD(max.).
7. tOFF(max.) and tOEZ(max.) define the time at which the output achieves the open circuit condition and are
not referenced to VOH or VOL.
8. tCRP(min) requirement should be applicable for RAS , CAS cycle preceded by any cycles.
9. Either tRCH(min.) or tRRH(min.) must be satisfied for a read cycle.
10. tWP(min.) is applicable for late write cycle or read modify write cycle. In early write cycles, tWCH(min.)
should be satisfied.
11.This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in
late write or read modify write cycles.
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-8-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Read Cycle
Note : DIN = OPEN
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-9-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Early Write Cycle
NOTE : DOUT = OPEN
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 10 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Late Write Cycle ( OE Controlled Write)
NOET : DOUT = OPEN
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 11 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Read - Modify - Write Cycle
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 12 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Fast Page Read Cycle
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 13 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Fast Page Early Write Cycle
NOTE : DOUT = OPEN
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 14 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Fast Page Mode Late Write Cycle
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 15 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Fast Page Read-Modify-Write Cycle
NOTE : DOUT = OPEN
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 16 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
CAS Before RAS Refresh Cycle
RAS-Only Refresh Cycle
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 17 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Hidden Refresh Cycle ( Read )
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 18 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Hidden Refresh Cycle ( Write )
NOTE : DOUT = OPEN
UW,LW
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 19 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Ordering Information
Part Number
GLT41316-30J4
GLT41316-35J4
GLT41316-40J4
GLT41316-45J4
GLT41316-30TC
GLT41316-35TC
GLT41316-40TC
GLT41316-45TC
SPEED
30ns
35ns
40ns
45ns
30ns
35ns
40ns
45ns
POWER
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
FEATURE
FPM
FPM
FPM
FPM
FPM
FPM
FPM
FPM
PACKAGE
SOJ 400mil 40L
SOJ 400mil 40L
SOJ 400mil 40L
SOJ 400mil 40L
TSOP 400mil 44L
TSOP 400mil 44L
TSOP 400mil 44L
TSOP 400mil 44L
Parts Numbers (Top Mark) Definition :
GLT 4 13
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
16 - 40 J4
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
VOLTAGE
Blank : 5V
L : 3.3V
M : Mix Voltage
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
Note : CÙCDROM , HÙHDD.
Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 20 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Package Information
400mil 40 pin Small Outline J-form Package (SOJ)
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 21 -
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
40/44 Lead Thin Small Outline Package TSOP(Type II)
G-Link Technology Corporation
G-Link Technology Corporation, Taiwan
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 22 -
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