CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 FEATURES: • • • • • • • • • • • • Memory storage capacity: IDT723622 – 256 x 36 x 2 IDT723632 – 512 x 36 x 2 IDT723642 – 1,024 x 36 x 2 Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Two independent clocked FIFOs buffering data in opposite directions Mailbox bypass register for each FIFO Programmable Almost-Full and Almost-Empty flags Microprocessor Interface Control Logic IRA, ORA, AEA, and AFA flags synchronized by CLKA IRB, ORB, AEB, and AFB flags synchronized by CLKB Supports clock frequencies up to 66.7MHz IDT723622 IDT723632 IDT723642 Fast access times of 10ns Available in space-saving 120-pin Thin Quad Flatpack (TQFP) Green parts available DESCRIPTION: The IDT723622/723632/723642 are a monolithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memory which supports clock frequencies up to 66.7MHz and have read access times as fast as 10ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or FUNCTIONAL BLOCK DIAGRAM MBF1 RST1 FIFO1, Mail1 Reset Logic Write Pointer 36 IRA AFA RAM ARRAY 256 x 36 512 x 36 1,024 x 36 Output Register Port-A Control Logic Input Register Mail 1 Register CLKA CSA W/RA ENA MBA 36 Read Pointer ORB AEB Status Flag Logic FIFO 1 Programmable Flag Offset Registers FS0 FS1 A0 - A35 B0 - B35 10 Read Pointer Output Register 36 Status Flag Logic IRB AFB 36 Write Pointer RAM ARRAY 256 x 36 512 x 36 1,024 x 36 Input Register FIFO 2 ORA AEA Mail 2 Register MBF2 FIFO2, Mail2 Reset Logic RST2 Port-B Control Logic CLKB CSB W/RB ENB MBB 3022 drw 01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE FEBRUARY 2015 1 © 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3022/6 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DESCRIPTION (CONTINUED) two-stage synchronized to the port clock that reads data from its array. Offset values for the Almost-Full and Almost-Empty flags of both FIFOs can be programmed from Port A. Two or more devices may be used in parallel to create wider data paths. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs will immediately take the device out of the power down state. The 723622/723632/723642 are characterized for operation from 0°C to 70°C. They are fabricated using high speed, submicron CMOS technology. coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a progammable Almost-Full flag (AFA and AFB). AEA and AEB indicate when a selected number of words remain in the FIFO memory. AFA and AFB indicate when the FIFO contains more than a selected number of words. The Input Ready (IRA, IRB) and Almost-Full (AFA, AFB) flags of a FIFO are two-stage synchronized to the port clock that writes data into its array. The Output Ready (ORA, ORB) and Almost-Empty (AEA, AEB) flags of a FIFO are 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 GND CLKA ENA W/RA CSA IRA ORA VCC AFA AEA MBF2 MBA RST1 FS0 GND FS1 RST2 MBB MBF1 VCC AEB AFB ORB IRB GND CSB W/RB ENB CLKB VCC PIN CONFIGURATION 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC B7 B8 B9 B10 B11 A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 TQFP (PNG120, order code: PF) TOP VIEW 2 3022 drw 03 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 PIN DESCRIPTIONS COMMERCIAL TEMPERATURE RANGE Symbol Name I/O A0-A35 Port A Data AEA Port A AlmostEmpty Flag O (Port A) Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2. AEB Port B AlmostEmpty Flag O (Port B) Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1. AFA Port A AlmostFull Flag O (Port A) Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1. AFB Port B AlmostFull Flag O (Port B) Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2. B0 - B35 Port B Data I/O CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the LOWto-HIGH transition of CLKB. CSA Port A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. FS1, FS0 Flag Offset Selects I The LOW-to-HIGH transition of a FlFO’s Reset input latches the values of FS0 and FS1. If either FS0 or FS1 is HIGH when a Reset goes HIGH, one of three preset values is selected as the offset for the FlFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the Almost-Empty and Almost-Full offsets for both FlFOs. IRA Input Ready Flag O (Port A) IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is LOW, FIFO1 is full and writes to its array are disabled. IRA is set LOW when FIFO1 is reset and is set HIGH on the second LOW-to-HIGH transition of CLKA after reset. IRB Input Ready Flag O (Port B) IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is LOW, FIFO2 is full and writes to its array are disabled. IRB is set LOW when FIFO2 is reset and is set HIGH on the second LOW-to-HIGH transition of CLKB after reset. MBA Port A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2 output register data for output. MBB Port B Mailbox Select I A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a LOW level selects FIFO1 output register data for output. MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1 is reset. MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOWto-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also set HIGH when FIFO2 is reset. I/0 Description 36-bit bidirectional data port for side A. 36-bit bidirectional data port for side B. 3 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O Description ORA Output Ready Flag O (Port A) ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is LOW, FIFO2 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is HIGH. ORA is forced LOW when FlFO2 is reset and goes HIGH on the third LOW-to-HIGH transition of CLKA after a word is loaded to empty memory. ORB Output Ready Flag O (Port B) ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB is LOW, FlFO1 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is HIGH. ORB is forced LOW when FIFO1 is reset and goes HIGH on the third LOW-toHIGH transition of CLKB after a word is loaded to empty memory. RST1 FIFO1 Reset I To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM. RST2 FIFO2 Reset I To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM. W/RA Port A Write/ Read Select I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH. W/RB Port B Write/ Read Select I A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is LOW. 4 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)(1) Symbol Rating Commercial Unit –0.5 to 7 V V VCC Supply Voltage Range VI Input Voltage Range –0.5 to VCC+0.5 Output Voltage Range (2) VO –0.5 to VCC+0.5 V IIK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA IOK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA IOUT Continuous Output Current (VO = 0 to VCC) ±50 mA ICC Continuous Current Through VCC or GND ±400 mA TSTG Storage Temperature Range –65 to 150 °C (2) NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage (Commercial) 4.5 5.0 5.5 V VIH High-Level Input Voltage (Commercial) 2 — — V VIL Low-Level Input Voltage (Commercial) — — 0.8 V IOH High-Level Output Current (Commercial) — — –4 mA IOL Low-Level Output Current (Commercial) — — 8 mA TA Operating Temperature (Commercial) 0 — 70 °C ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREEAIR TEMPERATURE RANGE (Unless otherwise noted) Symbol Parameter Test Conditions IDT723622 IDT723632 IDT723642 Commercial tCLK = 15 ns Max. Min. Typ.(1) Unit VOH Output Logic "1" Voltage VCC = 4.5V, IOH = –4 mA 2.4 — — V VOL Output Logic "0" Voltage VCC = 4.5V, IOL = 8 mA — — 0.5 V ILI Input Leakage Current (Any Input) VCC = 5.5V, VI = VCC or 0 — — ±10 μA ILO Output Leakage Current VCC = 5.5V, VO = VCC or 0 — — ±10 μA ICC2(2) Standby Current (with CLKA & CLKB running) VCC = 5.5V, VI = VCC –0.2V or 0V — — 8 mA ICC3(2) Standby Current (no clocks running) VCC = 5.5V, VI = VCC –0.2V or 0V — — 1 mA CIN Input Capacitance VI = 0, f = 1 MHz — 4 — pF Output Capacitance VO = 0, f = 1 MHZ — 8 — pF (3) COUT (3) NOTES: 1. All typical values are at VCC = 5V, TA = 25°C. 2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS). 3. Characterized values, not currently tested. 5 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723622/723632/723642 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by: PT = VCC x [ICC(f) + (N x ΔICC x dc)] + Σ(CL x VCC2 X fo) where: N ΔI CC dc CL fo = = = = = number of outputs = 36 increase in power supply current for each input at a TTL HIGH level duty cycle of inputs at a TTL HIGH level of 3.4 V output capacitance load switching frequency of an output 300 fdata = 1/2 fS TA = 25°C CL = 0pF 250 VCC = 5.5V mA 150 ICC(f) 200 Supply Current VCC = 5.0V VCC = 4.5V 100 50 0 0 10 20 30 40 50 60 70 fS ⎯ Clock Frequency ⎯ MHz Figure 1. Typical Characteristics: Supply Current (ICC) vs Clock Frequency (fS) 6 80 3022 drw 03a 90 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C) Symbol fS tCLK tCLKH tCLKL tDS tENS1 tENS2 tRSTS tFSS tDH tENH tRSTH tFSH tSKEW1(2) tSKEW2(2,3) Parameter Clock Frequency, CLKA or CLKB Clock Cycle Time, CLKA or CLKB Pulse Duration, CLKA or CLKB HIGH Pulse Duration, CLKA and CLKB LOW Commercial IDT723622L15 IDT723632L15 IDT723642L15 Min. Max. — 66.7 15 — 6 — 6 — Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑ Setup Time, ENA and MBA, before CLKA↑; ENB and MBB before CLKB↑ Setup Time, RST1 or RST2 LOW before CLKA or CLKB (2) 4 4.5 4.5 5 — — — — ns ns ns ns Setup Time, FS0 and FS1 before RST1 and RST2 HIGH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑ Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑(2) Hold Time, FS0 and FS1 after RST1 and RST2 HIGH Skew Time, between CLKA↑ and CLKB↑ for ORA, ORB, IRA, and IRB Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 7.5 1 1 — — — ns ns ns 4 2 7.5 12 — — — — ns ns ns ns NOTES: 1. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 3. Design simulated, not tested. 7 Unit MHz ns ns ns IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 PF (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C) Commercial IDT723622L15 IDT723632L15 IDT723642L15 Min. Max. 2 10 Symbol Parameter tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 Unit ns tPIR Propagation Delay Time, CLKA↑ to IRA and CLKB↑ to IRB 2 8 ns tPOR Propagation Delay Time, CLKA↑ to ORA and CLKB↑ to ORB 1 8 ns tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 1 8 ns tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB 1 8 ns tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH 0 8 ns tPMR Propagation Delay Time, CLKA↑ to B0-B35(1) and CLKB↑ to A0-A35(2) 2 10 ns tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid 2 10 ns tRSF Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH 1 15 ns tEN Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB HIGH to B0-B35 Active 2 10 ns tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or W/RB LOW to B0-B35 at high-impedance 1 8 ns NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. 8 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE SIGNAL DESCRIPTION — PARALLEL LOAD FROM PORT A To program the X1, X2, Y1, and Y2 registers from port A, both FlFOs should be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH transition of the Reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in the FIFO memory but load the offset registers in the order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723622, IDT723632, or IDT723642, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers ranges from 1 to 252 for the IDT723622; 1 to 508 for the IDT723632; and 1 to 1,020 for the IDT723642. After all the offset registers are programmed from port A, the port B Input Ready flag (IRB) is set HIGH, and both FIFOs begin normal operation. See Figure 3 for relevant offset register parallel programming timing diagram. RESET After power up, a Master Reset operation must be performed by providing a LOW pulse to RST1 and RST2 simultaneously. Afterwards, the FIFO memories of the IDT723622/723632/723642 are reset separately by taking their Reset (RST1, RST2) inputs LOW for at least four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output Ready flag (ORA, ORB) LOW, the AlmostEmpty flag (AEA, AEB) LOW, and the Almost-Full flag (AFA, AFB) HIGH. Resetting a FIFO also forces the Mailbox Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a FlFO is reset, its Input Ready flag is set HIGH after two clock cycles to begin normal operation. A LOW-to-HIGH transition on a FlFO Reset (RST1, RST2) input latches the value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and Almost-Empty offset programming method (for details see Table 1, Flag Programming and the Almost-Empty Flag and Almost-Full Flag Offset Programming section that follows). The relevant FIFO Reset timing diagram can be found in Figure 2. FIFO WRITE/READ OPERATION The state of the port A data (A0-A35) outputs is controlled by port A Chip Select (CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is LOW, and IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and ORA is HIGH (see Table 2). FIFO reads and writes on port A are independent of any concurrent port B operation. Write and Read cycle timing diagrams for port A can be found in Figure 4 and 7. The port B control signals are identical to those of port A with the exception that the port B Write/Read select (W/RB) is the inverse of the port A Write/Read select (W/RA). The state of the port B data (B0-B35) outputs is controlled by the port B Chip Select (CSB) and port B Write/Read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOWto-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and ORB is HIGH (see Table 3) . FIFO reads and writes on port B are independent of any concurrent port A operation. Write and Read cycle ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAMMING Four registers in these devices are used to hold the offset values for the Almost-Empty and Almost-Full flags. The port B Almost-Empty flag (AEB) Offset register is labeled X1 and the port A Almost-Empty flag (AEA) Offset register is labeled X2. The port A Almost-Full flag (AFA) Offset register is labeled Y1 and the port B Almost-Full flag (AFB) Offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1). — PRESET VALUES To load the FIFO's Almost-Empty flag and Almost-Full flag Offset registers with one of the three preset values listed in Table 1, at least one of the flag select inputs must be HIGH during the LOW-to-HIGH transition of its Reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be HIGH when FlFO1 Reset (RST1) returns HIGH. Flag offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 Reset (RST2) toggled simultaneously with FIFO1 Reset (RST1). For preset value loading timing diagram, see Figure 2. TABLE 1 — FLAG PROGRAMMING FS1 FS0 RST1 RST2 X1 AND Y1 REGlSTERS(1) X2 AND Y2 REGlSTERS(2) H H ↑ X 64 X H H X ↑ X 64 H L ↑ X 16 X H L X ↑ X 16 L H ↑ X 8 X L H X ↑ X 8 L L ↑ ↑ Programmed from port A Programmed from port A NOTES: 1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB. 9 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE timing diagrams for port B can be found in Figure 5 and 6. The setup and hold time constraints to the port Clocks for the port Chip Selects and Write/Read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and Write/Read select may change states during the setup and hold time window of the cycle. When a FIFO Output Ready flag is LOW, the next word written is automatically sent to the FIFO output register automatically by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH. When the Output Ready flag is HIGH, subsequent data is clocked to the output registers only when a FIFO read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. OUTPUT READY FLAGS (ORA, ORB) The Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the Output Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is empty, empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FlFO output register and three cycles of the port Clock that reads data from the FIFO have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. A LOW-to-HIGH transition on an Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 8 and 9 for ORA and ORB timing diagrams). INPUT READY FLAGS (IRA, IRB) The Input Ready flag of a FlFO is synchronized to the port clock that writes data to its array. When the Input Ready flag is HIGH, a memory location is free in the FIFO to receive new data. No memory locations are free when the Input Ready flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an Input Ready flag monitors a write pointer and read TABLE 2 — PORT A ENABLE FUNCTION TABLE CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O PORT FUNCTION H X X X X High-Impedance None L H L X X Input None L H H L ↑ Input FIFO1 write L H H H ↑ Input Mail1 write L L L L X Output None L L H L ↑ Output FIFO2 read L L L H X Output None L L H H ↑ Output Mail2 read (set MBF2 HIGH) TABLE 3 — PORT B ENABLE FUNCTION TABLE CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O PORT FUNCTION H X X X X High-Impedance None L L L X X Input None L L H L ↑ Input FIFO2 write L L H H ↑ Input Mail2 write L H L L X Output None L H H L ↑ Output FIFO1 read L H L H X Output None L H H H ↑ Output Mail1 read (set MBF1 HIGH) 10 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE pointer comparator that indicates when the FlFO memory status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of two cycles of the Input Ready flag synchronizing clock. Therefore, an Input Ready flag is LOW if less than two cycles of the Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Input Ready flag synchronizing Clock after the read sets the Input Ready flag HIGH. A LOW-to-HIGH transition on an Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 10 and 11 for timing diagrams). a write pointer and read pointer comparator that indicates when the FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset or programmed from port A (see Almost-Empty flag and Almost-Full flag offset programming section). An Almost-Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock are required after a FIFO write for its Almost-Empty flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. ALMOST-EMPTY FLAGS (AEA, AEB) The Almost-Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost-Empty flag monitors TABLE 4 — FIFO1 FLAG OPERATION IDT723622(3) 0 Number of Words in FIFO(1,2) IDT723632(3) 0 IDT723642(3) 0 Synchronized to CLKB ORB AEB L L Synchronized to CLKA AFA IRA H H 1 to X1 1 to X1 1 to X1 H L H H (X1+1) to [256-(Y1+1)] (X1+1) to [512-(Y1+1)] (X1+1) to [1,024-(Y1+1)] H H H H (256-Y1) to 255 (512-Y1) to 511 (1,024-Y1) to 1,023 H H L H 256 512 1,024 H H L L NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from port A. TABLE 5 — FIFO2 FLAG OPERATION IDT723622(3) Number of Words in FIFO(1,2) IDT723632(3) IDT723642(3) Synchronized to CLKA ORA AEA Synchronized to CLKB AFB IRB 0 0 0 L L H H 1 to X2 1 to X2 1 to X2 H L H H (X2+1) to [256-(Y2+1)] (X2+1) to [512-(Y2+1)] (X2+1) to [1,024-(Y2+1)] H H H H (256-Y2) to 255 (512-Y2) to 511 (1,024-Y2) to 1,023 H H L H 256 512 1,024 H H L L NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from port A. 11 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. (See Figures 12 and 13). ALMOST-FULL FLAGS (AFA, AFB) The Almost-Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost-Full flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FlFO reset or programmed from port A (see Almost-Empty flag and Almost-Full flag offset programming section). An Almost-Full flag is LOW when the number of words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y) for the IDT723622, IDT723632, or IDT723642 respectively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723622, IDT723632, or IDT723642 respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for its Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [256/ COMMERCIAL TEMPERATURE RANGE 512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOWto-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [256/512/1,024(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle (see Figures 14 and 15). MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The Mailbox select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port A Write is selected by CSA, W/RA, and ENA and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port B Write is selected by CSB, W/ RB, and ENB and with MBB HIGH. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port Mailbox select input is LOW and from the mail register when the port-mailbox select input is HIGH. The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port B Read is selected by CSB, W/RB, and ENB and with MBB HIGH. The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port A read is selected by CSA, W/RA, and ENA and with MBA HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register. For mail register and Mail Register flag timing diagrams, see Figure 16 and 17. 12 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKA tRSTH CLKB tRSTS tFSS tFSH RST1 FS1,FS0 0,1 tPIR tPIR IRA tPOR ORB tRSF AEB tRSF AFA tRSF MBF1 3022 drw 04 NOTE: 1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value. Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1) CLKA 1 4 RST1, RST2 FS1,FS0 2 tFSS tFSH 0,0 tPIR IRA tENS2 (1) tENH tSKEW1 ENA tDS tDH A0 - A35 AFA Offset (Y1) AEB Offset (X1) CLKB AFB Offset (Y2) AEA Offset (X2) First Word to FIFO1 1 2 tPIR IRB 3022 drw 05 NOTES: 1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown. 2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles. Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset 13 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKA IRA HIGH tENS1 CSA tENH tENS1 tENH tENS2 tENH tENS2 tENH W/RA MBA tENS2 tENH tENS2 tENH ENA tDH tDS W1(1) A0 - A35 W2(1) No Operation 3022 drw 06 NOTE: 1. Written to FIFO1. Figure 4. Port A Write Cycle Timing for FIFO1 tCLK tCLKH tCLKL CLKB IRB HIGH tENS1 tENH tENS1 tENH tENS2 tENH tENS2 tENH CSB W/RB MBB tENS2 tENH tENS2 tENH ENB B0 - B35 tDS W1(1) tDH W2(1) No Operation 3022 drw 07 NOTE: 1. Written to FIFO2. Figure 5. Port B Write Cycle Timing for FIFO2 14 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB ORB HIGH CSB W/RB tENS2 MBB tENH tENS2 tENH tENS2 tENH ENB No Operation tMDV tEN B0 - B35 tA tDIS tA W1(1) W2(1) W3 (1) 3022 drw 08 NOTE: 1. Read From FIFO1. Figure 6. Port B Read Cycle Timing for FIFO1 tCLK tCLKH tCLKL CLKA ORA CSA W/RA tENS2 MBA tENH tENH tENH tENS2 tENS2 ENA tDMV tEN A0 - A35 No Operation tA tA W1(1) W2(1) tDIS W3(1) 3022 drw 09 NOTE: 1. Read From FIFO2. Figure 7. Port A Read Cycle Timing for FIFO2 15 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKA CSA LOW WRA HIGH tENS2 tENH tENS2 tENH MBA ENA IRA HIGH tDH tDS A0 - A35 W1 (1) tSKEW1 CLKB tCLKH 1 tCLK tCLKL 2 3 tPOR ORB FIFO1 Empty CSB LOW W/RB HIGH MBB LOW tPOR tENS2 tENH ENB tA B0 - B35 W1 Old Data in FIFO1 Output Register 4660 drw 10 NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB cycle later than shown. Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty 16 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB CSB LOW W/RB LOW tENS2 tENH tENS2 tENH MBB ENB IRB HIGH tDS B0 - B35 tDH W1 (1) tSKEW1 CLKA tCLKH 1 tCLK tCLKL 2 3 tPOR tPOR ORA FIFO2 Empty CSA LOW W/RA LOW MBA LOW tENS2 tENH ENA tA A0-A35 Old Data in FIFO2 Output Register W1 3022 drw 11 NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA cycle later than shown. Figure 9. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty 17 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB CSB LOW W/RB MBB HIGH LOW tENS2 tENH ENB ORB B0 -B35 HIGH tA Previous Word in FIFO1 Output Register tSKEW1(1) CLKA Next Word From FIFO1 tCLKH 1 tCLK tCLKL 2 tPIR tPIR IRA FIFO1 Full CSA LOW W/RA HIGH tENS2 tENH tENS2 tENH MBA ENA tDS tDH Write A0-A35 To FIFO1 3022 drw 12 NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown. Figure 10. IRA Flag Timing and First Available Write when FIFO1 is Full 18 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 tCLKH tCLK COMMERCIAL TEMPERATURE RANGE tCLKL CLKA CSA LOW W/RA LOW MBA LOW tENS2 tENH ENA ORA A0 -A35 HIGH tA Previous Word in FIFO2 Output Register tSKEW1 Next Word From FIFO2 (1) tCLKH 1 CLKB tCLK tCLKL 2 tPIR tPIR IRB FIFO2 FULL CSB LOW W/RB LOW tENS2 tENH tENS2 tENH tDS tDH MBB ENB B0 - B35 Wriite To FIFO2 3022 drw 13 NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown. Figure 11. IRB Flag Timing and First Available Write when FIFO2 is Full CLKA tENS2 tENH ENA tSKEW2 (1) 1 CLKB 2 tPAE tPAE AEB (X1+1) Words in FIFO1 X1 Words in FIFO1 tENS2 tENH ENB 3022 drw 14 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. Figure 12. Timing for AEB when FIFO1 is Almost-Empty 19 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB tEN2S tENH ENB tSKEW2 (1) 1 CLKA 2 tPAE tPAE AEA X2 Words in FIFO2 (X2+1) Words in FIFO2 tENS2 tENH ENA 3022 drw 15 NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. Figure 13. Timing for AEA when FIFO2 is Almost-Empty tSKEW2 (1) 1 CLKA tENS2 2 tENH ENA tPAF tPAF AFA (D-Y1) Words in FIFO1 [D-(Y1+1)] Words in FIFO1 CLKB tENH tENS2 ENB 3022 drw 16 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642. Figure 14. Timing for AFA when FIFO1 is Almost-Full 20 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tSKEW2 (1) 1 CLKB tENS2 2 tENH ENB tPAF AFB tPAF (D-Y2) Words in FIFO2 [D-(Y2+1)] Words in FIFO2 CLKA tENH tENS2 ENA 3022 drw 17 NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown. 2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. 3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642. Figure 15. Timing for AFB when FIFO2 is Almost-Full CLKA tENS1 tENH tENS1 tENH tENS2 tENH tENS2 tENH CSA W/RA MBA ENA tDS W1 A0 - A35 tDH CLKB tPMF tPMF MBF1 CSB W/RB MBB tENS2 tENH ENB tEN B0 - B35 tMDV tPMR tDIS W1 (Remains valid in Mail1 Register after read) FIFO1 Output Register 3022 drw 18 Figure 16. Timing for Mail1 Register and MBF1 Flag 21 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB tENS1 tENH tENS1 tENH tENS2 tENH tENS2 tENH CSB W/RB MBB ENB tDS W1 B0-B35 tDH CLKA tPMF tPMF MBF2 CSA W/RA MBA tENS2 tENH ENA tEN tPMR tDIS tMDV W1 (Remains valid in Mail 2 Register after read) A0-A35 FIFO2 Output Register 3022 drw19 Figure 17. Timing for Mail2 Register and MBF2 Flag 22 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION 5V 1.1 k Ω From Output Under Test 30 pF 680 Ω (1) PROPAGATION DELAY LOAD CIRCUIT 3V Timing Input 1.5 V GND tS 3V High-Level Input 1.5 V GND th tW 3V Data, Enable Input 3V 1.5 V 1.5 V 1.5 V Low-Level Input GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V GND VOLTAGE WAVEFORMS PULSE DURATIONS 3V Output Enable 1.5 V tPLZ 1.5 V tPZL GND ≈3 V Input 1.5 V Low-Level Output VOL tPZH VOH High-Level tPHZ Output 1.5 V 3V 1.5 V 1.5 V tPD tPD GND VOH In-Phase Output 1.5 V 1.5 V ≈ OV VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTE: 1. Includes probe and jig capacitance. Figure 18. Load Circuit and Voltage Waveforms 23 VOL 3022 drw 20 ORDERING INFORMATION XXXXXX Device Type X Power XX Speed X X Package X Process/ Temperature Range X BLANK 8 Tube or Tray Tape and Reel BLANK Commercial (0°C to +70°C) G Green PF Thin Quad Flat Pack (TQFP, PNG120) 15 Commercial Only L Low Power 723622 723632 723642 256 x 36 x 2 - SyncBiFIFO™ 512 x 36 x 2 - SyncBiFIFO™ 1,024 x 36 x 2 - SyncBiFIFO™ Clock Cycle Time (tCLK) Speed in Nanoseconds 3022 drw 21 DATASHEET DOCUMENT HISTORY 10/04/2000 03/21/2001 08/01/2001 12/18/2001 02/05/2009 02/19/2015 pgs. pgs. pgs. pg. pgs. pgs. 1 through 25, except pages 35. 6 and 7. 1, 6, 8, 9 and 25. 23. 1 and 25. 1, 2, 5, 7, 8, 9 and 24. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 24 for Tech Support: 408-360-1753 email: [email protected]