DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 Quad, Current Output, Serial Input 14-Bit Multiplying Digital-to-Analog Converter FEATURES DESCRIPTION • • • The DAC8803 is a quad, 14-bit, current-output digital-to-analog converter (DAC) designed to operate from a single 2.7 V to 5-V supply. • • • • • • • • The applied external reference input voltage VREF determines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I-to-V precision amplifier. A doubled buffered serial data interface offers high-speed, 3-wire, SPI and microcontroller compatible inputs using serial data in (SDI), clock (CLK), and a chip select (CS). In addition, a serial data out pin (SDO) allows for daisy chaining when multiple packages are used. A common level-sensitive load DAC strobe (LDAC) input allows simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power on reset forces the output voltage to zero at system turn on. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or to half-scale code when MSB = 1. APPLICATIONS • • • Automatic Test Equipment Instrumentation Digitally Controlled Calibration The DAC8803 is packaged in a SSOP package. VREFA B C D D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 SDO SDI RFBA Input Register R DAC A Register R DAC A IOUTA AGNDA RFBB 16 Input Register R DAC B Register R DAC B IOUTC AGNDB RFBC Input Register R DAC C Register R DAC C IOUTC AGNDC CS CLK RFBD EN DAC A B C D 2:4 Decode DGND Input Register R DAC D Register R DAC D IOUTD AGNDD Power-on Reset RS MSB AGNDF LDAC VSS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2005, Texas Instruments Incorporated PRODUCT PREVIEW • • • Relative Accuracy: 1 LSB Max Differential Nonlinearity: 1 LSB Max 2-mA Full-Scale Current ±20%, With VREF = ±10 V 0.5-µs Settling Time Midscale or Zero-Scale Reset Four Separate 4-Quadrant Multiplying Reference Inputs Reference Bandwidth: 10 MHz Reference Dynamics: -105 dB THD 50-MHz SPI™-Compatible 3-Wire Interface Double Buffered Registers Enable Simultaneous Multichannel Update Internal Power On Reset Compact SSOP-28 Package Industry-Standard Pin Configuration DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM RELATIVE ACCURACY (LSB) DIFFERENTIAL NONLINEARITY (LSB) SPECIFIED TEMPERATURE RANGE PACKAGELEAD PACKAGE DESIGNATOR DAC8803 ±1 ±1 -40°C to +85°C SSOP-28 DB (1) ORDERING NUMBER TRANSPORT MEDIA QUANTITY DAC8803IDBT Tape and Reel, 250 DAC8803IDBR Tape and Reel, 2500 For the most current specifications and package information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com ABSOLUTE MAXIMUM RATINGS (1) PRODUCT PREVIEW DAC8803 UNIT -0.3 to +8 V VSS to GND -0.3 to -7 V VREF to GND -18 to +18 V Logic inputs and output to GND -0.3 to +8 V V(IOUT) to GND -0.3 to VDD + 0.3 V AGNDX to DGND -0.3 to +0.3 V ±50 mA VDD to GND Input current to any pin except supplies Package power dissipation Thermal resistance, θJA (TJmax - TA)/θJA 28-Lead shrink surface-mount (RS-28) 100 °C/W Maximum junction temperature (TJmax) 150 °C Operating temperature range, Model A -40 to +85 °C Storage temperature range -65 to +150 °C Lead temperature RS-28 (Vapor phase 60s) 215 °C Lead temperature RS-28 (Infrared 15s) 220 °C (1) 2 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (1) VDD = 5 V ± 10%; VSS = 0 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless otherwise noted. DAC8803 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE (2) Resolution Relative accuracy Differential nonlinearity DNL Output leakage current IOUTX Data = 0000h, TA = 25°C IOUTX Data = 0000h, TA = TA max Full-scale gain error GFSE Data = FFFFh Full-scale tempco (3) TCVFS Feedback resistor RFBX ±0.75 14 Bits ±1 LSB ±1 LSB 10 nA 20 nA ±3 mV 1 ppm/°C VDD = 5 V kΩ VREFX Range VREFX -15 Input resistance RREFX 4 Input resistance match RREFX Input capacitance (3) CREFX Channel-to-channel 6 15 V 8 kΩ 1 % 5 pF PRODUCT PREVIEW REFERENCE INPUT ANALOG OUTPUT Output current Output capacitance (3) IOUTX Data = FFFFh COUTX Code-dependent 1.25 2.5 80 mA pF LOGIC INPUTS AND OUTPUT Input low voltage Input high voltage VIL VDD = +2.7 V 0.6 V VIL VDD = +5 V 0.8 V VIH VDD = +2.7 V 2.1 V VIH VDD = +5 V 2.4 V Input leakage current IIL 1 µA Input capacitance (3) CIL 10 pF 0.4 V Logic output low voltage Logic output high voltage INTERFACE TIMING (3), VOL IOL = 1.6 mA VOH IOH = 100 µA 4 V tCH 25 ns (4) Clock width high Clock width low tCL 25 ns CS to Clock setup tCSS 0 ns Clock to CS hold tCSH 25 tPD 2 Clock to SDO prop delay Load DAC pulsewidth ns 20 ns tLDAC 25 ns Data setup tDS 20 ns Data hold tDH 20 ns Load setup tLDS 5 ns Load hold tLDH 25 ns SUPPLY CHARACTERISTICS Power supply range Positive supply current (1) (2) (3) (4) VDD 2.7 RANGE IDD Logic inputs = 0 V 2 5.5 V 5 µA Specifications subject to change without notice. All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter amplifier. The DAC8803 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C. These parameters are specified by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 3 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (continued) VDD = 5 V ± 10%; VSS = 0 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless otherwise noted. DAC8803 PARAMETER Negative supply current Power dissipation Power supply sensitivity AC SYMBOL TYP MAX IDD VDD = +4.5 V to +5.5 V CONDITIONS 2 5 µA IDD VDD = +2.7 V to +3.6 V 1 2.5 µA ISS Logic inputs = 0 V, VSS = -5 V PDISS PSS MIN 0.001 UNIT 1 µA Logic inputs = 0 V 0.025 mW ∆VDD = ±5% 0.006 % CHARACTERISTICS (5) Output voltage settling time Reference multiplying BW ts To ±0.1% of full-scale, Data = 0000h to FFFFh to 0000h 0.5 ts To ±0.006% of full-scale, Data = 0000h to FFFFh to 0000h 1 µs 10 MHz Q VREFX = 10 V, Data = 0000h to 8000h to 0000h 1 nV/s Feedthrough error VOUTX/VREFX Data = 0000h, VREFX = 100 mVRMS, f = 100 kHz -70 Crosstalk error VOUTA/VREFB Data = 0000h, VREFB = 100 mVRMS, Adjacent channel, f = 100 kHz -90 DAC glitch impulse PRODUCT PREVIEW Digital feedthrough Total harmonic distortion Output spot noise voltage (5) 4 BW -3 dB VREFX = 100 mVRMS, Data = FFFFH, CFB = 15 pF µs Q THD en CS = 1 and fCLK = 1 MHz VREF = 5 VPP, Data = FFFFh, f = 1 kHz 2 -105 f = 1 kHz, BW = 1 Hz All ac characteristic tests are performed in a closed-loop system using an OPA627 I-to-V converter amplifier. 12 dB dB nV/s dB nV/√Hz DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 PIN CONFIGURATIONS DAC8803 (TOP VIEW) AGNDA IOUTA VREFA RFBA MSB RS VDD CS CLK SDI RFBB VREFB IOUTB AGNDB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AGNDD IOUTD VREFD RFBD DGND VSS AGNDF LDAC SDO NC RFBC VREFC IOUTC AGNDC PIN DESCRIPTION PIN NAME 1, 14, 15, 28 AGNDA, AGNDB, AGNDC, AGNDD DAC A, B, C, D Analog ground DESCRIPTION 2, 13, 16, 27 IOUTA, IOUTB, IOUTC, IOUTD DAC A, B, C, D Current output 3, 12, 17, 26 VREFA, VREFB, VREFC, VREFD DAC A, B, C, D Reference voltage input terminal. Establishes DAC A, B, C, D full-scale output voltage. Can be tied to VDD. 4, 11, 18, 25 RFBA, RFBB, RFBC, RFBD, Establish voltage output for DAC A, B, C, D by connecting to external amplifier output. 5 MSB 6 RS Reset pin, active low. Input register and DAC registers are set to all zeros or half scale code (8000h) determined by the voltage on the MSB pin. Register data = 8000h when MSB = 1. 7 VDD Positive power-supply input. Specified range of operation 5 V ±10%. 8 CS Chip-select; active low input. Disables shift register loading when high. Transfers shift register data to input register when CS/LDAC goes high. Does not affect LDAC operation. MSB Bit set during a reset pulse (RS) or at system power on if tied to ground or VDD 9 CLK Clock input; positive edge triggered clocks data into shift register 10 SDI Serial data input; data loads directly into the shift register. 19 NC Not connected; leave floating 20 SDO Serial data output; input data load directly into shift register. Data appears at SDO, 19 clock pulses after input at the SDI pin. 21 LDAC Load DAC register strobe; level sensitive active low. Tranfers all input register data to the DAC registers. Asynchronous active low input. See Table 1 for operation. 22 AGNDF High current analog force ground. 23 VSS 24 DGND Negative bias power-supply input. Specified range of operation -0.3 V to -5.5 V. Digital ground. 5 PRODUCT PREVIEW NC − No internal connection DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel A LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Graphic Forthcoming PRODUCT PREVIEW Figure 1. Figure 2. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 3. 6 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 4. DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Graphic Forthcoming Figure 5. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 6. PRODUCT PREVIEW LINEARITY ERROR vs DIGITAL INPUT CODE 7 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel B LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Graphic Forthcoming PRODUCT PREVIEW Figure 7. Figure 8. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 9. 8 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 10. DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Graphic Forthcoming Figure 11. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 12. PRODUCT PREVIEW LINEARITY ERROR vs DIGITAL INPUT CODE 9 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel C LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Graphic Forthcoming PRODUCT PREVIEW Figure 13. Figure 14. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 15. 10 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 16. DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Graphic Forthcoming Figure 17. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 18. PRODUCT PREVIEW LINEARITY ERROR vs DIGITAL INPUT CODE 11 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel D LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Graphic Forthcoming PRODUCT PREVIEW Figure 19. Figure 20. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 21. 12 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 22. DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Graphic Forthcoming Figure 23. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 24. PRODUCT PREVIEW LINEARITY ERROR vs DIGITAL INPUT CODE 13 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE REFERENCE MULTIPLYING BANDWIDTH 6 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 −60 −66 −72 −78 −84 −90 −96 −102 −108 −114 1.6 VDD = +5.0V 1.2 Attenuation (dB) Supply Current, IDD (mA) 1.4 1.0 0.8 0.6 0.4 0.2 VDD = +2.7V 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 1k 10k 100k 1M Figure 25. Figure 26. DAC GLITCH DAC SETTLING TIME Code: 7FFFh to 8000h Output Voltage (5V/div) PRODUCT PREVIEW Output Voltage (50mV/div) 100 10M Bandwidth (Hz) Logic Input Voltage (V) Voltage Output Settling Trigger Pulse Trigger Pulse Time (0.2µs/div) Time (0.1µs/div) Figure 27. Figure 28. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Channel A Graphic Forthcoming Figure 29. 14 Graphic Forthcoming Figure 30. 100M DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Graphic Forthcoming DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 31. Figure 32. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 33. PRODUCT PREVIEW LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 34. 15 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel B LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Graphic Forthcoming PRODUCT PREVIEW Figure 35. Figure 36. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 37. 16 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 38. DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Graphic Forthcoming Figure 39. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 40. PRODUCT PREVIEW LINEARITY ERROR vs DIGITAL INPUT CODE 17 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel C LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Graphic Forthcoming PRODUCT PREVIEW Figure 41. Figure 42. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 43. 18 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 44. DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Graphic Forthcoming Figure 45. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 46. PRODUCT PREVIEW LINEARITY ERROR vs DIGITAL INPUT CODE 19 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel D LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Graphic Forthcoming PRODUCT PREVIEW Figure 47. Figure 48. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 49. 20 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Figure 50. DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Graphic Forthcoming Graphic Forthcoming Figure 52. PRODUCT PREVIEW Figure 51. PARAMETER MEASUREMENT INFORMATION SDI A1 A0 D13 D13 D12 D11 D10 D8 D9 D7 D2 D1 CLK Input REG. LD tCSS CS D0 tds tdh tch tcsh tcl tlds LDAC tpd SDO tLDH tLDAC Figure 53. DAC8803 Timing Diagram CIRCUIT OPERATION The DAC8803 contains four 14-bit, current-output, digital-to-analog converters respectively. Each DAC has its own independent multiplying reference input. The DAC8803 uses a 3-wire SPI compatible serial data interface, with a configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an LDAC strobe enables four channel simultaneous updates for hardware synchronized output voltage changes. D/A Converter The DAC8803 contains four current-steering R-2R ladder DACs. Figure 54 shows a typical equivalent DAC. Each DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFBX pin is connected to the output of the external amplifier. The IOUTX terminal is connected to the inverting input of the external amplifier. The AGNDX pin should be Kelvin-connected to the load point in the circuit requiring the full 14-bit accuracy. 21 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 The DAC is designed to operate with both negative or positive reference voltages. The VDD power pin is only used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the internal 5 kΩ feedback resistor. If users are attempting to measure the value of RFB, power must be applied to VDD in order to achieve continuity. An additional VSS bias pin is used to guard the substrate during high temperature applications to minimize zero-scale leakage currents that double every 10°C. The DAC output voltage is determined by VREF and the digital data (D) according to Equation 1: V OUT VREF D 16384 (1) Note that the output polarity is opposite to the VREF polarity for dc reference voltages. VDD RRR VREFX RFBX 2R 2R 2R R 5 k S2 S1 IOUTX AGNDF AGNDX PRODUCT PREVIEW From Other DACS AGND VCC DGND Digital interface connections omitted for clarity. Switches S1 and S2 are closed, VDD must be powered. Figure 54. Typical Equivalent DAC Channel The DAC is also designed to accommodate ac reference input signals. The DAC8803 accommodates input reference voltages in the range of -12 V to +12 V. The reference voltage inputs exhibit a constant nominal input resistance of 5 kΩ, ± 20%. On the other hand, the DAC outputs IOUTA, B, C, D are code-dependent and produce various output resistances and capacitances. The choice of external amplifier should take into account the variation in impedance generatedby the DAC8803 on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance, dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor (CFB) may be needed to provide a critically damped output response for step changes in reference input voltages. Figure 5 and Figure 6 show the gain vs frequency performance at various attenuation settings using a 23 pF external feedback capacitor connected across the IOUTX and RFBX terminals. In order to maintain good analog performance, power supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under these conditions, clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not suitable for this application due to the higher ripple voltage and PSS frequency-dependent characteristics. It is best to derive the DAC8803 5-V supply from the system analog supply voltages. (Do not use the digital 5-V supply.) See Figure 55. 22 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 15 V 2R 5V + Analog Power Supply R VDD RRR RFBX VREFX 2R 2R 2R R 5 k 15 V S2 S1 IOUTX VCC AGNDF AGNDX From Other DACS AGND VSS Digital interface connections omitted for clarity. Switches S1 and S2 are closed, VDD must be powered. VOUT A1 + VEE Load DGND PRODUCT PREVIEW Figure 55. Recommended Kelvin-Sensed Hookup 23 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 VREF A B C D CS EN VDD CLK SDI SDO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 16 RFBA DAC A Register R Input Register R DAC A IOUTA AGNDA RFBB DAC B Register R Input Register R DAC B ADC A B C D 2:4 Decode IOUTC AGNDB RFBC DAC C Register R PRODUCT PREVIEW Input Register R DAC C IOUTC AGNDC RFBD DAC D Register R Input Register R DAC D IOUTD AGNDD Set MSB Set MSB Poweron Reset DGND AGNDF MSB LDAC RS VSS Figure 56. System Level Digital Interfacing SERIAL DATA INTERFACE The DAC8803 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. Serial data of the DAC8803 is clocked into the serial input register in an 14-bit data-word format. MSB bits are loaded first. Table 3 defines the 16 data-word bits for the DAC8803. Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data setup and data hold time requirements specified in the Interface Timing Specifications. Data can only be clocked in while the CS chip select pin is active low. For the DAC8803, only the last 16 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state. Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the DAC8803. Keeping the CS line low between the first, second, and third byte transfers results in a successful serial register update. Similarly, two right-justified data bytes can be written to the DAC8803. Keeping the CS line low between the first and second byte transfer will result in a successful serial register update. 24 DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new data to the target DAC register, determined by the decoding of address bits A1and A0. For DAC8803, Table 1, Table 3 and Figure 57 define the characteristics of the software serial interface. Figures 8 and 9 show the equivalent logic interface for the key digital control pins for DAC8803. To Input Register Address Decoder CS A B C D EN Shift Register CLK SDI 19th/17th CLOCK SDO Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1). POWER ON RESET When the VDD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the zero-code state or half-scale, depending on the MSB pin voltage. The VDD power supply should have a smooth positive ramp without drooping in order to have consistent results, especially in the region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect on the power-on reset performance. The DAC register data stays at zero or half-scale setting until a valid serial register data load takes place. ESD Protection Circuits All logic-input pins contain back-biased ESD protection Zener diodes connected to ground (DGND) and VDD as shown in Figure 58. VDD DIGITAL INPUTS 5 k DGND Figure 58. Equivalent ESD Protection Circuits 25 PRODUCT PREVIEW Figure 57. DAC8803 Equivalent Logic Interface DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 PCB LAYOUT In printed circuit board (PCB) layout, all analog ground, AGNDX, should be tied together. Amplifiers suitable for: Table 1. Control Logic Truth Table (1) CS CLK LDAC RS MSB H X H H X No effect Latched Latched L L H H X No effect Latched Latched L ↑+ H H X Shift register data advanced one bit Latched Latched L H H H X No effect Latched Latched ↑+ L H H X No effect Selected DAC updated with current SR contents Latched H X L H X No effect Latched Transparent H X H H X No effect Latched Latched H X ↑+ H X No effect Latched Latched H X H L 0 No effect Latched data = 0000h Latched data = 0000h X ↑+ H L H No effect Latched data = 8000h Latched data = 8000h (1) SERIAL SHIFT REGISTER INPUT REGISTER DAC REGISTER ↑+ Positive logic transition; X = Do not care Table 2. Serial Input Register Data Format, Data Loaded MSB First (1) PRODUCT PREVIEW Bit B17 (MSB) B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) Data A1 A0 X X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (1) Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line's positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8803 shift register are ignored, only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 3. Address Decode 26 A1 A0 DAC DECODE 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D DAC8803 www.ti.com SBAS340A – JANUARY 2005 – REVISED APRIL 2005 APPLICATION INFORMATION The DAC8803, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the full-scale output IOUT is the inverse of the input reference voltage at VREF. Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. An additional external op amp A2 is added as a summing amp. In this circuit the first and second amps (A1 and A2) provide a gain of 2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implemented by using a 10-V offset of the reference voltage to bias A2. According to the following circuit transfer equation ( Equation 2), input data (D) from code 0 to full scale produces output voltages of VOUT = -10 V to VOUT = 10 V. V OUT (D32, 768 1) VREF (2) 10 k 10 k 10 V 5 k A2 VREF VOUT −10 V < VOUT< +10 V VREFX VFBX One Channel DAC8803 VSS IOUTX A1 AGNDFA AGNDX Digital interface connections omitted for clarity. Figure 59. Four-Quadrant Multiplying Application Circuit Cross-Reference The DAC8803 has an industry-standard pinout. Table 4 provides the cross-reference information. Table 4. Cross-Reference PRODUCT INL (LSB) DNL (LSB) SPECIFIED TEMPERATURE RANGE DAC8803IDB ±1 ±1 -40°C to +85°C PACKAGE DESCRIPTION PACKAGE OPTION CROSSREFERENCE PART 28-Lead MicroSOIC SSOP-28 AD5554BRS 27 PRODUCT PREVIEW VDD PACKAGE OPTION ADDENDUM www.ti.com 13-Apr-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC8803IDBR PREVIEW SSOP DB 28 2500 TBD Call TI Call TI DAC8803IDBT PREVIEW SSOP DB 28 250 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. 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