HV219 Low Charge Injection 8-Channel High Voltage Analog Switch General Description Features ► ► ► ► ► ► ► ► ► ► ► HVCMOS® technology for high performance Very low quiescent power dissipation -10µA Output ON-resistance typically 11Ω Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Serial shift register logic control with latches Flexible operating supply voltages Surface mount packages Applications ► Medical ultrasound imaging ► Non-destructive evaluation The Supertex HV219 is a low switch resistance, low charge injection 8-channel 200V analog switch integrated circuit (IC) intended primarily for medical ultrasound imaging. The device can also be used for NDE, non-destructive evaluation applications. The HV219 is a lower switch resistance, 11Ω versus 22Ω, version of the Supertex HV20220 device. The lower switch resistance will help reduce insertion loss. It has the same pin configuration as that of the Supertex HV20220PJ and the HV20220FG. The device is manufactured using Supertex’s HVCMOS® (high voltage CMOS) technology with high voltage bilateral DMOS structures for the outputs and low voltage CMOS logic for the input control. The outputs are configured as eight independent single pole single throw 11Ω analog switches. The input logic is an 8-bit serial to parallel shift register followed by an 8-bit parallel latch. The switch states are determined by the data in the latch. Logic high will correspond to a closed switch and logic low as an opened switch. The HV219 is designed to operate on various combinations of high voltage supplies. For example the VPP and VNN supplies can be: +40V/-160V, +100V/-100V, or +160V/-40V. This allows the user to maximize the signal voltage for uni-polar negative, bi-polar, or unipolar positive. Block Diagram Level Output Latches Shifters Switches DIN D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 CLK 8-Bit Shift Register DOUT VDD GND LE CL VNN VPP HV219 Ordering Information Pin Configurations Package Options Device HV219 1 4 28-Lead PLCC 48-Lead LQFP (7x7x1.4mm) HV219PJ HV219FG HV219PJ-G HV219FG-G 25 -G indicates the part is RoHS compliant (Green) 28-Lead (J) PLCC (PJ) (top view) Absolute Maximum Ratings Parameter VDD logic power supply voltage Value -0.5V to +15V VPP - VNN supply voltage VPP positive high voltage supply VNN negative high voltage supply 220V -0.5V to VNN +200V +0.5V to -200V Logic input voltages -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel Storage temperature 48 1 48-Lead LQFP (FG) (7x7x1.4mm) 3.0A (top view) -65OC to +150OC Power dissipation: 28-Lead PLCC 48-Lead LQFP (7x7x1.4mm) Product Marking 1.2W 1.0W Top Marking Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Conditions Symbol Parameter YYWW HV219PJ LLLLLLLLLL Bottom Marking Value CCCCCCCCCCC AAA VDD Logic power supply voltage VPP Positive high voltage supply 40V to VNN +200V VNN Negative high voltage supply -40V to -160V VIH High level input logic voltage VDD -1.5V to VDD VIL Low-level input logic voltage 0V to 1.5V Bottom Marking VSIG Analog signal voltage peak-to-peak VNN +10V to VPP -10V CCCCCCCC AAA TA Operating free air temperature 4.5V to 13.2V YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging *May be part of top marking. 28-Lead PLCC (PJ) Top Marking YYWW HV219FG LLLLLLLLL 0OC to 70OC YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging *May be part of top marking 48-Lead LQFP (FG) 2 HV219 DC Electrical Characteristics (over recommended operating conditions unless otherwise noted) Sym Parameter 0OC +25OC +70OC Units Conditions Min Max Min Typ Max Min Max - 15 - 13 19 - 24 - 13 - 11 14 - 16 VPP = +40V VNN = ISIG = 200mA 160V - 13 - 11 14 - 15 ISIG = 5mA - 9 - 9 12 - 14 - 12 - 10 13 - 15 - 11 - 8 13 - 14 Small signal switch On-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5mA, VPP = +100V, VNN = -100V RONL Large signal switch On-resistance - - - 8 - - - Ω VSIG = VPP - 10V, ISIG = 1A ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 µA VSIG= VPP -10V & VNN +10V DC offset switch off - 300 - 100 300 - 300 mV RLOAD = 100KΩ DC offset switch on - 500 - 100 500 - 500 mV RLOAD = 100KΩ IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches on, ISW = 5mA INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches on, ISW = 5mA Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycle < 0.1% Output switch frequency - - - - 50 - - kHz - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 RONS ΔRONS fSW IPP INN Small signal switch On-resistance Average VPP supply current Average VNN supply current ISIG = 5mA Ω VPP = +100V ISIG = 200mA VNN = 100V VPP = +160V ISIG = 200mA V = -40V NN ISIG = 5mA Duty cycle = 50% VPP = +40V VNN = -160V mA mA VPP = +100V VNN = -100V All output VPP = +160V switches are turning VNN = -40V ON and VPP = +40V OFF at VNN = -160V 50kHz with VPP = +100V no load VNN = -100V VPP = +160V VNN = -40V IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA fCLK = 5MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 µA All logic inputs are static ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD - 0.7V ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V CIN Large input capacitance - 10 - - 10 - 10 pF --- 3 HV219 AC Electrical Characteristics (over recommended operating conditions, V DD Sym Parameter 0OC +25OC = 5.0V, unless otherwise noted) +70OC Min Max Min Typ Max Min Max Units Conditions tSD Set-up time before LE rises 150 - 150 - - 150 - ns --- tWLE Time width of LE 150 - 150 - - 150 - ns --- tDO Clock delay time to data out - 150 - - 150 - 150 ns --- twCL Time width of CL 150 - 150 - - 150 - ns --- tSU Set-up time data to clock 15 - 15 8.0 - 20 - ns --- tH Hold time data from clock 35 - 35 - - 35 - ns --50% duty cycle, fDATA = fCLK/2 fCLK Clock frequency - 5.0 - - 5.0 - 5.0 MHz tr, tf Clock rise and fall times - 50 - - 50 - 50 ns --- TON Turn-on time - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10KΩ TOFF Turn-off time - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10KΩ - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 -33 - - - -58 - -58 - - - - Switch crosstalk - - -60 - - - - dB F = 5MHz, 50Ω load Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2% duty cycle CSG(OFF) Off capacitance SW to GND 14 25 14 20 25 14 25 pF 0V, f = 1MHz CSG(ON) 40 60 40 50 60 40 60 pF 0V, f = 1MHz +VSPK - - - - 150 - - -VSPK - - - - 200 - - - - - - 150 - - - - - - 200 - - +VSPK - - - - 150 - - -VSPK - - - - 200 - - - - - 1450 - - - - - - 1050 - - - - - - 550 - - - dv/dt KO KCR IID +VSPK -VSPK Q Maximum VSIG slew rate Off isolation On capacitance SW to GND Output voltage spike Charge injection 4 VPP = +40V, VNN = -160V V/ns VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V dB F = 5MHz, 1KΩ//15pF load F = 5MHz, 50Ω load VPP = +40V, VNN = -160V, RLOAD = 50Ω mV VPP = +100V, VNN = -100V, RLOAD = 50Ω VPP = +160V, VNN = -40V, RLOAD = 50Ω VPP = +40V, VNN = -160V, VSIG = 0V pC VPP = +100V, VNN = -100V, VSIG = 0V VPP = +160V, VNN = -40V, VSIG = 0V HV219 Truth Table Data in 8-Bit Shift Register Output Switch State LE CL L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON D0 D1 D2 D3 D4 D5 D6 D7 SW0 SW1 SW2 SW4 SW5 SW6 SW7 L L L OFF H L L ON L L L OFF H L L ON X X X X X X X X H L X X X X X X X X X H Hold Previous State OFF OFF OFF Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition clock. 3. The switches go to a state retaining their present condition at the rising edge of the LE. 4. When LE is low, the shift register data flows through the latch. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The clear input overrides all other inputs. Logic Timing Waveforms D DN N+1 DATA IN 50% LE 50% DN-1 50% 50% t WLE t SD 50% CLOCK t SU 50% th t DO DATA OUT 50% t ON t OFF OFF V OUT (TYP) ON CLR SW3 90% 10% 50% 50% t WCL 5 OFF OFF OFF OFF OFF HV219 Test Circuits VPP -10V VPP -10V RL 10KΩ ISOL VOUT VOUT 100KΩ VNN +10V VPP VPP VDD VNN VNN GND 5V RL VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND TON /TOFF Test Circuit DC Offset ON/OFF Switch OFF Leakage 5V VIN = 10 VP-P @5MHz VIN = 10 VP-P @5MHz VSIG IID VOUT 50Ω NC VNN RL 50Ω VPP VPP VDD VNN VNN GND KO = 20Log 5V VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND VOUT VIN KCR = 20Log OFF Isolation Isolation Diode Current Crosstalk +VSPK VOUT VOUT VOUT -V SPK 1000pF 50Ω VSIG 1KΩ VPP VPP VDD VNN VNN GND 5V RL VPP VPP VDD VNN VNN GND Q = 1000pF x VOUT Charge Injection Output Voltage Spike 6 VOUT VIN 5V 5V HV219 Pin Description 28-Lead (J-Lead) PLCC (PJ) Pin Function Pin Function Pin Function Pin Function 1 SW3 8 SW0 15 NC 22 SW7 2 SW3 9 NC 16 DIN 23 SW6 3 SW2 10 VPP 17 CLK 24 SW6 4 SW2 11 NC 18 LE 25 SW5 5 SW1 12 VNN 19 CL 26 SW5 6 SW1 13 GND 20 DOUT 27 SW4 7 SW0 14 VDD 21 SW7 28 SW4 Function Pin Function Pin Function Pin Description 48-Lead LQFP (7x7x1.4mm) (FG) Pin Function Pin 1 SW5 13 NC 25 VNN 37 DOUT 2 NC 14 SW2 26 NC 38 NC 3 SW4 15 NC 27 NC 39 SW7 4 NC 16 SW1 28 GND 40 NC 5 SW4 17 NC 29 VDD 41 SW7 6 NC 18 SW1 30 NC 42 NC 7 NC 19 NC 31 NC 43 SW6 8 SW3 20 SW0 32 NC 44 NC 9 NC 21 NC 33 DIN 45 SW6 10 SW3 22 SW0 34 CLK 46 NC 11 NC 23 NC 35 LE 47 SW5 12 SW2 24 VPP 36 CLR 48 NC Power Up/Down Sequence 1) Power up/down sequence is arbitrary except GND must be powered up first and powered down last. This applies for applications powering GND of the IC with different voltages. 2) VSIG must always be at or in between VPP and VNN or floating during power up/down transition. 3) Rise and fall times of the power supplies VDD, VPP, and VNN should not be less than 1.0ms. 7 HV219 28-Lead PLCC Package Outline (PJ) D D1 1 .048/.042 x 45O 4 26 28 0.150 MAX .056/.042 x 45O Note 1 (Index Area) 0.075 MAX E1 E 0.20max 3 Places Top View View B A Base Plane A1 A2 .020 MIN e Seating Plane b Side View Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol Dimension (inches) A A1 A2 b D D1 E E1 MIN .165 .090 .062 .013 .485 .450 .485 .450 NOM .172 .105 - - .490 .453 .490 .453 MAX .180 .120 .083 .021 .495 .456 .495 .456 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. 8 e .050 BSC HV219 48-Lead LQFP (7x7x1.4mm) Package Outline (FG) D D1 E E1 Note 1 (Index Area D1/4 x E1/4) L2 Gauge Plane 48 L 1 Seating Plane θ L1 b e Top View View B View B A A2 Seating Plane A1 Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol Dimension (mm) A A1 A2 b D D1 E E1 MIN 1.40 0.05 1.35 0.17 8.80 6.80 8.80 6.80 NOM - - 1.40 0.22 9.00 7.00 9.00 7.00 MAX 1.60 0.15 1.45 0.27 9.20 7.20 9.20 7.20 e L L1 L2 0O 0.45 0.50 BSC 0.60 0.75 θ 1.00 REF 0.25 BSC 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV219 NR050807 9