Integrated Circuit Systems, Inc. ICS9169C-272 Frequency Generator for Pentium™ Based Systems General Description Features The ICS9169C-272 is a low-cost frequency generator designed specifically for Pentium based chip set systems. The integrated buffer minimizes skew and provides all the clocks required. A 14.318 MHz XTAL oscillator provides the reference clock to generate standard Pentium frequencies. The CPU clock makes gradual frequency transitions without violating the PLL timing of internal microprocessor clock multipliers. A raised frequency setting of 68.5MHz is available in the Turbo-mode of the 66.8MHz CPU. The ICS9169C-272 contains 12 CPU clocks, 4 PCI clocks, 1 REF at 48MHz and 1 at 24MHz. • • • • The twelve CPU clock outputs provide sufficient clocks for the CPU, chip set, memory and up to two DIMM connectors (with four clocks to each DIMM). Either synchronous(CPU/ 2) or asynchronous (32 MHz) PCI bus operation can be selected by latching data on the BSEL input • • • • • • Twelve selectable CPU clocks operate up to 83.3MHz Maximum CPU jitter of ± 200ps Six BUS clocks support sync or async bus operation 250ps skew window for CPU outputs, 500ps skew window for BUS outputs CPU clocks BUS clocks skew 1-4ns (CPU early) Integrated buffer outputs drive up to 30pF loads 3.0V - 3.7V supply range, CPU(1:6) outputs 2.5V(2.3752.62V) VDD option 32-pin SOIC/SOJ package Logic inputs latched at Power-On for frequency selection saving pins as Input/Output 48 MHz clock for USB support and 24 MHz clock for FD. Pin Configuration Block Diagram 32-Pin SOIC/SOJ Functionality 3.3V±10%, 0-70°C Crystal (X1, X2) = 14.31818 MHz A D D R E SS SELECT VDD Groups: VDD1 = X1, X2, REF/BSEL VDDC1 = CPU1-6 VDDC2 = CPU7-12 & PLL Core VDDB = BUS1-6 VDDF = 48/24 MHz Latched Inputs: L1 = BSEL L2 = FS0 L3 = FS1 L4 = FS2 9169C-272RevC060297P FS2 FS1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 FS0 0 1 0 1 0 1 0 1 C PU (1:12) (M H z) 50 60 66.8 75.9 55 75.9 83.3 68.5 BU S (1:6)M H z BSEL=1 25 30 33.4 32 27.5 37.5 41.7 34.25 BSEL=0 32 32 32 32 32 32 32 32 48M H z 24M H z R EF 48 48 48 48 48 48 48 48 24 24 24 24 24 24 24 24 REF REF REF REF REF REF REF REF Pentium is a trademark of Intel Corporation. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9169C-272 Pin Descriptions PIN NUM BER PIN NAM E TYPE DESCRIPTION Power for device logic and crystal oscillator circuit and 14.318 M Hz output. XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12-16M Hz crystal, nominally 14.31818M Hz external crystal load of 30pF to GND recommended for VDD power on faster than 2.0ms. XTAL output which includes XTAL load capacitance. External crystal load of 10pF to GND recommended for VDD power on faster than 2.0ms. Ground for device logic. 1 VDD 2 X1 IN 3 X2 OUT GND PW R CPU(1) OUT Processor clock output which is a multiple of the input reference frequency. IN Frequency multiplier select pins. 350K internal pull up. 4,11,20,26 PW R 5 FS0 6,7,9,10,15,16,17,18,19 8 CPU (2:5) (8:12) OUT VDDC1 PW R CPU(6) OUT Processor clock outputs which are a multiple of the input reference frequency. Power for CPU(1:6) output buffers only. Can be reduced VDD for 2.5V (2.375-2.62V) next generation processor clocks. Processor clock output which is a multiple of the input reference frequency internal pull up devices. 12 FS1 Frequency multiplier select pin. See shared pin description. 350K internal pull up. IN CPU(7) Processor clock output which is a multiple of the input reference frequency internal pull up devices. Frequency multiplier select pin. See shared pin description. 350K internal pull up. Power for CPU PLL, logic and CPU(7:12)output buffers. M ust be nominal 3.3V (3.0 to 3.7V). BUS clock outputs which are a multiple of the input reference clock. Power for BUS clock buffers BUS(1:6). Power for fixed clock buffer (48 M Hz, 24 M hz). Fixed 24M Hz clock (assuming a 14.31818M Hz REF frequency). Fixed 48M Hz clock (assuming a 14.31818M Hz REF frequency). Fixed 14.31818M Hz clock (assuming a 14.31818M Hz REF frequency). Selection for synchronous or asynchronous bus clock operation. See shared pin programming description late in this data sheet for further explanation. 350K internal pull up. OUT 13 FS2 14 IN VDDC2 PW R BUS (1:6) OUT 23 29 VDDB VDDF PW R PW R 30 24M Hz OUT 31 48M Hz OUT REF OUT 21,22,24,25,27,28 32 BSEL IN * The internal pull up will vary from 350K to 500K based on temperature 2 ICS9169C-272 Shared Pin Operation Input/Output Pins Test Mode Operation The ICS9169C-272 includes a production test verification mode of operation. This requires that the FS0 and FS1 pins be programmed to a logic high and the FS2 pin be programmed to a logic low(see Shared Pin Operation section). In this mode the device will output the following frequencies. Shared Pin Operation - Input/Output Pins 5, 12, 13 and 32 on the ICS9169C-272 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operation for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Pin REF 48MHz 24MHz CPU (1:12) BSEL=1 BUS (1:6) BSEL = 0 To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Frequency REF REF/2 REF/4 REF2 REF/4 REF/3 Note: REF is the frequency of either the crystal connected between the devices X1and X2 or, in the case of a device being driven by an external reference clock, the frequency of the reference (or test) clock on the device’s X1 pin. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device’s internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). (Resistors are surface mount devices shown schematically between 5.m. pads) *use only one programming resistor Fig. 1 3 ICS9169C-272 Fig. 2b Fig. 2a Fig. 3 4 ICS9169C-272 Technical Pin Function Descriptions VDD This is the power supply to the internal logic of the device as well as the following clock output buffers: systems plug-in card bus. The voltage swing of these clocks is control-led by the supply that is applied to the VDD pin of the device. See the Functionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. A. REF clock output buffers B. BUS clock output buffers C. Fixed clock output buffers FS0, FS1, FS2 These pins control the frequency of the clocks at the CPU, CPUL, BUS & SDRAM pins. See the Funtionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. The device reads these pins at power-up and stores the programmed selection code in an internal data latch. (See programming section of this data sheet for configuration circuitry recommendations. This pin may be operated at any voltage between 3.0 and 5.5 volts. Clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. For the actual guaranteed high and low voltage levels of these clocks, please consult the AC parameter table in this data sheet. GND This is the power supply ground return pin for the internal logic of the device as well as the following clock output buffers: A. B. C. D. BSEL This pin controls whether the BUS clocks will be synchronous (run at half the frequency) with the CPU and CPUL clocks or whether they will be asynchronous (run at a pre-programmed fixed frequency) clock rate. It is a shared pin and is pro grammed the same way as the frequency select pins. REF clock output buffers BUS clock output buffers CPU clock output buffers Fixed clock output buffers X1 This pin serves one of two functions. When the device is used with a crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device’ input pin for that reference clock. This pin also implements an internal crystal loading capacitor that is connected to ground. See the data tables for the value of the capacitor. VDDC (1:2) These are the power supply pins for the CPU (1:6) and CPU (7:12) clock buffers. By separating the clock power pins, each group can receive the appropriate power decoupling and bypassing necessary to minimize EMI and crosstalk between the individual signals. VDDCL can be reduced to 2.5V VDD for advanced processor clocks, which will bring CPU (1:6) outputs at 0 to 2.5V output swings. X2 This pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete crystal. This pin also implements an internal crystal loading capacitor that is connected to ground. See the data tables for the value of the capacitor. 48 MHz This is a fixed frequency clock that is typically used to drive Super I/O peripheral device needs. 24 MHz This is a fixed frequency clock that is typically used to drive Keyboard controller clock needs. CPU This pin is the clock output that drives processor and other CPU related circuitry that require clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these clocks is controlled by that which is applied to the VDDC pins of the device. See note on VDDC (1:2). See the Functionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. REF This is a fixed frequency clock that runs at the same frequency as the input reference clock (typically 14.31818 MHz) is and typically used to drive Video and ISA BUS requirements. VDDB This power pin supplies the BUS clock buffers. VDDF This power pin supplies the 48/24 MHz clocks. BUS This pin is the clock output that is intended to drive the 5 ICS9169C-272 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 – 3.7 V, TA = 0 – 70 ° C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.2VDD V Input High Voltage VIH 0.7VDD - - V Input Low Current IIL VIN=0V -28.0 -10.5 - µA Input High Current IIH VIN = VDD -5.0 - 5.0 µA Output Low Current1 IOL VOL = 0.8V; for CPU, BUS, REF 19.0 30.0 - mA 1 IOH VOL = 2.0V; for CPU, BUS, REF - -38.0 -16.0 mA Output Low Current1 IOL VOL = 0.8V; for fixed CLKs 16.0 25.0 - mA 1 IOH VOL = 2.0V; for fixed CLKs - -30.0 -14.0 mA Output Low Voltage1 VOL IOL = 10mA; for CPU, BUS, REF - 0.3 0.4 V 1 VOH IOH = -15mA; for CPU, BUS, REF 2.4 2.8 - V Output Low Voltage1 VOL IOL = 8mA; for fixed CLKs - 0.3 0.4 V 1 VOH IOH = -8mA; for fixed CLKs 2.4 2.8 - V IDD @66.6 MHz; all outputs unloaded - 90 180 mA Output High Current Output High Current Output High Voltage Output High Voltage Supply Current Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 6 ICS9169C-272 Electrical Characteristics at 3.3V VDD = 3.0 – 3.7 V, TA = 0 – 70° C unless otherwise stated AC Characteristics PARAMETER SYMBOL Rise Time 1 Tr1 Fall Time 1 Tf1 Rise Time 1 Tr2 Fall Time 1 Tf2 Duty Cycle1 Dt TEST CONDITIONS 20pF load, 0.8 to 2.0V CPU & BUS 20pF load, 2.0 to 0.8V CPU & BUS 20pF load, 20% to 80% CPU & BUS 20pF load, 80% to 20% CPU & BUS 20pF load @ VOUT=1.4V CPU & BUS Clocks; Load=20pF, BSEL=1 CPU & BUS Clocks; Load=20pF, BSEL=1 MIN TYP MAX UNITS - 0.9 1.5 ns - 0.8 1.4 ns - 1.5 2.5 ns - 1.4 2.4 ns 45 50 60 % - 50 150 ps -250 - 250 ps Jitter, One Sigma1 Tj1s1 Jitter, Absolute1 Tjab1 Jitter, One Sigma1 Tj1s2 REF & Fixed CLKs; Load=20pF - 1 3 % Jitter, Absolute1 Tjab2 REF & Fixed CLKs; Load=20pF -5 2 5 % Input Frequency1 Fi 12.0 14.318 16.0 MHz Logic Input Capacitance 1 CIN Logic input pins - 5 - pF Crystal Oscillator Capacitance 1 CINX X1, X2 pins - 18 - pF ton From V DD=1.6V to 1st crossing of 66.6 MHz VDD supply ramp < 40ms - 2.5 4.5 ms Clock Skew1 Tsk1 CPU to CPU; Load=20pF; @1.4V - 150 250 ps Clock Skew1 Tsk2 BUS to BUS; Load=20pF; @1.4V - 150 250 ps 1 2.6 4 ns 0.5 1 ns Power-on Time 1 Clock Skew1 Tsk3 Clock Skew1 TSR4 CPU to BUS; Load=20pF; @1.4V (CPU is early) CPU (@3.3V) to CPU (@2.5V) (2.5V CPU is late) Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 7 ICS9169C-272 0.818 SOIC Package Ordering Information ICS9169CM-272 ICS9169CJ-272 SOJ Package Example: ICS XXXX M - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC J=SOJ Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 8 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.