Freescale MCF54455VR266 Mcf5445x coldfireâ® microprocessor data sheet Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MCF54455
Rev. 3, 12/2008
MCF54455
MAPBGA–256
17mm x 17mm
MCF5445x ColdFire®
Microprocessor Data Sheet
Features
• Version 4 ColdFire® Core with MMU and EMAC
• Up to 410 Dhrystone 2.1 MIPS @ 266 MHz
• 16-KBytes instruction cache and 16-KBytes data cache
• 32-KBytes internal SRAM
• Support for booting from SPI-compatible flash, EEPROM,
and FRAM devices
• Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
• 16-channel DMA controller
• 16-bit 133-MHz DDR/mobile-DDR/DDR2 controller
• USB 2.0 On-the-Go controller with ULPI support
• 32-bit PCI controller @ 66MHz
• ATA/ATAPI controller
• 2 10/100 Ethernet MACs
• Coprocessor for acceleration of the DES, 3DES, AES,
MD5, and SHA-1 algorithms
• Random number generator
• Synchronous serial interface (SSI)
• 4 periodic interrupt timers (PIT)
• 4 32-bit timers with DMA support
• DMA-supported serial peripheral interface (DSPI)
• 3 UARTs
• I2C bus interface
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
TEPBGA–360
23mm x 23mm
Table of Contents
1
2
3
4
5
MCF5445x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Analog Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 Oscillator Power Filtering . . . . . . . . . . . . . . . . . . . . . . . .6
3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6
3.3.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . .7
3.3.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . .7
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .7
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.2 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3 Pinout—360 TEPBGA. . . . . . . . . . . . . . . . . . . . . . . . . .16
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .19
5.5 ClockTiming Specifications . . . . . . . . . . . . . . . . . . . . . .20
5.6 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . .22
5.7 FlexBus Timing Specifications . . . . . . . . . . . . . . . . . . .23
5.8 SDRAM AC Timing Characteristics. . . . . . . . . . . . . . . .25
5.9
6
7
8
9
PCI Bus Timing Specifications . . . . . . . . . . . . . . . . . . 27
5.9.1 Overshoot and Undershoot . . . . . . . . . . . . . . . 28
5.10 ULPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 29
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 30
5.12 I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 32
5.13 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . 33
5.13.1 Receive Signal Timing Specifications . . . . . . . 33
5.13.2 Transmit Signal Timing Specifications . . . . . . . 34
5.13.3 Asynchronous Input Signal Timing Specifications34
5.13.4 MII Serial Management Timing Specifications . 35
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 35
5.15 ATA Interface Timing Specifications. . . . . . . . . . . . . . . 36
5.16 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 36
5.17 SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 38
5.18 General Purpose I/O Timing Specifications. . . . . . . . . 39
5.19 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40
5.20 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
2
Freescale Semiconductor
MCF54455
JTAG
Oscillator
PLL
Version 4 ColdFire Core
16K
Instruction
Cache
16K
Data
Cache
EMAC
Hardware
Divide
32K
SRAM
BDM
2 FECs
MMU
CAU
eDMA
USB OTG
PCI
Serial Boot
Crossbar Switch (XBS)
Peripheral Bridge
ATA
DSPI
I2C
RTC
SSI
RNG
GPIO
EPORT
Watchdog
2 INTCs
4 PITs
3 UARTs
4 DMA
Timers
SDRAM
Controller
FlexBus
LEGEND
ATA
BDM
CAU
DSPI
eDMA
EMAC
EPORT
FEC
GPIO
I2 C
– Advanced Technology Attachment Controller
– Background debug module
– Cryptography acceleration unit
– DMA serial peripheral interface
– Enhanced direct memory access
– Enchance multiply-accumulate unit
– Edge port module
– Fast Ethernet Controller
– General Purpose Input/Output Module
– Inter-Intergrated Circuit
INTC
JTAG
MMU
PCI
PIT
PLL
RNG
RTC
SSI
USB OTG
– Interrupt controller
– Joint Test Action Group interface
– Memory management unit
– Peripheral Component Interconnect
– Programmable interrupt timers
– Phase locked loop module
– Random Number Generator
– Real time clock
– Synchronous Serial Interface
– Universal Serial Bus On-the-Go controller
Figure 1. MCF54455 Block Diagram
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
3
MCF5445x Family Comparison
1
MCF5445x Family Comparison
The following table compares the various device derivatives available within the MCF5445x family.
Table 1. MCF5445x Family Configurations
Module
MCF54450
MCF54451
MCF54452
MCF54453
MCF54454
MCF54455
ColdFire Version 4 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
•
•
•
•
•
•
Core (System) Clock
up to 240 MHz
up to 266 MHz
Peripheral Bus Clock
(Core clock ÷ 2)
up to 120 MHz
up to 133 MHz
External Bus Clock
(Core clock ÷ 4)
up to 60 MHz
up to 66 MHz
up to 370
up to 410
Performance (Dhrystone/2.1 MIPS)
Independent Data/Instruction Cache
16 KBytes each
Static RAM (SRAM)
32 KBytes
PCI Controller
•
•
•
•
•
•
Cryptography Acceleration Unit (CAU)
—
•
—
•
—
•
ATA Controller
—
—
—
—
•
•
DDR SDRAM Controller
•
•
•
•
•
•
FlexBus External Interface
•
•
•
•
•
•
USB 2.0 On-the-Go
•
•
•
•
•
•
UTMI+ Low Pin Interface (ULPI)
•
•
•
•
•
•
Synchronous Serial Interface (SSI)
•
•
•
•
•
•
Fast Ethernet Controller (FEC)
1
1
2
2
2
2
UARTs
3
3
3
3
3
3
I2C
•
•
•
•
•
•
DSPI
•
•
•
•
•
•
Real Time Clock
•
•
•
•
•
•
32-bit DMA Timers
4
4
4
4
4
4
Watchdog Timer (WDT)
•
•
•
•
•
•
Periodic Interrupt Timers (PIT)
4
4
4
4
4
4
Edge Port Module (EPORT)
•
•
•
•
•
•
Interrupt Controllers (INTC)
2
2
2
2
2
2
16-channel Direct Memory Access (DMA)
•
•
•
•
•
•
General Purpose I/O Module (GPIO)
•
•
•
•
•
•
JTAG — IEEE 1149.1 Test Access Port
•
•
•
•
•
•
Package
256 MAPBGA
®
360 TEPBGA
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
4
Freescale Semiconductor
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
Description
Package
MCF54450VM180
Speed
Temperature
180 MHz
0° to +70° C
MCF54450 Microprocessor
MCF54450VM240
240 MHz
256 MAPBGA
MCF54451CVM180
180 MHz
–40° to +85° C
240 MHz
0° to +70° C
200 MHz
–40° to +85° C
266 MHz
0° to +70° C
200 MHz
–40° to +85° C
266 MHz
0° to +70° C
200 MHz
–40° to +85° C
266 MHz
0° to +70° C
200 MHz
–40° to +85° C
266 MHz
0° to +70° C
MCF54451 Microprocessor
MCF54451VM240
MCF54452CVR200
MCF54452 Microprocessor
MCF54452VR266
MCF54453CVR200
MCF54453 Microprocessor
MCF54453VR266
360 TEPBGA
MCF54454CVR200
MCF54454 Microprocessor
MCF54454VR266
MCF54455CVR200
MCF54455 Microprocessor
MCF54455VR266
3
Hardware Design Considerations
3.1
Analog Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for the analog VDD pins (VDD_A_PLL,
VDD_RTC). The filter shown in Figure 2 should be connected between the board IVDD and the analog pins. The resistor and
capacitors should be placed as close to the dedicated analog VDD pin as possible. The 10-Ω resistor in the given filter is required.
Do not implement the filter circuit using only capacitors. The analog power pins draw very little current. Concerns regarding
voltage loss across the 10-ohm resistor are not valid.
10 Ω
Board IVDD
Analog VDD Pin
10 µF
0.1 µF
GND
Figure 2. System Analog VDD Power Filter
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
5
Hardware Design Considerations
3.2
Oscillator Power Filtering
Figure 3 shows an example for isolating the oscillator power supply from the I/O supply (EVDD) and ground.
10 Ω
VDD_OSC
EVDD Pin
1 µF
0.1 µF
VSS_OSC
100 MHz
GND
Figure 3. Oscillator Power Filter
3.3
Supply Voltage Sequencing
Figure 4 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD (PVDD), and internal
logic/core VDD (IVDD).
EVDD (3.3V)
3.3V
DC Power Supply Voltage
Supplies Stable
2.5V
SDVDD (2.5V — DDR)
1.8V
SDVDD (1.8V — DDR2)
1.5V
IVDD, PVDD
0
Time
Notes:
1
Input voltage must not be greater than the supply voltage (EVDD, SDVDD, IVDD, or PVDD) by more than 0.5V
at any time, including during power-up.
2
Use 50 V/millisecond or slower rise time for all supplies.
Figure 4. Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or
1.8V) and EVDD are specified relative to IVDD.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
6
Freescale Semiconductor
Pin Assignments and Reset States
3.3.1
Power-Up Sequence
If EVDD/SDVDD are powered up with the IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected
to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD
must power up. The rise times on the power supplies should be slower than 50 V/millisecond to avoid turning on the internal
ESD protection clamp diodes.
3.3.2
Power-Down Sequence
If IVDD/PVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IVDD and PVDD power down before EVDD or SDVDD must power down. There are no
requirements for the fall times of the power supplies.
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF5445x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 4, “Pin Assignments and Reset States,” for package diagrams. For a more detailed discussion
of the MCF5445x signals, consult the MCF54455 Reference Manual (MCF54455RM).
NOTE
In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., FB_AD23), while designations for multiple signals within a
group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two
bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that
are muxed with GPIO default to their GPIO functionality. See Table 3 for a list of the
exceptions.
Table 3. Special-Case Default Signal Functionality
Pin
256 MAPBGA
360 TEPBGA
FB_AD[31:0]
FB_AD[31:0] except when serial boot selects 0-bit
boot port size.
FB_BE/BWE[3:0]
FB_BE/BWE[3:0]
FB_CS[3:1]
FB_CS[3:1]
FB_OE
FB_OE
FB_R/W
FB_R/W
FB_TA
FB_TA
FB_TS
FB_TS
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
7
Pin Assignments and Reset States
Table 3. Special-Case Default Signal Functionality (continued)
Pin
256 MAPBGA
360 TEPBGA
PCI_GNT[3:0]
GPIO
PCI_GNT[3:0]
PCI_REQ[3:0]
GPIO
PCI_REQ[3:0]
IRQ1
GPIO
PCI_INTA and
configured as an agent.
ATA_RESET
GPIO
ATA reset
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
Table 4. MCF5445x Signal Information and Muxing
MCF54450
MCF54451
256 MAPBGA
RESET
—
—
—
U
I
EVDD
L4
Y18
RSTOUT
—
—
—
—
O
EVDD
M15
B17
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
Reset
Clock
EXTAL/PCI_CLK
—
—
—
—
I
EVDD
M16
A16
XTAL
—
—
—
U3
O
EVDD
L16
A17
—
I
EVDD
M5, M7
AB17, AB21
Mode Selection
BOOTMOD[1:0]
—
—
—
FlexBus
FB_AD[31:24]
PFBADH[7:0]4
FB_D[31:24]
—
—
I/O
EVDD
A14, A13, D12,
C12, B12, A12,
D11, C11
J2, K4, J1, K1–3,
L1, L4
FB_AD[23:16]
PFBADMH[7:0]4
FB_D[23:16]
—
—
I/O
EVDD
B11, A11, D10,
C10, B10, A10, D9,
C9
L2, L3, M1–4,
N1–2
FB_AD[15:8]
PFBADML[7:0]4
FB_D[15:8]
—
—
I/O
EVDD
B9, A9, D8, C8, B8,
A8, D7, C7
P1–2, R1–3, P4,
T1–2
FB_AD[7:0]
PFBADL[7:0]4
FB_D[7:0]
—
—
I/O
EVDD
B7, A7, D6, C6, B6, T3–4, U1–3, V1–2,
A6, D5, C5
W1
FB_BE/BWE[3:2]
PBE[3:2]
FB_TSIZ[1:0]
—
—
O
EVDD
B5, A5
Y1, W2
FB_BE/BWE[1:0]
PBE[1:0]
—
—
—
O
EVDD
B4, A4
W3, Y2
FB_CLK
—
—
—
—
O
EVDD
B13
J3
FB_CS[3:1]
PCS[3:1]
—
—
—
O
EVDD
C2, D4, C3
W5, AA4, AB3
FB_CS0
—
—
—
—
O
EVDD
C4
Y4
FB_OE
PFBCTL3
—
—
—
O
EVDD
A2
AA1
FB_R/W
PFBCTL2
—
—
—
O
EVDD
B2
AA3
FB_TA
PFBCTL1
—
—
U
I
EVDD
B1
AB2
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
8
Freescale Semiconductor
Pin Assignments and Reset States
Signal Name
GPIO
Alternate 1
Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54450
MCF54451
256 MAPBGA
FB_TS
PFBCTL0
FB_ALE
FB_TBST
—
O
EVDD
A3
Y3
—
C11, D11, A10,
B10, J4, G2, G3,
F1
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
PCI Controller5
PCI_AD[31:24]
—
FB_A[31:24]
—
—
I/O
EVDD
PCI_AD[23:0]
—
FB_A[23:0]
—
—
I/O
EVDD
PCI_CBE[3:0]
—
—
—
—
I/O
EVDD
—
G4, E4, D1, B1
PCI_DEVSEL
—
—
—
—
O
EVDD
—
F2
PCI_FRAME
—
—
—
—
I/O
EVDD
—
B2
PCI_GNT3
PPCI7
ATA_DMACK
—
—
O
EVDD
—
B7
PCI_GNT[2:1]
PPCI[6:5]
—
—
—
O
EVDD
—
C8, C9
PCI_GNT0/
PCI_EXTREQ
PPCI4
—
—
—
O
EVDD
—
A9
PCI_IDSEL
—
—
—
—
I
EVDD
—
D5
PCI_IRDY
—
—
—
—
I/O
EVDD
—
C3
PCI_PAR
—
—
—
—
I/O
EVDD
—
C4
PCI_PERR
—
—
—
—
I/O
EVDD
—
B4
PCI_REQ3
PPCI3
ATA_INTRQ
—
—
I
EVDD
—
C7
PCI_REQ[2:1]
PPCI[2:1]
—
—
—
I
EVDD
—
D7, C5
PCI_REQ0/
PCI_EXTGNT
PPCI0
—
—
—
I
EVDD
—
A2
PCI_RST
—
—
—
—
O
EVDD
—
B6
PCI_SERR
—
—
—
—
I/O
EVDD
—
A6
PCI_STOP
—
—
—
—
I/O
EVDD
—
A7
PCI_TRDY
—
—
—
—
I/O
EVDD
—
C10
K14–13, J15–13,
D12, C12, B12,
H13–15, G15–13, A11, B11, B9, D9,
F14–13, E15–13,
D10, A8, B8, A5,
D16, B16, C15, B5, A4, A3, B3, D4,
B15, C14, D15, D3, E3–E1, F3, C2,
C16, D14
D2, C1
SDRAM Controller
SD_A[13:0]
—
—
—
—
O
SDVDD
R1, P1, N2, P2,
R2, T2, M4, N3,
P3, R3, T3, T4, R4,
N4
V22, U20–22,
T19–22, R20–22,
N19, P20–21
SD_BA[1:0]
—
—
—
—
O
SDVDD
P4, T5
P22, P19
SD_CAS
—
—
—
—
O
SDVDD
T6
L19
SD_CKE
—
—
—
—
O
SDVDD
N5
N22
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
9
Pin Assignments and Reset States
Signal Name
GPIO
Alternate 1
Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54450
MCF54451
256 MAPBGA
SD_CLK
—
—
—
—
O
SDVDD
T9
L22
SD_CLK
—
—
—
—
O
SDVDD
T8
M22
SD_CS[1:0]
—
—
—
—
O
SDVDD
P6, R6
L20, M20
SD_D[31:16]
—
—
—
—
I/O
SDVDD N6, T7, N7, P7, R7,
L21, K22, K21,
R8, P8, N8, N9, K20, J20, J19, J21,
T10, R10, P10,
J22, H20, G22,
N10, T11, R11,
G21, G20, G19,
P11
F22, F21, F20
SD_DM[3:2]
—
—
—
—
O
SDVDD
P9, N12
H21, E21
SD_DQS[3:2]
—
—
—
—
O
SDVDD
R9, N11
H22, E22
SD_RAS
—
—
—
—
O
SDVDD
P5
N21
SD_VREF
—
—
—
—
I
SDVDD
M8
M21
SD_WE
—
—
—
—
O
SDVDD
R5
N20
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
External Interrupts Port6
IRQ7
PIRQ7
—
—
—
I
EVDD
L1
ABB13
IRQ4
PIRQ4
—
SSI_CLKIN
—
I
EVDD
L2
ABB13
IRQ3
PIRQ3
—
—
—
I
EVDD
L3
AB14
IRQ1
PIRQ1
PCI_INTA
—
—
I
EVDD
F15
C6
FEC0
FEC0_MDC
PFECI2C3
—
—
—
O
EVDD
F3
AB8
FEC0_MDIO
PFECI2C2
—
—
—
I/O
EVDD
F2
Y7
FEC0_COL
PFEC0H4
—
ULPI_DATA7
—
I
EVDD
E1
AB7
FEC0_CRS
PFEC0H0
—
ULPI_DATA6
—
I
EVDD
F1
AA7
FEC0_RXCLK
PFEC0H3
—
ULPI_DATA1
—
I
EVDD
G1
AA8
FEC0_RXDV
PFEC0H2
FEC0_RMII_
CRS_DV
—
—
I
EVDD
G2
Y8
FEC0_RXD[3:2]
PFEC0L[3:2]
—
ULPI_DATA[5:4]
—
I
EVDD
G3, G4
AB9, Y9
FEC0_RXD1
PFEC0L1
FEC0_RMII_RXD1
—
—
I
EVDD
H1
W9
FEC0_RXD0
PFEC0H1
FEC0_RMII_RXD0
—
—
I
EVDD
H2
AB10
FEC0_RXER
PFEC0L0
FEC0_RMII_RXER
—
—
I
EVDD
H3
AA10
FEC0_TXCLK
PFEC0H7
FEC0_RMII_
REF_CLK
—
—
I
EVDD
H4
Y10
FEC0_TXD[3:2]
PFEC0L[7:6]
—
ULPI_DATA[3:2]
—
O
EVDD
J1, J2
W10, AB11
FEC0_TXD1
PFEC0L5
FEC0_RMII_TXD1
—
—
O
EVDD
J3
AA11
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
10
Freescale Semiconductor
Pin Assignments and Reset States
Signal Name
GPIO
Alternate 1
Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54450
MCF54451
256 MAPBGA
FEC0_TXD0
PFEC0H5
FEC0_RMII_TXD0
—
—
O
EVDD
J4
Y11
FEC0_TXEN
PFEC0H6
FEC0_RMII_TXEN
—
—
O
EVDD
K1
W11
FEC0_TXER
PFEC0L4
—
ULPI_DATA0
—
O
EVDD
K2
AB12
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
FEC1
FEC1_MDC
PFECI2C5
—
ATA_DIOR
—
O
EVDD
—
W20
FEC1_MDIO
PFECI2C4
—
ATA_DIOW
—
I/O
EVDD
—
Y22
FEC1_COL
PFEC1H4
—
ATA_DATA7
—
I
EVDD
—
AB18
FEC1_CRS
PFEC1H0
—
ATA_DATA6
—
I
EVDD
—
AA18
FEC1_RXCLK
PFEC1H3
—
ATA_DATA5
—
I
EVDD
—
W14
FEC1_RXDV
PFEC1H2
FEC1_RMII_
CRS_DV
ATA_DATA15
—
I
EVDD
—
AB15
FEC1_RXD[3:2]
PFEC1L[3:2]
—
ATA_DATA[4:3]
—
I
EVDD
—
AA15, Y15
FEC1_RXD1
PFEC1L1
FEC1_RMII_RXD1
ATA_DATA14
—
I
EVDD
—
AA17
FEC1_RXD0
PFEC1H1
FEC1_RMII_RXD0
ATA_DATA13
—
I
EVDD
—
Y17
FEC1_RXER
PFEC1L0
FEC1_RMII_RXER
ATA_DATA12
—
I
EVDD
—
W17
FEC1_TXCLK
PFEC1H7
FEC1_RMII_
REF_CLK
ATA_DATA11
—
I
EVDD
—
AB19
FEC1_TXD[3:2]
PFEC1L[7:6]
—
ATA_DATA[2:1]
—
O
EVDD
—
Y19, W18
FEC1_TXD1
PFEC1L5
FEC1_RMII_TXD1
ATA_DATA10
—
O
EVDD
—
AA19
FEC1_TXD0
PFEC1H5
FEC1_RMII_TXD0
ATA_DATA9
—
O
EVDD
—
Y20
FEC1_TXEN
PFEC1H6
FEC1_RMII_TXEN
ATA_DATA8
—
O
EVDD
—
AA21
FEC1_TXER
PFEC1L4
—
ATA_DATA0
—
O
EVDD
—
AA22
USB On-the-Go
USB_DM
—
—
—
—
O
USB
VDD
F16
A14
USB_DP
—
—
—
—
O
USB
VDD
E16
A15
USB_VBUS_EN
PUSB1
USB_PULLUP
ULPI_NXT
—
O
USB
VDD
E5
AA2
USB_VBUS_OC
PUSB0
—
ULPI_STP
UD7
I
USB
VDD
B3
V4
ATA
ATA_BUFFER_EN
PATAH5
—
—
—
O
EVDD
—
Y13
ATA_CS[1:0]
PATAH[4:3]
—
—
—
O
EVDD
—
W21, W22
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
11
Pin Assignments and Reset States
Signal Name
GPIO
Alternate 1
Alternate 2
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54450
MCF54451
256 MAPBGA
ATA_DA[2:0]
PATAH[2:0]
—
—
—
O
EVDD
—
V19–21
ATA_RESET
PATAL2
—
—
—
O
EVDD
—
W13
ATA_DMARQ
PATAL1
—
—
—
I
EVDD
—
AA14
ATA_IORDY
PATAL0
—
—
—
I
EVDD
—
Y14
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
Real Time Clock
EXTAL32K
—
—
—
—
I
EVDD
J16
A13
XTAL32K
—
—
—
—
O
EVDD
H16
A12
SSI
SSI_MCLK
PSSI4
—
—
—
O
EVDD
T13
D20
SSI_BCLK
PSSI3
U1CTS
—
—
I/O
EVDD
R13
E19
SSI_FS
PSSI2
U1RTS
—
—
I/O
EVDD
P12
E20
SSI_RXD
PSSI1
U1RXD
—
UD
I
EVDD
T12
D21
SSI_TXD
PSSI0
U1TXD
—
UD
O
EVDD
R12
D22
I2C
I2C_SCL
PFECI2C1
—
U2TXD
U
I/O
EVDD
K3
AA12
I2C_SDA
PFECI2C0
—
U2RXD
U
I/O
EVDD
K4
Y12
DMA
DACK1
PDMA3
—
ULPI_DIR
—
O
EVDD
M14
C17
DREQ1
PDMA2
—
USB_CLKIN
U
I
EVDD
P16
C18
DACK0
PDMA1
DSPI_PCS3
—
—
O
EVDD
N15
A18
DREQ0
PDMA0
—
—
U
I
EVDD
N16
B18
DSPI
DSPI_PCS5/PCSS
PDSPI6
—
—
—
O
EVDD
N14
D18
DSPI_PCS2
PDSPI5
—
—
—
O
EVDD
L13
A19
DSPI_PCS1
PDSPI4
SBF_CS
—
—
O
EVDD
P14
B20
DSPI_PCS0/SS
PDSPI3
—
—
U
I/O
EVDD
R16
D17
DSPI_SCK
PDSPI2
SBF_CK
—
—
I/O
EVDD
R15
A20
DSPI_SIN
PDSPI1
SBF_DI
—
8
I
EVDD
P15
B19
DSPI_SOUT
PDSPI0
SBF_DO
—
—
O
EVDD
N13
C20
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
12
Freescale Semiconductor
Pin Assignments and Reset States
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54450
MCF54451
256 MAPBGA
U1CTS
PUART7
—
—
—
I
EVDD
—
V3
U1RTS
PUART6
—
—
—
O
EVDD
—
U4
U1RXD
PUART5
—
—
—
I
EVDD
—
P3
U1TXD
PUART4
—
—
—
O
EVDD
—
N3
U0CTS
PUART3
—
—
—
I
EVDD
M3
Y16
U0RTS
PUART2
—
—
—
O
EVDD
M2
AA16
U0RXD
PUART1
—
—
—
I
EVDD
N1
AB16
U0TXD
PUART0
—
—
—
O
EVDD
M1
W15
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
UARTs
Note: The UART1 and UART 2 signals are multiplexed on the DMA timers and I2C pins.
DMA Timers
DT3IN
PTIMER3
DT3OUT
U2RXD
—
I
EVDD
C13
H2
DT2IN
PTIMER2
DT2OUT
U2TXD
—
I
EVDD
D13
H1
DT1IN
PTIMER1
DT1OUT
U2CTS
—
I
EVDD
B14
H3
DT0IN
PTIMER0
DT0OUT
U2RTS
—
I
EVDD
A15
G1
BDM/JTAG9
PSTDDATA[7:0]
—
—
—
—
O
EVDD
JTAG_EN
—
—
—
D
I
EVDD
M11
C21
PSTCLK
—
TCLK
—
—
I
EVDD
P13
C22
DSI
—
TDI
—
U
I
EVDD
T15
C19
DSO
—
TDO
—
—
O
EVDD
T14
A21
BKPT
—
TMS
—
U
I
EVDD
R14
B21
DSCLK
—
TRST
—
U
I
EVDD
M13
B22
E2, D1, F4, E3, D2, AA6, AB6, AB5,
C1, E4, D3
W6, Y6, AA5, AB4,
Y5
Test
TEST
—
—
—
D
I
EVDD
M6
AB20
PLLTEST
—
—
—
—
O
EVDD
K16
D15
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
13
Pin Assignments and Reset States
Pull-up (U)1
Pull-down (D)
Direction2
Voltage Domain
Table 4. MCF5445x Signal Information and Muxing (continued)
MCF54450
MCF54451
256 MAPBGA
IVDD
—
—
—
—
—
—
E6–12, F5, F12
EVDD
—
—
—
—
—
—
SD_VDD
—
—
—
—
—
—
L7–11, M9, M10
F19, H19, K19,
M19, R19, U19
VDD_OSC
—
—
—
—
—
—
L14
B16
VDD_A_PLL
—
—
—
—
—
—
K15
C14
VDD_RTC
—
—
—
—
—
—
M12
C13
VSS
—
—
—
—
—
—
VSS_OSC
—
—
—
—
—
—
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54452
MCF54453
MCF54454
MCF54455
360 TEPBGA
Power Supplies
1
2
3
4
5
6
7
8
9
D6, D8, D14, F4,
H4, N4, R4, W4,
W7, W8, W12,
W16, W19
G5, G12, H5, H12,
D13, D19, G8,
J5, J12, K5, K12, G11, G14, G16, J7,
L5–6, L12
J16, L7, L16, N16,
P7, R16, T8, T12,
T14, T16
A1, A16, F6–11, A1, A22, B14, G7,
G6–11, H6–11,
G9–10, G12–13,
J6–11, K6–11, T1,
G15, H7, H16,
T16
J9–14, K7, K9–14,
K16, L9–14, M7,
M9–M14, M16,
N9–14, P9–14,
P16, R7, T7,
T9–11, T13, T15,
AB1, AB22
L15
C16
Pull-ups are generally only enabled on pins with their primary function, except as noted.
Refers to pin’s primary function.
Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
Serial boot must select 0-bit boot port size to enable the GPIO mode on these pins.
When the PCI is enabled, all PCI bus pins come up configured as such. This includes the PCI_GNT and PCI_REQ lines, which have
GPIO. The IRQ1/PCI_INTA signal is a special case. It comes up as PCI_INTA when booting as a PCI agent and as GPIO when booting
as a PCI host.
For the 360 TEPBGA, booting with PCI disabled results in all dedicated PCI pins being safe-stated. The PCI_GNT and PCI_REQ lines
and IRQ1/PCI_INTA come up as GPIO.
GPIO functionality is determined by the edge port module. The pin multiplexing and control module is only responsible for assigning
the alternate functions.
Depends on programmed polarity of the USB_VBUS_OC signal.
Pull-up when the serial boot facility (SBF) controls the pin
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The pin multiplexing and control module is not
responsible for assigning these pins.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
14
Freescale Semiconductor
Pin Assignments and Reset States
4.2
Pinout—256 MAPBGA
The pinout for the MCF54450 and MCF54451 packages are shown below.
1
2
3
A
VSS
FB_OE
FB_TS
B
FB_TA
USB_
FB_R/W VBUS_
OC
4
5
6
7
8
9
10
11
12
13
14
15
16
FB_BE/ FB_BE/
BWE0
BWE2
FB_AD
2
FB_AD
6
FB_AD
10
FB_AD
14
FB_AD
18
FB_AD
22
FB_AD
26
FB_AD
30
FB_AD
31
T0IN
VSS
FB_BE/ FB_BE/
BWE1
BWE3
FB_AD
3
FB_AD
7
FB_AD
11
FB_AD
15
FB_AD
19
FB_AD
23
FB_AD
27
FB_CLK
T1IN
C
PST
FB_AD
FB_CS3 FB_CS1 FB_CS0
DDATA2
0
FB_AD
4
FB_AD
8
FB_AD
12
FB_AD
16
FB_AD
20
FB_AD
24
FB_AD
28
T3IN
PCI_AD PCI_AD PCI_AD
C
3
5
1
D
PST
PST
PST
FB_AD
FB_CS2
DDATA6 DDATA3 DDATA0
1
FB_AD
5
FB_AD
9
FB_AD
13
FB_AD
17
FB_AD
21
FB_AD
25
FB_AD
29
T2IN
PCI_AD PCI_AD PCI_AD
D
0
2
7
E
FEC0_
COL
USB_
PST
PST
PST
VBUS_
DDATA7 DDATA4 DDATA1
EN
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
PCI_AD PCI_AD PCI_AD
8
9
10
USB_
DP
E
F
FEC0_
CRS
FEC0_
MDIO
FEC0_
MDC
PST
DDATA5
IVDD
VSS
VSS
VSS
VSS
VSS
VSS
IVDD
PCI_AD PCI_AD
11
12
USB_
DM
F
G
FEC0_
RXCLK
FEC0_
RXDV
FEC0_
RXD3
FEC0_
RXD2
EVDD
VSS
VSS
VSS
VSS
VSS
VSS
EVDD
PCI_AD PCI_AD PCI_AD
13
14
15
NC
G
H
FEC0_
RXD1
FEC0_
RXD0
FEC0_
RXER
FEC0_
TXCLK
EVDD
VSS
VSS
VSS
VSS
VSS
VSS
EVDD
PCI_AD PCI_AD PCI_AD
18
17
16
XTAL
32K
H
J
FEC0_
TXD3
FEC0_
TXD2
FEC0_
TXD1
FEC0_
TXD0
EVDD
VSS
VSS
VSS
VSS
VSS
VSS
EVDD
PCI_AD PCI_AD PCI_AD
19
20
21
EXTAL
32K
J
K
FEC0_
TXEN
FEC0_
TXER
I2C_
SCL
I2C_
SDA
EVDD
VSS
VSS
VSS
VSS
VSS
VSS
EVDD
PCI_AD PCI_AD VDD_A
22
23
_PLL
PLL
TEST
K
L
IRQ_7
IRQ_4
IRQ_3
RESET
EVDD
EVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
EVDD
DSPI_
PCS2
VDD_
OSC
VSS_
OSC
XTAL
L
M U0TXD
U0RTS
U0CTS
SD_A7
BOOT
MOD1
TEST
BOOT
MOD0
SD_
VREF
SDVDD
SDVDD
JTAG_
EN
VDD_
RTC
TRST
DACK1
RST
OUT
EXTAL M
N U0RXD SD_A11 SD_A6
SD_A0
SD_
CKE
SD_D31 SD_D29 SD_D24 SD_D23 SD_D19
SD_
DQS2
SD_DM2
DSPI_
SOUT
DSPI_
PCS5
DACK0
DREQ0 N
SSI_FS
TCLK
DSPI_
PCS1
DSPI_
SIN
DREQ1 P
P SD_A12 SD_A10 SD_A5 SD_BA1
SD_D28 SD_D25
SD_
DM3
SD_
DQS3
SD_D21 SD_D17 SSI_TXD
SSI_
BCLK
TMS
DSPI_
SCK
DSPI_
PCS0
R
SD_D22 SD_D18 SSI_RXD
SSI_
MCLK
TDO
TDI
VSS
T
13
14
15
16
SD_A1
SD_WE
SD_
CS0
SD_D27 SD_D26
T
SD_A2 SD_BA0
SD_
CAS
SD_D30
SD_
CLK
SD_
CLK
6
7
8
9
SD_A3
1
2
3
4
IRQ_1
SD_
CS1
SD_A4
SD_A8
PCI_AD PCI_AD
B
4
6
SD_
RAS
R SD_A13 SD_A9
VSS
A
5
SD_D20 SD_D16
10
11
12
Figure 5. MCF54450 and MCF54451 Pinout (256 MAPBGA)
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
15
Pin Assignments and Reset States
4.3
Pinout—360 TEPBGA
The pinout for the MCF54452, MCF54453, MCF54454, and MCF54455 packages are shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
GND
PCI_
REQ0
PCI_
AD10
PCI_
AD11
PCI_
AD13
PCI_
SERR
PCI_
STOP
PCI_
AD15
PCI_
GNT0
PCI_
AD29
PCI_
AD20
XTAL
32K
EXTAL
32K
USB_
DM
USB_
DP
16
EXTAL
B
PCI_
CBE0
PCI_
FRAME
PCI_
AD9
PCI_
PERR
PCI_
AD12
PCI_
RST
PCI_
GNT3
PCI_
AD14
PCI_
AD18
PCI_
AD28
PCI_
AD19
PCI_
AD21
NC
GND
NC
C
PCI_
AD0
PCI_
AD2
PCI_
IRDY
PCI_
PAR
PCI_
REQ1
IRQ1
PCI_
REQ3
PCI_
GNT2
PCI_
GNT1
PCI_
TRDY
PCI_
AD31
PCI_
AD22
VDD_
RTC
VDD_
A_PLL
D
PCI_
CBE1
PCI_
AD1
PCI_
AD7
PCI_
AD8
PCI_
IDSEL
IVDD
PCI_
REQ2
IVDD
PCI_
AD17
PCI_
AD16
PCI_
AD30
PCI_
AD23
EVDD
IVDD
E
PCI_
AD4
PCI_
AD5
PCI_
AD6
F
PCI_
AD24
PCI_DE
VSEL
G
T0IN
H
17
18
19
20
21
22
XTAL
DACK0
DSPI_
PCS2
DSPI_
SCK
TDO
GND
A
VDD_
OSC
RST
OUT
DREQ0
DSPI_
SIN
DSPI_
PCS1
TMS
TRST
B
NC
VSS_
OSC
DACK1
DREQ1
TDI
DSPI_
SOUT
JTAG_
EN
TCLK
C
PLL
TEST
NC
DSPI_
PCS0
DSPI_
PCS5
EVDD
SSI_
MCLK
SSI_
RXD
SSI_
TXD
D
PCI_
CBE2
SSI_
BCLK
SSI_FS
SD_
DM2
SD_
DQS2
E
PCI_
AD3
IVDD
SDVDD
PCI_
AD26
PCI_
AD25
PCI_
CBE3
GND
T2IN
T3IN
T1IN
IVDD
GND
J
FB_AD
29
FB_AD
31
FB_CLK
PCI_
AD27
EVDD
GND
GND
GND
GND
GND
K
FB_AD
28
FB_AD
27
FB_AD
26
FB_AD
30
GND
GND
GND
GND
GND
L
FB_AD
25
FB_AD
23
FB_AD
22
FB_AD
24
EVDD
GND
GND
GND
M
FB_AD
21
FB_AD
20
FB_AD
19
FB_AD
18
GND
GND
GND
N
FB_AD
17
FB_AD
16
U1TXD
IVDD
GND
GND
P
FB_AD
15
FB_AD
14
U1RXD
FB_AD
10
EVDD
GND
R
FB_AD
13
FB_AD
12
FB_AD
11
IVDD
GND
T
FB_AD
9
FB_AD
8
FB_AD
7
FB_AD
6
GND
U
FB_AD
5
FB_AD
4
FB_AD
3
V
FB_AD
2
FB_AD
1
W
FB_AD
0
Y
SD_D16 SD_D17 SD_D18
F
EVDD
SD_D19 SD_D20 SD_D21 SD_D22
G
GND
SDVDD
GND
EVDD
SD_D26 SD_D27 SD_D25 SD_D24
J
GND
GND
GND
SDVDD
K
GND
GND
GND
EVDD
SD_
CAS
SD_
CS1
SD_D31
SD_
CLK
L
GND
GND
GND
GND
GND
SDVDD
SD_
CS0
SD_
VREF
SD_
CLK
M
GND
GND
GND
GND
GND
EVDD
SD_A2
SD_WE
SD_
RAS
SD_
CKE
N
GND
GND
GND
GND
GND
GND
SD_
BA0
SD_A1
SD_A0
SD_
BA1
P
EVDD
SDVDD
SD_A5
SD_A4
SD_A3
R
EVDD
SD_A9
SD_A8
SD_A7
SD_A6
T
U1RTS
SDVDD
SD_A12 SD_A11 SD_A10
U
U1CTS
USB_
VBUS_
OC
ATA_
DA2
ATA_
DA1
ATA_
DA0
SD_A13
V
FB_BE/
BWE2
FB_BE/
BWE1
IVDD
FB_BE/
BWE3
FB_BE/
BWE0
FB_TS
FB_CS0
AA
FB_OE
USB_
VBUS_
EN
FB_R/W FB_CS2
AB
GND
FB_TA
FB_CS1
1
2
3
EVDD
GND
GND
GND
GND
EVDD
GND
GND
EVDD
GND
GND
EVDD
EVDD
GND
GND
SD_D23
SD_
DM3
SD_
DQS3
SD_D28 SD_D29 SD_D30
IVDD
FEC0_
RXD1
FEC0_
TXD3
FEC0_
TXEN
IVDD
ATA_
RESET
FEC1_
RXCLK
U0TXD
IVDD
FEC1_
RXER
FEC1_
TXD2
IVDD
FEC1_
MDC
ATA_
CS1
ATA_
CS0
W
PST
PST
DDATA0 DDATA3
FEC0_
MDIO
FEC0_
RXDV
FEC0_
RXD2
FEC0_
TXCLK
FEC0_
TXD0
I2C_
SDA
ATA_BU
FFER_
EN
ATA_
IORDY
FEC1_
RXD2
U0CTS
FEC1_
RXD0
RESET
FEC1_
TXD3
FEC1_
TXD0
NC
FEC1_
MDIO
Y
PST
PST
DDATA2 DDATA7
FEC0_
CRS
FEC0_
RXCLK
NC
FEC0_
RXER
FEC0_
TXD1
I2C_
SCL
IRQ4
ATA_
DMARQ
FEC1_
RXD3
U0RTS
FEC1_
RXD1
FEC1_
CRS
FEC1_
TXD1
NC
FEC1_
TXEN
FEC1_
TXER
AA
PST
PST
PST
DDATA1 DDATA5 DDATA6
FEC0_
COL
FEC0_
MDC
FEC0_
RXD3
FEC0_
RXD0
FEC0_
TXD2
FEC0_
TXER
IRQ7
IRQ3
FEC1_
RXDV
U0RXD
BOOT
MOD1
FEC1_
COL
FEC1_
TXCLK
TEST
BOOT
MOD0
GND
AB
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
4
5
6
Figure 6. MCF54452, MCF54453, MCF54454, and MCF54455 Pinout (360 TEPBGA)
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
16
H
IVDD
FB_CS3
PST
DDATA4
EVDD
Freescale Semiconductor
Electrical Characteristics
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF54455 microprocessor. This
section contains detailed information on DC/AC electrical characteristics and AC timing specifications.
The electrical specifications are preliminary and from previous designs or design simulations. These specifications may not be
fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications will
be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
NOTE
The parameters specified in this MCU document supersede any values found in the module
specifications.
5.1
Absolute Maximum Ratings
Table 5. Absolute Maximum Ratings1, 2
Rating
Symbol
Pin Name
Value
Units
External I/O pad supply voltage
EVDD
EVDD
-0.3 to +4.0
V
Internal oscillator supply voltage
OSCVDD
VDD_OSC
-0.3 to +4.0
V
Real-time clock supply voltage
RTCVDD
VDD_RTC
-0.5 to +2.0
V
IVDD
IVDD
-0.5 to +2.0
V
SDVDD
SD_VDD
-0.3 to +4.0
V
PVDD
VDD_A_PLL
-0.5 to +2.0
V
Digital input voltage3
VIN
—
-0.3 to +3.6
V
Instantaneous maximum current
Single pin limit (applies to all pins) 3, 4, 5
IDD
—
25
mA
Operating temperature range (packaged)
TA
(TL - TH)
—
-40 to +85
°C
Tstg
—
-55 to +150
°C
Internal logic supply voltage
SDRAM I/O pad supply voltage
PLL supply voltage
Storage temperature range
1
2
3
4
5
Functional operating conditions are given in Table 8. Absolute maximum ratings are stress ratings only, and functional
operation at the maximum is not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is
advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level
(e.g., VSS or EVDD).
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, and then use the larger of the two values.
All functional non-supply pins are internally clamped to VSS and EVDD.
Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum
current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of EVDD
and could result in external power supply going out of regulation. Ensure the external EVDD load shunts current greater
than maximum injection current. This is the greatest risk when the MPU is not consuming power (ex; no clock). The power
supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current
conditions.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
17
Electrical Characteristics
5.2
Thermal Characteristics
Table 6. Thermal Characteristics
Characteristic
Symbol
256
MAPBGA
360
TEPBGA
Unit
Junction to ambient, natural convection
Four layer board
(2s2p)
θJA
291,2
241,2
°C/W
Junction to ambient (@200 ft/min)
Four layer board
(2s2p)
θJMA
251,2
211,2
°C/W
Junction to board
θJB
183
153
°C/W
Junction to case
θJC
104
114
°C/W
Junction to top of package
Ψjt
1,5
2
2
1,5
°C/W
Maximum operating junction temperature
Tj
105
105
1
2
3
4
5
o
C
θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of θJmA and power dissipation specifications in the system design to prevent
device junction temperatures from exceeding the rated specification. System designers should be aware that
device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the
customer’s system using the Ψjt parameter, the device power dissipation, and the method described in
EIA/JESD Standard 51-2.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.
Board temperature is measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in °C can be obtained from:
T J = T A + ( P D × Θ JMA )
Eqn. 1
Where:
TA
QJMA
PD
PINT
PI/O
=
=
=
=
=
Ambient Temperature, °C
Package Thermal Resistance, Junction-to-Ambient, °C/W
PINT + PI/O
IDD × IVDD, Watts - Chip Internal Power
Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
K
P D = --------------------------------( T J + 273°C )
Eqn. 2
Solving equations 1 and 2 for K gives:
2
K = P D × ( T A × 273°C ) + Q JMA × P D
Eqn. 3
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
18
Freescale Semiconductor
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
5.3
ESD Protection
Table 7. ESD Protection Characteristics1, 2
Characteristics
ESD Target for Human Body Model
Symbol
Value
Units
HBM
2000
V
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 8. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Units
IVDD
1.35
1.65
V
PLL analog operation voltage range 1
PVDD
1.35
1.65
V
External I/O pad supply voltage
EVDD
3.0
3.6
V
Internal oscillator supply voltage
OSCVDD
3.0
3.6
V
Real-time clock supply voltage
RTCVDD
1.35
1.65
V
SDRAM I/O pad supply voltage — DDR mode
SDVDD
2.25
2.75
V
SDRAM I/O pad supply voltage — DDR2 mode
SDVDD
1.7
1.9
V
SDRAM I/O pad supply voltage — Mobile DDR mode
SDVDD
1.7
1.9
V
SDRAM input reference voltage
SDVREF
Internal logic supply
voltage1
0.49 x SDVDD 0.51 x SDVDD
V
Input High Voltage
VIH
0.7 x EVDD
3.65
V
Input Low Voltage
VIL
VSS – 0.3
0.35 x EVDD
V
VHYS
0.06 x EVDD
—
mV
Input Leakage Current
Vin = VDD or VSS, Input-only pins
Iin
–1.0
1.0
μA
High Impedance (Off-State) Leakage Current2
Vin = VDD or VSS, All input/output and output pins
IOZ
–10.0
10.0
μA
Output High Voltage (All input/output and all output pins)
IOH = –5.0 mA
VOH
0.85 × EVDD
__
V
Output Low Voltage (All input/output and all output pins)
IOL = 5.0mA
VOL
__
0.15 × EVDD
V
Input Hysteresis
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
19
Electrical Characteristics
Table 8. DC Electrical Specifications
Characteristic
Weak Internal Pull Up Device Current, tested at VIL Max.3
4
Load Capacitance
Low drive strength
High drive strength
3
4
5
6
7
5.5
Max
Units
IAPU
–10
–130
μA
—
—
7
7
pF
pF
CL
DC Injection Current 3, 5, 6, 7
VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3
Single Pin Limit
Total MCU Limit, Includes sum of all stressed pins
2
Min
Cin
Input Capacitance
All input-only pins
All input/output (three-state) pins
1
Symbol
25
50
IIC
mA
-1.0
-10
1.0
10
IVDD and PVDD should be at the same voltage. PVDD should have a filtered input. Please see the PLL section of this
specification for an example circuit. There are three PVDD inputs, one for each PLL. A filter circuit should used on each
PVDD input.
Worst-case tristate leakage current with only one I/O pin high. Since all I/Os share power when high, the leakage current
is distributed among them. With all I/Os high, this spec reduces to ±2 μA min/max.
Refer to the MCF54455 Reference Manual signals description chapter for pins having weak internal pull-up devices.
This parameter is characterized before qualification rather than 100% tested.
All functional non-supply pins are internally clamped to VSS and their respective VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Ensure the external VDD load shunts current greater
than the maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up,
the system clock is not present during the power-up sequence until the PLL has attained lock.
ClockTiming Specifications
The clock module configures the device for one of several clocking methods. Clocking modes include internal phase-locked
loop (PLL) clocking with an external clock reference or an external crystal reference supported by an internal crystal amplifier.
The PLL can also be disabled, and an external oscillator can directly clock the device.
The specifications in Table 9 are for the CLKIN input pin (EXTAL input driven by an external clock reference). The duty cycle
specification is based on an acceptable tolerance for the PLL, which yields 50% duty-cycle internal clocks to all on-chip
peripherals. The MCF5445x devices use the input clock signal as its synchronous bus clock for PCI. A poor duty cycle on the
input clock, may affect the overall timing margin to external devices. If negative edge logic is used to interface to PCI, providing
a 50% duty-cycle input clock aids in simplifying overall system design.
Table 9. Input Clock Timing Requirements
Item
C1
Specification
Cycle time
Min
Max
Unit
15
40
ns
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
20
Freescale Semiconductor
Electrical Characteristics
Table 9. Input Clock Timing Requirements (continued)
Item
Specification
Min
Max
Unit
25
66.66
MHz
1 / C1 Frequency
C2
Rise time (20% of vdd to 80% of vdd)
-
2
ns
C3
Fall time (80% of vdd to 20% of vdd)
-
2
ns
C4
Duty cycle (at 50% of vdd)
40
60
%
C1
Input Clock (CLKIN)
C4
C4
C2
C3
Figure 7. Input Clock Timing Diagram
Table 10. PLL Electrical Characteristics
Symbol
Min.
Value
Max.
Value
Unit
fref_crystal
fref_ext
16
16
40
66.66
MHz
MHz
Core/System Frequency
fsys
512 Hz1
266.67 MHz
—
Core/System Clock Period
tsys
—
1/fsys
ns
VCO Frequency (fvco = fref × PFDR)
fvco
300
540
MHz
tcst
—
10
ms
Num
1
2
19
Characteristic
PLL Reference Frequency Range
Crystal reference
External reference
2, 3
3
Crystal Start-up Time
4
EXTAL Input High Voltage
Crystal Mode4
All other modes (External, Limp)
VIHEXT
VIHEXT
VXTAL + 0.4
EVDD/2 + 0.4
—
—
V
V
EXTAL Input Low Voltage
Crystal Mode4
All other modes (External, Limp)
VILEXT
VILEXT
—
—
VXTAL - 0.4
EVDD/2 - 0.4
V
V
1
2
ns
tlpll
—
50000
CLKIN
tdc
40
60
%
IXTAL
1
3
mA
5
6
EXTAL Input Rise & Fall Time (20% to 80% EVDD)
(External, Limp)
7
PLL Lock Time 3, 5
reference 3
8
Duty Cycle of
9
XTAL Current
10
Total on-chip stray capacitance on XTAL
CS_XTAL
—
1.5
pF
11
Total on-chip stray capacitance on EXTAL
CS_EXTAL
—
1.5
pF
(External, Limp)
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
21
Electrical Characteristics
Table 10. PLL Electrical Characteristics (continued)
Num
12
Crystal capacitive load
13
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
14
15
17
1
2
3
4
5
6
7
Characteristic
Symbol
CL
Min.
Value
Max.
Value
Unit
See crystal spec
CL_XTAL
CL_EXTAL
—
2 × (CL CS_XTAL CS_EXTAL CS_PCB)6
pF
Frequency un-LOCK Range
fUL
-4.0
4.0
% fsys
Frequency LOCK Range
fLCK
-2.0
2.0
% fsys
—
—
10
TBD
% FB_CLK
% FB_CLK
3, 4, 7
CLKOUT Period Jitter,
Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
Cjitter
The minimum system frequency is the minimum input clock divided by the maximum low-power divider (16 MHz ÷ 32,768).
When the PLL is enabled, the minimum system frequency (fsys) is 150 MHz.
This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock
reference only.
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time.
CS_PCB is the measured PCB stray capacitance on EXTAL and XTAL.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval.
5.6
Reset Timing Specifications
Table 11 lists specifications for the reset timing parameters shown in Figure 8.
Table 11. Reset and Configuration Override Timing
Num
R11
R2
Characteristic
Min
Max
Unit
RESET valid to CLKIN (setup)
9
—
ns
CLKIN to RESET invalid (hold)
1.5
—
ns
5
—
CLKIN cycles
time2
R3
RESET valid
R4
CLKIN to RSTOUT valid
—
10
ns
R5
RSTOUT valid to Configuration Override inputs valid
0
—
ns
R6
Configuration Override inputs valid to RSTOUT invalid (setup)
20
—
CLKIN cycles
R7
Configuration Override inputs invalid after RSTOUT invalid (hold)
0
—
ns
R8
RSTOUT invalid to Configuration Override inputs High Impedance
—
1
CLKIN cycles
1
RESET and Configuration Override data lines are synchronized internally. Setup and hold times must be met only if
recognition on a particular clock is required.
2 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously
to the system. Thus, RESET must be held a minimum of 100 ns.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
22
Freescale Semiconductor
Electrical Characteristics
CLKIN
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides*:
(BOOTMOD[1:0],
Override pins])
Figure 8. RESET and Configuration Override Timing
5.7
FlexBus Timing Specifications
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 66MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices, a simple chip-select based interface can be used.
All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a
reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock
(FB_CLK). All other timing relationships can be derived from these values.
Table 12. FlexBus AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
Frequency of Operation
25
66.66
MHz
FB1
Clock Period
15
40
ns
FB2
Output Valid
—
7.0
ns
1
FB3
Output Hold
1.0
—
ns
1
FB4
Input Setup
3.0
—
ns
2
FB5
Input Hold
0
—
ns
2
1
Specification is valid for all FB_AD[31:0], FB_BS[3:0], FB_CS[3:0], FB_OE, FB_R/W, FB_TBST,
FB_TSIZ[1:0], and FB_TS.
2 Specification is valid for all FB_AD[31:0] and FB_TA.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and PCI
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
23
Electrical Characteristics
S0
S1
S2
S3
FB_CLK
FB1
FB3
FB_AD[Y:0]
ADDR[Y:0]
Mux’d Bus
FB2
FB_AD[31:X]
FB5
ADDR[31:X]
DATA
FB4
FB_A[31:0]
ADDR[31:0]
Non-Mux’d Bus
FB_D[31:X]
ADDR[31:X]
DATA
FB_R/W
FB_ALE
FB_CSn, FB_OE,
FB_BE/BWEn
FB4
FB5
FB_TA
TSIZ[1:0]
FB_TSIZ[1:0]
Figure 9. FlexBus Read Timing
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[Y:0]
FB_AD[Y:0]
Mux’d Bus
FB2
FB_AD[31:X]
DATA
ADDR[31:X]
ADDR[31:0]
FB_A[31:0]
Non-Mux’d Bus
FB_D[31:X]
ADDR[31:X]
DATA
FB_R/W
FB_ALE
FB_CSn, FB_BE/BWEn
FB_OE
FB4
FB5
FB_TA
FB_TSIZ[1:0]
TSIZ[1:0]
Figure 10. Flexbus Write Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
24
Freescale Semiconductor
Electrical Characteristics
5.8
SDRAM AC Timing Characteristics
The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing
numbers are relative to the four DQS byte lanes.
Table 13. SDRAM Timing Specifications
Num
Characteristic
Symbol
Frequency of Operation
1
3
4
5
6
7
8
Max
Unit
Notes
60
133.33
MHz
1
DD1
Clock Period
tSDCK
7.5
16.67
ns
DD2
Pulse Width High
tSDCKH
0.45
0.55
tSDCK
2
DD3
Pulse Width Low
tSDCKL
0.45
0.55
tSDCK
3
DD4
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] — Output Valid
tCMV
—
(0.5 x tSDCK)
+ 1.0ns
ns
3
DD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] — Output Hold
tCMH
2.0
—
ns
DD6
Write Command to first DQS Latching Transition
tDQSS
(1.0 x tSDCK)
- 0.6ns
(1.0 x tSDCK)
+ 0.6ns
ns
DD7
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
tQS
1.0
—
ns
DD8
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
tQH
1.0
—
ns
6
DD9
Input Data Skew Relative to DQS (Input Setup)
tIS
—
1.0
ns
7
tIH
(0.25 x tSDCK)
+ 0.5ns
—
ns
8
DD10 Input Data Hold Relative to DQS.
2
Min
4
5
The SDRAM interface operates at the same frequency as the internal system bus.
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (tSDCK) plus some minor adjustments for process, temperature, and
voltage variations.
This specification relates to the required input setup time of DDR memories. The microprocessor’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid
for each subsequent DQS edge.
This specification relates to the required hold time of DDR memories.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes
valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
25
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
DD6
DD4
SD_A[13:0]
ROW
COL
DD7
SD_DM3/SD_DM2
DD8
SD_DQS3/SD_DQS2
DD7
SD_D[31:24]/SD_D[23:16]
WD1 WD2 WD3 WD4
DD8
Figure 11. DDR Write Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
26
Freescale Semiconductor
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CL=2
CMD
DD4
SD_A[13:0]
CL=2.5
ROW
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
CL = 2
SD_DQS3/SD_DQS2
DD10
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
DQS Read
DQS Read
Preamble
Postamble
CL = 2.5
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 12. DDR Read Timing
5.9
PCI Bus Timing Specifications
The PCI bus on the device is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Refer to the
PCI 2.2 spec for a more detailed timing analysis.
Table 14. PCI Timing Specifications1,2
33 MHz3
Num
66 MHz3
Characteristic
Min
Max
Min
Max
Unit
Frequency of Operation
—
33.33
33.33
66.66
MHz
P1
Clock Period
30
—
15
30
ns
P2
Bused PCI signals — input setup
7.0
—
3.0
—
ns
P3
PCI_GNT[3:0]/PCI_REQ[3:0] — input setup
10.0
—
5.0
—
ns
P4
All PCI signals — input hold
0
—
0
—
ns
P5
Bused PCI signals — output valid
—
11.0
—
6.0
ns
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
27
Electrical Characteristics
Table 14. PCI Timing Specifications1,2 (continued)
33 MHz3
Num
66 MHz3
Characteristic
Min
Max
Min
Max
Unit
P6
PCI_REQ[3:0]/PCI_GNT[3:0] — output valid
—
12.0
—
6.0
ns
P7
All PCI signals — output hold
2.0
—
1.0
—
ns
1
The PCI bus operates at the CLKIN frequency. All timings are relative to the input clock, CLKIN.
All PCI signals are bused signals except for PCI_GNT[3:0] and PCI_REQ[3:0]. These signals are defined as point-to-point
signals by the PCI Specification.
3
The 66-MHz parameters are only guaranteed when the 66-MHz PCI pad slew rates are selected. Likewise, the 33-MHz
parameters are only guaranteed when the 33-MHz PCI pad slew rates are selected.
2
P1
CLKIN
P5
P6
Output
Valid/Hold
P7
Output Valid
P2
P3
Input
Setup/Hold
P4
Input Valid
Figure 13. PCI Timing
5.9.1
Overshoot and Undershoot
Figure 14 shows the specification limits for overshoot and undershoot for PCI I/O. To guarantee long term reliability, the
specification limits shown must be followed. Good transmission line design practices should be observed to guarantee the
specification limits.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
28
Freescale Semiconductor
Electrical Characteristics
VDD + 0.9V
VDD + 0.5V
VDD
GND
GND - 0.5V
GND - 1.0V
Not to exceed 17%
of PCI Cycle
Figure 14. Overshoot and Undershoot Limits
5.10
ULPI Timing Specifications
The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing
requirements for the ULPI pins are given in Table 15. These timings apply to synchronous mode only. All timings are measured
with respect to the clock as seen at the USB_CLKIN pin on the MCF5445x. The ULPI PHY is the source of the 60MHz clock.
NOTE
The USB controller requires a 60-MHz clock, even if using the on-chip FS/LS transceiver
instead of the ULPI interface. In this case, the 60-MHz clock can be generated by the PLL
or input on the USB_CLKIN pin.
Table 15. ULPI Interface Timing
Num
Characteristic
Min
Nominal
Max
Units
USB_CLKIN operating frequency
—
60
—
MHz
USB_CLKIN duty cycle
—
50
—
%
U1
USB_CLKIN clock period
—
16.67
—
ns
U2
Input Setup (control and data)
5.0
—
—
ns
U3
Input Hold (control and data)
1.0
—
—
ns
U4
Output Valid (control and data)
—
—
9.5
ns
U5
Output Hold (control and data)
1.0
—
—
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
29
Electrical Characteristics
U1
USB_CLKIN
U3
U2
ULPI_DIR / ULPI_NXT
(Control Input)
U2
U3
ULPI_DATA[7:0]
(Data Input)
U5
U4
ULPI_STP
(Control Output)
U5
U4
ULPI_DATA[7:0]
(Data Output)
Figure 15. ULPI Timing Diagram
5.11
SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
Table 16. SSI Timing — Master Modes1
Num
Description
Symbol
Min
Max
Units
Notes
tMCLK
2 × tSYS
—
ns
2
45%
55%
tMCLK
8 × tSYS
—
ns
45%
55%
tBCLK
S1
SSI_MCLK cycle time
S2
SSI_MCLK pulse width high / low
S3
SSI_BCLK cycle time
S4
SSI_BCLK pulse width
S5
SSI_BCLK to SSI_FS output valid
—
15
ns
S6
SSI_BCLK to SSI_FS output invalid
0
—
ns
S7
SSI_BCLK to SSI_TXD valid
—
15
ns
S8
SSI_BCLK to SSI_TXD invalid / high impedence
-2
—
ns
S9
SSI_RXD / SSI_FS input setup before SSI_BCLK
10
—
ns
S10
SSI_RXD / SSI_FS input hold after SSI_BCLK
0
—
ns
tBCLK
3
1
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (fsys).
3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of the internal system clock (f ).
sys
2
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
30
Freescale Semiconductor
Electrical Characteristics
Table 17. SSI Timing — Slave Modes1
Num
1
Description
Symbol
Min
Max
Units
tBCLK
8 × tSYS
—
ns
45%
55%
tBCLK
S11
SSI_BCLK cycle time
S12
SSI_BCLK pulse width high / low
S13
SSI_FS input setup before SSI_BCLK
10
—
ns
S14
SSI_FS input hold after SSI_BCLK
2
—
ns
S15
SSI_BCLK to SSI_TXD / SSI_FS output valid
—
15
ns
S16
SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
0
—
ns
S17
SSI_RXD setup before SSI_BCLK
10
—
ns
S18
SSI_RXD hold after SSI_BCLK
2
—
ns
Notes
All timings specified with a capactive load of 25pF.
S1
S2
S2
SSI_MCLK
(Output)
S3
SSI_BCLK
(Output)
S4
S4
S5
S6
SSI_FS
(Output)
S9
S10
SSI_FS
(Input)
S7
S7
S8
S8
SSI_TXD
S9
S10
SSI_RXD
Figure 16. SSI Timing — Master Modes
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
31
Electrical Characteristics
S11
SSI_BCLK
(Input)
S12
S12
S15
S16
SSI_FS
(Output)
S13
S14
SSI_FS
(Input)
S15
S16
S16
S15
SSI_TXD
S17
S18
SSI_RXD
Figure 17. SSI Timing — Slave Modes
5.12
I2C Timing Specifications
Table 18 lists specifications for the I2C input timing parameters shown in Figure 18.
Table 18. I2C Input Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2
—
tSYS
I2
Clock low period
8
—
tSYS
I3
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
ms
I4
Data hold time
0
—
ns
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
ms
I6
Clock high time
4
—
tSYS
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2
—
tSYS
I9
Stop condition setup time
2
—
tSYS
Table 19 lists specifications for the I2C output timing parameters shown in Figure 18.
Table 19. I2C Output Timing Specifications between SCL and SDA
Num
I1
1
I21
Characteristic
Min
Max
Units
Start condition hold time
6
—
tSYS
Clock low period
10
—
tSYS
I3
2
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
—
µs
I4
1
Data hold time
7
—
tSYS
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
3
ns
I53
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
32
Freescale Semiconductor
Electrical Characteristics
Table 19. I2C Output Timing Specifications between SCL and SDA (continued)
Num
Characteristic
Min
Max
Units
I61
Clock high time
10
—
tSYS
I71
Data setup time
2
—
tSYS
Start condition setup time (for repeated start condition only)
20
—
tSYS
Stop condition setup time
10
—
tSYS
I8
1
I91
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 19. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR. However, the numbers
given in Table 19 are minimum values.
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
3 Specified at a nominal 50-pF load.
I5
I6
I2
I2C_SCL
I1
I7
I4
I8
I3
I9
I2C_SDA
Figure 18. I2C Input/Output Timings
5.13
Fast Ethernet Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
5.13.1
Receive Signal Timing Specifications
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.
Table 20. Receive Signal Timing
MII Mode
Num
—
1
RMII Mode
Characteristic
Unit
RXCLK frequency
1
Min
Max
Min
Max
—
25
—
50
MHz
5
—
4
—
ns
5
—
2
—
ns
E1
RXD[n:0], RXDV, RXER to RXCLK setup
E2
RXCLK to RXD[n:0], RXDV, RXER hold1
E3
RXCLK pulse width high
35%
65%
35%
65%
RXCLK period
E4
RXCLK pulse width low
35%
65%
35%
65%
RXCLK period
In MII mode, n = 3; In RMII mode, n = 1
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
33
Electrical Characteristics
E4
RXCLK (Input)
E3
E1
RXD[n:0]
RXDV,
RXER
E2
Valid Data
Figure 19. MII Receive Signal Timing Diagram
5.13.2
Transmit Signal Timing Specifications
Table 21. Transmit Signal Timing
MII Mode
Num
1
RMII Mode
Characteristic
Unit
—
TXCLK frequency
E5
TXCLK to TXD[n:0], TXEN, TXER invalid1
valid1
Min
Max
Min
Max
—
25
—
50
MHz
5
—
5
—
ns
—
25
—
14
ns
E6
TXCLK to TXD[n:0], TXEN, TXER
E7
TXCLK pulse width high
35%
65%
35%
65%
tTXCLK
E8
TXCLK pulse width low
35%
65%
35%
65%
tTXCLK
In MII mode, n = 3; In RMII mode, n = 1
E8
TXCLK (Input)
E7
E6
TXD[n:0]
TXEN,
TXER
E5
Valid Data
Figure 20. MII Transmit Signal Timing Diagram
5.13.3
Asynchronous Input Signal Timing Specifications
Table 22. MII Transmit Signal Timing
Num
E9
Characteristic
CRS, COL minimum pulse width
Min
Max
Unit
1.5
—
TXCLK period
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
34
Freescale Semiconductor
Electrical Characteristics
CRS, COL
E9
Figure 21. MII Async Inputs Timing Diagram
5.13.4
MII Serial Management Timing Specifications
Table 23. MII Serial Management Channel Signal Timing
Num
Characteristic
Symbol
Min
Max
Unit
tMDC
400
—
ns
E10
MDC cycle time
E11
MDC pulse width
40
60
% tMDC
E12
MDC to MDIO output valid
—
375
ns
E13
MDC to MDIO output invalid
25
—
ns
E14
MDIO input to MDC setup
10
—
ns
E15
MDIO input to MDC hold
0
—
ns
E10
E11
MDC (Output)
E11
E13
E12
Valid Data
MDIO (Output)
E14
MDIO (Input)
E15
Valid Data
Figure 22. MII Serial Management Channel TIming Diagram
5.14
32-Bit Timer Module Timing Specifications
Table 24 lists timer module AC timings.
Table 24. Timer Module AC Timing Specifications
Name
Characteristic
Min
Max
Unit
T1
DTnIN cycle time (n = 0:3)
3
—
tsys/2
T2
DTnIN pulse width (n = 0:3)
1
—
tsys/2
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
35
Electrical Characteristics
5.15
ATA Interface Timing Specifications
The ATA controller is compatible with the ATA/ATAPI-6 industry standard. Refer to the ATA/ATAPI-6 Specficiation and the
ATA controller chapter of the MCF54455 Reference Manual for timing diagrams of the various modes of operation.
The timings of the various ATA data transfer modes are determined by a set of timing equations described in the ATA section
of the MCF54455 Reference Manual. These timing equations must be fulfilled for the ATA host to meet timing. Table 25
provides implementation specific timing parameters necessary to complete the timing equations.
Table 25. ATA Interface Timing Specifications1,2
Name
Characteristic
Symbol
Min
Max
Unit
Notes
A1
Setup time — ATA_IORDY to SYSCLK falling
tSUI
4.0
—
ns
A2
Hold time — ATA_IORDY from SYSCLK falling
tHI
3.0
—
ns
A3
Setup time — ATA_DATA[15:0] to SYSCLK rising
tSU
4.0
—
ns
A4
Propagation delay — SYSCLK rising to all outputs
tCO
—
7.0
ns
3
A5
Output skew
tSKEW1
—
1.5
ns
3
A6
Setup time — ATA_DATA[15:0] valid to ATA_IORDY
tI_DS
2.0
—
ns
4
A7
Hold time — ATA_IORDY to ATA_DATA[15:0] invalid
tI_DH
3.5
—
ns
4
1
These parameters are guaranteed by design and not testable.
All timings specified with a capacitive load of 40pF.
3 Applies to ATA_CS[1:0], ATA_DA[2:0], ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA[15:0]
4
Applies to Ultra DMA data-in burst only
2
5.16
DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the
transfer attributes are programmable. Table 26 provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the MCF54455 Reference Manual for information on the modified transfer formats used for communicating
with slower peripheral devices.
Table 26. DSPI Module AC Timing Specifications1
Name
Characteristic
Symbol
Min
Max
Unit
Notes
DS1
DSPI_SCK Cycle Time
tSCK
4 x tSYS
—
ns
2
DS2
DSPI_SCK Duty Cycle
—
(tsck ÷ 2) - 2.0
(tsck ÷ 2) + 2.0
ns
3
Master Mode
DS3
DSPI_PCSn to DSPI_SCK delay
tCSC
(2 × tSYS) - 1.5
—
ns
4
DS4
DSPI_SCK to DSPI_PCSn delay
tASC
(2 × tSYS) - 3.0
—
ns
5
DS5
DSPI_SCK to DSPI_SOUT valid
—
—
5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
—
-5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
—
9
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
—
0
—
ns
—
—
10
ns
Slave Mode
DS9
DSPI_SCK to DSPI_SOUT valid
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
36
Freescale Semiconductor
Electrical Characteristics
Table 26. DSPI Module AC Timing Specifications1 (continued)
Name
1
2
3
4
5
Characteristic
Symbol
Min
Max
Unit
DS10
DSPI_SCK to DSPI_SOUT invalid
—
0
—
ns
DS11
DSPI_SIN to DSPI_SCK input setup
—
2
—
ns
DS12
DSPI_SCK to DSPI_SIN input hold
—
7
—
ns
DS13
DSPI_SS active to DSPI_SOUT driven
—
—
10
ns
DS14
DSPI_SS inactive to DSPI_SOUT not driven
—
—
10
ns
Notes
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin
on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR].
This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR],
DCTARn[CPHA], and DCTARn[PBR].
The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
DS3
DS4
DSPI_PCSn
DS1
DS2
DSPI_SCK
(DCTARn[CPOL] = 0)
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS7
DS8
DSPI_SIN
First Data
Data
DS6
DSPI_SOUT
First Data
Last Data
DS5
Data
Last Data
Figure 23. DSPI Classic SPI Timing — Master Mode
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
37
Electrical Characteristics
DSPI_SS
DS1
DSPI_SCK
(DCTARn[CPOL] = 0)
DS2
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS13
DSPI_SOUT
First Data
DS11
DSPI_SIN
DS9
DS10
Data
Last Data
Data
Last Data
DS14
DS12
First Data
Figure 24. DSPI Classic SPI Timing — Slave Mode
5.17
SBF Timing Specifications
The Serial Boot Facility (SBF) provides a means to read configuration information and system boot code from a broad array of
SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 27 provides the AC timing specifications for the SBF.
Table 27. SBF AC Timing Specifications
Name
1
Characteristic
Symbol
Min
Max
Unit
Notes
tSBFCK
40
—
ns
1
SB1
SBF_CK Cycle Time
SB2
SBF_CK High/Low Time
—
30%
—
tSBFCK
SB3
SBF_CS to SBF_CK delay
—
tSBFCK - 2.0
—
ns
SB4
SBF_CK to SBF_CS delay
—
tSBFCK - 2.0
—
ns
SB5
SBF_CK to SBF_DO valid
—
-5
—
ns
SB6
SBF_CK to SBF_DO invalid
—
5
—
ns
SB7
SBF_DI to SBF_SCK input setup
—
10
—
ns
SB8
SBF_CK to SBF_DI input hold
—
0
—
ns
At reset, the SBF_CK cycle time is tREF × 67. The first byte of data read from the serial memory contains a divider value
that is used to set the SBF_CK cycle time for the duration of the serial boot process.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
38
Freescale Semiconductor
Electrical Characteristics
SBF_CS
SB3
SB1
SB2
SBF_CK
SB7
SBF_DI
SB4
SB2
SB8
First Data
Data
Last Data
SB5
SB6
SBF_DO
First Data
Data
Last Data
Figure 25. SBF Timing
5.18
General Purpose I/O Timing Specifications
Table 28. GPIO Timing1
Num
1
Characteristic
Min
Max
Unit
G1
FB_CLK High to GPIO Output Valid
—
9
ns
G2
FB_CLK High to GPIO Output Invalid
1.5
—
ns
G3
GPIO Input Valid to FB_CLK High
9
—
ns
G4
FB_CLK High to GPIO Input Invalid
1.5
—
ns
These general purpose specifications apply to the following signals: IRQn, all UART signals, all timer
signals, DACKn and DREQn, and all signals configured as GPIO.
FB_CLK
G1
G2
GPIO Outputs
G3
G4
GPIO Inputs
Figure 26. GPIO Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
39
Electrical Characteristics
5.19
JTAG and Boundary Scan Timing
Table 29. JTAG and Boundary Scan Timing
Characteristics1
Num
1
Min
Max
Unit
J1
TCLK Frequency of Operation
DC
20
MHz
J2
TCLK Cycle Period
50
—
ns
J3
TCLK Clock Pulse Width
20
30
ns
J4
TCLK Rise and Fall Times
—
3
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
5
—
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
20
—
ns
J7
TCLK Low to Boundary Scan Output Data Valid
—
33
ns
J8
TCLK Low to Boundary Scan Output High Z
—
33
ns
J9
TMS, TDI Input Data Setup Time to TCLK Rise
4
—
ns
J10
TMS, TDI Input Data Hold Time after TCLK Rise
10
—
ns
J11
TCLK Low to TDO Data Valid
—
11
ns
J12
TCLK Low to TDO High Z
—
11
ns
J13
TRST Assert Time
50
—
ns
J14
TRST Setup Time (Negation) to TCLK High
10
—
ns
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 27. Test Clock Input Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
40
Freescale Semiconductor
Electrical Characteristics
TCLK
VIL
VIH
J5
Data Inputs
J6
Input Data Valid
J7
Data Outputs
Output Data Valid
J8
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 28. Boundary Scan (JTAG) Timing
TCLK
VIL
VIH
J9
TDI
TMS
J10
Input Data Valid
J11
TDO
Output Data Valid
J12
TDO
J11
TDO
Output Data Valid
Figure 29. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 30. TRST Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
41
Electrical Characteristics
5.20
Debug AC Timing Specifications
Table 30 lists specifications for the debug AC timing parameters shown in Figure 31 and Table 32.
Table 30. Debug AC Timing Specification
Num
1
Characteristic
Min
Max
Units
D0
PSTCLK cycle time
1
1
tSYS
D1
PSTCLK rising to PSTDDATA valid
—
3.0
ns
D2
PSTCLK rising to PSTDDATA invalid
1.5
—
ns
D3
DSI-to-DSCLK setup
1
—
PSTCLK
D41
DSCLK-to-DSO hold
4
—
PSTCLK
D5
DSCLK cycle time
5
—
PSTCLK
D6
BKPT assertion time
1
—
PSTCLK
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized
DSCLK input relative to the rising edge of PSTCLK.
D0
PSTCLK
D2
D1
PSTDDATA[7:0]
Figure 31. Real-Time Trace AC Timing
D5
DSCLK
D3
DSI
Current
Next
D4
DSO
Past
Current
Figure 32. BDM Serial Port AC Timing
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
42
Freescale Semiconductor
Power Consumption
6
Power Consumption
All power consumption data is lab data measured on an M54455EVB running the Freescale Linux BSP.
Table 31. MCF4455 Application Power Consumption1
Core
Freq.
266 MHz
200 MHz
1
Idle
MP3
Playback
TFTP
Download
USB HS
File Copy
IVDD
215.6
288.8
274.4
263.7
EVDD
27.6
33.6
32.6
32.4
SDVDD
142.9
158.2
161.1
158.0
Total Power
672
829
809
787
IVDD
163.8
228.0
213.8
207.9
EVDD
29.9
34.7
34.3
33.8
SDVDD
142.2
158.5
160.0
153.4
Total Power
601
742
722
699
Units
mA
mW
mA
mW
All voltage rails at nominal values: IVDD = 1.5 V, EVDD = 3.3 V, and SDVDD = 1.8 V.
850
266 MHz
200 MHz
Total Power (mW)
800
750
700
650
600
550
500
Idle
MP3 Playback
TFTP Download USB HS File Copy
Figure 33. Power Consumption in Various Applications
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
43
Power Consumption
All current consumption data is lab data measured on a single device using an evaluation board. Table 32 shows the typical
power consumption in low-power modes. These current measurements are taken after executing a STOP instruction.
Table 32. Current Consumption in Low-Power Modes1,2
System Frequency
Mode
RUN
WAIT/DOZE
STOP 0
STOP 1
STOP 2
STOP 3
Voltage Supply
166 (Typ)3
200 (Typ)3
233 (Typ)3
266 (Typ)3 266 (Peak)4
IVDD (mA)
93.4
110.9
128.2
145.4
202.1
Power (mW)
140.1
166.3
192.4
218.1
303.2
IVDD (mA)
28.0
32.7
37.5
41.1
100.2
Power (mW)
42.0
49.1
56.2
61.7
150.3
IVDD (mA)
17.1
19.8
22.5
25.2
25.2
Power (mW)
25.7
29.7
33.7
37.8
37.8
IVDD (mA)
17.9
19.8
22.4
25.1
25.1
Power (mW)
26.8
29.6
33.6
37.6
37.6
IVDD (mA)
5.7
5.7
5.7
5.7
5.7
Power (mW)
8.6
8.6
8.6
8.6
8.6
IVDD (mA)
1.8
1.8
1.8
1.8
1.8
Power (mW)
2.6
2.6
2.6
2.6
2.6
1
All values are measured on an M54455EVB with 1.5V IVDD power supply. Tests performed at room
temperature.
2 Refer to the Power Management chapter in the MCF54455 Reference Manual for more information
on low-power modes.
3
All peripheral clocks are off except UART0, INTC0, IACK, edge port, reset controller, CCM, PLL, and
FlexBus prior to entering low-power mode.
4 All peripheral clocks on prior to entering low-power mode.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
44
Freescale Semiconductor
Package Information
325.0
300.0
IVDD Power Consumption (mW)
275.0
250.0
225.0
Run
200.0
Wait/Doze
175.0
Stop 0
150.0
Stop 1
125.0
Stop 2
Stop 3
100.0
75.0
50.0
25.0
0.0
166
200
233
266
266 (peak)
System Frequency (MHz)
Figure 34. IVDD Power Consumption in Low-Power Modes
7
Package Information
The latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire.
Table 33 lists the case outline numbers per device. Use these numbers in the web page’s keyword search engine to find the latest
package outline drawings.
Table 33. Package Information
Device
Package Type
Case Outline Numbers
256 MAPBGA
98ARH98219A
360 TEPBGA
98ARE10605D
MCF54450
MCF54451
MCF54452
MCF54453
MCF54454
MCF54455
8
Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution
Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire.
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
45
Revision History
9
Revision History
Table 34 summarizes revisions to this document.
Table 34. Revision History
Rev. No.
Date
Summary of Changes
0
Sept 17, 2007 Initial public release.
1
Feb 15, 2008 Corrected VSS pin locations in MCF5445x signal information and muxing table for the 360 TEPBGA
package: changed “...M9, M16, M17...” to “...M9–M14, M16...”
Updated FlexBus read and write timing diagrams and added two notes before them.
Change FB_A[23:0] to FB_A[31:0] in FlexBus read and write timing diagrams.
Added power consumption section.
2
May 1, 2008 In Family Configurations table, added PCI as feature on 256-pin devices. On these devices the
PCI_AD bus is limited to 24-bits.
In Absolute Maximum Ratings table, changed RTCVDD specification from “-0.3 to +4.0” to “-0.5 to
+2.0”.
In DC Electrical Specifications table:
• Changed RTCVDD specification from 3.0–3.6 to 1.35–1.65.
• Changed High Impedance (Off-State) Leakage Current (IOZ) specification from ±1 to ±10μA, and
added footnote to this spec: “Worst-case tristate leakage current with only one I/O pin high. Since
all I/Os share power when high, the leakage current is distributed among them. With all I/Os high,
this spec reduces to ±2 μA min/max.“
3
Dec 1, 2008 Changed “360PBGA” heading to “360 TEPBGA” in Table 6.
Changed the following specs in Table 13:
• Minimum frequency of operation from — to 60MHz
• Maximum clock period from — to 16.67 ns
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
46
Freescale Semiconductor
Revision History
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
47
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Document Number: MCF54455
Rev. 3
12/2008
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