TI1 LMP7707MAX/NOPB Precision, cmos input, rrio, wide supply range decompensated amplifier Datasheet

LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B – JUNE 2007 – REVISED MARCH 2013
LMP7707/LMP7708/LMP7709 Precision, CMOS Input, RRIO, Wide Supply Range
Decompensated Amplifiers
Check for Samples: LMP7707, LMP7708, LMP7709
FEATURES
DESCRIPTION
•
The LMP7707/LMP7708/LMP7709 devices are
single, dual, and quad low offset voltage, rail-to-rail
input and output precision amplifiers which each have
a CMOS input stage and a wide supply voltage
range. The LMP7707/LMP7708/LMP7709 are part of
the LMP™ precision amplifier family and are ideal for
sensor
interface
and
other
instrumentation
applications. These decompensated amplifiers are
stable at a gain of 6 and higher.
1
23
•
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•
•
•
•
•
•
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•
•
•
Unless Otherwise Noted, Typical Values at
VS = 5V.
Input Offset Voltage (LMP7707) ±200 µV (Max)
Input Offset Voltage (LMP7708/LMP7709)
±220 µV (Max)
Input Bias Current ±200 fA
Input Voltage Noise 9 nV/√Hz
CMRR 130 dB
Open Loop Gain 130 dB
Temperature Range −40°C to 125°C
Gain Bandwidth Product (AV =10) 14 MHz
Stable at a Gain of 10 or Higher
Supply Current (LMP7707) 715 µA
Supply Current (LMP7708) 1.5 mA
Supply Current (LMP7709) 2.9 mA
Supply Voltage Range 2.7V to 12V
Rail-to-Rail Input and Output
APPLICATIONS
•
•
•
•
•
•
High Impedance Sensor Interface
Battery Powered Instrumentation
High Gain Amplifiers
DAC Buffer
Instrumentation Amplifier
Active Filters
The ensured low offset voltage of less than ±200 µV
along with the ensured low input bias current of less
than ±1 pA make the LMP7707/LMP7708/LMP7709
ideal
for
precision
applications.
The
LMP7707/LMP7708/LMP7709 are built utilizing VIP50
technology, which allows the combination of a CMOS
input stage and a supply voltage range of 12V with
rail-to-rail common mode voltage capability. The
LMP7707/LMP7708/LMP7709 are the perfect choice
in many applications where conventional CMOS parts
cannot operate due to the voltage conditions.
The unique design of the rail-to-rail input stage of
each
of
the
LMP7707/LMP7708/LMP7709
significantly reduces the CMRR glitch commonly
associated with rail-to-rail input amplifiers. Both sides
of the complimentary input stage have been trimmed,
thereby reducing the difference between the NMOS
and PMOS offsets. The output swings within 40 mV
of either rail to maximize the signal dynamic range in
applications requiring low supply voltage.
The LMP7707 is offered in the space-saving 5-pin
SOT-23 and 8-pin SOIC packages, the LMP7708 is
offered in the 8-pin VSSOP and 8-pin SOIC
packages, and the quad LMP7709 is offered in the
14-pin TSSOP and 14-pin SOIC packages. These
small packages are ideal solutions for area
constrained PC boards and portable electronics.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMP7707, LMP7708, LMP7709
SNOSAW5B – JUNE 2007 – REVISED MARCH 2013
www.ti.com
Open Loop Frequency Response
DECOMPENSATED OP AMP
AOL
UNITY-GAIN STABLE OP AMP
Gmin
fGBWP
fd
f1
fu
f2
fu'
Figure 1. Increased Bandwidth for Same Supply Current at AV> 10
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Human Body Model
ESD Tolerance (3)
2000V
Machine Model
200V
Charge Device Model
1000V
VIN Differential
±300 mV
Supply Voltage (VS = V+ – V−)
13.2V
V++ 0.3V to V− − 0.3V
Voltage at Input/Output Pins
Input Current
10 mA
−65°C to +150°C
Storage Temperature Range
Junction Temperature (4)
Soldering Information
(1)
(2)
(3)
(4)
+150°C
Infrared or Convection (20 sec)
235°C
Wave Soldering Lead Temp. (10 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Operating Ratings (1)
Temperature Range (2)
−40°C to +125°C
Supply Voltage (VS = V+ – V−)
Package Thermal Resistance (θJA) (2)
(1)
(2)
2
2.7V to 12V
5-Pin SOT-23
265°C/W
8-Pin SOIC
190°C/W
8-Pin VSSOP
235°C/W
14-Pin TSSOP
122°C/W
14-Pin SOIC
145°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics tables.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B – JUNE 2007 – REVISED MARCH 2013
3V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
VOS
Min (2)
LMP7707
Input Offset Voltage
LMP7708/LMP7709
TCVOS
Input Offset Voltage Drift (4)
IB
IOS
PSRR
CMVR
Power Supply Rejection Ratio
Input Common-Mode Voltage Range
AVOL
Open Loop Voltage Gain
VO
Output Swing High
Output Swing Low
(4)
(5)
±200
±500
±56
±220
±520
±1
±5
Units
μV
μV/°C
±1
±50
−40°C ≤ TA ≤ 125°C
±400
pA
40
Common Mode Rejection Ratio
(3)
±37
−40°C ≤ TA ≤ 85°C
Input Offset Current
CMRR
(2)
Max (2)
±0.2
Input Bias Current (4) (5)
(1)
Typ (3)
0V ≤ VCM ≤ 3V
LMP7707
86
80
130
0V ≤ VCM ≤ 3V
LMP7708/LMP7709
84
78
130
2.7V ≤ V+ ≤ 12V, VO = V+/2
86
82
98
fA
dB
dB
CMRR ≥ 80 dB
−0.2
3.2
CMRR ≥ 77 dB
−0.2
3.2
RL = 2 kΩ (LMP7707)
VO = 0.3V to 2.7V
100
96
114
RL = 2 kΩ (LMP7708/LMP7709)
VO = 0.3V to 2.7V
100
94
114
RL = 10 kΩ
VO = 0.2V to 2.8V
100
96
124
V
dB
RL = 2 kΩ to V+/2
LMP7707
40
80
120
RL = 2 kΩ to V+/2
LMP7708/LMP7709
40
80
150
RL = 10 kΩ to V+/2
LMP7707
30
40
60
RL = 10 kΩ to V+/2
LMP7708/LMP7709
35
50
100
RL = 2 kΩ to V+/2
LMP7707
40
60
80
RL = 2 kΩ to V+/2
LMP7708/LMP7709
45
100
170
RL = 10 kΩ to V+/2
LMP7707
20
40
50
RL = 10 kΩ to V+/2
LMP7708/LMP7709
20
50
90
mV
from V+
mV
Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
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3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Min (2)
Typ (3)
Sourcing VO = V /2
VIN = 100 mV
25
15
42
Sinking VO = V+/2
VIN = −100 mV (LMP7707)
25
20
42
Sinking VO = V+/2
VIN = −100 mV
(LMP7708/LMP7709)
25
15
42
Parameter
Conditions
+
IO
Output Short Circuit Current (6) (7)
IS
LMP7707
Supply Current
LMP7708
LMP7709
Max (2)
Units
mA
0.670
1.0
1.2
1.4
1.8
2.1
2.9
3.5
4.5
mA
SR
Slew Rate (8)
VO = 2 VPP,10% to 90%
5.1
V/μs
GBWP
Gain Bandwidth Product
AV = 10
13
MHz
Total Harmonic Distortion + Noise
f = 1 kHz, AV = 10, VO = 2.5V,
RL = 10 kΩ
0.024
%
en
Input-Referred Voltage Noise
f = 1 kHz
9
nV/√Hz
in
Input-Referred Current Noise
f = 100 kHz
1
fA/√Hz
THD+N
(6)
(7)
(8)
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
The short circuit test is a momentary test.
The number specified is the slower of positive and negative slew rates.
5V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
VOS
Min (2)
Conditions
LMP7707
Input Offset Voltage
LMP7708/LMP7709
TCVOS
Input Offset Voltage Drift (4)
IB
Input Bias Current (4) (5)
IOS
Common Mode Rejection Ratio
PSRR
(1)
(2)
(3)
(4)
(5)
4
Power Supply Rejection Ratio
Max (2)
±37
±200
±500
±32
±220
±520
±1
±5
±0.2
±1
−40°C ≤ TA ≤ 85°C
±50
−40°C ≤ TA ≤ 125°C
±400
Input Offset Current
CMRR
Typ (3)
40
0V ≤ VCM ≤ 5V
LMP7707
88
83
130
0V ≤ VCM ≤ 5V
LMP7708/LMP7709
86
81
130
2.7V ≤ V+ ≤ 12V, VO = V+/2
86
82
100
Units
μV
μV/°C
pA
fA
dB
dB
Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B – JUNE 2007 – REVISED MARCH 2013
5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
CMVR
Parameter
Conditions
Input Common-Mode Voltage Range
AVOL
Open Loop Voltage Gain
VO
Output Swing High
Output Swing Low
IO
Output Short Circuit Current (6) (7)
IS
Typ (3)
Max (2)
CMRR ≥ 80 dB
−0.2
5.2
CMRR ≥ 78 dB
−0.2
5.2
RL = 2 kΩ (LMP7707)
VO = 0.3V to 4.7V
100
96
119
RL = 2 kΩ (LMP7708/LMP7709)
VO = 0.3V to 4.7V
100
94
119
RL = 10 kΩ
VO = 0.2V to 4.8V
100
96
130
60
110
130
RL = 2 kΩ to V+/2
LMP7708/LMP7709
60
120
200
RL = 10 kΩ to V+/2
LMP7707
40
50
70
RL = 10 kΩ to V+/2
LMP7708/LMP7709
40
60
120
RL = 2 kΩ to V+/2
LMP7707
50
80
90
RL = 2 kΩ to V+/2
LMP7708/LMP7709
50
120
190
RL = 10 kΩ to V+/2
LMP7707
30
40
50
RL = 10 kΩ to V+/2
LMP7708/LMP7709
30
50
100
Sourcing VO = V+/2
VIN = 100 mV (LMP7707)
40
28
66
Sourcing VO = V+/2
VIN = 100 mV (LMP7708/LMP7709)
38
25
66
Sinking VO = V+/2
VIN = −100 mV (LMP7707)
40
28
76
Sinking VO = V+/2
VIN = −100 mV (LMP7708/LMP7709)
40
23
76
LMP7708
LMP7709
Units
V
dB
RL = 2 kΩ to V+/2
LMP7707
LMP7707
Supply Current
Min (2)
mV
from V+
mV
mA
0.715
1.0
1.2
1.5
1.9
2.2
2.9
3.7
4.6
mA
SR
Slew Rate (8)
VO = 4 VPP, 10% to 90%
5.6
V/μs
GBWP
Gain Bandwidth Product
AV = 10
14
MHz
Total Harmonic Distortion + Noise
f = 1 kHz, AV = 10, VO = 4.5V,
RL = 10 kΩ
0.024
%
en
Input-Referred Voltage Noise
f = 1 kHz
9
nV/√Hz
in
Input-Referred Current Noise
f = 100 kHz
1
fA/√Hz
THD+N
(6)
(7)
(8)
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
The short circuit test is a momentary test.
The number specified is the slower of positive and negative slew rates.
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
Submit Documentation Feedback
5
LMP7707, LMP7708, LMP7709
SNOSAW5B – JUNE 2007 – REVISED MARCH 2013
www.ti.com
±5V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = −5V, VCM = 0V, and RL > 10 kΩ to 0V.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
VOS
Min (2)
LMP7707
Input Offset Voltage
LMP7708/LMP7709
TCVOS
Input Offset Voltage Drift (4)
IB
IOS
PSRR
CMVR
Power Supply Rejection Ratio
Input Common-Mode Voltage Range
AVOL
Open Loop Voltage Gain
VO
Output Swing High
Output Swing Low
(4)
(5)
6
±200
±500
±37
±220
±520
±1
±5
−40°C ≤ TA ≤ 125°C
±400
−5V ≤ VCM ≤ 5V
LMP7707
92
88
138
−5V ≤ VCM ≤ 5V
LMP7708/LMP7709
90
86
138
2.7V ≤ V+ ≤ 12V, V− = 0V, VO = V+/2
86
82
98
Units
μV
μV/°C
1
±50
40
Common Mode Rejection Ratio
(3)
±37
−40°C ≤ TA ≤ 85°C
Input Offset Current
CMRR
(2)
Max (2)
±0.2
Input Bias Current (4) (5)
(1)
Typ (3)
pA
fA
dB
dB
CMRR ≥ 80 dB
−5.2
5.2
CMRR ≥ 78 dB
−5.2
5.2
RL = 2 kΩ (LMP7707)
VO = −4.7V to 4.7V
100
98
121
RL = 2 kΩ (LMP7708/LMP7709)
VO = −4.7V to 4.7V
100
94
121
RL = 10 kΩ (LMP7707)
VO = −4.8V to 4.8V
100
98
134
RL = 10 kΩ (LMP7708/LMP7709)
VO = −4.8V to 4.8V
100
97
134
V
dB
RL = 2 kΩ to 0V
LMP7707
90
150
170
RL = 2 kΩ to 0V
LMP7708/LMP7709
90
180
290
RL = 10 kΩ to 0V
LMP7707
40
80
100
RL = 10 kΩ to 0V
LMP7708/LMP7709
40
80
150
RL = 2 kΩ to 0V
LMP7707
90
130
150
RL = 2 kΩ to 0V
LMP7708/LMP7709
90
180
290
RL = 10 kΩ to 0V
LMP7707
40
50
60
RL = 10 kΩ to 0V
LMP7708/LMP7709
40
60
110
mV
from V+
mV
from V–
Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B – JUNE 2007 – REVISED MARCH 2013
±5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = −5V, VCM = 0V, and RL > 10 kΩ to 0V.
Boldface limits apply at the temperature extremes.
Symbol
Min (2)
Typ (3)
Sourcing VO = 0V
VIN = 100 mV (LMP7707)
50
35
86
Sourcing VO = 0V
VIN = 100 mV (LMP7708/LMP7709)
48
33
86
Sinking VO = 0V
VIN = −100 mV
50
35
84
Parameter
Conditions
IO
Output Short Circuit Current (6) (7)
IS
LMP7707
Supply Current
LMP7708
LMP7709
Max (2)
Units
mA
0.790
1.1
1.3
1.7
2.1
2.5
3.2
4.2
5.0
mA
SR
Slew Rate (8)
VO = 9 VPP, 10% to 90%
5.9
V/μs
GBWP
Gain Bandwidth Product
AV = 10
15
MHz
Total Harmonic Distortion + Noise
f = 1 kHz, AV = 10, VO = 9V,
RL = 10 kΩ
0.024
%
en
Input-Referred Voltage Noise
f = 1 kHz
9
nV/√Hz
in
Input-Referred Current Noise
f = 100 kHz
1
fA/√Hz
THD+N
(6)
(7)
(8)
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
The short circuit test is a momentary test.
The number specified is the slower of positive and negative slew rates.
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
Submit Documentation Feedback
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Connection Diagrams
Top View
OUT
Top View
5
1
+
V
2
IN-
V
2
+
IN+
IN+
4
3
IN-
Figure 2. LMP7707 5-Pin SOT-23
See DBV Package
V
-
3
6
+
5
NC
+
V
OUT
NC
Figure 3. LMP7707 8-Pin SOIC
See D Package
Top View
Figure 4. LMP7708 8-Pin VSSOP (See DGK
Package)
LMP7708 8-Pin SOIC (See D Package)
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7
-
4
Top View
8
8
1
NC
Figure 5. LMP7709 14-Pin TSSOP (See PW
Package)
LMP7709 14-Pin SOIC (See D Package)
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
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SNOSAW5B – JUNE 2007 – REVISED MARCH 2013
Typical Performance Characteristics
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Offset Voltage Distribution
TCVOS Distribution
20
25
VS = 3V
VS = 3V
-40°C d TA d 125°C
16
PERCENTAGE (%)
PERCENTAGE (%)
20
TA = 25°C
15
10
12
8
4
5
0
-200
0
-100
0
100
200
-3
-2
-1
0
TCVOS (PV/°C)
Figure 6.
Figure 7.
Offset Voltage Distribution
3
TCVOS Distribution
VS = 5V
VS = 5V
TA = 25°C
-40°C d TA d 125°C
16
PERCENTAGE (%)
20
PERCENTAGE (%)
2
20
25
15
10
12
8
4
5
0
-200
0
-100
0
100
OFFSET VOLTAGE (PV)
200
-3
-2
-1
0
1
2
3
TCVOS (PV/°C)
Figure 8.
Figure 9.
Offset Voltage Distribution
TCVOS Distribution
20
25
VS = 10V
VS = 10V
-40°C d TA d 125°C
TA = 25°C
16
PERCENTAGE (%)
20
PERCENTAGE (%)
1
OFFSET VOLTAGE (PV)
15
10
8
4
5
0
-200
12
0
-100
0
100
OFFSET VOLTAGE (PV)
200
-3
-2
Figure 10.
-1
0
1
2
3
TCVOS (PV/°C)
Figure 11.
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
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LMP7707, LMP7708, LMP7709
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
-20
150
-40
-20
100
-40
-60
-60
-80
-80
VS = 3V
50
CMRR (dB)
OFFSET VOLTAGE (PV)
Offset Voltage vs. Temperature
200
0
-50
VS = 5V
CMRR vs. Frequency
VS = 3V
VS = 5V
-100
-100
-120
-120
-140
-100
-150
-160
-140
-200
-160
VS = 10V
VS = 10V
-40 -20
0
20
40
60
10
80 100 120125
100
1k
Figure 12.
200
150
150
VS = 3V
100
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
1M
Offset Voltage vs. VCM
200
-40°C
50
0
25°C
-50
-100
125°C
-40°C
100
50
25°C
0
-50
125°C
-100
-150
-150
-200
2
4
6
8
10
-200
-0.5
12
0
0.5 1
1.5
2
2.5
3
3.5
VCM (V)
SUPPLY VOLTAGE (V)
Figure 14.
Figure 15.
Offset Voltage vs. VCM
Offset Voltage vs. VCM
200
200
VS = 10V
VS = 5V
150
150
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
100k
Figure 13.
Offset Voltage vs. Supply Voltage
100
-40°C
50
0
25°C
-50
-100
125°C
-150
100
-40°C
50
0
25°C
-50
-100
-150
125°C
-200
-200
-1
10
10k
FREQUENCY (Hz)
TEMPERATURE (°C)
0
1
2
3
4
5
6
-1 0
1
2
3
4
5
6
VCM (V)
VCM (V)
Figure 16.
Figure 17.
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8
9 10 11
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Input Bias Current vs. VCM
Input Bias Current vs. VCM
300
200
VS = 3V
VS = 3V
200
100
IBIAS (pA)
IBIAS (fA)
100
-40°C
0
85°C
0
-100
-100
-200
125°C
25°C
-300
-200
0
0.5
1
2
1.5
2.5
0
3
0.5
1.5
1
2
Figure 18.
3
Figure 19.
Input Bias Current vs. VCM
Input Bias Current vs. VCM
300
300
VS = 5V
VS = 5V
200
200
100
100
IBIAS (pA)
IBIAS (fA)
2.5
VCM (V)
VCM (V)
-40°C
0
85°C
0
-100
-100
-200
-200
25°C
125°C
-300
-300
0
1
2
3
4
1
0
5
2
3
4
5
VCM (V)
VCM (V)
Figure 20.
Figure 21.
Input Bias Current vs. VCM
Input Bias Current vs. VCM
300
500
VS = 10V
VS = 10V
200
250
IBIAS (pA)
IBIAS (fA)
100
-40°C
0
85°C
0
-100
-250
-200
25°C
125°C
-500
-300
0
2
4
6
8
10
0
2
4
6
VCM (V)
VCM (V)
Figure 22.
Figure 23.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Supply Current vs.
Supply Voltage (Per Channel)
PSRR vs. Frequency
1.2
-PSRR VS = 3V
120
1
SUPPLY CURRENT (mA)
-PSRR VS = 5V
100
PSRR (dB)
+PSRR VS = 10V
80
-PSRR VS = 10V
60
40
+PSRR VS = 3V
10
+PSRR VS = 5V
100
25°C
0.8
0.6
-40°C
0.4
0.2
20
AV = +10
125°C
1k
10k
100k
FREQUENCY (Hz)
0
1M
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
Figure 24.
Figure 25.
Sinking Current vs. Supply Voltage
Sourcing Current vs. Supply Voltage
120
120
-40°C
100
-40°C
100
25°C
25°C
60
ISOURCE (mA)
ISINK (mA)
80
125°C
40
20
80
125°C
60
40
20
0
0
2
4
6
8
10
12
2
4
SUPPLY VOLTAGE (V)
6
Figure 26.
Output Voltage vs. Output Current
TA = -40°C, 25°C, 125C
AV = +10
7.5
+
+
(V ) -2
|
3V
2
1
VS = 3V, 5V, 10V
SLEW RATE (V/Ûs)
VOUT FROM RAIL (V)
(V ) -1
20
40
60
80
100
FALLING EDGE
7.0
8.0
7.5
6.5
7.0
6.5
6.0
6.0
5.5
5.5
5.0
4.5
5.0
4.0
3.5
4.5
3.0
4.0
RISING EDGE
2
4
Figure 28.
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RL = 10 k:
CL = 10 pF
OUTPUT CURRENT (mA)
12
VIN = 200 mV
3.5
3.0
0
12
Slew Rate vs. Supply Voltage
8.0
|
10
Figure 27.
+
V
0
8
SUPPLY VOLTAGE (V)
6
8
10
SUPPLY VOLTAGE (V)
12
Figure 29.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Open Loop Frequency Response
25°C
135
90
90
45
45
0
0
-45
-90
-45
-135
100
80
60
40
20
0
-20
-40
-60
-90
100k
125°C
1M
10M
225
180
VS = 10V
135
CL = 22 pF 90
45
0
-45
VS = 3V
-90
CL = 100 pF
AV = -10
-135
VS = 3V, 5V, 10V
PHASE
CL = 22 pF, 47 pF, 100 pF
-135
100M
1k
10k
1M
10M
100M
Figure 30.
Figure 31.
Small Signal Step Response, AV = 10
Large Signal Step Response, AV = 10
VS = 5V
f = 10 kHz
AV = +10
500 mV/DIV
VIN = 10 mVPP
VIN = 200 mVPP
RL = 10 k:
RL = 10 k:
CL = 10 pF
CL = 10 pF
10 Ûs/DIV
10 Ûs/DIV
Figure 32.
Figure 33.
Small Signal Step Response, AV = 100
Large Signal Step Response, AV = 100
500 mV/DIV
25 mV/DIV
25 mV/DIV
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
VS = 5V
f = 10 kHz
AV = +10
VS = 5V
f = 10 kHz
AV = +100
VIN = 1 mVPP
PHASE (°)
-40°C
PHASE
AV = -10
-40
-20 VS = 5V
-60
RL = 10 k:
-40
CL = 22 pF
-60
1k
10k
GAIN
180
225
135
180
GAIN
GAIN (dB)
GAIN (dB)
80
100
60
80
60
40
40
20
20
0
0
-20
Open Loop Frequency Response
225
PHASE (°)
100
VS = 5V
f = 10 kHz
AV = +100
VIN = 20 mVPP
RL = 10 k:
RL = 10 k:
CL = 10 pF
CL = 10 pF
10 Ûs/DIV
10 Ûs/DIV
Figure 34.
Figure 35.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
Open Loop Gain vs.
Output Voltage Swing
Input Voltage Noise vs. Frequency
150
VS = 10V
100
80
VS = 3V
60
VS = 5V
40
130
120
RL = 10 k:
110
VS = 3V
100
90
80
20
1
10
RL = 2 k:
70
VS = 10V
0
100
1k
10k
60
500
100k
FREQUENCY (Hz)
Output Swing Low vs.
Supply Voltage
0
50
RL = 10 k:
25°C
40
125°C
30
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
100
Output Swing High vs.
Supply Voltage
-40°C
20
10
2
4
6
8
10
30
25°C
125°C
20
10
0
12
-40°C
2
4
SUPPLY VOLTAGE (V)
6
8
10
12
SUPPLY VOLTAGE (V)
Figure 38.
Figure 39.
Output Swing High vs.
Supply Voltage
Output Swing Low vs.
Supply Voltage
100
100
RL = 2 k:
RL = 2 k:
25°C
25°C
80
80
125°C
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
200
Figure 37.
40
60
-40°C
40
20
0
300
Figure 36.
RL = 10 k:
0
400
OUTPUT SWING FROM RAIL (mV)
50
2
4
6
8
10
12
125°C
60
-40°C
40
20
0
2
4
SUPPLY VOLTAGE (V)
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6
8
10
12
SUPPLY VOLTAGE (V)
Figure 40.
14
VS = 5V
140
OPEN LOOP GAIN (dB)
INPUT REFERRED VOLTAGE NOISE
(nV/ Hz)
120
Figure 41.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, VCM = VS/2, RL > 10 kΩ connected to (V++V−)/2
THD+N vs. Frequency
THD+N vs. Output Voltage
100
1
VS = 5V
VOUT = 4.5VPP
RL = 100 k:
Noise band = 500 kHz
AV = +10
10
0.1
THD+N (%)
THD+N (%)
AV = +100
AV = +100
AV = +10
0.01
10
100
1k
10k
1
0.1 V = 5V
S
f = 1 kHz
RL = 100 k:
Noise band = 500 kHz
0.01
0.01
0.1
100k
1
FREQUENCY (Hz)
VOUT (VPP)
Figure 42.
Figure 43.
10
Crosstalk Rejection Ratio vs.
Frequency(LMP7708/LMP7709)
140
CROSSTALK REJECTION (dB)
VS = 12V
120
VS = 5V
VS = 3V
100
80
60
40
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 44.
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APPLICATION INFORMATION
LMP7707/LMP7708/LMP7709
The LMP7707/LMP7708/LMP7709 devices are single, dual and quad low offset voltage, rail-to-rail input and
output precision amplifiers each with a CMOS input stage and the wide supply voltage range of 2.7V to 12V. The
LMP7707/LMP7708/LMP7709 have a very low input bias current of only ±200 fA at room temperature.
The wide supply voltage range of 2.7V to 12V over the extensive temperature range of −40°C to 125°C makes
either the LMP7707, LMP7708 or LMP7709 an excellent choice for low voltage precision applications with
extensive temperature requirements.
The LMP7707/LMP7708/LMP7709 have only ±37 µV of typical input referred offset voltage and this offset is
ensured to be less than ±500 µV for the single and ±520 µV for the dual and quad over temperature. This
minimal offset voltage allows more accurate signal detection and amplification in precision applications.
The low input bias current of only ±200 fA along with the low input referred voltage noise of 9 nV/√Hz give the
LMP7707/LMP7708/LMP7709 superior qualities for use in sensor applications. Lower levels of noise introduced
by the amplifier mean better signal fidelity and a higher signal-to-noise ratio.
The LMP7707/LMP7708/LMP7709 are stable for a gain of 6 or higher. With proper compensation though, the
LMP7707, LMP7708 or LMP7709 can be operational at a gain of ±1 and still maintain much faster slew rates
than comparable fully compensated amplifiers. The increase in bandwidth and slew rate is obtained without any
additional power consumption.
Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical
support and extensive characterization data is available for sensitive applications or applications with a
constrained error budget.
The LMP7707 is offered in the space-saving 5-pin SOT-23 and 8-pin SOIC packages, the LMP7708 comes in the
8-pin VSSOP and 8-pin SOIC packages, and the LMP7709 is offered in the 14-pin TSSOP and 14-pin SOIC
packages. These small packages are ideal solutions for area constrained PC boards and portable electronics.
CAPACITIVE LOAD
The LMP7707/LMP7708/LMP7709 devices can each be connected as a non-inverting voltage follower. This
configuration is the most sensitive to capacitive loading.
The combination of a capacitive load placed on the output of an amplifier along with the amplifier’s output
impedance creates a phase lag which in turn reduces the phase margin of the amplifier. If the phase margin is
significantly reduced, the response will be either underdamped or it will oscillate.
In order to drive heavier capacitive loads, an isolation resistor, RISO, as shown in the circuit in Figure 45 should
be used. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output, and hence, the
pole caused by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the output
voltage will be. If values of RISO are sufficiently large, the feedback loop will be stable, independent of the value
of CL. However, larger values of RISO result in reduced output swing and reduced output current drive.
VIN
RISO
+
VOUT
-
R1
CL
R2
Figure 45. Isolating Capacitive Load
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INPUT CAPACITANCE
CMOS input stages inherently have low input bias current and higher input referred voltage noise. The
LMP7707/LMP7708/LMP7709 enhances this performance by having the low input bias current of only ±200 fA,
as well as a very low input referred voltage noise of 9 nV/√Hz. In order to achieve this a large input stage has
been used. This large input stage increases the input capacitance of the LMP7707/LMP7708/LMP7709. The
typical value of this input capacitance, CIN, for the LMP7707/LMP7708/LMP7709 is 25 pF. The input capacitance
will interact with other impedances such as gain and feedback resistors, which are seen on the inputs of the
amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at low frequencies and
DC conditions, but will play a bigger role as the frequency increases. At higher frequencies, the presence of this
pole will decrease phase margin and will also cause gain peaking. In order to compensate for the input
capacitance, care must be taken in choosing the feedback resistors. In addition to being selective in picking
values for the feedback resistor, a capacitor can be added to the feedback path to increase stability.
CF
R2
R1
+
VIN
CIN
+
+
-
-
VOUT
Figure 46. Compensating for Input Capacitance
Using this compensation method will have an impact on the high frequency gain of the op amp, due to the
frequency dependent feedback of this amplifier. Low gain settings can, again, introduce instability issues.
DIODES BETWEEN THE INPUTS
The LMP7707/LMP7708/LMP7709 have a set of anti-parallel diodes between the input pins, as shown in
Figure 47. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the
amount of differential input voltage that is allowed on the input pins. A differential signal larger than one diode
voltage drop might damage the diodes. The differential signal between the inputs needs to be limited to ±300 mV
or the input current needs to be limited to ±10 mA. Exceeding these limits will damage the part.
V
V
D1
ESD
IN
+
+
R1
ESD
R2
+
IN
ESD
ESD
D2
V
-
R1 = R2 = 130Ö
-
-
V
Figure 47. Input of the LMP7707
TOTAL NOISE CONTRIBUTION
The LMP7707/LMP7708/LMP7709 have very low input bias current, very low input current noise and very low
input voltage noise. As a result, these amplifiers are ideal choices for circuits with high impedance sensor
applications.
Figure 48 shows the typical input noise of the LMP7707/LMP7708/LMP7709 as a function of source resistance.
The total noise at the input can be calculated using Equation 1.
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eni =
2
2
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2
en + ei + et
where
•
•
•
•
eni is the total noise on the input
en denotes the input referred voltage noise
ei is the voltage drop across source resistance due to input referred current noise or ei = RS * in
et is the thermal noise of the source resistance
(1)
The input current noise of the LMP7707/LMP7708/LMP7709 is so low that it will not become the dominant factor
in the total noise unless source resistance exceeds 300 MΩ, which is an unrealistically high value.
As is evident in Figure 48, at lower RS values, the total noise is dominated by the amplifier’s input voltage noise.
Once RS is larger than a few kilo-Ohms, then the dominant noise factor becomes the thermal noise of RS. As
mentioned before, the current noise will not be the dominant noise factor for any practical application.
VOLTAGE NOISE DENSITY (nV/ Hz)
1000
100
eni
en
10
et
ei
1
0.1
10
100
1k
10k
100k
1M
10M
RS (:)
Figure 48. Total Input Noise
HIGH IMPEDANCE SENSOR INTERFACE
Many sensors have high source impedances that may range up to 10 MΩ. The output signal of sensors often
needs to be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier
can load the sensor’s output and cause a voltage drop across the source resistance as shown in Figure 49,
where VIN + = VS – IBIAS*RS
The last term, IBIAS*RS, shows the voltage drop across RS. To prevent errors introduced to the system due to this
voltage, an op amp with very low input bias current must be used with high impedance sensors. This is to keep
the error contribution by IBIAS*RS less than the input voltage noise of the amplifier, so that it will not become the
dominant noise factor. The LMP7707/LMP7708/LMP7709 have very low input bias current, typically 200 fA.
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SENSOR
+
IB
RS
VS
V
VIN+
+
-
+
R1
-
V
R2
Figure 49. Noise Due to IBIAS
USAGE OF DECOMPENSATED AMPLIFIERS
This section discusses the differences between compensated and decompensated op amps and presents the
advantages of decompensated amplifiers. In high gain applications decompensated amplifiers can be used
without any changes compared to standard amplifiers. However, for low gain applications special frequency
compensation measures have to be taken to ensure stability.
Feedback circuit theory is discussed in detail, in particular as it applies to decompensated amplifiers. Bode plots
are presented for a graphical explanation of stability analysis. Two solutions are given for creating a feedback
network for decompensated amplifiers when relatively low gains are required: A simple resistive feedback
network and a more advanced frequency dependent feedback network with improved noise performance. Finally,
a design example is presented resulting in a practical application. The results are compared to fully compensated
amplifiers (Texas Instruments LMP7701/LMP7702/LMP7704).
COMPENSATED AMPLIFIERS
A (fully) compensated op amp is designed to operate with good stability down to gains of ±1. For this reason, the
compensated op amp is also called a unity gain stable op amp.
Figure 50 shows the Open Loop Response of a compensated amplifier.
80
100
80
100
60
120
40
140
20
160
PHASE (°)
GAIN (dB)
Phase LMP7701
Gain LMP7701
0
-20
180
1k
10k
100k
1M
10M
200
100M
FREQUENCY (Hz)
Figure 50. Open Loop Frequency Response Compensated Amplifier (LMP7701)
This amplifier is unity gain stable, because the phase shift is still < 180°, when the gain crosses 0 dB (unity gain).
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Stability can be expressed in two different ways:
Phase Margin This is the phase difference between the actual phase shift and 180°, at the point where the gain
is 0 dB.
Gain Margin This is the gain difference relative to 0 dB, at the frequency where the phase shift crosses the 180°.
The amplifier is supposed to be used with negative feedback but a phase shift of 180° will turn the negative
feedback into positive feedback, resulting in oscillations. A phase shift of 180° is not a problem when the gain is
smaller than 0 dB, so the critical point for stability is 180° phase shift at 0 dB gain. The gain margin and phase
margin express the margin enhancing overall stability between the amplifiers response and this critical point.
DECOMPENSATED AMPLIFIERS
Decompensated amplifiers, such as the LMP7707/LMP7708/LMP7709, are designed to maximize the bandwidth
and slew rate without any additional power consumption over the unity gain stable op amp. That is, a
decompensated op amp has a higher bandwidth to power ratio than an equivalent compensated op amp.
Compared with the unity gain stable amplifier, the decompensated version has the following advantages:
1. A wider closed loop bandwidth
2. Better slew rate due to reduced compensation capacitance within the op amp
3. Better Full Power Bandwidth, given with Equation 2
FPBW =
SR
2 í VP
(2)
Figure 51 shows the frequency response of the decompensated amplifier.
80
100
80
100
60
120
40
140
PHASE (°)
GAIN (dB)
Phase LMP7707
160
20
Gain LMP7707
0
-20
180
1k
10k
100k
1M
10M
200
100M
FREQUENCY (Hz)
Figure 51. Open Loop Frequency Response Decompensated Amplifier (LMP7707)
As shown in Figure 51, the reduced internal compensation moves the first pole to higher frequencies. The
second open loop pole for the LMP7707/LMP7708/LMP7709 occurs at 4 MHz. The extrapolated unity gain (see
dashed line in Figure 51) occurs at 14 MHz. An ideal two pole system would give a phase margin of > 45° at the
location of the second pole. Unfortunately, the LMP7707/LMP7708/LMP7709 have parasitic poles close to the
second pole, giving a phase margin closer to 0°. The LMP7707/LMP7708/LMP7709 can be used at frequencies
where the phase margin is > 45°. The frequency where the phase margin is 45° is at 2.4 MHz. The
corresponding value of the open loop gain (also called GMIN) is 6 times.
Stability has only to do with the loop gain and not with the forward gain (G) of the op amp. For high gains, the
feedback network is attenuating and this reduces the loop gain; therefore the op amp will be stable for G > GMIN
and no special measures are required. For low gains the feedback network attenuation may not be sufficient to
ensure loop stability for a decompensated amplifier. However, with an external compensation network
decompensated amplifiers can still be made stable while maintaining their advantages over unity gain stable
amplifiers.
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EXTERNAL COMPENSATION FOR GAINS LOWER THAN GMIN.
This section explains how decompensated amplifiers can be used in configurations requiring a gain lower than
GMIN. In the next sections the concept of the feedback factor is introduced. Subsequently, an explanation is given
how stability can be determined using the frequency response curve of the op amp together with the feedback
factor. Using the circuit theory, it will be explained how decompensated amplifiers can be stabilized at lower
gains.
FEEDBACK THEORY
Stability issues can be analyzed by verifying the loop gain function GF, where G is the open loop gain of the
amplifier and F is the feedback factor of the feedback circuit.
The feedback function (F) of arbitrary electronic circuits, as shown in Figure 52, is defined as the ratio of the
input and output signal of the same circuit.
RF
R1
VA
VB
RF
R1
-
VA
VOUT
+
VIN
VB
-
VOUT
+
VIN
Figure 52. Op Amp with Resistive Feedback. (a) Non-inverting (b) Inverting
The feedback function for a three-terminal op amp as shown in Figure 52 is the feedback voltage VA – VB across
the op amp input terminals relative to the op amp output voltage, VOUT. That is
VA - VB
F=
VOUT
(3)
GRAPHICAL EXPLANATION OF STABILITY ANALYSIS
Stability issues can be observed by verifying the closed loop gain function GF. In the frequencies of interest, the
open loop gain (G) of the amplifier is a number larger than 1 and therefore positive in dB. The feedback factor (F)
of the feedback circuit is an attenuation and therefore negative in dB. For calculating the closed loop gain GF in
dB we can add the values of G and F (both in dB).
One practical approach to stabilizing the system, is to assign a value to the feedback factor F such that the
remaining loop gain GF equals one (unity gain) at the frequency of GMIN. This realizes a phase margin of 45° or
greater. This results in the following requirement for stability: 1/F > GMIN. The inverse feedback factor 1/F is
constant over frequency and should intercept the open loop gain at a value in dB that is greater than or equal to
GMIN.
The inverse feedback factor for both configurations shown in Figure 52, is given by:
R
1
=1+ F
R1
F
(4)
The closed loop gain for the non-inverting configuration (a) is:
RF
1
ACL = 1 +
=
F
R1
(5)
The closed loop gain for the inverting configuration (b) is:
RF
1
ACL = - R = 1 F
1
(6)
For stable operation the phase margin must be equal to or greater than 45°. The corresponding closed loop gain
GMIN, for a non-inverting configuration, is
|ACL|(min) = Gmin
(7)
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For an inverting configuration:
|ACL|(min) = Gmin - 1
(8)
If R1 and RF and are chosen so that the closed loop gain is lower than the minimum gain required for stability,
then 1/F intersects the open loop gain curve for a value that is lower than GMIN. For example, assume the GMIN is
equal to 10 V/V (20 dB). This is shown as the dashed line in Figure 53. The resistor choice of RF = R1 = 2 kΩ
makes the inverse feedback equal 2 V/V (6 dB), shown in Figure 53 as the solid line. The intercept of G and 1/F
represents the frequency for which the loop gain is identical to 1 (0 dB). Consequently, the total phase shift at the
frequency of this intercept determines the phase margin and the overall system stability. In this system example
1/F crosses the open loop gain at a frequency which is larger than the frequency where GMIN occurs, therefore
this system has less than 45° phase margin and is most likely instable.
AOL
Gmin = 20 dB
RF
1
=1+
F
R1
1
= 6 dB
F
f1
f2
Figure 53. 1/F for RF = R1 and Open Loop Gain Plot
RESISTIVE COMPENSATION
A straightforward way to achieve a stable amplifier configuration is to add a resistor RC between the inverting and
the non-inverting inputs as shown in Figure 54.
RF
R1
RC
VOUT
+
Figure 54. Op Amp with Compensation Resistor between Inputs
This additional resistor RC will not affect the closed loop gain of the amplifier but it will have positive impact on
the feedback network.
The inverse feedback function of this circuit is:
RF
R
1
R
=1+
=1+ F + F
Rc
F
R1//Rc
R1
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Proper selection of the value of RC results in the shifting of the 1/F function to GMIN or greater, thus fulfilling the
condition for circuit stability. The compensation technique of reducing the loop gain may be used to stabilize the
circuit for the values given in the previous example, that is GMIN = 20 dB and RF = R1 = 2 kΩ. A resistor value of
250 Ω applied between the amplifier inputs shifts the 1/F curve to the value GMIN (20 dB) as shown by the
dashed line in Figure 55. This results in overall stability for the circuit. This figure shows a combination of the
open and closed loop gain and the inverse feedback function.
This example, represented by Figure 52 and Figure 53, is generic in the sense that the GMIN as specified did not
distinguish between inverting and non-inverting configurations.
AOL
Gmin = 20 dB
1+
RF
RF
= 6 dB
f1
f2
Figure 55. Compensation with Reduced Loop Gain
The technique of reducing loop gain to stabilize a decompensated op amp circuit will be illustrated using the noninverting input configuration shown in Figure 56.
RF
R1
VX
-
VOUT
RC
+
VIN
Figure 56. Closed Loop Gain Analysis with RC
The effect of the choice of resistor RC in Figure 56 on the closed loop gain can be analyzed in the following
manner:
Assume the voltage at the inverting input of the op amp is VX. Then,
(VIN ± VX) G = VOUT
where
•
VX
R1
+
G is the open loop gain of the op amp
VX - VIN
RC
=
(10)
VOUT - VX
RF
(11)
Combining Equation 10, Equation 11, and Equation 9 produces the following equation for closed loop gain,
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VOUT
VIN
1+
=
1+
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RF
R1
1
GF
(12)
By inspection of Equation 12, RC does not affect the ideal closed loop gain. In this example where RF = R1, the
closed loop gain remains at 6 dB as long as GF >> 1. The closed loop gain curve is shown as the solid line in
Figure 55.
The addition of RC affects the circuit in the following ways:
1.
1/F is moved to a higher gain, resulting in overall system stability.
However, adding RC results in reduced loop gain and increased noise gain. The noise gain is defined as the
inverse of the feedback factor, F. The noise gain is the gain from the amplifier input referred noise to the output.
In effect, loop gain is traded for stability.
2.
The ideal closed loop gain retains the same value as the circuit without the compensation resistor RC.
LEAD-LAG COMPENSATION
This section presents a more advanced compensation technique that can be used to stabilize amplifiers. The
increased noise gain of the prior circuit is prevented by reducing the low frequency attenuation of the feedback
circuit. This compensation method is called Lead-Lag compensation. Lead-lag compensation components will be
analyzed and a design example using this procedure will be discussed.
The feedback function in a lead-lag compensation circuit is shaped using a resistor and a capacitor. They are
chosen in a way that ensures sufficient phase margin.
Figure 57 shows a Bode plot containing: the open loop gain of the decompensated amplifier, a feedback function
without compensation and a feedback function with lead-lag compensation.
100
80
GAIN (dB)
-20 dB/dec
60
40
20
20 dB/dec
1/F with compensation
1/F without compensation
0
1M
FREQUENCY (Hz)
Figure 57. Bode Plot of Open Loop gain G and 1/F with and without Lead-Lag Compensation
The shaped feedback function presented in Figure 57 can be realized using the amplifier configuration in
Figure 58. Note that resistor RP is only used for compensation of the input voltage caused by the IBIAS current. RP
can be used to introduce more freedom for calculating the lead-lag components. This will be discussed later in
this section.
24
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SNOSAW5B – JUNE 2007 – REVISED MARCH 2013
RF
R1
RC
C
+
RP
Figure 58. LMP7707 with Lead-Lag Compensation for Inverting Configuration
The inverse feedback factor of the circuit in Figure 58 is:
RF 1 + s(RC + R1//RF + RP)C
1
= (1 +
)(
)
1 + sRCC
F
R1
(13)
The pole of the inverse feedback function is located at:
1
fP =
2íRCC
(14)
The zero of the inverse feedback function is located at:
1
fZ =
2í(RC + R1//RF + RP) C
(15)
The low frequency inverse feedback factor is given by:
RF
1
=1+
R
f
=
0
F
1
(16)
The high frequency inverse feedback factor is given by:
RF
RP + R1//RF
1
= (1 +
)(1 +
)
F f=ñ
R1
RC
(17)
From these formulas, we can tell that
1. The 1/F's zero is located at a lower frequency compared to 1/F's pole.
2. The intersection point of 1/F and the open loop gain G is determined by the choice of resistor values for RP
and RC if the values of R1 and RF are set before compensation.
3. This procedure results in the creation of a pole-zero pair, the positions of which are interdependent.
4. This pole-zero pair is used to:
– Raise the 1/F value to a greater value in the region immediately to the left of its intercept with the A
function in order to meet the Gmin requirement.
– Achieve the preceding with no additional loop phase delay.
5. The location of the 1/F zero is determined by the following conditions:
– The value of 1/F at low frequency.
– The value of 1/F at the intersection point.
– The location of 1/F pole.
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Note that the constraint 1/F ≥ Gmin needs to be satisfied only in the vicinity of the intersection of G and 1/F; 1/F
can be shaped elsewhere as needed. Two rules must be satisfied in order to maintain adequate phase margin.
Rule 1 The plot of 1/F should intersect with the plot of the open loop gain at a value larger than GMIN. At that
point, the open loop gain G has a phase margin of 45°.
The location f2 in Figure 59 illustrates the proper intersection point for the LMP7707/LMP7708/LMP7709
using the circuit of Figure 58. The intersection of G and 1/F at the op amp's second pole location is the
45° phase margin reference point.
Rule 2 The 1/F pole (see Figure 59) should be positioned at the frequency that is at least one decade below the
intersection point f2 of 1/F and G. This positioning takes full advantage of the 90° of phase lead brought
about by the 1/F pole. This additional phase lead accompanies the increase in magnitude of 1/F observed
at frequencies greater than the 1/F pole.
The resulting system has approximately 45° of phase margin, based upon the fact that the open loop gain's
dominant pole and the second pole are more than one decade apart and that the open loop gain has no other
pole within one decade of its intersection point with 1/F. If there is a third pole in the open loop gain G at a
frequency greater than f2 and if it occurs less than a decade above that frequency, then there will be an effect on
phase margin.
DESIGN EXAMPLE
The input lead-lag compensation method can be applied to an application using the LMP7707, LMP7708 or
LMP7709 in an inverting configuration, as shown in Figure 58.
Phase
GAIN (dB) AND PHASE (°)
100
Gain
80
60
40
1/F
20
0
GMIN
-20
1k
10k
100k
1M
f2
f2/10
10M
100M
FREQUENCY (Hz)
Figure 59. LMP7707 Open Loop Gain and 1/F Lead-Lag Feedback Network.
Figure 59 shows that GMIN = 16 dB and f2 (intersection point) = 2.4 MHz.
A gain of 6 dB (or a magnitude of –1) is well below the LMP7707’s GMIN. Without external lead-lag compensation,
the inverse feedback factor is found using Equation 4 which applies to both inverting and non-inverting
configurations. Unity gain implementation for the inverting configuration means RF = R1, and 1/F = 2 (6 dB).
Procedure:
The compensation circuit shown in Figure 58 is implemented. The inverse feedback function is shaped by the
solid line in Figure 59. The 1/F plot is 6 dB at low frequencies. At higher frequencies, it is made to intersect the
loop gain G at frequency f2 with gain amplitude of 16 dB (GMIN), which equals a magnitude of six times. This
follows the recommendations in Rule 1. The 1/F pole fp is set one decade below the intersection point (f2 = 2.4
MHz) as given in Rule 2, and results in a frequency fp = 240 kHz. The next steps should be taken to calculate the
values of the compensation components:
Step 1) Set 1/F equal to GMIN using Equation 17. This gives a value for resistor RC.
Step 2) Set the 1/F pole one decade below the intersection point using Equation 14. This gives a value for
capacitor C.
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This method uses bode plot approximation. Some fine-tuning may be needed to get the best results.
Calculations:
As described in Step 1, use Equation 17:
RF
RP + R1//RF
1
= (1 +
)(1 +
) = 6 V/V
F f=ñ
R1
RC
(18)
Now substitute RF/R1 = 1 into the equation above since this is a unity gain, inverting amplifier, then
RP + R1//RF = 2 RC
(19)
According to Step 2 use Equation 14:
1
fP =
= 240 kHz
2SRCC
(20)
which leads to:
1
C=
2SfRC
(21)
Choose a value of RF that is below 2 kΩ, in order to minimize the possibility of shunt capacitance across high
value resistors producing a negative effect on high frequency operation. If RF = R1 = 1 kΩ, then RF // R1 = 500 Ω.
For simplicity, choose RP = 0 Ω . The value of RC is derived from Equation 19 and has a value of RC = 250 Ω.
This is not a standard value. A value of RC = 330 Ω is a first choice (using 10% tolerance components).
The value of capacitor C is 2.2 nF. This value is significantly higher than the parasitic capacitances associated
with passive components and board layout, and is therefore a good solution.
Bench results:
For bench evaluation the LMP7707 in an inverting configuration has been verified under three different
conditions:
• Uncompensated
• Lead-lag compensation resulting in a phase margin of 45°
• Lead lag overcompensation resulting in a phase margin larger than 45°
The calculated components for these three conditions are
Condition
RC
C
Uncompensated
NA
NA
Compensated
330 Ω
2.2 nF
Overcompensated
240 Ω
3.3 nF
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VOUT (0.5V/DIV)
Figure 60 shows the results of the compensation of the LMP7707.
0
uncompensated
0
compensated
0
overcompensated
TIME (1 Ps/DIV)
Figure 60. Bench Results for Lead- Lag Compensation
The top waveform shows the output response of a uncompensated LMP7707 using no external compensation
components. This trace shows ringing and is unstable (as expected). The middle waveform is the response of a
compensated LMP7707 using the compensation components calculated with the described procedure. The
response is reasonably well behaved. The bottom waveform shows the response of an overcompensated
LMP7707.
Finally, Figure 61 compares the step response of the compensated LMP7707 to that of the unity gain stable
LMP7701. The increase in dynamic performance is clear.
0.8
VOUT (V)
0.4
0.0
LMP7701
-0.4
-0.8
LMP7707 compensated
TIME (1 Ps/DIV)
Figure 61. Bench Results for Comparison of LMP7701 and LMP7707
The application of input lead-lag compensation to a decompensated op amp enables the realization of circuit
gains of less than the minimum specified by the manufacturer. This is accomplished while retaining the
advantageous speed versus power characteristic of decompensated op amps.
28
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SNOSAW5B – JUNE 2007 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 28
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMP7707MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMP77
07MA
LMP7707MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMP77
07MA
LMP7707MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AH4A
LMP7707MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AH4A
LMP7708MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP77
08MA
LMP7708MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP77
08MA
LMP7708MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AJ4A
LMP7708MME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AJ4A
LMP7708MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AJ4A
LMP7709MA/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMP7709
MA
LMP7709MAX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMP7709
MA
LMP7709MT/NOPB
ACTIVE
TSSOP
PW
14
94
Pb-Free
(RoHS)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP77
09MT
LMP7709MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Pb-Free
(RoHS)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP77
09MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMP7707MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP7707MF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMP7707MFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMP7708MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP7708MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP7708MME/NOPB
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP7708MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP7709MAX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LMP7709MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP7707MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP7707MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMP7707MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMP7708MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP7708MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMP7708MME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LMP7708MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMP7709MAX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LMP7709MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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