ON MC33566 Smart voltage regulator for peripheral card application Datasheet

MC33566
Smart Voltage Regulator for
Peripheral Card Applications
The MC33566 Low Dropout Regulator is designed for computer
peripheral card applications complying with the instantly available
requirements as specified by ACPI objectives. The MC33566 permits
glitch−free transitions from “sleep” to “active” system modes and has
internal logic circuitry to detect whether the system is being powered
from the motherboard main 5.0 V power supply or the 3.3 V aux supply.
The MC33566 provides a regulated output voltage of 3.3 V via
either an internal low dropout 5.0 V−to−3.3 V voltage regulator or an
external P−channel MOSFET, depending on the operating status of the
system in which the card is installed. During normal operating mode
(5.0 V main supply available) the 3.3 V output is provided from the
internal low dropout regulator at an output current of 0.4 A. When the
motherboard enters sleep mode, the MC33566 operates from the 3.3 V
aux supply and routes the aux current to the output via the external
P−channel MOSFET bypass transistor controlled by the drive out pin.
As a result, the output voltage provided to the peripheral card remains
constant at 3.3 V even during host systems transitions to and from
sleep mode.
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MARKING
DIAGRAM
D2PAK
D2T SUFFIX
CASE 936A
1
5
Pin
1. Vaux
2. Vin
3. Gnd
4. Vout
5. Drv
1
5
Note: Tab is ground
MC33566 Features:
•
•
•
•
•
•
M5
661
AWLYWW
Output Current up to 0.4 A
Excellent Line and Load Regulation
Low Dropout Voltage
Prevents Reverse Current Flow During Sleep Mode
Glitch−Free Transfer from Sleep Mode to Active Mode
Compatible with Instantly Available PC Systems
A
WL
Y
WW
ORDERING INFORMATION
+3.3 Vaux
External
P−channel
MOSFET
Hyst sw
Comp
Driver
Drive out
Compensation
&
Hysteresis
= Assembly Location
= Wafer Lot
= Year
= Work Week
Device
Package
Shipping†
MC33566D2T−1
D2PAK
50 Units/Rail
MC33566D2T−1RK
D2PAK
800 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
+3.3 Vout
5V detect
Ref &
Detect
Vref
+3.3 Vout
+5 Vin
External
4.7 μF
cap
LDO
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2006
September, 2006 − Rev. 3
1
Publication Order Number:
MC33566/D
MC33566
PIN ASSIGNMENTS AND FUNCTIONS
Pin #
Pin Name
Pin Description
1
+3.3 Vaux
2
+5.0 Vin
3
Gnd
4
+3.3 Vout
3.3 V output provided to the application circuit (output current is sourced to this pin from the
5.0 V input.)
5
Drive out
This output drives a P−channel MOSFET with up to 2000 pF of “effective” gate capacitance.
Recommended devices are the MMFT5P03HD and MTSF1P02HD. Drive out has active internal
pull−up and pull−down circuitry to guarantee fast transitions.
Auxiliary input. Typical voltage 3.3 V.
This is the input supply for the IC. Typical voltage 5.0 V. (Notes 1 and 2)
Logic and power ground.
MAXIMUM RATINGS (TC = 25°C, unless otherwise noted)
Symbol
Value
Unit
Vin
7.0
Vdc
Vin
−0.5 (Note 3)
Vdc
Operating Ambient Temperature
Ta
−5.0 to +85
°C
Operating Junction Temperature
TJ
− 5.0 to +150
°C
Lead Temperature (Soldering, 10 seconds)
TL
300
°C
Storage Temperature
Tstg
− 55 to +150
°C
RθJA (Note 4)
65
°C/W
Rating
+5.0 Vin Supply Voltage
Package Thermal Resistance
AC ELECTRICAL SPECIFICATIONS (Notes 5, 6, and 7)
Symbol
Min
Typ
Max
Unit
Drive High Delay (Vin ramping up)
Cdrive = 1.2 nF, measured from +5.0 Vin = VthresHi to VDrive = 2.0 V
tDH
−
0.5
3.5
μS
Drive Low Delay (Vin ramping down)
Cdrive = 1.2 nF, measured from +5.0 Vin = VthresLo to VDrive = 2.0 V
tDL
−
0.5
3.5
μS
Characteristic
1. See 5.0 V Detect Thresholds Diagram.
2. Recommended source impedance for 5.0 V supply: ≤ 0.12 W. This will ensure that Io x Rsource < Vhyst, thus avoiding driveout toggling during
5.0 V detect threshold transitions.
3. Vin should not be allowed to go negative relative to ground.
4. Mounted on recommended minimum PCB pad on FR4, 2−oz. copper circuit board.
5. AC specs are guaranteed by characterization, but not production tested after characterization.
6. See Figure 3. Application Block Diagram.
7. See Timing Diagram.
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2
MC33566
DC ELECTRICAL CHARACTERISTICS (Note 8)
Symbol
Min
Typ
Max
Unit
+5.0 Vin Supply Voltage Range
+5.0 Vin
4.35
5.0
5.5
Vdc
Reverse Leakage Current from Output
Ireverse
−
−
25
μA
Vaux Quiescent Current
Iqaux
−
−
2.0
mA
+5.0 Vin Quiescent Current, Operating
Iqvin
−
−
10
mA
Load Capacitance (Note 9)
Cload
4.7
22
−
mF
3.267
3.234
3.30
3.30
3.333
3.366
Vd
3.0
−
−
Vdc
Voltage Out at Max Voltage In
(Vin = 7.0 V)
Voutmax
3.1
3.3
3.5
Vdc
Line Regulation
(Io = 400 mA)
Linereg
−
−
0.4
%
Load Regulation
(Io = 0 to 400 mA)
Loadreg
−
−
0.8
%
Low Threshold Voltage
(+5.0 Vin Falling, Io = 400 mA)
VthresLo
3.9
4.05
−
Vdc
High Threshold Voltage
(+5.0 Vin Rising, Io = 400 mA)
VthresHi
−
4.2
4.35
Vdc
Vhyst
0.05
−
−
Vdc
Output Peak Source Current
(+5.0 Vin > VthresHi)
Ipeak
15
−
−
mA
Output Peak Sink Current
(+5.0 Vin < VthresLo)
Ipeak
15
−
−
mA
Low Output Voltage
(IoL = 200 μA, Vin < VthresLo)
VoL
−
100
200
mVdc
High Output Voltage
(IoH = 200 μA)
VoH
3.4
−
−
Vdc
Characteristic
REGULATOR OUTPUT
+3.3 Vout
Output Voltage
(4.35 V ≤ Vin ≤ 5.5 V, 0 mA ≤ Io ≤ 400 mA) TA = 25°C
(TJ = −5°C to 150°C)
In−to−Out Voltage
(3.9 V ≤ Vin ≤ 4.35 V, Vaux = 3.3 V)
Vdc
5.0 V DETECT
Hysteresis
DRIVE OUTPUT
8. −5°C < Ta < 70°C, 4.35 V < Vin < 5.5 V, Cload ≥ 4.7 μF unless otherwise noted.
9. 4.7 μF minimum over temperature; 22 μF recommended; 500 mW ESR maximum.
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3
MC33566
+3.3 Vaux
External
P−channel
MOSFET
Hyst sw
Comp
Driver
Drive out
Compensation
&
Hysteresis
+3.3 Vout
5V detect
Ref &
Detect
Vref
+3.3 Vout
+5 Vin
External
4.7 μF
cap
LDO
Figure 2. Functional Block Diagram
FUNCTIONAL DESCRIPTION
Glitch−free Transfer − The design of the 5.0 V detect
Input Blocking − The internal NPN pass transistor of the
circuitry and drive out control circuitry guarantees that the
LDO regulator ensures that no significant reverse current
+3.3 Vout will not exceed the output voltage specification
will flow from +3.3 Vout back to the +5.0 Vin input when the
5.0 V input is not powered and the 3.3 Vin supply is present.
listed in the table of DC Operating Specifications even with
+5.0 Vin ramping up and down at the extremes of the slew
5.0 Volt Detect − Internal circuitry detects the presence of
rates in the table of AC Operating Specifications.
the 5.0 V input supply. When the 5.0 V supply drops below
Offset Voltage Performance − To ensure performance
a given threshold, the +3.3 Vin bypass transistor (an external
P−channel MOSFET) is enabled. The 5.0 V detect logic is
when external offsets are present on the +5.0 Vin and
active throughout the entire range of ramp−up from 0 to
+3.3 Vin power inputs, the device has been designed to be
capable of operating with either one or both of these inputs
5.5 V. Additionally, the drive out signal is never turned ON
rising from or falling to zero volts, or with offsets of 0.05 V
or OFF inappropriately during ramp−up of the +5.0 Vin
supply. Also, +3.3 Vout never drops below 3.0 V while
to 0.9 V as the inputs ramp up and down.
+5.0 Vin is above the 5.0 V detect minimum threshold.
3.3V aux
Motherboard/
Mainboard
PCI Slot
5V
PCI Card
Circuitry
4.7 μF
5 4 3 2
D V G V
R O N I
D N
1
V
A
U
X
Figure 3. Application Block Diagram
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4
4.7 μF
MC33566
4.4V
4.4V
VHYST
VTH(HI)
VIN
VIN
VTH(LO)
3.8V
3.8V
tDH
DR
2.0V
DR
2.0V
NOTE:
(1) Vin rise and fall times (10% to 90%) to be ≥ 100 μs.
2.0V
Figure 5. Timing Diagram
200
200
Vout capacitor 5μF
20mW ESR
Phase Margin °
or Gain (dB)
Vout capacitor 5μF
20mW ESR
Phase Margin °
or Gain (dB)
2.0V
NOTE:
(1) Vin rise and fall times (10% to 90%) to be ≤ 100 ns.
Figure 4. 5.0 V Detect Thresholds Diagram
100
tDL
Phase Margin °
100
Phase Margin °
Gain dB
0
101
103
Gain dB
0
101
105
Frequency (Hz)
103
105
Frequency (Hz)
NOTE: Vout capacitor ≥ 4.7 μF over operating temperature range.
Maximum ESR permissable = 500 mW over operating temperature range.
Figure 6. Predicted Gain and Phase
at Zero Load Current
Figure 7. Predicted Gain and Phase
at Full Load Current
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5
MC33566
PACKAGE DIMENSIONS
(D2PAK)
D2T SUFFIX
PLASTIC PACKAGE
CASE 936A−02
ISSUE B
−T−
OPTIONAL
CHAMFER
A
U
S
K
B
V
H
1 2 3 4 5
M
D
0.010 (0.254)
TERMINAL 6
E
M
T
L
P
N
G
R
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS
A AND K.
4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 6.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAXIMUM.
DIM
A
B
C
D
E
G
H
K
L
M
N
P
R
S
U
V
INCHES
MIN
MAX
0.386
0.403
0.356
0.368
0.170
0.180
0.026
0.036
0.045
0.055
0.067 BSC
0.539
0.579
0.050 REF
0.000
0.010
0.088
0.102
0.018
0.026
0.058
0.078
5 _ REF
0.116 REF
0.200 MIN
0.250 MIN
MILLIMETERS
MIN
MAX
9.804 10.236
9.042
9.347
4.318
4.572
0.660
0.914
1.143
1.397
1.702 BSC
13.691 14.707
1.270 REF
0.000
0.254
2.235
2.591
0.457
0.660
1.473
1.981
5 _ REF
2.946 REF
5.080 MIN
6.350 MIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC33566/D
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