[AK4345] AK4345 100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC with DIT GENERAL DESCRIPTION The AK4345 is a 24bit low voltage and low power stereo DAC with an integrated Digital Audio Interface Transmitter. The AK4345 uses an Advanced Multi-Bit ΔΣ architecture, which achieves 100dB dynamic range at 3.3V operation. The AK4345 integrates both switched-capacitor and continuous time filters, enabling performance for systems that have excessive clock jitter. The output voltage level can be set as high as 1Vrms. The AK4345 is offered in a space saving 16pin TSSOP package. FEATURES Sampling Rate: 8kHz ∼ 96kHz 24-Bit 8 times FIR Digital Filter SCF with high tolerance to clock jitter Single-ended output buffer Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling I/F Format: 24-Bit MSB justified, 16/24-Bit LSB justified, I2S Compatible Master Clock: 512/768/1024/1536fs for Half Speed (8kHz ∼ 24kHz) 256/384/512/768fs for Normal Speed (8kHz ∼ 48kHz) 128/192/256/384fs for Double Speed (48kHz ∼ 96kHz) µP Interface: 4-wire/3-wire DIT Bypass mode CMOS Input Level THD+N: -90dB DR, S/N: 100dB DAC output voltage level: 1Vrms (@VDD=3.3V) DIT - AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible - 1-channel Transmission output - 42-bit Channel Status Buffer Power Supply: 2.7 to 3.6V Ta = −20 ∼ 85°C 16pin TSSOP MS0635-E-01 2010/09 -1- [AK4345] MCLK CSN CCLK CDTI CDTO µP Interface De-emphasis Control LRCK Clock Divider VSS VCOM DIT TX SDTI1 VDD Audio Data Interface BICK TEST 8X Interpolator ΔΣ Modulator SCF LPF LOUT 8X Interpolator ΔΣ Modulator SCF LPF ROUT PDN Figure 1. AK4345 Block Diagram (Mode= “0”) MCLK CSN CCLK CDTI µP Interface De-emphasis Control SDTI1 LRCK Clock Divider VSS VCOM DIT TX SDTI2 VDD Audio Data Interface BICK TEST 8X Interpolator ΔΣ Modulator SCF LPF LOUT 8X Interpolator ΔΣ Modulator SCF LPF ROUT PDN Figure 2. AK4345 Block Diagram (Mode= “1”) MS0635-E-01 2010/09 -2- [AK4345] ■ Ordering Guide −20 ∼ +85°C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4345 AK4345ET AKD4345 ■ Pin Layout MCLK 1 16 TX BICK 2 15 CDTO/ SDTI2 SDTI1 3 14 VDD LRCK 4 13 VSS PDN 5 12 VCOM CSN 6 11 LOUT CCLK 7 10 ROUT CDTI 8 9 TEST1 AK4345 Top View MS0635-E-01 2010/09 -3- [AK4345] PIN/FUNCTION No. 1 2 3 4 Pin Name MCLK BICK SDTI1 LRCK I/O I I I I 5 PDN I 6 7 8 CSN CCLK CDTI I I I 9 TEST1 I 10 11 ROUT LOUT O O 12 VCOM O 13 14 VSS VDD CDTO SDTI2 TX O I O 15 16 Function Master Clock Input Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin1 Input Channel Clock Pin Full Power Down Mode Pin “L” : Power down, “H” : Power up Chip Select Pin Control Data Clock Pin Control Data Input Pin TEST Pin This pin must be OPEN. Rch Analog Output Pin, The output is “Hi-Z” when PDN pin = “L”. Lch Analog Output Pin, The output is “Hi-Z” when PDN pin = “L”. Common Voltage Output Pin, 0.5 × VDD Normally connected to VSS with a 4.7μF (min. 1μF, max. 10μF) electrolytic Capacitor. The output is “L” when PDN pin = “L”. Ground Pin Power Supply Pin, 2.7 ∼ 3.6V Control Data Output Pin, The output is “Hi-Z” when PDN pin = “L”. Audio Serial Data Input Pin2 Transmit Channel Output Pin, The output is “L” when PDN pin = “L”. Note: All digital input pins should not be left floating. MS0635-E-01 2010/09 -4- [AK4345] ABSOLUTE MAXIMUM RATINGS (VSS=0V; Note 1) Parameter Symbol Power Supply VDD Input Current, Any Pin Except Supplies IIN Digital Input Voltage (Note 2) VIND Ambient Temperature (Powered applied) Ta Storage Temperature Tstg Note 1. All voltages with respect to ground. Note 2. MCLK, BICK, SDTI1, LRCK, PDN, CSN, CCLK, CDTI, SDTI2 min −0.3 −0.3 −20 −65 max 4.6 ±10 VDD+0.3 85 150 Units V mA V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Symbol min typ Power Supply VDD 2.7 3.3 Note 1. All voltages with respect to ground. max 3.6 Units V WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0635-E-01 2010/09 -5- [AK4345] ANALOG CHARACTERISTICS (Ta=25°C; VDD=3.3V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 20Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units Dynamic Characteristics (GAIN bit= “1”) : Resolution 24 Bits 0dBFS THD+N fs=44.1kHz -90 -80 dB −60dBFS BW=20kHz −37 dB 0dBFS fs=96kHz -88 dB −60dBFS BW=40kHz −34 dB DR (−60dBFS with A-weighted) 92 100 dB S/N (A-weighted) 92 100 dB Interchannel Isolation 80 100 dB DC Accuracy: Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 100 ppm/°C Output Voltage: GAIN bit= “1” (Note 3) 2.60 2.8 3.0 Vpp Output Voltage: GAIN bit=“0” (Note 4) 2.05 2.2 2.35 Vpp Load Resistance (Note 5) 10 kΩ Load Capacitance 25 pF Power Supplies Power Supply Current mA 7.0 Normal Operation (PDN pin = “H”, fs=44.1kHz) (Note 6) mA 12.8 8.5 Normal Operation (PDN pin = “H”, fs=96kHz) (Note 6) μA 50 10 Full Power-down mode (PDN pin = “L”) (Note 7) Note 3. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, Vout = 0.85 × VDD (typ). Note 4. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, Vout = 0.67 × VDD (typ). Note 5. For AC-load. Note 6. RSTN bit= “1”, PW bit= “1”, TX pin: open. When TX pin = 20pF, power supply current ([email protected]) is 9.0mA(typ)@fs= 96kHz. Note 7. All digital input pins are fixed to VDD or VSS. MS0635-E-01 2010/09 -6- [AK4345] FILTER CHARACTERISTICS (Ta=25°C; VDD=2.7 ∼ 3.6V; fs=44.1kHz; DEM1 bit= “0”, DEM0 bit= “1”) Parameter Symbol min typ max Units DAC Digital Filter: Passband (Note 8) ±0.05dB PB 0 20.0 kHz −6.0dB 22.05 kHz Stopband (Note 8) SB 24.1 kHz Passband Ripple PR ±0.01 dB Stopband Attenuation SA 54 dB Group Delay (Note 9) GD 24.0 1/fs Digital Filter + SCF + CTF: FR ±0.1 dB Frequency Response 0 ∼ 20kHz ±0.2 dB ∼ 40kHz (Note 10) Note 8. The passband and stopband frequencies scale with fs (system sampling rate). Note 9. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. Note 10. At fs=96kHz. DC CHARACTERISTICS (Ta=25°C; VDD=2.7 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-80μA) Low-Level Output Voltage (Iout=80µA) Input Leakage Current Symbol VIH VIL VOH1 VOL1 Iin min 70%VDD VDD-0.4 - typ - max 30%VDD 0.4 ± 10 Units V V V V µA typ - max 0.4 50 Units V V pF TX CHARACTERISTICS (Ta=25°C; VDD=2.7 ∼ 3.6V) Parameter High-Level Output Voltage ( Iout=-400μA) Low-Level Output Voltage ( Iout=400μA) Load Capacitance Symbol VOH2 VOL2 CL MS0635-E-01 min VDD-0.4 - 2010/09 -7- [AK4345] SWITCHING CHARACTERISTICS (Ta=25°C; VDD=2.7 ∼ 3.6V; CL = 20pF) Parameter Symbol min Master Clock Frequency 4.096 fCLK Half Speed Mode (512/768/1024/1536fs) 2.048 fCLK Normal Speed Mode (256/384/512/768fs) 6.144 fCLK Double Speed Mode (128/192/256/384fs) 40 dCLK Duty Cycle LRCK Frequency 8 fsh Half Speed Mode (DFS1-0 = “10”) 8 fsn Normal Speed Mode (DFS1-0 = “00”) 48 fsd Double Speed Mode (DFS1-0 = “01”) 45 dCLK Duty Cycle Audio Interface Timing BICK Period 1/128fs tBCK Half Speed Mode 1/128fs tBCK Normal Speed Mode 1/64fs tBCK Double Speed Mode 70 tBCKL BICK Pulse Width Low 70 tBCKH Pulse Width High 40 tBLR BICK “↑” to LRCK Edge (Note 11) 40 tLRB LRCK Edge to BICK “↑” (Note 11) 40 tSDH SDTI Hold Time 40 tSDS SDTI Setup Time Control Interface Timing CCLK Period 200 tCCK CCLK Pulse Width Low 80 tCCKL Pulse Width High 80 tCCKH CDTI Setup Time 40 tCDS CDTI Hold Time 40 tCDH CSN “H” Time 150 tCSW 150 CSN “↓” to CCLK “↑” tCSS 50 tCSH CCLK “↑” to CSN “↑” tDCD CDTO Delay tCCZ CSN “↑” to CDTO Hi-Z typ max Units 36.864 36.864 36.864 60 MHz MHz MHz % 24 48 96 55 kHz kHz kHz % ns ns ns ns ns ns ns ns ns 45 70 ns ns ns ns ns ns ns ns ns ns Power-Down & Reset Timing PDN Pulse Width (Note 12) tPD 4 ms/μF Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. The AK4345 can be reset by bringing PDN pin = “L”. The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4000× C. When C = 4.7μF, tPD is 19ms(min). The value of the capacitor (C) connected with VCOM pin should be 1μF ≤ C ≤ 10μF. MS0635-E-01 2010/09 -8- [AK4345] ■ Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 3. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Figure 4. Serial Interface Timing MS0635-E-01 2010/09 -9- [AK4345] VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS CDTI C1 C0 A4 R/W VIH VIL Hi-Z CDTO Figure 5. WRITE/READ Command Input Timing in 3-wire/4-wire serial mode tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL Hi-Z CDTO Figure 6. WRITE Data Input Timing in 3-wire/4-wire serial mode VIH CSN VIL VIH CCLK VIL CDTI A1 VIH A0 VIL tDCD CDTO Hi-Z D7 D6 D5 50%VDD Figure 7. READ Data Output Timing 1 in 4-wire serial mode MS0635-E-01 2010/09 - 10 - [AK4345] tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ CDTO D3 D2 D1 D0 Hi-Z 50%VDD Figure 8. READ Data Output Timing 2 in 4-wire serial mode tPD PDN VIL Figure 9. Power-Down & Reset Timing MS0635-E-01 2010/09 - 11 - [AK4345] OPERATION OVERVIEW ■ System Clock The external clocks, which are required to operate the AK4345, are MCLK, BICK and LRCK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 bits (Table 1). The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 bit = DFS0 bit = “1”) (Table 2). The AK4345 is automatically placed in the reset mode when MCLK stops in the normal operation mode (PDN pin = “H”), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4345 is powered up. After exiting reset by PDN pin at power-up etc., the AK4345 is in the reset mode until MCLK and LRCK are input. Mode Normal Speed Double Speed Half Speed Auto DFS1 0 0 1 1 DFS0 fs 0 8 ∼ 48kHz 1 48 ∼ 96kHz 0 8 ∼ 24kHz 1 8 ∼ 96kHz Table 1. System Clock Example MCLK Frequency 512/768fs 128/192/256/384fs 1024/1536fs Sampling Speed Mode Normal Speed Double Speed Half Speed Table 2. Auto Mode MCLK Frequency 256/384/512/768fs 128/192/256/384fs 512/768/1024/1536fs Table 2 Fs 8 ∼ 48kHz 48 ∼ 96kHz 8 ∼ 24kHz ■ Audio Interface Format The Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 bits as shown in Table 3 can select four serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 3 can be used for 16bit I2S Compatible format by zeroing the unused LSBs at BICK ≥ 48fs or BICK = 32fs. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 SDTI Format 0 16bit, LSB justified 1 24bit, LSB justified 0 24bit, MSB justified 1 16/24bit, I2S Compatible Table 3. Audio Interface Format MS0635-E-01 BICK ≥ 32fs ≥ 48fs ≥ 48fs ≥ 48fs or 32fs Figure Figure 10 Figure 11 Figure 12 Figure 13 2010/09 - 12 - [AK4345] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 0 1 2 3 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1 BICK(64fs) SDTI(i) Don't Care 15 14 13 12 1 0 Don't Care 15 14 13 12 2 1 0 SDTI-15:MSB, 0:LSB Lch Data Rch Data Figure 10. Mode 0 Timing LRCK 0 1 2 8 9 24 31 0 1 2 8 9 24 31 0 1 BICK(64fs) SDTI(i) Don't Care 23 1 0 8 Don't Care 8 23 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 11. Mode 1 Timing LRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 12. Mode 2 Timing LRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23:MSB, 0:LSB Lch Data Rch Data Figure 13. Mode 3 Timing MS0635-E-01 2010/09 - 13 - [AK4345] ■ Data Transmission Format Data transmitted on the TX outputs is formatted in blocks as shown in Figure 14. Each block consists of 192 frames. A frame of data contains two sub-frames. A sub-frame consists of 32 bits of information. Each received data bit is coded using a bi-phase mark encoding as a two binary state symbol. The preambles violate bi-phase encoding so they may be differentiated from data. In bi-phase encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. For a logic 0, the second state of the symbol is the same as the first state. For a logic 1, the second state is the opposite of the first. Figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states. M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2 Sub-frame Frame 191 Sub-frame Frame 0 Frame 1 Figure 14. Block format 0 1 1 0 0 0 1 0 Figure 15. A biphase-encoded bit stream The sub-frame is defined in Figure 16 below. Bits 0-3 of the sub-frame represent a preamble for synchronization. There are three preambles. The block preamble, B, is contained in the first sub-frame of Frame 0. The channel 1 preamble, M, is contained in the first sub-frame of all other frames. The channel 2 preamble, W, is contained in all of the second sub-frames. Table 4 below defines the symbol encoding for each of the preambles. Bits 4-27 of the sub-frame contain the 24 bit audio sample in 2’s complement format with bit 27 as the most significant bit. For 16 bit mode, Bits 4-11 are all 0. Bit 28 is the validity flag. This is “H” if the audio sample is unreliable. Bit 29 is a user data bit. Frame 0 contains the first bit of a 192 bit user data word. Frame 191 contains the last bit of the user data word. Bit 30 is a channel status bit. Again frame 0 contains the first bit of the 192 bit word with the last bit in frame 191. Bit 31 is an even parity bit for bits 4-31 of the sub-frame. 0 3 4 L S Sync B 27 28 29 30 31 M S V U C P B Audio sam ple Figure 16. Sub-frame format The block of data contains consecutive frames transmitted at a state-bit rate of 64 times the sample frequency, fs. For stereophonic audio, the left or A channel data is in channel 1 while the right or B data is in channel 2. For monophonic audio, channel 1 contains the audio data. Preamble B M W Preceding state = 0 11101000 11100010 11100100 Preceding state = 1 00010111 00011101 00011011 Table 4. Sub-frame preamble encoding ■ Channel Status bit In the consumer mode (bit0 = “0”), bits20-23(audio channel) must be controlled by the CS20 bit. When the CS20 bit is “1”, the AK4345 corresponds to “stereo mode”, bits20-23 are set to “1000”(left channel) in sub-frame 1, and is set to “0100”(right channel) in sub-frame 2. When the CS20 bit is “0”, bits20-23 is set to “0000” in both sub-frame 1 and sub-frame 2. MS0635-E-01 2010/09 - 14 - [AK4345] ■ De-emphasis Filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is controlled by DEM0 and DEM1. In double speed and quad speed mode, the digital de-emphasis filter is always off. DEM1 DEM0 Mode 0 0 1 1 0 1 0 1 44.1kHz OFF 48kHz 32kHz (default) Table 5. De-emphasis Filter Control (Normal Speed Mode) ■ Power-down The AK4345 is placed in the power-down mode by bringing PDN pin = “L”. and the digital filter is reset at the same time. This reset should always be done after power up. PDN Internal State (1) Normal Operation Power-down D/A In (Digital) “0” data GD (2) GD (3) (4) D/A Out (Analog) Clock In (2) (4) (5) Don’t care MCLK, BICK, LRCK External MUTE Normal Operation (6) Mute ON Notes: (1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7μF is attached between VCOM pin and VSS. (2) The analog output corresponding to digital input has the group delay (GD). (3) When PDN pin = “L”, the analog output is Hi-Z. (4) Click noise occurs in 3 ∼ 4LRCK at both edges (↑ ↓) of PDN signal. This noise is output even if “0” data is input. (5) The external clocks (MCLK, BICK and LRCK) can be stopped in the power down mode (PDN pin = “L”). (6) Please mute the analog output externally if the click noise (4) influences system application. The timing example is shown in this figure. Figure 17. Power-down/up sequence example MS0635-E-01 2010/09 - 15 - [AK4345] ■ Reset Function (1) Reset by RSTN bit When RSTN bit =0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage Figure 18 shows the example of reset by RSTN bit. RSTN bit 3~4/fs (6) 2~3/fs (6) Internal RSTN bit Internal State Normal Operation P D/A In (Digital) d “0” data (1) D/A Out (Analog) Normal Operation Digital Block GD GD (3) (2) (3) (1) (4) Clock In Don’t care MCLK,LRCK,BICK Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage (VDD/2). (3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “0”). (5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the internal RSTN bit “1”. Figure 18. Reset Sequence Example1 MS0635-E-01 2010/09 - 16 - [AK4345] (2) RESET by MCLK stop (PDN pin = “H”) When MCLK stops, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage. PDN pin (1) Internal State Power-down D/A In (Digital) Power-down Normal Operation (2) GD (4) Hi-Z VCOM (2) (4) (4) Clock In (5) MCLK Stop MCLK, BICK, LRCK External MUTE Normal Operation (3) GD D/A Out (Analog) Reset (6) (6) (6) Notes: (1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7μF is attached between VCOM pin and VSS. (2) The analog output corresponding to digital input has the group delay (GD). (3) The digital data can be stopped. The click noise after MCLK is input again by inputting the “0” data to this section can be reduced. (4) Click noise occurs in 3 ∼ 4LRCK at both edges (↑ ↓) of PDN signal, MCLK inputs and MCLK stops. This noise is output even if “0” data is input. (5) The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop). (6) Please mute the analog output externally if the click noise (4) influences system application. The timing example is shown in this figure. Figure 19. Reset Sequence Example 2 MS0635-E-01 2010/09 - 17 - [AK4345] ■ μP Control Interface The AK4345 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”). 1.4-wire μP I/F mode (MODE bit = “0”, default) The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI and CDTO. The data on this interface consists of Chip address (2bits, C1/0; fixed to “01”), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. CSN should be set to “H” once after 16 CCLKs. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the registers to their default values. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 WRITE Hi-Z CDTO CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 READ CDTO C1-C0: R/W: A4-A0: D7-D0: Hi-Z D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z Chip Address: (Fixed to “01”) READ/WRITE (0:READ, 1:WRITE) Register Address Control Data Figure 20. 4-wire Serial Control I/F Timing *When the AK4345 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control register is inhibited. MS0635-E-01 2010/09 - 18 - [AK4345] 2.3-wire μP I/F mode (MODE bit = “1”) Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). AK4345 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by 16th CCLK after a high to low transition of CSN. CSN should be set to “H” once after 16 CCLKs for each address. The clock speed of CCLK is 5MHz (max). PDN pin = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are not initialized. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to “01”) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 21. Control I/F Timing *The AK4345 does not support the read command and chip address. C1/0 and R/W are fixed to “011” *When the AK4345 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control register is inhibited. ■ DAC and DIT input select The AK4345 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”). In 3-wire μP I/F mode, the AK4345 can select the input data of DAC and DIT from SDTI1 or SDTI2 data. MODE 0 1 1 1 1 SEL1 x 0 0 1 1 μP I/F 4-wire 3-wire 3-wire 3-wire Reserved SEL0 x 0 1 0 1 DAC input SDTI1 SDTI1 SDTI2 SDTI2 DIT input SDTI1 SDTI1 SDTI2 Bypass (x: Don’t care) Table 6. DAC and DIT Input MS0635-E-01 2010/09 - 19 - [AK4345] ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 1 0 0 0 DIF1 DIF0 PW RSTN 01H 02H Control 2 Control 3 0 0 1 0 0 0 DFS1 INVL DFS0 INVR DEM1 MODE DEM0 SEL1 GAIN SEL0 03H TX 0 0 0 0 0 0 V TXE 04H 05H 06H 07H 08H 09H Channel Status Byte0 Channel Status Byte1 Channel Status Byte2 Channel Status Byte3 Channel Status Byte4 Channel Status Byte5 CS7 CS15 CS23 CS39 CS39 0 CS6 CS14 CS22 CS38 CS38 0 CS5 CS13 CS21 CS37 CS37 0 CS4 CS12 CS20 CS36 CS36 0 CS3 CS11 CS19 CS35 CS35 0 CS2 CS10 CS18 CS34 CS34 0 CS1 CS9 CS17 CS33 CS33 CS41 CS0 CS8 CS16 CS32 CS32 CS40 Notes: For addresses from 0AH to 1FH, data must not be written. When PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values. All data can be written to the register even if PW or RSTN bit is “0”. The bits shown as “0” should be written “0” and the bits shown as “1” should be written “1”. ■ Register Definitions Addr 00H Register Name Control 1 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 DIF1 DIF0 PW RSTN 1 1 1 1 R/W Default R/W 1 0 0 0 RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS changes the click noise occurs. It can be reduced by RSTN bit. PW: Power down control 0: Power down. All registers are not initialized. 1: Normal Operation DIF1-0: Audio data interface formats (Table 3) Initial: “11”, Mode 3 MS0635-E-01 2010/09 - 20 - [AK4345] Addr 01H Register Name Control 2 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 DFS1 DFS0 DEM1 DEM0 GAIN 1 0 1 1 R/W Default R/W 0 1 0 1 DEM1-0: De-emphasis Response (Table 5) Initial: “01”, OFF DFS1-0: Sampling speed control 00: Normal speed 01: Double speed 10: Half speed 11: Auto (default) When changing between Normal/Double Speed Mode and Half Speed Mode, some click noise occurs. GAIN: Output Voltage scale 0: Vout = 0.67 × VDD (typ) at Full-scale voltage (0dB) . 1: Vout = 0.85 × VDD (typ) at Full-scale voltage (0dB) . Register Name 02H Control 3 D7 D6 D5 D4 0 0 0 INVL R/W Default D3 D2 D1 D0 INVR MODE SEL1 SEL0 0 0 0 0 R/W 0 0 0 0 INVR: Inverting Lch Output Polarity 0: Normal Output 1: Inverted Output INVL: Inverting Rch Output Polarity 0: Normal Output 1: Inverted Output MODE: Mode Control 0: 4 wire mode 1: 3 wire mode SEL1-0: DAC and DIT input 00: SDTI1 input 01: SDTI2 input 10: SDTI2 input (DIT Bypass) 11: Reserved SEL1-0 bits are disabled in 4-wire μP I/F mode (MODE bit = “0”). SDTI1 data is input to both DAC and DIT. MS0635-E-01 2010/09 - 21 - [AK4345] Register Name 03H TX D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 V TXE 0 0 0 1 R/W Default R/W 1 0 0 0 V: Validity Flag 0: Valid 1: Invalid TXE: TX output 0: “L” 1: Normal Operation Register Name 04H Channel Status Byte0 Default 05H Channel Status Byte1 Default D7 D6 D5 D4 D3 D2 D1 D0 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 0 0 0 0 0 1 0 0 CS15 CS14 CS13 CS12 CS11 CS10 CS9 CS8 0 0 0 0 0 0 0 0 CS23 CS22 CS21 CS20 CS19 CS18 CS17 CS16 06H Channel Status Byte2 0 0 0 0 0 0 0 0 07H Channel Status Byte3 CS31 CS30 CS29 CS28 CS27 CS26 CS25 CS24 08H Default Channel Status Byte4 0 CS39 0 CS38 0 CS37 0 CS36 0 CS35 0 CS34 0 CS33 0 CS32 09H Default Channel Status Byte5 0 0 0 0 0 0 0 0 0 0 0 0 0 CS41 0 CS40 0 0 0 0 0 0 0 0 Default Default CS7-0: Transmitter Channel Status Byte 0 Default: “00000100” CS39-8: Transmitter Channel Status Byte 4-1 Default: “00000000” CS41-CS40: Transmitter Channel Status Byte 5 Default: “00000000”, D7-D2 bits should be written “0”. MS0635-E-01 2010/09 - 22 - [AK4345] SYSTEM DESIGN Figure 22 and Figure 23 shows the system connection diagram. The evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 300 Master Clock 1 MCLK 64fs 2 24bit Audio Data 3 fs Reset & Power down Micro Controller Digital Ground TX 16 BICK CDTO 15 SDTI VDD 14 Optic transmitting module 0.1u + 10u 4 LRCK VSS 13 5 PDN VCOM 12 6 CSN LOUT 11 Lch Out 7 CCLK ROUT 10 Rch Out 8 CDTI TEST1 9 AK4345 4.7u Analog Supply 2.7 to 3.6V + Analog Ground Figure 22. Typical Connection Diagram (Mode bit = “0”, 4 wire mode ) 24bit Audio Data2 300 Master Clock 1 MCLK 64fs 2 3 24bit Audio Data1 fs Reset & Power down Micro Controller Digital Ground TX 16 BICK SDTI2 15 SDTI VDD 14 Optic transmitting module 0.1u 4 LRCK 5 PDN 6 7 8 + 10u VSS 13 VCOM 12 CSN LOUT 11 Lch Out CCLK ROUT 10 Rch Out CDTI TEST1 9 AK4345 4.7u Analog Supply 2.7 to 3.6V + Analog Ground Figure 23. Typical Connection Diagram (Mode bit = “1”, 3 wire mode ) MS0635-E-01 2010/09 - 23 - [AK4345] 1. Grounding and Power Supply Decoupling The AK4345 requires careful attention for power supply and grounding arrangements. VDD is usually supplied from the analog supply in the system. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4345 as possible, with the small value ceramic capacitor being the closest. 2. Voltage Reference The differential Voltage between VDD and VSS sets the analog output range. VCOM is used as a common voltage of the analog signal. VCOM pin is a signal ground of this chip. An electrolytic capacitor about 4.7μF should be attached between VCOM pin and VSS. No load current may be drawn from VCOM pin. Especially, the ceramic capacitor should be connected to this pin as near as possible. 3. Analog Outputs The analog outputs are single-ended and centered around the VCOM voltage (0.5 × VDD). The output signal range is typically 2.8Vpp (typ@VDD=3.3V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage (0.5 × VDD) for 000000H (@24bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV. Figure 24 shows an example of the external LPF with 2.8Vpp (1Vrms) output. AK4345 10u 220 Analog Out LOUT / ROUT 2.8Vpp (1Vrms) 22k 1nF fc=723.4kHz, g=-0.013dB at 40kHz Figure 24. External 1st order LPF Circuit Example MS0635-E-01 2010/09 - 24 - [AK4345] PACKAGE 16pin TSSOP (Unit: mm) 1.1 (max) *5.0±0.1 16 9 8 1 0.13 M 6.4±0.2 *4.4±0.1 A 0.65 0.22±0.1 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0635-E-01 2010/09 - 25 - [AK4345] MARKING AKM 4345ET XXYYY 1) 2) 3) 4) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4345ET Asahi Kasei Logo REVISION HISTORY Date (YY/MM/DD) 07/06/20 Revision 00 10/09/28 01 Reason First Edition Specification Change Page Contents 25 PACKAGE The package dimensions were changed. MS0635-E-01 2010/09 - 26 - [AK4345] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0635-E-01 2010/09 - 27 -